Array server remote batch burning method based on SPI topology addressing

Abstract

The invention discloses an array server remote batch burning method based on SPI topology addressing, and relates to the technical field of server firmware management.The method comprises the steps that a BMC collects a new-version BIOS mirror image file from a remote server, compares binary differences of old-version BIOS mirror images and generates an increment mapping table; the BMC constructs an SPI instruction sequence based on the incremental mapping table, an instruction frame and a data frame in the SPI instruction sequence are packaged through a multi-modal rule, and a dual-channel assembly line data packet is generated; and the SPI Switch receives the dual-channel pipeline data packet, transmits the packaged instruction frame and data frame in a time window, executes a recombination operation, adds a verification signature, and outputs a complete data block and the verification signature. According to the BIOS upgrading method, dual guarantee of signature verification and write-in verification is realized, data integrity and fault-tolerant recovery are ensured, and a safe and reliable BIOS upgrading effect is achieved.

Description

Technical Field

[0001] This invention relates to the field of server firmware management technology, and in particular to a method for remote batch programming of array servers based on SPI topology addressing. Background Technology

[0002] In the field of server cluster firmware management, firmware burning for array servers typically relies on the baseboard management controller (BMC) to achieve multi-node communication via an SPI bus topology. The conventional method employs a full-image transmission mode, where the BMC obtains the complete BIOS image from a remote server, broadcasts the data to all SoC nodes via a hierarchical SPI switch, and finally completes the burning process synchronously. This method relies on the physical addressing mechanism of the SPI topology, uses chip select signals to distinguish target nodes, and ensures bus conflict avoidance through timing control. Current technologies generally verify basic integrity through checksums and are suitable for centralized firmware deployment in small to medium-sized clusters.

[0003] In the field of remote batch programming of array servers based on SPI topology addressing, the traditional full transmission mode leads to inefficient use of bandwidth resources. When the image version iteration only involves local modifications, redundant data transmission significantly prolongs the programming cycle. In addition, the centralized result verification mechanism is difficult to dynamically respond to node-level anomalies. Due to the SPI bus polling delay and the lack of retry strategy, the failure of a local node can easily cause the overall process to be interrupted, requiring manual intervention to locate the fault point. Summary of the Invention

[0004] In view of the aforementioned existing problems, the present invention is proposed.

[0005] Therefore, this invention provides a remote batch programming method for array servers based on SPI topology addressing to solve the problems of transmission redundancy and fault tolerance mechanism defects in the batch programming process.

[0006] To solve the above-mentioned technical problems, the present invention provides the following technical solution:

[0007] This invention provides a remote batch programming method for an array server based on SPI topology addressing, comprising:

[0008] BMC collects the new BIOS image file from a remote server, compares the binary differences with the old BIOS image, and generates an incremental mapping table.

[0009] BMC constructs the SPI instruction sequence based on the incremental mapping table, and encapsulates the instruction frame and data frame in the SPI instruction sequence through multimodal rules to generate dual-channel pipeline data packets.

[0010] The SPI Switch receives dual-channel pipelined data packets, transmits encapsulated instruction frames and data frames within a time window, performs reassembly operations and adds verification signatures, and outputs complete data blocks and verification signatures.

[0011] The SoC receives the complete data block and verification signature, performs a differentiated write operation to perform CRC verification, and generates verification results and status frames.

[0012] BMC collects all status frames and verification results to obtain the burning results, initiates a retry process for failed nodes, synchronously records node performance data, and outputs a burning report.

[0013] As a preferred embodiment of the remote batch programming method for array servers based on SPI topology addressing described in this invention, wherein: the BMC acquiring the new BIOS image file from the remote server means that the BMC connects to the remote server via HTTPS protocol and downloads the new BIOS image file to the BMC's local cache.

[0014] As a preferred embodiment of the remote batch programming method for array servers based on SPI topology addressing described in this invention, the steps of comparing the binary differences of the old BIOS image and generating an incremental mapping table are as follows:

[0015] Access the SPI Flash memory of each node in the current SoC array via the SPI bus and extract the old BIOS image file of the node;

[0016] By comparing the new BIOS image file with the old BIOS image file, the offset address and length of the difference bytes are identified, and an incremental mapping table is generated by defining structured fields.

[0017] As a preferred embodiment of the remote batch programming method for array servers based on SPI topology addressing described in this invention, the BMC constructs an SPI instruction sequence based on an incremental mapping table, and encapsulates the instruction frames and data frames in the SPI instruction sequence using multimodal rules, as follows:

[0018] BMC reads the structured fields of the incremental mapping table and extracts the address parameters and binary data for each difference region;

[0019] Based on the address parameters and binary data of each different region, instruction frames and data frames are generated according to the SPI protocol conversion rules.

[0020] As a preferred embodiment of the remote batch programming method for array servers based on SPI topology addressing described in this invention, the generation of dual-channel pipelined data packets refers to encapsulating all instruction frames and data frames separately, adding packet sequence numbers and topology addressing headers, and generating dual-channel pipelined data packets.

[0021] As a preferred embodiment of the remote batch programming method for array servers based on SPI topology addressing described in this invention, the SPI switch receives dual-channel pipelined data packets, transmits encapsulated instruction frames and data frames within a time window, performs a reassembly operation and adds a verification signature, and outputs a complete data block and verification signature. The steps are as follows.

[0022] SPISwitch receives dual-channel pipelined data packets and separates command frame packets and data frame packets;

[0023] The SPI switch decodes the instruction frame packet according to the SPI protocol frame format and extracts the SPI instruction header fields according to the timestamp order.

[0024] Locate the start offset field and length field of the data frame packet to generate the original content of the data block;

[0025] Reassemble the SPI instruction header field and the original content of the data block into an initial complete data block;

[0026] Verify the hash digest of the initial complete data block, generate a verification signature, and append the verification signature to the end of the initial complete data block to generate the complete data block.

[0027] As a preferred embodiment of the remote batch programming method for an array server based on SPI topology addressing described in this invention, the SoC receives a complete data block and a verification signature, and performs a differentiated write operation for CRC verification, as follows:

[0028] The SoC receives the complete data block and verification signature via the SPI bus, and parses the header of the complete data block to obtain the target write address field and the difference data length field;

[0029] The complete data block is recalculated using the SHA-256 hash algorithm, and then a signature verification is performed.

[0030] When the signature verification is successful, the SPI Flash physical sector is located according to the target write address field, the sector area corresponding to the difference data length field is erased, and the content field of the complete data block is written to the sector.

[0031] After writing is complete, the written data content is read back from the position specified in the target write address field, and a CRC check is performed.

[0032] As a preferred embodiment of the remote batch programming method for array servers based on SPI topology addressing described in this invention, the steps for generating the verification result Boolean value and status frame are as follows:

[0033] Based on the fields that have successfully passed CRC verification, a status frame is constructed through field combination operations.

[0034] Based on the status frame, determine the Boolean value of the signature verification and CRC check results, and output the Boolean value of the check results and the status frame to the BMC.

[0035] As a preferred embodiment of the remote batch programming method for array servers based on SPI topology addressing described in this invention, the BMC collects all status frames and verification results to obtain programming results, and initiates a retry process for failed nodes, with the following steps:

[0036] BMC polls all SoC nodes via the SPI bus to obtain the verification result boolean value and status frame of all SoC nodes, iterates through and verifies the verification result boolean value of all nodes, and marks the nodes that are successfully verified as successfully programmed nodes.

[0037] For nodes that fail verification, extract the failure address field from the status frame, relocate the node, roll back to the pre-divided sector, and re-execute the differential data write.

[0038] As a preferred embodiment of the remote batch programming method for array servers based on SPI topology addressing described in this invention, the steps for synchronously recording node performance data and outputting programming reports are as follows:

[0039] Extract the SPI bus transmission timestamp field, record the image write duration and the number of retries for writing differential data for each node, and generate a node performance data record table;

[0040] Read the three-level SPI switch topology configuration file and update the node status field according to the marker of the successfully programmed node;

[0041] Combine the status frames of all nodes, the Boolean values ​​of the verification results, the updated node status fields, and the node performance data record table to generate a burning report text file.

[0042] The beneficial effects of this invention are as follows: By encapsulating data into dual-channel pipelines using multimodal rules, it achieves separate transmission and timing synchronization of instruction frames and data frames, optimizes data stream scheduling, and improves the efficiency of multi-node parallel programming. By performing CRC verification through differentiated write operations, it achieves dual protection of signature verification and write verification, ensuring data integrity and fault tolerance recovery, thus achieving a safe and reliable BIOS upgrade. Attached Figure Description

[0043] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the following description of the embodiments will be briefly introduced. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0044] Figure 1 This is a flowchart of a remote batch programming method for an array server based on SPI topology addressing.

[0045] Figure 2 A flowchart for BIOS image acquisition and incremental mapping table generation.

[0046] Figure 3 This is a flowchart for dual-channel pipelined data packet generation and verification.

[0047] Figure 4 The flowchart for differentiation. Detailed Implementation

[0048] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0049] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of the invention. Therefore, the invention is not limited to the specific embodiments disclosed below.

[0050] Secondly, the term "one embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. The phrase "in one embodiment" appearing in different places in this specification does not necessarily refer to the same embodiment, nor is it a single or selective embodiment that is mutually exclusive with other embodiments.

[0051] Reference Figures 1-4 This is one embodiment of the present invention, which provides a remote batch programming method for an array server based on SPI topology addressing, including the following steps:

[0052] S1 and BMC collect the new BIOS image file from the remote server, compare the binary differences of the old BIOS image, and generate an incremental mapping table.

[0053] BMC connects to the remote server via HTTPS protocol and downloads the new BIOS image file to the BMC's local cache.

[0054] Furthermore, BMC activates a TLS encrypted session using the remote server's URL address and digital certificate, and sends an HTTP request message to the remote server to obtain the new BIOS image file. The remote server responds and returns an HTTPS encrypted data stream. BMC uses the AES decryption algorithm in the OpenSSL library to decrypt the HTTPS encrypted data stream block by block and reassembles it into a new BIOS image file. Then, it allocates contiguous storage space in BMC's local cache and sequentially writes the new BIOS image file into it.

[0055] It should be noted that BMC refers to the independent embedded controller on the server motherboard used to perform hardware monitoring and management functions, coordinating remote BIOS image download, SPI bus communication and burning process; OpenSSL library refers to the open source SSL / TLS protocol toolkit, which provides cryptographic algorithms (such as AES), digital certificate management and secure communication interfaces.

[0056] Access the SPI Flash memory of each node in the current SoC array via the SPI bus and extract the old BIOS image file of the node;

[0057] Furthermore, the BMC uses the SPI bus and calls the dynamic chip select algorithm to traverse all SoC nodes. When the target SoC node is located, the BMC sends an SPI protocol read command frame (containing the start address and length parameters of the old BIOS image file) to the target SoC's SPIFlash memory. The SPIFlash memory returns a response frame containing the binary data of the old BIOS image. The BMC receives the response frame in blocks and reassembles it into a complete old BIOS image file in the buffer.

[0058] It should be noted that the SPI bus refers to a four-wire synchronous serial communication interface used to connect the BMC and the SoC array; the SoC array refers to a hardware cluster composed of multiple x86 architecture system-on-a-chip chips with integrated processor cores, memory controllers and peripheral interfaces, which serves as the carrier of BIOS firmware and forms a master-slave communication architecture with the BMC through the SPI bus.

[0059] BMC uses a byte-level comparison algorithm to compare the new BIOS image file with the old BIOS image file, identify the offset address and length of the different bytes, and generate an incremental mapping table by defining structured fields.

[0060] Furthermore, the BMC uses a byte-by-byte scanning algorithm to sequentially traverse every byte position of the new and old BIOS image files. It uses the memcmp function to compare the binary content of the two files bit by bit. When it detects differences in the binary content bytes of the two files, it records the offset address of the difference byte and the length of the continuous difference region. By concatenating fields, it combines the offset address, the length of the continuous difference region, and the difference byte to generate a complete incremental mapping table. The incremental mapping table is finally stored in a designated area of ​​the BMC memory.

[0061] It should be noted that the memcmp function is a C language library function used to compare the binary contents of two memory regions byte by byte, and is called directly through embedded firmware; the continuous difference region refers to the binary data segment in which the bytes that differ consecutively start from the first byte that differs.

[0062] S2 and BMC construct SPI instruction sequences based on incremental mapping tables, and encapsulate instruction frames and data frames in the SPI instruction sequences through multimodal rules to generate dual-channel pipeline data packets.

[0063] BMC reads the structured fields of the incremental mapping table and extracts the address parameters and binary data for each difference region;

[0064] Furthermore, BMC loads the incremental mapping table, reads the structured field records in the incremental mapping table one by one through the field parsing function, extracts the offset address field as the positioning identifier of the address parameter from each record, extracts the length field as the size identifier of the address parameter, and extracts the difference byte sequence field as binary data; uses the memcpy function to concatenate the positioning identifier and the size identifier into a complete address parameter, and uses the complete address parameter as the key and the corresponding binary data as the value to perform key-value pair mapping, forming a set of difference region data.

[0065] It should be noted that the memcpy function is a standard C language library function, whose core function is to copy binary data from one memory region to another memory region byte by byte.

[0066] Based on the address parameters and binary data of each different region, instruction frames and data frames are generated according to the SPI protocol conversion rules.

[0067] Furthermore, based on the complete address parameters and associated binary data of each difference region in the difference region data set, an operation command containing an opcode and address segment is generated as an instruction frame through the SPI protocol conversion rules, while the associated binary data is encapsulated into a data frame by byte alignment.

[0068] It should be noted that the SPI protocol conversion rules refer to the specifications for converting the complete address parameters and associated binary data of the different regions into instruction frames and data frames that conform to the SPI communication protocol. Through the embedded firmware settings of the BMC, the core rules include generating operation commands containing opcodes and address fields as instruction frames, and simultaneously encapsulating the associated binary data into data frames by byte alignment.

[0069] All instruction frames and data frames are encapsulated separately using multimodal rules, and packet sequence numbers and topology addressing headers are added to generate dual-channel pipelined data packets.

[0070] Furthermore, BMC adds high-priority timing identifiers to all instruction frames through multimodal rules, while also attaching a topology addressing header, and adds integrity check identifiers (such as CRC32 check codes) and incremental packet sequence number identifiers to all data frames; through a hardware buffer management mechanism, the encapsulated instruction frame stream and data frame stream are input into independent dual-channel transmission queues respectively; at the output of the independent dual-channel transmission queues, they are merged into dual-channel pipeline data packets carrying logical channel markers according to a preset frame interval.

[0071] It should be noted that multimodal rules refer to the encapsulation and synchronization specifications for handling multiple data streams (such as instruction frames and data frames) in SPI communication. These include dual-channel separation, timing synchronization, and integrity verification. This is achieved by defining dual-channel separation parameters (such as independent encapsulation of instruction channels and data channels), adding identifiers (such as timestamps, checksums, and packet sequence numbers), and configuring transmission queue parameters (such as buffer size and frame interval). The frame interval is set by configuring transmission queue parameters, with a preset fixed value and a dynamically calculated value during initialization. The value range is typically from 1μs to 50μs.

[0072] S3 and SPISwitch receive dual-channel pipelined data packets, transmit encapsulated instruction frames and data frames within a time window, perform reassembly operations and add verification signatures, and output complete data blocks and verification signatures.

[0073] The SPI switch receives dual-channel pipeline data packets and separates instruction frame packets and data frame packets using a preset fixed offset field.

[0074] Furthermore, after receiving the dual-channel pipeline data packet, the SPI Switch directly accesses a specific position of the data packet through a preset fixed offset field, extracts field information (such as type and length), and identifies the start position of the instruction frame packet and the start position of the data frame packet in the dual-channel pipeline data packet based on the specific position defined by the preset fixed offset field, thus separating the instruction frame packet and the data frame packet.

[0075] It should be noted that the SPI Switch is a hardware-level data routing and protocol conversion component used to extend the SPI bus topology between the BMC and the SoC array, enabling multi-node addressing and packet routing functions. The fixed offset field is based on the communication protocol specifications jointly followed by both communicating parties (such as the BMC and the SPI Switch). It is set by embedding the communication protocol specifications into the hardware logic or firmware of the SPI Switch, and its value range usually depends on the specific hardware and communication protocol format. The specific position refers to the absolute position in the binary data packet defined by the fixed offset address field in the communication protocol specification. For example, the starting position of the instruction frame packet is fixed at 0x0000, which is directly preset by the offset parameter embedded in the SPI Switch hardware logic.

[0076] It should be noted that the communication protocol specification is a set of data packet formats and communication rules defined on top of the basic SPI protocol to meet the requirements of high performance and high reliability (such as multi-node BIOS incremental updates, multi-SoC node arrays and high-speed pipelines).

[0077] The SPI switch decodes the instruction frame packet according to the SPI protocol frame format and extracts the SPI instruction header fields according to the timestamp order.

[0078] Furthermore, the SPISwitch parses the binary content of the instruction frame packet according to the SPI protocol frame format, extracts the SPI instruction header field composed of the opcode and address field. The SPI Switch reads the value of the timestamp field based on the high-priority timing identifier in the instruction frame packet and processes the instruction frame packet in the order of the timestamp field value to ensure that the SPI instruction header field is extracted in the order of the timestamp.

[0079] Locate the start offset field and length field of the data frame packet to generate the original content of the data block;

[0080] Furthermore, based on a specific position defined by a preset fixed offset field, the SPI Switch directly accesses the start offset field and length field of the data frame packet; according to the start offset field and length field, it extracts a continuous binary data stream from the storage area corresponding to the dual-channel pipeline data packet, and copies it to the buffer in byte order to generate the original content of the data block that perfectly matches the length field.

[0081] Reassemble the SPI instruction header field and the original content of the data block into an initial complete data block;

[0082] Furthermore, based on the SPI instruction header field and the original content of the data block, the address parameters in the SPI instruction header field are used to match and associate the corresponding original content of the data block. The specific steps include: extracting the opcode and address segment combination from the SPI instruction header field, using the address segment in the SPI instruction header field as a unique identifier to associate the corresponding original content of the data block in the difference region data set; allocating a contiguous memory buffer, copying the complete binary content of the SPI instruction header field to the beginning of the buffer using the memcpy function, and simultaneously copying the complete binary stream of the associated original content of the data block; and sequentially concatenating the binary content of the SPI instruction header field and the binary data stream of the original content of the data block to generate the initial complete data block.

[0083] The hash digest of the initial complete data block is verified using the SHA-256 hash algorithm, a verification signature is generated, and the verification signature is appended to the end of the initial complete data block to generate the complete data block.

[0084] Furthermore, the initial complete data block is loaded into the memory buffer and input into the SHA-256 hash algorithm. Based on the byte sequence in the initial complete data block, a fixed-length hash digest is generated block by block as a verification signature. The verification signature is copied and appended to the end of the initial complete data block through memory operations to generate a complete data block.

[0085] S4 and SoC receive the complete data block and verification signature, and perform a differentiated write operation to perform CRC verification, generating a Boolean value of the verification result and a status frame;

[0086] The SoC receives the complete data block and verifies the signature via the SPI bus. It parses the header of the complete data block according to the preset fixed offset field to obtain the target write address field and the difference data length field.

[0087] Furthermore, the SoC receives the complete data block and verification signature transmitted from the SPI Switch via the SPI bus, parses the SPI instruction header field by directly accessing the start position of the complete data block based on the fixed offset field preset in the communication protocol specification, and uses the SPI protocol decoding rules to extract the target write address field and the difference data length field from the address parameter of the SPI instruction header field.

[0088] It should be noted that the SPI protocol decoding rules refer to the logical specifications used to parse the header fields of the received SPI instructions to extract parameters such as the target write address and the length of the differential data. These rules are preset and fixed into the hardware logic of the SPISwitch through the communication protocol specifications.

[0089] The complete data block is recalculated using the SHA-256 hash algorithm, and then a signature verification is performed.

[0090] Furthermore, the complete data block is loaded into a memory buffer and input into the SHA-256 hash algorithm. Based on the byte sequence in the complete data block, a fixed-length hash digest is generated block by block as a new verification signature. By calling the standard memory comparison function, the newly generated hash digest is compared with the received verification signature. If each byte matches and there is no difference, the signature verification passes. If the bytes do not match and there is a difference, the signature verification fails, the complete data block is discarded, and an error code is returned to the BMC.

[0091] When the signature verification is successful, the SPI Flash physical sector is located according to the target write address field, and the sector area corresponding to the difference data length field is erased. The content field of the complete data block is written to the sector through SPI Flash programming.

[0092] Furthermore, when the signature verification is successful, the physical address space of the SPI Flash memory is accessed via the SPI protocol, and the target write address field is used as the starting point to map to the sector boundary. Based on the number of consecutive bytes specified by the difference data length field, the sector erase operation is performed using the SPI Flash standard erase command. The erase range extends from the target write address field to the end position defined by the difference data length field. After the erase is completed, the SoC calls the write function in the embedded firmware through the SPI Flash programming interface to write the content field of the complete data block to the erased sector area in byte order.

[0093] It should be noted that the end position is set based on the start position of the target write address field as a reference point. The number of consecutive bytes specified by the difference data length field is used to extend the termination boundary of the sector acquisition operation. The value range is usually the size of the data block, such as 256KB.

[0094] After writing is complete, the written data content is read back from the position specified in the target write address field, and a CRC check is performed.

[0095] Furthermore, after the write operation is completed, the SoC sends an instruction frame containing the SPI protocol read command to the SPI Flash memory via the SPI bus based on the target write address field. It reads the data length from the start point of the target write address field (including the specific difference byte sequence data of the number of bytes specified by the difference data length field starting from the start point of the target write address field), and reads back the written data content. By calling the standard CRC32 calculation function in the embedded firmware, it calculates the cyclic redundancy check code byte by byte on the read-back data content, compares the calculated cyclic redundancy check code with the pre-stored integrity identifier (the CRC32 check code added before the complete data block is written), and determines whether the verification result is successful. If each byte matches completely and there is no difference, the CRC verification is considered successful.

[0096] Based on the fields that have successfully passed CRC verification, a status frame is constructed through field combination operations.

[0097] Furthermore, based on the field that has been successfully checked by CRC, the SoC calls the field combination function in the embedded firmware through field combination operation, allocates contiguous memory space, and uses the field that has been successfully checked by CRC as a success identifier, the target write address field as a starting position reference, and the difference data length field as a data size reference to perform binary field concatenation operation, and finally generates a status frame.

[0098] It should be noted that the construction of the field combination function allocates a contiguous memory buffer by calling a dynamic memory allocation function (such as malloc) through the embedded firmware, defines the splicing logic in sequence, and uses a memory copy function (such as memcpy) to write byte by byte and fill the remaining space to ensure alignment.

[0099] Based on the status frame, the Boolean values ​​of the signature verification and CRC verification results are determined through dual conditional logic, and the Boolean values ​​of the verification results and the status frame are output to the BMC.

[0100] Furthermore, based on the status frame, the signature verification result (i.e., whether the hash digest recalculated by the SHA-256 hash algorithm matches the received verification signature byte by byte) and the CRC check result (i.e., whether the cyclic redundancy check code calculated by reading back the data matches the pre-stored integrity identifier byte by byte) are checked through dual conditional logic. If both signature verification and CRC check are successful, the verification result boolean value is true; otherwise, it is false. The verification result boolean value and the status frame are output to the BMC.

[0101] The S5 and BMC collect all status frames and verification results to obtain the burning results, initiate a retry process for failed nodes, synchronously record node performance data, and output a burning report.

[0102] BMC polls all SoC nodes via the SPI bus to obtain the verification result boolean value and status frame of all SoC nodes, iterates through and verifies the verification result boolean value of all nodes, and marks the nodes that are successfully verified as successfully programmed nodes.

[0103] Furthermore, the BMC uses the SPI bus and dynamic chip select algorithm to traverse each SoC node and obtain the verification result boolean value and status frame of all SoC nodes. The BMC receives the verification result boolean value and status frame returned by each SoC node in sequence, and traverses all nodes to verify the verification result boolean value. The BMC judges whether the verification result boolean value is true. When the boolean value is true, it means that both signature verification and CRC verification are successful. The BMC marks the SoC node that has been successfully verified as a successfully programmed node.

[0104] It should be noted that the dynamic chip select algorithm refers to an addressing mechanism used by the BMC to accurately locate and select the target SoC node in a multi-SoC node array. By dynamically adjusting the chip select signal on the SPI bus, addressing and communication between multiple SPI slave devices connected to the same SPI bus can be achieved.

[0105] For nodes that fail verification, extract the failure address field from the status frame, relocate the node using a dynamic chip select algorithm, roll back to the pre-divided sector, and re-execute the differential data writing.

[0106] Furthermore, for nodes that fail verification, the BMC extracts the failure address field from the status frame by calling the field parsing function in the embedded firmware; the BMC calls the dynamic chip select algorithm to relocate the target node; the failure address field is mapped to a pre-divided backup sector on the SPI Flash memory, the boundary of the pre-divided backup sector is located (the end position is set based on the starting point of the target write address field plus the number of consecutive bytes specified by the difference data length field), and the SPI Flash standard erase command is executed to clear the backup sector. The content field of the complete data block is rewritten to the backup sector in byte order through the SPI Flash programming interface; after writing, the data content is read back and the standard CRC32 calculation function in the embedded firmware is called for verification, a new status frame and a new verification result boolean value are generated, and the verification result boolean value is re-verified. Nodes that successfully verify are marked as successfully programmed nodes, and nodes that fail verification repeat the difference data writing step; the difference data writing loop continues until the verification result boolean value is true or the preset maximum fault tolerance retry threshold is reached.

[0107] It should be noted that field parsing functions refer to a set of utility functions in the BMC embedded firmware used to extract specific field values ​​from received data frames or status information. Field parsing functions typically read target fields by accessing preset fixed offset fields in the data structure. Backup sectors are statically preset during the design phase through partition tables and linker scripts based on the physical characteristics of SPI Flash and business fault tolerance requirements, and are then solidified into the BMC firmware and configuration files. The maximum fault tolerance retry threshold is set based on business fault tolerance requirements and hardware operation fault tolerance mechanisms, and is preset through the BMC firmware initialization configuration parameters. The value range is typically 1 to 5 times.

[0108] Extract the SPI bus transmission timestamp field, record the image write duration and the number of retries for writing differential data for each node, and generate a node performance data record table;

[0109] Furthermore, the SPI bus transmission timestamp field is extracted by accessing a specific position defined by a preset fixed offset field in the SPI bus transmission data packet; the time difference calculation function in the embedded firmware is used to calculate the time difference between the start timestamp field value of the differential data write operation and the end timestamp field value of the write operation, and the image write duration of each node is obtained; in the retry process, whenever a node needs to re-execute the differential data write operation, the number of retryes for the node is increased by the counter function in the embedded firmware; a contiguous memory buffer is allocated by calling the dynamic memory allocation function in the embedded firmware, and the memory copy function is used to concatenate and combine the SPI bus transmission timestamp field, the node image write duration, and the number of retryes for differential data writes for each node in the order of the fields to generate a node performance data record table.

[0110] Read the three-level SPI switch topology configuration file and update the node status field according to the marker of the successfully programmed node;

[0111] Furthermore, the predefined SoC node and SPISwitch mapping rules in the three-level SPI Switch topology configuration file are read. Based on the SPI Switch mapping rules and the markers of successfully programmed nodes, the target SoC node is located in the hierarchical position of the three-level topology through a dynamic chip select algorithm, and the node status field is rewritten as a success identifier.

[0112] It should be noted that the predefined SoC nodes are logical mappings of physical hardware connections, corresponding one-to-one with the SoC nodes to be programmed. The predefinition process involves solidifying a three-level SPI Switch topology configuration file. SPI Switch mapping rules refer to the predefined logical specifications in the array server hardware architecture, including hierarchical addressing rules (number of extended sub-links of the first-level switch), port allocation rules (number of SoCs managed by the second-level switch), and logical operation rules. The logical specifications are based on the physical connection relationships and expansion requirements in the array server hardware architecture, and are set by solidifying the hierarchical addressing rules, port allocation rules, and logical operation rules in the three-level SPI Switch topology configuration file.

[0113] Combine the status frames of all nodes, the Boolean values ​​of the verification results, the updated node status fields, and the node performance data record table to generate a burning report text file.

[0114] Furthermore, based on the status frames, verification result boolean values, and node performance data record tables of all SoC nodes, BMC allocates a contiguous memory buffer by calling a file generation function through the embedded firmware. It then uses a memory copy function to concatenate the status frames, verification result boolean values, updated node status fields, SPI bus transmission timestamp fields, node image write duration, and number of retries for differential data writes in the node performance data record table according to the field order, and generates a programming report text file.

[0115] This embodiment also provides a computer device applicable to the remote batch programming method for an array server based on SPI topology addressing, comprising: a memory and a processor; the memory is used to store computer-executable instructions, and the processor is used to execute the computer-executable instructions to implement the remote batch programming method for an array server based on SPI topology addressing as proposed in the above embodiment.

[0116] The computer device can be a terminal, comprising a processor, memory, communication interface, display screen, and input devices connected via a system bus. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The communication interface is used for wired or wireless communication with external terminals; wireless communication can be achieved through Wi-Fi, carrier networks, NFC (Near Field Communication), or other technologies. The display screen can be an LCD screen or an e-ink screen. The input devices can be a touch layer covering the display screen, buttons, a trackball, or a touchpad on the computer device's casing, or an external keyboard, touchpad, or mouse.

[0117] This embodiment also provides a storage medium storing a computer program. When executed by a processor, the program implements the remote batch programming method for an array server based on SPI topology addressing as proposed in the above embodiments. The storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as Static Random Access Memory (SRAM), Electrically Erasable Programmable Read-Only Memory (EEPROM), Erasable Programmable Read Only Memory (EPROM), Programmable Red-Only Memory (PROM), Read-Only Memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk.

[0118] In summary, this invention achieves separate transmission and timing synchronization of instruction frames and data frames by encapsulating data into dual-channel pipelined data packets using multimodal rules, optimizing data stream scheduling, and improving the efficiency of multi-node parallel programming. Furthermore, by performing CRC checks through differentiated write operations, it provides dual protection through signature verification and write verification, ensuring data integrity and fault tolerance recovery, thus achieving a safe and reliable BIOS upgrade.

[0119] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A method for remote bulk programming of an array server based on SPI topology addressing, characterized in that: Comprising, The BMC collects a new version of BIOS image file from a remote server, compares the binary difference of the old version of BIOS image, and generates an incremental mapping table; The BMC constructs an SPI instruction sequence based on the incremental mapping table, encapsulates the instruction frames and data frames in the SPI instruction sequence through multi-modal rules, and generates a dual-channel pipeline data packet; The SPI Switch receives the dual-channel pipeline data packet, transmits the encapsulated instruction frames and data frames within a time window, performs a recombination operation and adds a verification signature, and outputs a complete data block and the verification signature; The SoC receives the complete data block and the verification signature, and performs a differential write operation for CRC check, generates a check result and a status frame; The BMC collects all status frames and check results to obtain a burning result, starts a retry process for a failed node, synchronously records node performance data, and outputs a burning report.

2. The method of claim 1, wherein the SPI topology-based addressing array server remote bulk burn-in method is characterized by: The BMC collects a new version of BIOS image file from a remote server, which means that the BMC connects to the remote server through the HTTPS protocol, downloads the new version of BIOS image file to the local cache area of the BMC. 3.The method of claim 2, wherein: The steps of comparing the binary difference of the old version of BIOS image and generating the incremental mapping table are as follows, Access the SPI Flash memory of each node in the current SoC array through the SPI bus, and extract the old version of BIOS image file of the node; Compare the new version of BIOS image file with the old version of BIOS image file, identify the offset address and length of the difference bytes, and generate an incremental mapping table by defining a structured field.

4. The method of claim 3, wherein the SPI topology-based addressing array server remote bulk burn-in method further comprises: The steps of the BMC constructing an SPI instruction sequence based on the incremental mapping table and encapsulating the instruction frames and data frames in the SPI instruction sequence through multi-modal rules are as follows, The BMC reads the structured field of the incremental mapping table, and extracts the address parameters and binary data of each difference area; Based on the address parameters and binary data of each difference area, generate instruction frames and data frames through SPI protocol conversion rules.

5. The method of claim 4, wherein the SPI topology-based addressing array server remote bulk burn-in method further comprises: The generation of a dual-channel pipeline data packet means that all instruction frames and data frames are encapsulated, a packet number and a topology addressing header are added, and a dual-channel pipeline data packet is generated.

6. The method of claim 5, wherein the SPI topology-based addressing array server remote bulk burn-in method further comprises: The steps of the SPI Switch receiving the dual-channel pipeline data packet, transmitting the encapsulated instruction frames and data frames within a time window, performing a recombination operation and adding a verification signature, and outputting a complete data block and the verification signature are as follows, The SPI Switch receives the dual-channel pipeline data packet, and separates the instruction frame packet and the data frame packet; The SPI Switch decodes the instruction frame packet according to the SPI protocol frame format, and extracts the SPI instruction header field according to the timestamp order; Locate the start offset field and the length field of the data frame packet, and generate the data block original content; Recombine the SPI instruction header field and the data block original content into an initial complete data block; Verify the hash digest of the initial complete data block, generate a verification signature, and attach the verification signature to the tail of the initial complete data block to generate a complete data block.

7. The method of claim 6, wherein the SPI topology-based addressing array server remote bulk burn-in method further comprises: The steps of the SoC receiving the complete data block and the verification signature, and performing a differential write operation for CRC check are as follows, The SoC receives the complete data block and verifies the signature through the SPI bus, parses the header of the complete data block to obtain the target write address field and the difference data length field; The complete data block is recalculated through the SHA-256 hash algorithm, and signature verification is performed; When the signature verification is passed, the SPI Flash physical sector is located according to the target write address field, the sector area corresponding to the difference data length field is erased, and the content field of the complete data block is written into the sector; After the writing is completed, the written data content is read from the position specified by the target write address field, and CRC check is performed.

8. The remote batch programming method for an array server based on SPI topology addressing as described in claim 7, characterized in that: The generation of the check result Boolean value and the state frame is as follows, Based on the CRC check success field, the state frame is constructed through field combination operation; Based on the state frame, the check result Boolean value of the signature verification and the CRC check is determined, and the check result Boolean value and the state frame are output to the BMC.

9. The remote batch programming method for an array server based on SPI topology addressing as described in claim 8, characterized in that: The BMC collects all state frames and check results to obtain the burning result, and starts a retry process for the failed node, and the steps are as follows, The BMC obtains the check result Boolean value and the state frame of all SoC nodes through the SPI bus, iterates through the check result Boolean value of all nodes, and marks the nodes that pass the verification as burning success nodes; For the nodes that fail the verification, the failure address field in the state frame is extracted, the node is repositioned, and the difference data writing is re-executed in the pre-divided sector.

10. The method of claim 9, wherein the SPI topology-based addressing array server remote bulk burn-in method further comprises: The node performance data is recorded synchronously, and the burning report is output, and the steps are as follows, The SPI bus transmission timestamp field is extracted, the image writing time length and the retry number of difference data writing of each node are recorded, and the node performance data record table is generated; The three-level SPI switch topology configuration file is read, and the node state field is updated according to the mark of the burning success node; The state frame, the check result Boolean value, the updated node state field and the node performance data record table of all nodes are combined to generate a burning report text file.

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