Method and device for allocating multiple emission instruction queues and electronic equipment

Abstract

The invention provides a multi-transmission instruction queue allocation method and device and electronic equipment, and the method comprises the steps: setting a shielding frequency, and shielding a target instruction to be allocated to a first type of transmission queues according to the shielding frequency under the condition that the target instruction to be allocated is a second type of instruction which can be allocated to the first type of transmission queues and the second type of transmission queues; according to the method and the device, a part of clock cycles in each time unit are in an'open state ', and a part of clock cycles are in a'shielding state' and an'open state ', so that a second type of instructions can be allocated to a first type of transmitting queues, functional units corresponding to the first type of transmitting queues are fully utilized, and the execution performance of a CPU (Central Processing Unit) is improved; in addition, vacancies allowed to be distributed can be reserved for the first type of instructions which can only be distributed to the first type of transmitting queues, so that the first type of instructions are prevented from blocking instruction streams to affect CPU performance.

Description

Technical Field

[0001] This application relates to the field of CPU architecture technology, and in particular to a method, apparatus and electronic device for allocating multiple issue instruction queues. Background Technology

[0002] In modern multi-issue CPUs, the instruction issue queue is a key microarchitectural component responsible for caching decoded instructions and scheduling them to functional units. In a distributed instruction issue queue (DIQ) CPU design, each functional unit has its own independent instruction issue queue. The CPU uses a specific allocation strategy to assign instructions executable within a particular functional unit to its corresponding instruction issue queue. Once the instructions meet the execution conditions, they are issued into the functional unit for execution. High-performance processors typically contain multiple functional units, such as the ALU and LSU. Some of these functional units exist independently, while others can exist in multiples. For example, with multiple ALUs, ALU instructions can be executed in any ALU unit. Meanwhile, some instructions can only be executed in a single functional unit. These instructions are less frequent and have variable execution times. During the idle period of these special instructions, their corresponding functional units may allow other instructions to execute in certain situations to improve performance. For example, the system instruction execution unit can also execute other simple ALU instructions. Therefore, when allocating instructions to the instruction issue queue, special instructions from a single functional unit can only be allocated to the instruction issue queue of that specific functional unit, while other ordinary instructions can be allocated to multiple instruction issue queues. Figure 1 The diagram illustrates the above allocation principle, depicting a scenario where the instruction issuance queue of a special function unit can be assigned both special instructions and ordinary instructions.

[0003] Furthermore, for multi-issue CPUs, multi-issue execution exists within the instruction issue queue and execution units. To ensure the correctness of instruction execution results, the CPU should allocate instructions according to their order of execution during the instruction allocation phase. When an instruction cannot be allocated into the instruction issue queue, it will block the allocation of subsequent instructions, affecting the overall performance of the CPU.

[0004] Currently, instruction dispatch queue allocation strategies are mostly Round Robin and real-time monitoring strategies. For ordinary instructions that can be executed in multiple functional units, the Round Robin round arbitration strategy is adopted, as shown in the example below. Figure 2 As shown, instructions are cyclically sent to the allocable instruction queue, achieving a preliminary even distribution.

[0005] However, instructions in the instruction issuance sequence must wait until they meet their execution conditions before being selected and issued to a functional unit. Different instructions require different waiting times; therefore, a simple Round Robin allocation strategy will result in a queue that is sometimes empty and sometimes full due to the varying waiting times. To address this issue, the current allocation strategy combines real-time monitoring with Round Robin. This strategy is as follows: Figure 3 As shown in the diagram. This strategy monitors the empty / full status of the instruction issuance queue in real time while performing Round Robin allocation. When an instruction issuance queue is found to be full, instruction allocation to it will be stopped.

[0006] However, the aforementioned allocation strategy combining real-time monitoring and Round Robin does not consider the need for instruction issuance queues for certain special instructions that can only be executed in a single functional unit. In programs where such special instructions coexist with other ordinary instructions, the ordinary instructions are evenly distributed according to the real-time monitoring and Round Robin allocation strategy, allowing a certain instruction issuance queue to be filled first. If the instruction issuance queue that is filled happens to be the one that the special instruction can only be allocated to, then the special instruction will be unable to be allocated, resulting in instruction flow blockage. When this scenario occurs within a loop, the special instruction in each loop will block the instruction flow, impacting CPU performance. Summary of the Invention

[0007] This specification provides a method, apparatus, and electronic device for allocating multiple issue instruction queues to improve CPU execution performance while avoiding instruction stream blocking.

[0008] To address the aforementioned technical problems, this specification provides a method for allocating multiple transmission command queues, the multiple transmission command queues including a first type of transmission queue and a second type of transmission queue; the method includes: determining the type of target command to be allocated; the type of target command to be allocated includes a first type of command and a second type of command, wherein the first type of command can only be allocated to the first type of transmission queue, and the second type of command can be allocated to both the first type of transmission queue and the second type of transmission queue; if the target command is a second type of command, the target command is blocked according to the shielding frequency and allocated to the first type of transmission queue.

[0009] In some embodiments, the method further includes: if the target instruction is a first type of instruction, assigning the target instruction to the first type of launch queue.

[0010] In some embodiments, the shielding frequency is a fixed frequency.

[0011] In some embodiments, the shielding frequency is dynamically adjusted according to the type variation characteristics of each instruction to be assigned.

[0012] In some embodiments, a first counter is used to count the number of first-type instructions, a second counter is used to count the total number of first-type instructions and second-type instructions, a divider is used to calculate the ratio of the two values ​​to obtain the proportion of the number of first-type instructions, and a frequency selector is used to determine the shielding frequency based on the proportion of the number of first-type instructions.

[0013] In some embodiments, the method further includes: obtaining the program counter (PC) value corresponding to the target instruction; comparing whether the program counter (PC) value corresponding to the current target instruction is the same as the program counter (PC) value corresponding to the previous branch instruction; if they are the same, counting the total number of first-type instructions and second-type instructions, and the number of first-type instructions; calculating the ratio of the number of first-type instructions to the total number; and dynamically adjusting the masking frequency according to the ratio.

[0014] In some embodiments, the method further includes: increasing the shielding frequency during loop execution; and / or decreasing the shielding frequency after loop execution ends.

[0015] In some embodiments, the method further includes: cyclically allocating each first type of instruction to be allocated in each first type of launch queue; and cyclically allocating each second type of instruction to be allocated in each first type of launch queue and each second type of launch queue.

[0016] In some embodiments, the method further includes: real-time monitoring of the empty / full status of each launch queue in the first type of launch queue and the second type of launch queue; if a launch queue is detected to be full, then controlling the cessation of allocating instructions to the launch queue.

[0017] A second aspect of this specification provides a multi-transmission command queue allocation device, the multi-transmission command queue including a first type of transmission queue and a second type of transmission queue; the device includes: a determining unit, configured to determine the type of a target command to be allocated; the type of the target command to be allocated includes a first type of command and a second type of command, wherein the first type of command can only be allocated to the first type of transmission queue, and the second type of command can be allocated to both the first type of transmission queue and the second type of transmission queue; and a shielding unit, configured to shield the target command from being allocated to the first type of transmission queue according to a shielding frequency when the target command is a second type of command.

[0018] In some embodiments, the apparatus further includes: a first allocation unit, configured to allocate the target instruction to the first type of launch queue when the target instruction is a first type of instruction.

[0019] In some embodiments, the shielding frequency is a fixed frequency.

[0020] In some embodiments, the shielding frequency is dynamically adjusted according to the type variation characteristics of each instruction to be assigned.

[0021] In some embodiments, a first counter is used to count the number of first-type instructions, a second counter is used to count the total number of first-type instructions and second-type instructions, a divider is used to calculate the ratio of the two values ​​to obtain the proportion of the number of first-type instructions, and a frequency selector is used to determine the shielding frequency based on the proportion of the number of first-type instructions.

[0022] In some embodiments, the apparatus further includes: an acquisition unit, configured to acquire the program counter (PC) value corresponding to the target instruction; a comparison unit, configured to compare whether the program counter (PC) value corresponding to the current target instruction is the same as the program counter (PC) value corresponding to the previous branch instruction; a statistics unit, configured to, under the same conditions, count the total number of first-type instructions and second-type instructions, and the number of first-type instructions; a calculation unit, configured to calculate the ratio of the number of first-type instructions to the total number; and a first adjustment unit, configured to dynamically adjust the shielding frequency according to the ratio.

[0023] In some embodiments, the apparatus further includes: a second adjustment unit for increasing the shielding frequency during loop execution; and / or decreasing the shielding frequency after loop execution ends.

[0024] In some embodiments, the apparatus further includes: a second allocation unit, configured to cyclically allocate each first type of instruction to be allocated in each first type of launch queue; and a third allocation unit, configured to cyclically allocate each second type of instruction to be allocated in each first type of launch queue and each second type of launch queue.

[0025] In some embodiments, the apparatus further includes: a monitoring unit for real-time monitoring of the empty / full status of each launch queue in the first type of launch queue and the second type of launch queue; and a control / stop unit for controlling the cessation of allocating commands to the launch queue if a launch queue is detected to be full.

[0026] A third aspect of this specification provides an electronic device, comprising: a memory and a processor, wherein the processor and the memory are communicatively connected to each other, the memory stores computer instructions, and the processor executes the computer instructions to implement the multi-issue instruction queue allocation method of any one aspect.

[0027] A fourth aspect of this specification provides a computer storage medium storing computer program instructions, which, when executed, implement the steps of the multi-issue instruction queue allocation method described in any of the first aspects.

[0028] This specification provides a computer program product in a fifth aspect, comprising a computer program that, when executed by a processor, implements the steps of the multi-issue instruction queue allocation method described in any of the first aspects.

[0029] The multi-issue instruction queue allocation method, apparatus, and electronic device provided in this specification, by setting a masking frequency, and when the target instruction to be allocated is a second type instruction that can be allocated to both the first and second type issue queues, the target instruction is masked according to the masking frequency and allocated to the first type issue queue. This ensures that within each time unit, some clock cycles are in an "open state" and some clock cycles are in a "masked state" and "open state". This allows the second type of instructions to be allocated to the first type issue queue, thereby fully utilizing the functional units corresponding to the first type issue queue and improving CPU execution performance. At the same time, it also reserves empty slots for the first type of instructions that can only be allocated to the first type issue queue, thereby preventing the first type of instructions from blocking the instruction flow and affecting CPU performance. Attached Figure Description

[0030] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0031] Figure 1 A schematic diagram illustrating the basic principles of allocating multiple-issue command queues; Figure 2 A schematic diagram of the Round Robin strategy for allocating multiple issue command queues; Figure 3 A schematic diagram of the Round Robin strategy and real-time monitoring strategy for allocating multiple launch command queues; Figure 4 A flowchart illustrating a multi-issue command queue allocation method provided in this specification; Figure 5 A schematic diagram of the hardware structure for calculating the percentage of the number of Class I instructions; Figure 6 A schematic diagram of the hardware structure used to compare whether the program counter (PC) values ​​corresponding to two target instructions are the same; Figure 7 This is a schematic diagram showing the correspondence between the values ​​of the register used to store the ratio and the masking frequency register; Figure 8 A schematic diagram illustrating a mapping relationship between shielding frequency and 64-bit shielding period; Figure 9 A schematic diagram of a hardware implementation method for selecting the shielding period based on the shielding frequency; Figure 10 This specification provides a structural block diagram of a multi-issue command queue allocation device; Figure 11 This is a schematic diagram of the electronic device provided in this specification. Detailed Implementation

[0032] To enable those skilled in the art to better understand the technical solutions in this application, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this application.

[0033] In the CPU instruction execution flow, the issue mechanism is the core link connecting "instruction preparation" and "instruction execution." It is responsible for rationally allocating "decoded and ready instructions" to the corresponding execution units (such as ALU, FPU, LSU, etc.) and determining the timing and parallelism of instruction execution. Essentially, it coordinates the matching relationship between instructions and hardware resources to ensure that the CPU's execution units work efficiently and orderly, and is a key technology for realizing "instruction-level parallelism (ILP)."

[0034] The issuance mechanism includes a Global Centralized Issue Queue (referred to as "Global Queue") and a Distributed Issue Queue.

[0035] In a globally centralized launch queue, all decoded instructions awaiting execution enter a unique, shared queue. A global scheduler is responsible for storing instructions, determining their readiness, and allocating execution units. The globally centralized launch queue offers advantages such as simple hardware implementation, high global resource utilization, and ease of global optimization for out-of-order execution. However, it also suffers from drawbacks such as the scheduler becoming a performance bottleneck, queue capacity limitations leading to congestion, and intense resource contention. This globally centralized launch queue is well-suited for scenarios with a small number of execution units and low instruction throughput requirements.

[0036] The distributed instruction dispatch queue breaks down the traditional "global centralized dispatch queue" into "discretion queues dedicated to each functional unit", thereby supporting the parallel operation of multifunctional units more efficiently. In the case of a distributed instruction dispatch queue, after the instruction is decoded, the hardware will identify the operation type (such as "add" belongs to integer operation, "ld" belongs to memory access) and send it to the dispatch queue of the corresponding functional unit through the allocation strategy; the instruction entering the functional unit's dedicated queue will wait in the queue for two core conditions: (1) the operand is ready (such as the result of the dependent preceding instruction has been generated); (2) the functional unit is currently idle (i.e., it is not executing other instructions); when the conditions are met, the functional unit will directly "take" the instruction from its own queue and execute it, without the need for coordination through the global scheduler.

[0037] Each queue in the distributed instruction issue queue processes only specific types of instructions (e.g., the integer queue only cares about ALU-related instructions), simplifying the scheduling logic and resulting in faster response, thereby reducing scheduling complexity. Different types of instructions wait in their respective queues, avoiding competition between integer instructions and memory access instructions for the same set of queue resources, thus reducing resource contention. When the CPU has multiple functional units of the same type (e.g., 4 ALUs), each ALU's dedicated queue can be independently scheduled in parallel, maximizing parallel execution efficiency, thus adapting to the parallel operation of multifunctional units.

[0038] Existing technologies employ distributed instruction issuance queues as a means of issuance, such as... Figure 3 As shown in the background section, the existing issuance mechanism does not take into account the requirement of the instruction issuance queue for certain special instructions that can only be executed in a separate functional unit. This can easily lead to the inability to allocate special instructions, thereby causing blockage of the instruction flow.

[0039] To improve CPU execution performance while avoiding instruction stream blocking, this specification provides a method for allocating multi-issue instruction queues. These multi-issue instruction queues can be divided into two categories: a first-type issue queue and a second-type issue queue, each corresponding to a different type of functional unit. For example... Figure 4 As shown, the method includes the following steps S10 and S20.

[0040] S10: Determine the type of target instruction to be assigned; the types of target instructions to be assigned are first type instruction and second type instruction. The first type instruction can only be assigned to the first type of launch queue in the first type of launch queue and the second type of launch queue. The second type instruction can be assigned to both the first type of launch queue and the second type of launch queue.

[0041] In a distributed instruction issue queue, each functional unit has an independent and parallel issue queue, allowing each functional unit to execute instructions in parallel.

[0042] It's important to note that the issue queue in a CPU architecture is implemented in hardware, specifically consisting of two parts: a memory unit and control logic. The memory unit is typically implemented using flip-flops or SRAM and is used to temporarily store critical instruction information (such as opcodes, source / destination physical registers, target execution unit ID, etc.). The control logic is typically implemented using combinational logic circuits (such as AND gates, OR gates, multiplexers, etc.).

[0043] The issue queue is not an independent component; it needs to interact with multiple hardware modules in real time. These interactions must be implemented through hardware circuits (data paths, control signals), and cannot be directly manipulated by software. For example, it interacts with the "Register Renaming Unit" to obtain the physical register number of the instruction and determine whether the source operand is ready; it interacts with the "Function Execution Unit" to query the execution unit status (idle / busy) and send instructions and operands; and it interacts with the "Reorder Buffer (ROB)" to synchronize the instruction issue status and ensure subsequent "in-order commits".

[0044] The purpose of implementing a launch queue in hardware within a computer includes three aspects: 1. In terms of speed requirements, matching the response time of the CPU clock cycle (typically in the nanosecond (ns) or even picosecond (ps) range); 2. In terms of hardware coupling, directly interacting with other hardware modules within the CPU; 3. Real-time handling of uncertainties, achieving dynamic adaptive scheduling. Specifically, the readiness time of instructions is dynamically changing (e.g., the execution delay of preceding instructions may vary due to data conflicts or cache hits), and cannot be statically planned in software (e.g., compilers can only perform static scheduling and cannot predict runtime resource conflicts). The hardware logic of the launch queue (such as a "dependency checker" or "resource arbiter") can check the readiness conditions of multiple instructions in parallel each clock cycle, and launch them immediately once the conditions are met, achieving "dynamic adaptive scheduling".

[0045] Common functional units in CPU architecture include: Arithmetic Logic Unit (ALU), Floating-Point Unit (FPU), Load / Store Unit (LSU), Branch Unit, Multipliers and Dividers, Vector Operation Unit, etc. In a distributed multi-issue architecture, these functional units each have their own dedicated issue queue.

[0046] Instructions in a CPU architecture can be divided into two categories: ordinary instructions (also known as user-mode instructions) and system instructions (also known as privileged instructions). Ordinary instructions run in user mode (non-privileged mode) and can only access the user address space and limited resources (such as general-purpose registers), such as simple addition, loading data, and function calls. System instructions run in kernel mode (privileged mode) and are used to manage system resources (such as memory, I / O, and interrupts), such as modifying page tables, performing division system calls, and configuring the interrupt controller.

[0047] If a functional unit A is responsible for operations that exist in both user mode and kernel mode, then functional unit A can process both ordinary instructions and system instructions. When there are fewer system instructions and more ordinary instructions, functional unit A can also process ordinary instructions during the intervals between processing system instructions.

[0048] The first type of instructions in this application includes system instructions that can run in parallel with ordinary instructions, such as instructions for reading and writing system registers and exception handling instructions; the second type of instructions includes ordinary instructions that can run in parallel, such as addition and subtraction instructions, logical operation instructions, and shift operation instructions.

[0049] The first type of launch queue includes launch queues corresponding to functional units that execute system instructions, while the second type of launch queue includes launch queues corresponding to functional units that execute ordinary instructions.

[0050] Type I instructions can only be assigned to Type I launch queues and Type II launch queues. Type II instructions can be assigned to both Type I and Type II launch queues; that is, Type II instructions can be assigned to either Type I or Type II launch queues.

[0051] The CPU internally determines the type of the target instruction to be allocated through an "instruction fetch-decode" process, combining the instruction's opcode and auxiliary fields. Based on the program counter (PC) value, the CPU fetches the next instruction to be executed from memory and stores it in the instruction register (IR), thus determining the content of the instruction to be analyzed. During the decoding stage, the opcode field in the instruction is parsed. The opcode is a unique identifier of the instruction type, and the CPU identifies the opcode through a hardware decoder (logic circuitry) to determine the instruction type. For more complex instruction sets or microarchitectures (such as some RISC-V and x86 architectures), in addition to the opcode, auxiliary fields (such as funct7, funct3, and address code structure) are used to further refine the instruction type. The specific methods for determining the instruction type already exist in existing technology and will not be detailed in this specification.

[0052] S20: If the target instruction is a second type of instruction, the target instruction is blocked and assigned to the first type of transmission queue according to the blocking frequency.

[0053] "Blocking the allocation of the target instruction to the first type of transmission queue according to the shielding frequency" essentially selectively restricts the allocation of the second type of instruction to the first type of transmission queue. Specifically, this can be achieved by making the ratio of the number of clock cycles that allow the second type of instruction to be allocated to the first type of transmission queue to the total number of clock cycles within a time unit equal to the shielding frequency, and then dividing the clock cycles into multiple units, one of which is a time unit. Each clock cycle within a time unit is either in an "open state" or a "shielded state." An "open state" means that the second type of instruction can be allocated to the first type of transmission queue, while a "shielded state" means that the second type of instruction cannot be allocated to the first type of transmission queue.

[0054] The aforementioned multi-issue instruction queue allocation method sets a masking frequency and, when the target instruction to be allocated is a second-type instruction that can be allocated to both the first and second-type issue queues, masks the target instruction according to the masking frequency and allocates it to the first-type issue queue. This ensures that within each time unit, some clock cycles are in an "open state," while others are in a "masked state" and an "open state." This allows second-type instructions to be allocated to the first-type issue queue, thus fully utilizing the functional units corresponding to the first-type issue queue and improving CPU execution performance. At the same time, it also reserves available slots for first-type instructions that can only be allocated to the first-type issue queue, thereby preventing first-type instructions from blocking the instruction flow and affecting CPU performance.

[0055] Following S10 above, if the target instruction is a first-type instruction, the target instruction can be assigned to the first-type launch queue.

[0056] S20 above specifies that when a first-type transmission queue and a second-type transmission queue exist, first-type instructions can only be assigned to the first transmission queue. However, it does not restrict the possibility of first-type instructions being assigned to other transmission queues. In some cases, first-type instructions may be assigned to a third transmission queue, which is a different transmission queue from the first and second transmission queues. In this case, after S10, if the target instruction is a first-type instruction, it can be assigned to either the first-type transmission queue or the third transmission queue.

[0057] The "disabling of the target instruction according to the shielding frequency and allocation to the first type of transmission queue" is implemented using hardware including digital circuitry.

[0058] In some embodiments, the shielding frequency is a fixed frequency.

[0059] In other embodiments, the shielding frequency is dynamically adjusted; more specifically, the shielding frequency is dynamically adjusted according to the changing characteristics of the types of instructions to be assigned.

[0060] "Type change characteristics of each instruction to be assigned" can be the quantity value change characteristics of the first type of instruction, or the quantity percentage change characteristics of the first type of instruction. Quantity value change characteristics could include, for example, whether the quantity of the first type of instruction exceeds a preset quantity value, or the magnitude of the quantity change; quantity percentage change characteristics could include, for example, whether the quantity percentage exceeds a preset percentage, or the magnitude of the quantity percentage change.

[0061] The type variation characteristics of the aforementioned instructions to be allocated are implemented in hardware. Taking the proportion of the first instruction as an example, the type variation characteristics of the instructions to be allocated can be implemented as follows: Figure 5 The hardware implementation shown uses a first counter to count the number of first-type instructions, a second counter to count the total number of first-type and second-type instructions, and a divider to calculate the ratio of the two values ​​to obtain the proportion of first-type instructions.

[0062] The CPU has a mask cycle register used to configure and record the timing parameters of the instruction masking policy. Its main function is to store thresholds, counts, or control information related to the "instruction mask cycle," providing hardware support for dynamically adjusting the masking frequency of the instruction issue queue. This mask cycle register is programmable, and its value can be dynamically modified during the allocation of various instructions to dynamically adjust the masking frequency.

[0063] Among the various instructions executed by the CPU, instructions within loops (such as loop counter updates, conditional checks, and arithmetic operations) are executed repeatedly (iterated), accounting for over 50% of the instruction stream. Due to the significantly increased proportion of loop instructions, the proportion of system instructions during loop execution decreases significantly. This leads to the issue queue corresponding to functional unit B, which executes system instructions, being more likely to be allocated to loop instructions, resulting in insufficient allocation of system instructions to functional unit B.

[0064] In view of the fact that the proportion of instructions in the loop body increases significantly during loop execution, which can easily lead to the inability to allocate system instructions, this specification proposes to increase the above-mentioned masking frequency during loop body execution to ensure that sufficient space is reserved for system instructions during loop body execution, thereby preventing instruction flow blockage.

[0065] Specifically, the shielding frequency can be dynamically adjusted using the following steps S30 to S70.

[0066] S30: Get the PC value of the program counter corresponding to the target instruction.

[0067] The program counter (PC) is a special-purpose register inside the CPU. Its core function is to store the address in memory of the next instruction to be executed. The PC value is the address value stored in this special-purpose register.

[0068] S40: Compare the program counter PC value corresponding to the current target instruction with the program counter PC value corresponding to the previous branch instruction.

[0069] Branch instructions are instructions used in a program to change the execution order. They determine which piece of code to execute next based on specific conditions (such as the value of a variable, comparison results, etc.), rather than simply executing sequentially. If the program counter (PC) values ​​corresponding to two branch instructions are the same, it means that one instruction has been executed repeatedly. This situation usually occurs in loop bodies. Therefore, we can determine whether the loop body is currently being executed by checking whether the PC values ​​corresponding to two consecutively executed branch instructions are the same. Figure 6 This is a schematic diagram of the hardware structure used to compare whether the program counter (PC) values ​​corresponding to two target instructions are the same.

[0070] If the program counter (PC) values ​​corresponding to multiple consecutive branch instructions are the same, and the program counter (PC) value corresponding to one branch instruction is different from the program counter (PC) value corresponding to the previous branch instruction, then it can be determined that a loop body has been completed.

[0071] S50: Under the same conditions, count the total number of Class I instructions and Class II instructions, and the number of Class I instructions.

[0072] S60: Calculate the ratio of the number of first-class instructions to the total number.

[0073] like Figure 5 As shown, S60 can be executed using a first counter, a second counter, and a divider.

[0074] S70: Dynamically adjust the shielding frequency according to the ratio.

[0075] Dynamically adjusting the shielding frequency can involve increasing the shielding frequency during the execution of the loop body and decreasing the shielding frequency after the loop body has finished executing.

[0076] In some embodiments, the frequency selector can be configured to select the shielding frequency value based on the aforementioned ratio. A shielding frequency selection method is provided below.

[0077] Assuming the masking frequency register supports 8 types of masking frequencies, represented by one-hot codes, if the calculated ratio is 8'b0100_1000, then keeping the most significant bit as 1 will yield the one-hot code 8'b0100_0000. Figure 7This diagram illustrates the correspondence between the values ​​of the register used to store the ratio and the masking frequency register.

[0078] After obtaining the shielding frequency, it is necessary to determine the specific shielding period based on the frequency, that is, how many clock cycles the shielding is performed once. Figure 8 This diagram illustrates a mapping between masking frequencies and 64-bit masking periods. The masking period register is a 64-bit hardware register divided into multiple fields. Each field pre-stores candidate masking periods (i.e., 1, 3, 7, 15, 31, 63, 127, 255 in the diagram). These values ​​are predefined masking period parameters, indicating either "masking occurs every X periods" or "masking lasts for X periods." Each bit in the 8-bit one-hot code representing the masking frequency corresponds to a candidate value in the masking period register. Figure 8 The shielding frequency corresponds to a shielding period of 3. (Through...) Figure 8 The mapping relationship between the shielding frequency and the shielding period shown allows the operating system or hardware logic to flexibly and quickly select the shielding period by setting the one-hot code of the shielding frequency.

[0079] Figure 7 , Figure 8 The shielding period selection method shown can be implemented in various circuit structures. For example, it can be achieved through... Figure 9 The circuit structure shown is implemented Figure 7 , Figure 8 The shielding cycle selection method is shown.

[0080] In some embodiments, Figure 4 The multi-issue command queue allocation method shown can be used in conjunction with the Round Robin allocation strategy. That is, the multi-issue command queue allocation method provided in this specification can also include: cyclically allocating each first-type command to be allocated in each first-type issue queue; and cyclically allocating each second-type command to be allocated in each first-type issue queue and each second-type issue queue.

[0081] In some embodiments, Figure 4 The multi-transmission command queue allocation method shown can be used simultaneously with the real-time monitoring strategy in the prior art. That is to say, the multi-transmission command queue allocation method provided in this specification can also include: real-time monitoring of the empty / full status of each transmission queue in the first type of transmission queue and the second type of transmission queue; if a transmission queue is detected, then stop allocating commands to the transmission queue.

[0082] This specification provides a multi-issue command queue allocation device, which can be used to implement the above-described multi-issue command queue allocation method. For example... Figure 10 As shown, the device includes a determining unit 10 and a shielding unit 20.

[0083] The determining unit 10 is used to determine the type of the target instruction to be assigned; the types of the target instruction to be assigned are a first type instruction and a second type instruction, wherein the first type instruction can only be assigned to the first type of the first type of the first type of the launch queue and the second type of the launch queue, and the second type instruction can be assigned to both the first type of the launch queue and the second type of the launch queue.

[0084] The shielding unit 20 is used to shield the target instruction from being assigned to the first type of transmission queue according to the shielding frequency when the target instruction is a second type of instruction.

[0085] In some embodiments, the apparatus further includes: a first allocation unit, configured to allocate the target instruction to the first type of launch queue when the target instruction is a first type of instruction; In some embodiments, the shielding frequency is a fixed frequency.

[0086] In some embodiments, the shielding frequency is dynamically adjusted according to the type variation characteristics of each instruction to be assigned.

[0087] In some embodiments, a first counter is used to count the number of first-type instructions, a second counter is used to count the total number of first-type instructions and second-type instructions, a divider is used to calculate the ratio of the two values ​​to obtain the proportion of the number of first-type instructions, and a frequency selector is used to determine the shielding frequency based on the proportion of the number of first-type instructions.

[0088] In some embodiments, the apparatus further includes an acquisition unit, a comparison unit, a statistics unit, a calculation unit, and a first adjustment unit.

[0089] The acquisition unit is used to acquire the PC value of the program counter corresponding to the target instruction.

[0090] The comparison unit is used to compare whether the program counter PC value corresponding to the current target instruction is the same as the program counter PC value corresponding to the previous branch instruction.

[0091] The statistics unit is used to count the total number of Class I instructions and Class II instructions, and the number of Class I instructions, under the same conditions.

[0092] The calculation unit is used to calculate the ratio of the number of first-type instructions to the total number.

[0093] The first adjustment unit is used to dynamically adjust the shielding frequency according to the ratio.

[0094] In some embodiments, the apparatus further includes: a second adjustment unit for increasing the shielding frequency during loop execution; and / or decreasing the shielding frequency after loop execution ends.

[0095] In some embodiments, the apparatus further includes a second allocation unit and a third allocation unit.

[0096] The second allocation unit is used to cyclically allocate each of the first type of instructions to be allocated in each of the first type of launch queues.

[0097] The third allocation unit is used to cyclically allocate each second-type instruction to be allocated in each first-type launch queue and each second-type launch queue.

[0098] In some embodiments, the device further includes a monitoring unit and a stop control unit.

[0099] The monitoring unit is used to monitor the empty / full status of each launch queue in the first and second type of launch queues in real time.

[0100] The control and stop unit is used to control and stop the allocation of instructions to a launch queue if it detects that the launch queue is full.

[0101] The descriptions and functions of the above devices can be understood by referring to the section on multi-issue command queue allocation methods, and will not be repeated here.

[0102] This invention also provides an electronic device, such as... Figure 11 As shown, the electronic device may include a processor 1101 and a memory 1102, wherein the processor 1101 and the memory 1102 may be connected via a bus or other means. Figure 11 Taking the example of a connection between China and Israel via a bus.

[0103] Processor 1101 may be a central processing unit (CPU). Processor 1101 may also be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or combinations thereof.

[0104] Memory 1102, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs, non-transitory computer-executable programs, and modules, such as program instructions / modules corresponding to the multi-issue instruction queue allocation method in this embodiment of the invention (e.g., Figure 10(See the determining unit 10 and the shielding unit 20 shown). The processor 1101 executes various functional applications and data processing by running non-transitory software programs, instructions, and modules stored in the memory 1102, thereby implementing the multi-issue instruction queue allocation method in the above method embodiment.

[0105] The memory 1102 may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function; the data storage area may store data created by the processor 1101, etc. Furthermore, the memory 1102 may include high-speed random access memory and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some embodiments, the memory 1102 may optionally include memory remotely located relative to the processor 1101, and these remote memories may be connected to the processor 1101 via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0106] The one or more modules are stored in the memory 1102, and when executed by the processor 1101, the above-described multi-issue instruction queue allocation method is performed.

[0107] The specific details of the above-mentioned electronic device can be understood by referring to the relevant descriptions and effects in the method embodiments, and will not be repeated here.

[0108] This specification also provides a computer storage medium storing computer program instructions, which, when executed, implement the steps of the above-described multi-issue instruction queue allocation method.

[0109] This specification also provides a computer program product comprising a computer program that, when executed by a processor, implements the steps of the above-described multi-issue instruction queue allocation method.

[0110] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), random access memory (RAM), flash memory, hard disk drive (HDD), or solid-state drive (SSD), etc.; the storage medium can also include combinations of the above types of memory.

[0111] The various embodiments in this specification are described in a progressive manner. For the same or similar parts between the various embodiments, please refer to each other. The focus of each embodiment is to describe the differences from other embodiments.

[0112] The systems, devices, modules, or units described in the above embodiments can be implemented by computer chips or entities, or by products with certain functions.

[0113] For ease of description, the above devices are described separately by function as various units. Of course, in implementing this application, the functions of each unit can be implemented in one or more software and / or hardware.

[0114] As can be seen from the above description of the embodiments, those skilled in the art can clearly understand that this application can be implemented by means of software plus necessary general-purpose hardware platforms. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute certain parts of the methods of various embodiments of this application.

[0115] This application can be used in a wide variety of general-purpose or special-purpose computer system environments or configurations. For example: personal computers, server computers, handheld or portable devices, tablet devices, multiprocessor systems, microprocessor-based systems, set-top boxes, programmable consumer electronics devices, network PCs, minicomputers, mainframe computers, distributed computing environments including any of the above systems or devices, etc.

[0116] This application can be described in the general context of computer-executable instructions, such as program modules, that are executed by a computer. Generally, program modules include routines, programs, objects, components, data structures, etc., that perform a specific task or implement a specific abstract data type. This application can also be practiced in distributed computing environments where tasks are performed by remote processing devices connected via a communication network. In distributed computing environments, program modules can reside in local and remote computer storage media, including storage devices.

[0117] Although this application has been described through embodiments, those skilled in the art will know that this application has many modifications and variations without departing from the spirit of this application, and it is intended that the appended claims cover such modifications and variations without departing from the spirit of this application.

Claims

1. A method for allocating multiple issue command queues, characterized in that, The multiple transmission instruction queue comprises a first type of transmission queue and a second type of transmission queue; the method comprises: determining the type of a target instruction to be allocated; the type of the target instruction to be allocated comprises a first type of instruction and a second type of instruction, wherein the first type of instruction can only be allocated to the first type of transmission queue in the first type of transmission queue and the second type of transmission queue, and the second type of instruction can be allocated to the first type of transmission queue and the second type of transmission queue; in the case that the target instruction is the second type of instruction, shielding the target instruction from being allocated to the first type of transmission queue according to a shielding frequency.

2. The method of claim 1, wherein, The method further comprises: in the case that the target instruction is the first type of instruction, allocating the target instruction to the first type of transmission queue.

3. The method of claim 1, wherein, The shielding frequency is a fixed frequency.

4. The method of claim 1, wherein, The shielding frequency is dynamically adjusted according to the type variation characteristics of each instruction to be allocated.

5. The method of claim 1, wherein, a first counter is used to count the number of the first type of instruction, a second counter is used to count the total number of the first type of instruction and the second type of instruction, and a divider is used to calculate the ratio of the two values to obtain the proportion of the number of the first type of instruction; a frequency selector is used to determine the shielding frequency according to the proportion of the number of the first type of instruction.

6. The method of claim 1, wherein, The method further comprises: obtaining the PC value of the program counter corresponding to the target instruction; comparing whether the program counter PC value corresponding to the current target instruction is the same as the program counter PC value corresponding to the last branch instruction; in the case of being the same, counting the total number of the first type of instruction and the second type of instruction, and the number of the first type of instruction; calculating the ratio of the number of the first type of instruction to the total number; dynamically adjusting the shielding frequency according to the ratio.

7. The method of claim 1, wherein, The method further comprises: increasing the shielding frequency during the execution of the loop body; and / or, after the execution of the loop body is completed, decreasing the shielding frequency.

8. The method of claim 1, wherein, The method further comprises: cyclically allocating each first type of instruction to be allocated in each first type of transmission queue; cyclically allocating each second type of instruction to be allocated in each first type of transmission queue and each second type of transmission queue.

9. The method of claim 1, wherein, The method further comprises: real-time monitoring the empty / full status of each transmission queue in the first type of transmission queue and the second type of transmission queue; if it is monitored that one transmission queue is full, controlling to stop allocating instructions to the transmission queue.

10. A multiple transmit instruction queue allocation apparatus, characterized by comprising: The multiple transmission instruction queue comprises a first type of transmission queue and a second type of transmission queue; the device comprises: a determination unit configured to determine the type of a target instruction to be allocated; the type of the target instruction to be allocated comprises a first type of instruction and a second type of instruction, wherein the first type of instruction can only be allocated to the first type of transmission queue in the first type of transmission queue and the second type of transmission queue, and the second type of instruction can be allocated to the first type of transmission queue and the second type of transmission queue; a shielding unit configured to shield the target instruction from being allocated to the first type of transmission queue according to a shielding frequency in the case that the target instruction is the second type of instruction.

11. An electronic device, comprising: comprise: a memory and a processor, which are communicatively connected, the memory stores computer instructions, and the processor executes the computer instructions to implement the method for allocating a multiple transmission instruction queue according to any one of claims 1 to 9.

12. A computer storage medium, characterized in that The computer storage medium stores computer program instructions, which, when executed, implement the steps of the multi-issue instruction queue allocation method of any one of claims 1 to 9.

13. A computer program product, characterised in that, The computer program is executed by a processor to implement the steps of the multi-issue instruction queue allocation method of any one of claims 1 to 9.

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