Single-gpio-based load driving and state detection circuit, method and electronic device

Abstract

The present application relates to the technical field of electronic circuit, specifically relates to load driving and state detection circuit, method and electronic equipment based on single GPIO, including coordination circuit, comparison circuit, at least one output drive circuit and at least one input detection circuit;The output end of coordination circuit is connected with the input end of comparison circuit, the output end of comparison circuit is connected with the input end of at least one output drive circuit, and the output end of output drive circuit is used to connect load;The input end of at least one input detection circuit is used to connect the object to be detected, and the output end is connected with the input end of coordination circuit;The mode of GPIO mouth connected with coordination circuit is configured by software, to control the output state of coordination circuit, and then through the cooperation of comparison circuit and output drive circuit, the closed loop or associated control function of input state detection and output drive control is completed by the same GPIO mouth, and the present application saves pin resources, reduces hardware cost and size.

Description

Technical Field

[0001] This invention relates to the field of electronic circuit technology, and more specifically to load driving and status detection circuits, methods and electronic devices based on a single GPIO. Background Technology

[0002] In existing microcontroller (MCU) or system-on-a-chip (SoC) designs, load driving and status detection typically require independent GPIO resources: one GPIO pin is configured as an output to drive the load, while another independent GPIO pin is configured as an input to detect the load's loop status, current, or voltage signals, thereby determining whether it is working properly, connected, or has failed. This approach has significant drawbacks in applications with limited pin resources or requiring high integration, increasing hardware design complexity, package size, and overall cost. Furthermore, load status detection often uses MCU active polling, which not only consumes processor resources but also makes it difficult to achieve real-time fault response.

[0003] To conserve pin resources, some existing GPIO multiplexing schemes exist. For example, by configuring the GPIO direction register, the same pin can be dynamically switched between input and output modes, i.e., "time-division multiplexing." However, such schemes are essentially just "sequential switching" of pin functions, not "cooperative control": they cannot monitor the status simultaneously during the output phase, nor can they provide drive during the input phase, failing to form a closed loop of "synchronous or tightly coupled drive and detection." More importantly, they lack hardware-level automatic decision-making and protection mechanisms; status identification and fault response still rely entirely on software timing and algorithms, failing to fundamentally solve the problems of resource consumption and real-time performance.

[0004] In addition, there are some solutions that use complex analog switches or multiplexers to switch signal paths, but these introduce additional control pins and chips, which defeats the purpose of saving resources.

[0005] Therefore, there is an urgent need for a circuit solution that can simultaneously achieve load driving and status detection through a single GPIO port, saving pin resources and reducing hardware cost and size. Summary of the Invention

[0006] The purpose of this invention is to overcome the shortcomings of the prior art and provide a load driving and status detection circuit, method and electronic device based on a single GPIO.

[0007] To achieve the above objectives / to solve the above technical problems, the present invention is implemented using the following technical solution:

[0008] In a first aspect, the present invention provides a load driving and status detection circuit based on a single GPIO, including a coordination circuit, a comparison circuit, at least one output driving circuit and at least one input detection circuit.

[0009] The output terminal of the coordination circuit is connected to the input terminal of the comparator circuit, the output terminal of the comparator circuit is connected to the input terminal of the at least one output driving circuit, and the output terminal of the output driving circuit is used to connect to the load.

[0010] The input terminal of the at least one input detection circuit is used to connect to the object being detected, and its output terminal is connected to the input terminal of the coordination circuit.

[0011] The GPIO port is connected to the coordination circuit and can be configured by software to be a floating input or a pull-down input mode to control the output state of the coordination circuit. Then, through the cooperation of the comparison circuit and the output drive circuit, the closed-loop or associated control function of input state detection and output drive control can be realized by the same GPIO port.

[0012] In conjunction with the first aspect, optionally, the output terminal of the output driving circuit is connected to one end of a load, and the other end of the load is connected to the input terminal of the input detection circuit, forming a driving and detection closed-loop circuit for the same load.

[0013] In conjunction with the first aspect, optionally, the input terminal of the input detection circuit is connected to a sensor, and the output terminal of the output drive circuit is connected to a load; the state of the sensor is detected by the input detection circuit, and the load is driven by the comparison circuit and the output drive circuit accordingly.

[0014] In conjunction with the first aspect, optionally, multiple input detection circuits and corresponding multiple input interfaces are included for simultaneously or time-divisionally detecting the state of multiple detected objects and feeding back the state information to the coordination circuit.

[0015] In conjunction with the first aspect, optionally, multiple output drive circuits and corresponding multiple output interfaces are included for simultaneously or time-sharing multiple loads.

[0016] In conjunction with the first aspect, optionally, the output terminal of the comparator circuit is simultaneously connected to the input terminals of all output drive circuits to centrally control the synchronous drive of multiple loads.

[0017] In conjunction with the first aspect, optionally, it includes multiple comparator circuits, and multiple output driver circuits and output interfaces respectively connected to the output terminal of each comparator circuit; the input terminal of each comparator circuit is connected to a coordination circuit, and the output terminal of each comparator circuit independently controls a corresponding output driver circuit, so as to realize independent or combined drive control of different loads.

[0018] Secondly, the present invention provides a load driving and status detection method based on a single GPIO, applied to the load driving and status detection circuit based on a single GPIO as described in the first aspect, the method comprising the following steps:

[0019] The GPIO port is initially configured as a floating input mode, and the state of the object being detected is determined by the input detection circuit.

[0020] Based on the test results, the GPIO port is reconfigured to pull-down input mode. The output drive circuit is changed by coordinating the circuit and the comparator circuit to achieve drive control of the load.

[0021] During load operation, the status is continuously or periodically monitored by the input detection circuit. If an abnormality is detected, the GPIO port is configured back to floating input mode and the drive is stopped.

[0022] Thirdly, the present invention provides an electronic device, including a microcontroller or a system-on-a-chip, characterized in that it employs a load driving and status detection circuit based on a single GPIO as described in any one of the first aspects, for realizing the driving and status monitoring of an external load.

[0023] Compared with the prior art, the beneficial effects achieved by the present invention are as follows:

[0024] This invention, through a closed-loop or associated design of a coordination circuit, a comparator circuit, an output drive circuit, and an input detection circuit, requires only a single GPIO pin to simultaneously complete the load drive control and status monitoring functions. This greatly alleviates the design pressure in situations where pin resources are scarce, creating conditions for product function expansion and high-density integration. At the same time, this invention reduces the need for external GPIO expansion chips and additional signal conditioning circuits, significantly reducing the bill of materials cost. The simplified circuit layout also reduces the printed circuit board area, which is conducive to the miniaturization and weight reduction of the device. In addition, unlike software polling or simple pin direction switching, this invention forms a fast response link of "detection-decision-drive-protection" through hardware circuitry. Status changes are directly reflected at the input of the comparator through the input detection circuit and the coordination circuit, and the comparator output drives the load or executes protection. The response speed is determined by the hardware circuitry, realizing real-time protection and control.

[0025] This invention forms a hardware closed loop for the same load, enabling not only driving but also real-time monitoring of load access, operating status, and anomalies. Upon detecting an anomaly, the circuit automatically cuts off the drive, providing a built-in, rapid hardware protection mechanism. When the input detection object is separated from the output load, load driving can depend on external conditions, achieving contactless, event-based intelligent control and expanding application scenarios. By integrating multiple input detection circuits, "AND" hardware logic can be implemented, enhancing the rigor and security of system control. This logic, implemented in hardware, offers rapid and reliable response. The architecture of this invention can be easily extended to drive multiple loads, meeting the multi-channel control needs of complex devices. Centralized control of multiple drive circuits through a single comparator output ensures strict synchronous start and stop of multiple loads, suitable for systems requiring coordinated action. By configuring multiple comparators and corresponding resistor networks, combined with dynamic sequence adjustment of GPIO modes, multiple loads can be driven in a time-sharing, independent, or specific order / priority manner using a single GPIO port. This enables complex multi-channel control strategies, such as sequential power-on and operating mode switching, with minimal pin resources, resulting in high control flexibility and system intelligence. Attached Figure Description

[0026] Figure 1 This is a circuit block diagram of the present invention;

[0027] Figure 2 This is a circuit diagram of Embodiment 2 of the present invention;

[0028] Figure 3 This is a circuit diagram of Embodiment 3 of the present invention;

[0029] Figure 4 This is a circuit diagram of Embodiment 4 of the present invention;

[0030] Figure 5 This is a circuit diagram of Embodiment 5 of the present invention;

[0031] Figure 6 This is a circuit diagram of Embodiment Six of the present invention. Detailed Implementation

[0032] The technical solution of the present invention will be described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the embodiments and specific features in the embodiments are detailed descriptions of the technical solution of the present application, rather than limitations thereof. In the absence of conflict, the embodiments and technical features in the embodiments can be combined with each other.

[0033] In the description of this invention, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0034] In this article, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0035] Example 1:

[0036] like Figure 1 As shown, the present invention provides a load driving and status detection circuit based on a single GPIO, including a coordination circuit, a comparison circuit, at least one output driving circuit and at least one input detection circuit;

[0037] The output of the coordination circuit is connected to the input of the comparator circuit, the output of the comparator circuit is connected to the input of at least one output driver circuit, and the output of the output driver circuit is used to connect to the load.

[0038] At least one input detection circuit has an input terminal for connecting to the object being detected, and its output terminal is connected to the input terminal of the coordination circuit.

[0039] The GPIO port is connected to the coordination circuit and can be configured as a floating input or pull-down input mode via software to control the output state of the coordination circuit. Then, through the cooperation of the comparator circuit and the output drive circuit, the closed-loop or associated control function of input state detection and output drive control can be realized by the same GPIO port.

[0040] Example 2:

[0041] Based on Embodiment 1, a load driving and status detection circuit based on a single GPIO is provided for application scenarios where the load connected to the output driving circuit and the object being detected connected to the input detection circuit are the same object. Specifically, the output terminal of the output driving circuit is connected to one end of a load, and the other end of the load is connected to the input terminal of the input detection circuit, forming a driving and detection closed-loop circuit for the same load.

[0042] like Figure 2As shown, in one embodiment, it includes a coordination circuit, a comparison circuit, an output driving circuit, and an input detection circuit;

[0043] The comparison circuit includes comparator U2A. The positive terminal of comparator U2A is connected to a 5V power supply, and the positive terminal of comparator U2A is grounded through capacitor C1. The negative terminal of comparator U2A is also grounded.

[0044] The output drive circuit includes transistor Q3, optocoupler U1, and MOSFET Q2. The base of transistor Q3 is connected to one end of resistor R7, and the other end of resistor R7 is connected to the output of comparator U2A. Resistor R9 is connected between the base and emitter of transistor Q3. The emitter of transistor Q3 is grounded. The collector of transistor Q3 is connected to pin 2 of optocoupler U1. Pin 1 of optocoupler U1 is connected to a 5V power supply after being connected to resistor R3. Pin 4 of optocoupler U1 is connected to a VDD power supply after being connected to resistor R4. Pin 3 of optocoupler U1 is connected to the gate of MOSFET Q2 after being connected to resistor R6. Resistor R8 is connected between the gate and source of MOSFET Q2. The source of MOSFET Q2 is connected to the power supply ground after being connected to fuse F1. The drain of MOSFET Q2 is connected to one end of the load, and the other end of the load is connected to the VDD power supply.

[0045] The input detection circuit includes optocoupler U3. Pin 1 of optocoupler U3 is connected to the drain of MOSFET Q2. Pin 2 of optocoupler U3 is connected to power ground via resistor R15. Pin 3 of optocoupler U3 is grounded. Pin 4 of optocoupler U3 is connected to 3.3V power supply via resistor R13. Pin 4 of optocoupler U3 is also connected to one end of resistor R14.

[0046] The coordination circuit includes transistors Q1 and Q4. The bases of both transistors Q1 and Q4 are connected to the other end of resistor R14. The emitters of both transistors Q1 and Q4 are connected to a 3.3V power supply. The emitter of transistor Q1 is connected to ground via resistors R2 and R5, and the collector of transistor Q1 is connected to ground via resistors R1 and R5. The collector of transistor Q1 is also connected to the positive input terminal of comparator U2A via resistor R1. The emitter of transistor Q4 is connected to ground via resistors R11 and R12, and the collector of transistor Q4 is connected to ground via resistors R10 and R12. The collector of transistor Q4 is also connected to the negative input terminal of comparator U2A and the GPIO port via resistor R10.

[0047] In some embodiments, the resistance and capacitance values ​​are selected according to actual needs such as load size, which will not be elaborated on here.

[0048] Combination Figure 2The circuit operation process of this embodiment two is as follows: Initially, the GPIO port is set to floating input mode. Upon power-up, no load is connected. At this time, optocoupler U3 is not conducting, the base clamps of transistors Q1 and Q4 are at a high level of 3.3V, and transistors Q1 and Q4 are in the off state. Pin 3 of comparator U2A is at a low level, and this potential is determined by the voltage division between resistors R1 and R5 and ground. Pin 2 of comparator U2A is at a low level, and this potential is determined by the voltage division between resistors R10 and R12 and ground. In some specific embodiments, the voltage level after voltage division must be less than 0.8V, and the voltage division by resistor R12 must be greater than that by resistor R5. Therefore, the voltage at pin 2 is greater than the voltage at pin 3, so pin 1 outputs at this time. When the voltage is low, the output drive circuit is not working. When a load is connected, VDD is connected to ground through the load, pins 1 and 2 of optocoupler U3, and resistor R15, forming a small current detection loop. In some embodiments, the value of resistor R15 can be designed according to the load to measure the current and keep it within 5~10mA. When optocoupler U3 is turned on, the voltage at pin 4 is pulled low to near 0V. This low level acts on the bases of transistors Q1 and Q4 through resistor R14. At this time, transistors Q1 and Q4 become turned on, thereby pulling the collector potential of transistors Q1 and Q4 high to near the emitter voltage of 3.3V. This causes both the positive and negative inputs of comparator U2A to become high, i.e., pins 2 and 3 become high. Therefore, the high / low level change of pin 2 can be used to determine whether a load is connected or whether it is used as a pure input detection port. However, at this time, the voltage of pin 2 of comparator U2A is still greater than that of pin 3, so pin 1 still outputs a low level, and the output drive circuit does not work. When it is determined that a load is connected, the GPIO port is configured as a pull-down input mode. At this time, there is a pull-down resistor inside the GPIO port to ground. This internal pull-down forcefully pulls the potential of pin 2 of comparator U2A down to close to 0V. Although transistor Q4 still tries to pull the potential of pin 2 of comparator U2A high due to the conduction of optocoupler U3, the strength of the internal pull-down is much greater than the pull-up effect of R10 and R12. Therefore, the potential of pin 2 of comparator U2A is clamped at a low level. At this time, the voltage of pin 3 of comparator U2A is greater than that of pin 2. When the voltage at pin 1 is high, the output drive circuit operates, turning on MOSFET Q2. The main load circuit then runs from VDD power supply – load – drain of MOSFET Q2 – source of MOSFET Q2 – fuse F1 – ground. The load is powered on and begins to operate. Although the GPIO port is still configured as an input, it can perform an output function after passing through the comparator. If an abnormality occurs during load operation, such as a disconnection of the load circuit, pin 2 of comparator U2A becomes high, indicating an abnormality in the downstream load. When the downstream load malfunctions, the GPIO port is reconfigured to floating input mode, restoring the voltage at pin 2 of comparator U2A to be greater than that at pin 3. Pin 1 outputs a low level, the output drive circuit stops operating, and load protection takes effect.

[0049] In one illustrative embodiment, the high and low level ranges of pins 2 and 3 of comparator U2A are divided by the 3.3V TTL level range boundary.

[0050] Example 3:

[0051] Based on Embodiment 1, a load driving and status detection circuit based on a single GPIO is provided for application scenarios where the load connected to the output driving circuit and the detected object connected to the input detection circuit are different objects. Specifically, the input terminal of the input detection circuit is connected to a sensor, and the output terminal of the output driving circuit is connected to the load. The state of the sensor is detected by the input detection circuit, and the load driving is controlled by the comparison circuit and the output driving circuit accordingly.

[0052] like Figure 3 As shown, it includes a coordination circuit, a comparison circuit, an output drive circuit, and an input detection circuit;

[0053] The comparison circuit includes comparator U2A. The positive terminal of comparator U2A is connected to a 5V power supply, and the positive terminal of comparator U2A is grounded through capacitor C1. The negative terminal of comparator U2A is also grounded.

[0054] The output drive circuit includes transistor Q3, optocoupler U1, and MOSFET Q2. The base of transistor Q3 is connected to one end of resistor R7, and the other end of resistor R7 is connected to the output of comparator U2A. Resistor R9 is connected between the base and emitter of transistor Q3. The emitter of transistor Q3 is grounded. The collector of transistor Q3 is connected to pin 2 of optocoupler U1. Pin 1 of optocoupler U1 is connected to a 5V power supply via resistor R3. Pin 4 of optocoupler U1 is connected to a VDD power supply via resistor R4. Pin 3 of optocoupler U1 is connected to the gate of MOSFET Q2 via resistor R6. Resistor R8 is connected between the gate and source of MOSFET Q2. The source of MOSFET Q2 is connected to the power supply ground via fuse F1. The drain of MOSFET Q2 is connected to one end of the output interface, and the other end of the output interface is connected to the VDD power supply. The output interface is used to connect the load.

[0055] The input detection circuit includes an optocoupler U3. Pin 1 of the optocoupler U3 is connected to one end of the input interface, and the other end of the input interface is connected to the VDD power supply. The input interface is used to connect the sensor. Pin 2 of the optocoupler U3 is connected to the power supply ground after connecting to resistor R15. Pin 3 of the optocoupler U3 is grounded. Pin 4 of the optocoupler U3 is connected to the 3.3V power supply after connecting to resistor R13. Pin 4 of the optocoupler U3 is also connected to one end of resistor R14.

[0056] The coordination circuit includes transistors Q1 and Q4. The bases of both transistors Q1 and Q4 are connected to the other end of resistor R14. The emitters of both transistors Q1 and Q4 are connected to a 3.3V power supply. The emitter of transistor Q1 is connected to ground via resistors R2 and R5, and the collector of transistor Q1 is connected to ground via resistors R1 and R5. The collector of transistor Q1 is also connected to the positive input terminal of comparator U2A via resistor R1. The emitter of transistor Q4 is connected to ground via resistors R11 and R12, and the collector of transistor Q4 is connected to ground via resistors R10 and R12. The collector of transistor Q4 is also connected to the negative input terminal of comparator U2A and the GPIO port via resistor R10.

[0057] Combination Figure 3 The working process of this embodiment three is as follows: In the initial stage, the GPIO is configured as a floating input. When the object being detected connected to the input interface is not connected or has no valid signal, its loop is closed, and the input detection optocoupler U3 is not conducting. The subsequent process is exactly the same as the "initial state" in embodiment two, and the output drive circuit does not work, which will not be elaborated here. When the object being detected is connected or generates a valid signal, the input detection loop is turned on, the optocoupler U3 is turned on, and the MCU reads a high level through the GPIO port, judging that the "trigger condition" is met. Subsequently, the MCU configures the GPIO to pull-down input mode. The subsequent logic is completely consistent with the "load drive state" in embodiment two, and finally the load connected to the output interface is powered on and works, which will not be elaborated here. As long as the input detection loop remains on, the output load will continue to work. If the input detection loop is disconnected due to the object being detected being disconnected or a fault, the optocoupler U3 is cut off, and the circuit state will be similar to the "abnormal protection state" in embodiment two, causing the output drive to be turned off. This means that the operation of the output load depends entirely on the state of the input detection object, realizing condition control.

[0058] Example 4:

[0059] Based on Embodiment 3, a load driving and status detection circuit based on a single GPIO is provided for application scenarios where the load connected to the output driving circuit and the detected object connected to the input detection circuit are different objects. It has multiple input detection circuits and one output driving circuit. Specifically, it includes multiple input detection circuits and corresponding multiple input interfaces for simultaneously or time-divisionally detecting the status of multiple detected objects and feeding back the status information to the coordination circuit. The other parts are the same as in Embodiment 3, and will not be described in detail here.

[0060] like Figure 4 As shown, it includes a coordination circuit, a comparison circuit, an output drive circuit, and two input detection circuits;

[0061] The comparison circuit includes comparator U2A. The positive terminal of comparator U2A is connected to a 5V power supply, and the positive terminal of comparator U2A is grounded through capacitor C1. The negative terminal of comparator U2A is also grounded.

[0062] The output drive circuit includes transistor Q4, optocoupler U1, and MOSFET Q3. The base of transistor Q4 is connected to one end of resistor R8, and the other end of resistor R8 is connected to the output of comparator U2A. Resistor R10 is connected between the base and emitter of transistor Q4. The emitter of transistor Q4 is grounded. The collector of transistor Q4 is connected to pin 2 of optocoupler U1. Pin 1 of optocoupler U1 is connected to a 5V power supply via resistor R4. Pin 4 of optocoupler U1 is connected to a VDD power supply via resistor R5. Pin 3 of optocoupler U1 is connected to the gate of MOSFET Q3 via resistor R7. Resistor R9 is connected between the gate and source of MOSFET Q3. The source of MOSFET Q3 is connected to the power supply ground via fuse F1. The drain of MOSFET Q3 is connected to one end of the output interface, and the other end of the output interface is connected to the VDD power supply. The output interface is used to connect the load.

[0063] The input detection circuit includes a first input detection circuit and a second input detection circuit. The first input detection circuit includes an optocoupler U3. Pin 1 of optocoupler U3 is connected to one end of the first input interface, and the other end of the first input interface is connected to VDD power. Pin 2 of optocoupler U3 is connected to power ground via resistor R17. Pin 3 of optocoupler U3 is grounded. Pin 4 of optocoupler U3 is connected to 3.3V power via resistor R15. Pin 4 of optocoupler U3 is also connected to one end of resistor R16. The second input detection circuit includes an optocoupler U4. Pin 1 of optocoupler U4 is connected to one end of the second input interface, and the other end of the second input interface is connected to VDD power. Pin 2 of optocoupler U4 is connected to power ground via resistor R20. Pin 3 of optocoupler U4 is grounded. Pin 4 of optocoupler U4 is connected to 3.3V power via resistor R18. Pin 4 of optocoupler U4 is also connected to one end of resistor R19. The first and second input interfaces are used to connect loads or sensors.

[0064] The coordination circuit includes transistors Q1, Q5, Q2, and Q6. The bases of transistors Q1 and Q5 are connected to the other end of resistor R19, and the bases of transistors Q2 and Q6 are connected to the other end of resistor R16. The emitters of transistors Q1, Q5, Q2, and Q6 are all connected to a 3.3V power supply. The emitters of transistors Q1 and Q2 are connected to resistors R3 and R6 in sequence and then grounded. The collector of transistor Q1 is connected to resistors R1 and R6 in sequence and then grounded. Transistor Q2... The collector of transistor Q1 is connected to resistors R2 and R6 in sequence and then grounded. The collector of transistor Q1 is also connected to the positive input terminal of comparator U2A through resistor R1. The emitters of transistors Q5 and Q6 are connected to resistors R13 and R14 in sequence and then grounded. The collector of transistor Q5 is connected to resistors R11 and R14 in sequence and then grounded. The collector of transistor Q6 is connected to resistors R12 and R14 in sequence and then grounded. The collector of transistor Q4 is also connected to the negative input terminal of comparator U2A and the GPIO port through resistor R11.

[0065] Combination Figure 4 The working process of this embodiment four is as follows: The two input interfaces are connected to two objects to be detected, such as two magnetic door switches. Only when the two input detection circuits are turned on at the same time, that is, when both optocoupler U3 and optocoupler U4 are turned on, the low-level signals generated by them work together to make the two sets of coordinating transistors Q1 / Q2 and Q5 / Q6 meet the conduction conditions, thereby pulling up pins 3 and 2 of comparator U2A. The MCU reads the high level through GPIO and determines that the trigger condition is met. The MCU then sets GPIO to pull-down input mode and forces pin 2 of comparator U2A to low. Comparator U2A flips and drives the output load to work. As long as any input detection circuit is disconnected, the corresponding coordinating transistor group will be cut off, and it will be unable to effectively pull up pin 3 of comparator U2A, or it will be unable to maintain the high level of pin 2 of comparator U2A when GPIO is floating, thus causing the driving condition to be invalid and the output load to stop working.

[0066] This structure can be flexibly configured for security and interlocking scenarios that require multiple conditions to be met simultaneously for activation. By adding more parallel input detection branches, more combinations of conditions can be determined.

[0067] Example 5:

[0068] Building upon Embodiment 3, a load driving and status detection circuit based on a single GPIO is provided. This circuit is used in application scenarios where the load connected to the output driving circuit and the object being detected connected to the input detection circuit are different objects. It includes one input detection circuit and multiple output driving circuits, with centralized control of these circuits. Specifically, it comprises multiple output driving circuits and corresponding output interfaces for simultaneously or time-divisionally driving multiple loads. The output of the comparator circuit is simultaneously connected to the input of all output driving circuits to centrally control the synchronous driving of multiple loads. Other parts are the same as in Embodiment 3 and will not be elaborated further here.

[0069] like Figure 5 As shown, it includes a coordination circuit, a comparison circuit, two output drive circuits and an input detection circuit;

[0070] The comparator circuit includes comparator U3A. The positive terminal of comparator U3A is connected to a 5V power supply, and the positive terminal of comparator U3A is grounded through capacitor C1. The negative terminal of comparator U3A is also grounded.

[0071] The output driving circuit includes a first output driving circuit and a second output driving circuit. The first output driving circuit includes a transistor Q2, an optocoupler U1, and a MOSFET Q1. The base of transistor Q2 is connected to one end of resistor R4, and the other end of resistor R4 is connected to the output of comparator U3A. A resistor R6 is connected between the base and emitter of transistor Q2. The emitter of transistor Q2 is grounded. The collector of transistor Q2 is connected to pin 2 of optocoupler U1. Pin 1 of optocoupler U1 is connected to a 5V power supply after being connected to resistor R1. Pin 4 of optocoupler U1 is connected to a VDD power supply after being connected to resistor R2. Pin 3 of optocoupler U1 is connected to the gate of MOSFET Q1 after being connected to resistor R3. A resistor R5 is connected between the gate and source of MOSFET Q1. The source of MOSFET Q1 is connected to the power supply ground after being connected to fuse F1. The drain of MOSFET Q1 is connected to one end of the first output interface, and the other end of the first output interface is connected to the VDD power supply. The second output drive circuit includes a transistor Q5, an optocoupler U2, and a MOSFET Q4. The base of transistor Q5 is connected to one end of resistor R13, and the other end of resistor R13 is connected to the output of comparator U3A. A resistor R15 is connected between the base and emitter of transistor Q5. The emitter of transistor Q5 is grounded. The collector of transistor Q5 is connected to pin 2 of optocoupler U2. Pin 1 of optocoupler U2 is connected to a 5V power supply via resistor R9. Pin 4 of optocoupler U2 is connected to a VDD power supply via resistor R10. Pin 3 of optocoupler U2 is connected to the gate of MOSFET Q4 via resistor R12. A resistor R14 is connected between the gate and source of MOSFET Q4. The source of MOSFET Q4 is connected to ground via fuse F2. The drain of MOSFET Q4 is connected to one end of the second output interface, and the other end of the second output interface is connected to the VDD power supply. The first and second output interfaces are used to connect loads.

[0072] The input detection circuit includes optocoupler U4. Pin 1 of optocoupler U4 is connected to one end of the input interface, and the other end of the input interface is connected to the VDD power supply. The input interface is used to connect a load or sensor. Pin 2 of optocoupler U4 is connected to the power supply ground after connecting to resistor R21. Pin 3 of optocoupler U4 is grounded. Pin 4 of optocoupler U3 is connected to the 3.3V power supply after connecting to resistor R19. Pin 4 of optocoupler U3 is also connected to one end of resistor R20.

[0073] The coordination circuit includes transistors Q3 and Q6. The bases of both transistors Q3 and Q6 are connected to the other end of resistor R20. The emitters of both transistors Q3 and Q6 are connected to a 3.3V power supply. The emitter of transistor Q3 is connected to ground via resistors R8 and R11, and the collector of transistor Q3 is connected to ground via resistors R7 and R11. The collector of transistor Q3 is also connected to the positive input terminal of comparator U3A via resistor R7. The emitter of transistor Q6 is connected to ground via resistors R17 and R18, and the collector of transistor Q6 is connected to ground via resistors R16 and R18. The collector of transistor Q6 is also connected to the negative input terminal of comparator U3A and the GPIO port via resistor R16.

[0074] Combination Figure 5 The working process of this fifth embodiment is as follows: The working process of this fifth embodiment is similar to that of the third embodiment. It realizes one input detection signal to synchronously drive two loads. Its core feature is that a single comparator output controls two independent output drive circuits at the same time. The specific working process will not be described in detail here.

[0075] Example 6:

[0076] Building upon Embodiment 3, a load driving and status detection circuit based on a single GPIO is provided. This circuit is used in application scenarios where the load connected to the output driving circuit and the object being detected connected to the input detection circuit are different objects. It includes one input detection circuit and multiple output driving circuits, which can be independently controlled. Specifically, it comprises multiple output driving circuits and corresponding multiple output interfaces for simultaneously or time-divisionally driving multiple loads. It includes multiple comparator circuits and multiple output driving circuits and output interfaces connected to the output terminals of each comparator circuit. The input terminal of each comparator circuit is connected to a coordination circuit, and the output terminal of each comparator circuit independently controls a corresponding output driving circuit, thereby achieving independent or combined driving control of different loads. Other parts are the same as in Embodiment 3 and will not be elaborated further here.

[0077] like Figure 6 As shown, it includes a coordination circuit, two comparison circuits, two output drive circuits, and one input detection circuit;

[0078] The comparator circuit includes comparator U2A and comparator U2B. The positive terminal of comparator U2A is connected to a 5V power supply, and the positive terminal of comparator U2A is grounded through capacitor C1. The negative terminal of comparator U2A is grounded. Comparator U2A and comparator U2B are in the same package.

[0079] The output driving circuit includes a first output driving circuit and a second output driving circuit. The first output driving circuit includes a transistor Q3, an optocoupler U1, and a MOSFET Q2. The base of transistor Q3 is connected to one end of resistor R6, and the other end of resistor R6 is connected to the output of comparator U2B. A resistor R9 is connected between the base and emitter of transistor Q3. The emitter of transistor Q3 is grounded. The collector of transistor Q3 is connected to pin 2 of optocoupler U1. Pin 1 of optocoupler U1 is connected to a 5V power supply after being connected to resistor R1. Pin 4 of optocoupler U1 is connected to a VDD power supply after being connected to resistor R2. Pin 3 of optocoupler U1 is connected to the gate of MOSFET Q2 after being connected to resistor R3. A resistor R8 is connected between the gate and source of MOSFET Q2. The source of MOSFET Q2 is connected to the power supply ground after being connected to fuse F1. The drain of MOSFET Q2 is connected to one end of the first output interface, and the other end of the first output interface is connected to the VDD power supply. The second output drive circuit includes a transistor Q6, an optocoupler U3, and a MOSFET Q5. The base of transistor Q6 is connected to one end of resistor R16, and the other end of resistor R16 is connected to the output of comparator U2A. A resistor R18 is connected between the base and emitter of transistor Q6. The emitter of transistor Q6 is grounded. The collector of transistor Q6 is connected to pin 2 of optocoupler U3. Pin 1 of optocoupler U3 is connected to a 5V power supply via resistor R12. Pin 4 of optocoupler U3 is connected to a VDD power supply via resistor R13. Pin 3 of optocoupler U3 is connected to the gate of MOSFET Q5 via resistor R15. A resistor R17 is connected between the gate and source of MOSFET Q5. The source of MOSFET Q5 is connected to power ground via fuse F2. The drain of MOSFET Q5 is connected to one end of the second output interface, and the other end of the second output interface is connected to the VDD power supply. The first and second output interfaces are used to connect loads.

[0080] The input detection circuit includes an optocoupler U4. Pin 1 of the optocoupler U4 is connected to one end of the input interface, and the other end of the input interface is connected to the VDD power supply. The input interface is used to connect a load or sensor. Pin 2 of the optocoupler U4 is connected to the power supply ground after being connected to resistor R24. Pin 3 of the optocoupler U4 is grounded. Pin 4 of the optocoupler U4 is connected to the 3.3V power supply after being connected to resistor R22. Pin 4 of the optocoupler U4 is also connected to one end of resistor R23.

[0081] The coordination circuit includes transistors Q1, Q4, and Q7. The bases of transistors Q1, Q4, and Q7 are all connected to the other end of resistor R23. The emitters of transistors Q1, Q4, and Q7 are all connected to a 3.3V power supply. The emitter of transistor Q1 is connected to ground via resistors R5 and R7, and the collector of transistor Q1 is connected to ground via resistors R4 and R7. The collector of transistor Q1 is also connected to the positive input terminal of comparator U2B via resistor R4. The emitter of transistor Q4 is connected to... After connecting resistors R11 and R14 to ground, the collector of transistor Q4 is connected to resistors R10 and R14 in sequence and then grounded. The collector of transistor Q4 is also connected to the positive input terminal of comparator U2A through resistor R10. The emitter of transistor Q7 is connected to resistors R20 and R21 in sequence and then grounded. The collector of transistor Q7 is connected to resistors R19 and R21 in sequence and then grounded. The collector of transistor Q7 is also connected to the negative input terminal of comparator U2A, the negative input terminal of comparator U2B, and the GPIO port through resistor R19.

[0082] Combination Figure 6 The working process of this embodiment six is ​​as follows: In the initial stage, the GPIO port is floating input, and the input detection circuit controls the base of all coordinating transistors Q1, Q4, and Q7. When the detection conditions are met, optocoupler U4 is turned on, and all these transistors are turned on. The turn-on of transistor Q7 pulls the negative input terminals of comparators U2A and U2B high.

[0083] The positive input voltage of comparator U2A is determined by the resistor network of the branch containing transistor Q4, and the positive input voltage of comparator U2B is determined by the resistor network of the branch containing transistor Q1. By designing the ratio of these resistor networks, different switching thresholds for comparators U2A and U2B can be preset. For example, setting the R4 / R7 network makes the threshold of comparator U2B lower, and the R10 / R14 network makes the threshold of comparator U2A higher. The resistance values ​​can be set as needed, which will not be elaborated on here.

[0084] When driving the load connected to the first output interface, the MCU configures the GPIO as a pull-down input. At this time, the GPIO port connection point is pulled to a certain intermediate voltage V1. This V1 may be lower than the threshold of comparator U2B but higher than the threshold of comparator U2A, causing comparator U2B to output a high level, the first output driving circuit to work, comparator U2A to output a low level, and the second drive output circuit to not work. Similarly, by adjusting the resistance network of transistors Q1 and Q4, the V1 voltage may be higher than the threshold of comparator U2B but lower than the threshold of comparator U2A, causing comparator U2B to output a low level, the first output driving circuit to not work, comparator U2A to output a high level, and the second drive output circuit to work.

[0085] In some illustrative embodiments, the driving time interval between different driving output circuits can be adjusted by adjusting the coordination circuit, such as by adding other peripheral devices or adjusting the resistance value. The input front end of the comparator is within the adjustable range of the coordination circuit.

[0086] This solution uses a hardware resistor network to preset priorities or timings, combined with the flexible software configuration of GPIO, to achieve complex logic far exceeding simple synchronous control. It is suitable for multi-load management systems that require sequential startup, priority control, or mode switching.

[0087] Example 7:

[0088] The present invention provides an electronic device, including a microcontroller or system-on-a-chip, employing a load driving and status detection circuit based on a single GPIO as described in any one of Embodiments 1 to 6, for driving and monitoring the status of an external load.

[0089] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the technical principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A load driving and status detection circuit based on a single GPIO, characterized in that, It includes a coordination circuit, a comparison circuit, at least one output drive circuit, and at least one input detection circuit; The output terminal of the coordination circuit is connected to the input terminal of the comparator circuit, the output terminal of the comparator circuit is connected to the input terminal of the at least one output driving circuit, and the output terminal of the output driving circuit is used to connect to the load. The input terminal of the at least one input detection circuit is used to connect to the object being detected, and its output terminal is connected to the input terminal of the coordination circuit. The GPIO port is connected to the coordination circuit and can be configured by software to either a floating input or a pull-down input mode to control the output state of the coordination circuit. Through the cooperation of the comparator circuit and the output drive circuit, a closed-loop or correlated control function can be achieved by using the same GPIO port to complete input state detection and output drive control. Specifically: In floating input mode, the coordination circuit adjusts the input level of the comparator circuit based on the detection signal from the input detection circuit to detect the input state of the object being detected; in pull-down input mode, the GPIO port forcibly pulls down the corresponding input level of the comparator circuit through an internal pull-down resistor, causing the comparator circuit to flip its output, triggering the output drive circuit to conduct and achieve load drive control. The input detection circuit continuously monitors the state of the object being detected and feeds it back to the coordination circuit. When an abnormality is detected, the GPIO port is configured back to floating input mode, resetting the comparator circuit and controlling the output drive circuit to turn off.

2. The load driving and status detection circuit based on a single GPIO according to claim 1, characterized in that, The output terminal of the output driving circuit is connected to one end of a load, and the other end of the load is connected to the input terminal of the input detection circuit, forming a closed-loop driving and detection circuit for the same load.

3. The load driving and status detection circuit based on a single GPIO according to claim 1, characterized in that, The input terminal of the input detection circuit is connected to a sensor, and the output terminal of the output drive circuit is connected to a load. The state of the sensor is detected by the input detection circuit, and the load is driven by the comparison circuit and the output drive circuit accordingly.

4. The load driving and status detection circuit based on a single GPIO according to claim 3, characterized in that, It includes multiple input detection circuits and corresponding multiple input interfaces, used to detect the status of multiple detected objects simultaneously or in a time-division manner, and to feed back the status information to the coordination circuit.

5. The load driving and status detection circuit based on a single GPIO according to claim 3, characterized in that, It includes multiple output drive circuits and corresponding multiple output interfaces, which are used to drive multiple loads simultaneously or in a time-sharing manner.

6. The load driving and status detection circuit based on a single GPIO according to claim 5, characterized in that, The output of the comparator circuit is simultaneously connected to the input of all output drive circuits to centrally control the synchronous drive of multiple loads.

7. The load driving and status detection circuit based on a single GPIO according to claim 5, characterized in that, It includes multiple comparator circuits, as well as multiple output driver circuits and output interfaces connected to the output terminals of each comparator circuit; the input terminal of each comparator circuit is connected to a coordination circuit, and the output terminal of each comparator circuit independently controls a corresponding output driver circuit to achieve independent or combined drive control of different loads.

8. A load driving and status detection method based on a single GPIO, applied to the load driving and status detection circuit based on a single GPIO as described in any one of claims 1 to 7, characterized in that, The method includes the following steps: The GPIO port is initially configured as a floating input mode, and the state of the object being detected is determined by the input detection circuit. Based on the test results, the GPIO port is reconfigured to pull-down input mode. The output drive circuit is changed by coordinating the circuit and the comparator circuit to achieve drive control of the load. During load operation, the status is continuously or periodically monitored by the input detection circuit. If an abnormality is detected, the GPIO port is configured back to floating input mode and the drive is stopped.

9. An electronic device, comprising a microcontroller or system-on-a-chip, characterized in that, The load driving and status detection circuit based on a single GPIO, as described in any one of claims 1 to 7, is used to drive and monitor the status of an external load.

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