FPGA platform multi-chip interconnection verification system and verification method

Abstract

The application provides an FPGA platform multi-chip interconnection verification system and method. The verification system comprises a plurality of programmable logic devices, each of which is in communication connection with at least one programmable logic device, and each programmable logic device is configured with a simulation logic module for simulating the function of a target chip. The verification system further comprises a host in communication connection with the plurality of programmable logic devices, the host being configured to perform data transmission with the plurality of programmable logic devices at the medium access control layer of the Ethernet through an Ethernet communication interface; and a plurality of inter-chip interconnection modules, each of which is in communication connection with the Ethernet communication interface in the corresponding programmable logic device, and the inter-chip interconnection module is configured to perform data transmission with at least one programmable logic device through the Ethernet communication interface and a serial-parallel transceiver unit of the programmable logic device in which the inter-chip interconnection module is located.

Description

Technical Field

[0001] This application mainly relates to the field of chip verification, and in particular to a multi-chip interconnect verification system and a multi-chip interconnect verification method for an FPGA platform. Background Technology

[0002] Functional verification of chips before mass production is a crucial step in ensuring product reliability, and the verification of GPUs, as an important chip type, is particularly important. In recent years, with the rapid development of artificial intelligence, especially large-scale models, a single GPU can no longer meet the continuously growing computing power demands. Therefore, it is necessary to provide higher computing power through the interconnection and collaboration of multiple GPUs. To support interconnection scenarios of different scales and topologies, GPU manufacturers have introduced various types of high-speed interconnect interfaces and protocols into their chips. Before mass production, it is necessary to verify the operation of GPUs under different network models in multi-GPU interconnection scenarios to ensure the functional correctness and operational stability of GPUs under complex network conditions. Considering factors such as efficiency and cost, verification platforms based on programmable logic devices are usually chosen for verification.

[0003] When using FPGAs to build complex network models, several technical challenges remain: on the one hand, the network scale is large and involves a large number of chips, requiring fine-grained access isolation and unified control management between different chips; on the other hand, the interconnection interface protocols of different GPU manufacturers are inconsistent, requiring protocol adaptation and connection mapping on the FPGA platform. Summary of the Invention

[0004] The technical problem to be solved by this application is to provide an FPGA platform multi-chip interconnection verification system and an FPGA platform multi-chip interconnection verification method, which have the advantages of low verification difficulty and low verification cost.

[0005] This application proposes a multi-chip interconnect verification system for an FPGA platform, comprising multiple programmable logic devices (PLDs), each PLD being communicatively connected to at least one PLD, and each PLD being configured with a simulation logic module for simulating the function of a target chip. The system further includes: a host computer, communicatively connected to the multiple PLDs, configured to transmit data with the multiple PLDs via an Ethernet communication interface at the Ethernet media access control layer; and multiple inter-chip interconnect modules, each inter-chip interconnect module being communicatively connected to an Ethernet communication interface in its corresponding PLD, wherein the inter-chip interconnect module is configured to transmit data with at least one PLD via the Ethernet communication interface and serial-to-parallel transceiver unit of its respective PLD.

[0006] This application also proposes a multi-chip interconnect verification method for an FPGA platform to verify the functionality of a target chip based on multiple simulation logic modules. These multiple simulation logic modules are respectively configured on corresponding programmable logic devices (PLDs), and each PLD is communicatively connected to at least one PLD. The method includes: transmitting data with the multiple PLDs via an Ethernet communication interface at the Ethernet media access control layer; and controlling the inter-chip interconnect module to transmit data with at least one PLD through the Ethernet communication interface and serial-to-parallel transceiver unit of its respective PLD, wherein the inter-chip interconnect module is communicatively connected to the Ethernet communication interface of its respective PLD.

[0007] The technical solution of this application has the following technical effects: Due to limitations such as production costs, manufacturer business strategies, and device resources, programmable logic devices typically do not possess a complete network protocol stack. This application uses an inter-chip interconnect module to establish communication connections between programmable logic devices and employs custom Ethernet frames or custom network layer messages for data transmission, thus solving the problem that programmable logic devices do not support protocol stacks, reducing dependence on hardware resources and protocol stacks, and lowering verification difficulty and costs. Furthermore, various types of verification scenarios can be flexibly built using the inter-chip interconnect module. Attached Figure Description

[0008] The accompanying drawings are included to provide a further understanding of this application; they are incorporated into and constitute a part of this application. The drawings illustrate embodiments of this application and, together with this specification, serve to explain the principles of this application. In the drawings:

[0009] Figure 1 This is a schematic diagram of the structure of an FPGA platform multi-chip interconnection verification system according to an embodiment of this application;

[0010] Figure 2 This is a network diagram of multiple programmable logic devices in one embodiment of this application;

[0011] Figure 3 This is a network diagram of multiple programmable logic devices in another embodiment of this application;

[0012] Figure 4 This is a schematic diagram of the message processing flow of a gigabit media-independent interface module in one embodiment of this application;

[0013] Figure 5 This is a schematic diagram of the communication connection between two programmable logic devices in one embodiment of this application;

[0014] Figure 6 This is a schematic diagram of the inter-chip interconnection module in one embodiment of this application;

[0015] Figure 7 This is a flowchart illustrating a multi-chip interconnect verification method for an FPGA platform according to one embodiment of this application.

[0016] Reference numerals: Programmable logic device 110, first programmable logic device 111, second programmable logic device 112, host 120, network card 121, switch 130, inter-chip interconnect module 140, first inter-chip interconnect module 141, second inter-chip interconnect module 142, emulation logic module 150, first emulation logic module 151, and second emulation logic module 152. Detailed Implementation

[0017] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are merely some examples or embodiments of this application. For those skilled in the art, these drawings can be applied to other similar scenarios without creative effort. Unless obvious from the context or otherwise specified, the same reference numerals in the drawings represent the same structures or operations.

[0018] As indicated in this application, unless the context clearly indicates otherwise, the words "a," "an," "an," and / or "the" do not specifically refer to the singular and may also include the plural. Generally speaking, the terms "comprising" and "including" only indicate the inclusion of explicitly identified steps and elements, which do not constitute an exclusive list, and the method or apparatus may also include other steps or elements.

[0019] Unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps described in these embodiments do not limit the scope of this application. It should also be understood that, for ease of description, the dimensions of the various parts shown in the drawings are not drawn to actual scale. Techniques, methods, and devices known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and devices should be considered part of the specification. In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limitations. Therefore, other examples of exemplary embodiments may have different values. It should be noted that similar reference numerals and letters in the following drawings denote similar items; therefore, once an item is defined in one drawing, it need not be further discussed in subsequent drawings.

[0020] In the description of this application, it should be understood that the orientation or positional relationship indicated by directional terms such as "front, back, up, down, left, right", "horizontal, vertical, horizontal" and "top, bottom" is usually based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing this application and simplifying the description. Unless otherwise stated, these directional terms do not indicate or imply that the device or element referred to must have a specific orientation or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on the scope of protection of this application; the directional terms "inner" and "outer" refer to the inner and outer contours relative to the outline of each component itself.

[0021] For ease of description, spatial relative terms such as "above," "on top of," "on the upper surface of," "above," etc., are used herein to describe the spatial positional relationship of a device or feature as shown in the figures to other devices or features. It should be understood that spatial relative terms are intended to encompass different orientations in use or operation beyond the orientation of the device as described in the figures. For example, if the device in the figures were inverted, a device described as "above" or "on top of" other devices or structures would subsequently be positioned as "below" or "under" other devices or structures. Thus, the exemplary term "above" can include both "above" and "below." The device may also be positioned in other different ways (rotated 90 degrees or in other orientations), and the spatial relative descriptions used herein will be interpreted accordingly.

[0022] Furthermore, it should be noted that the use of terms such as "first" and "second" to define components is merely for the purpose of distinguishing the corresponding components. Unless otherwise stated, these terms have no special meaning and therefore should not be construed as limiting the scope of protection of this application. In addition, although the terminology used in this application is selected from commonly known and used terms, some terms mentioned in this application's specification may have been chosen by the applicant according to his or her judgment, and their detailed meanings are explained in the relevant sections of this description. Moreover, this application should be understood not only through the actual terms used, but also through the meaning implied by each term.

[0023] Flowcharts are used in this application to illustrate the operations performed by the system according to embodiments of this application. It should be understood that the preceding or following operations are not necessarily performed in exact order. Instead, various steps can be processed in reverse order or simultaneously. Furthermore, other operations may be added to these processes, or one or more steps may be removed from these processes.

[0024] When verifying chips using a verification platform based on programmable logic devices (FPGAs), the interconnection protocols between different chips are inconsistent, and FPGAs lack a complete network protocol stack. This makes it difficult to perform efficient data transmission between chips and to perform efficient control and management of the chips, resulting in high verification difficulty and cost. In this application, the programmable logic device refers to a Field-Programmable Gate Array (FPGA), also known as a "Field-Programmable Gate Array." The term "programmable logic device" itself is not the focus of this application; please refer to relevant technologies for related explanations, which will not be elaborated upon here. The FPGA platform multi-chip interconnection verification system and method of this application can solve the above problems, and will be described in detail below through specific embodiments.

[0025] refer to Figure 1 The diagram shows a structural schematic of an FPGA platform multi-chip interconnect verification system in one embodiment. The FPGA platform multi-chip interconnect verification system includes four programmable logic devices 110, a host 120, and multiple inter-chip interconnect modules. The host 120 is communicatively connected to the four programmable logic devices 110. Each inter-chip interconnect module is set on the corresponding programmable logic device 110, which will be described one by one below.

[0026] The host 120 can be a computer or other computer. The host 120 communicates with the switch 130 via a network interface card (NIC) 121. The switch 130 communicates with four programmable logic devices (PLDs) 110. For example, the host 120 sends instructions to the switch 130 via NIC 121, and the switch 130 forwards the instructions to the designated PLDs 110. Instructions can be edited and sent using a software development kit (SDK) running on the host 120. Instructions can be for verification or for configuring the PLDs 110; instructions can be sent as needed and are not limited to the aforementioned categories.

[0027] like Figure 1 As indicated by the arrows connecting the programmable logic devices 110, each programmable logic device 110 is communicatively connected to at least one programmable logic device 110. The connection methods between the programmable logic devices 110 are not limited to... Figure 1 As shown, for example, it could also be Figure 2 The communication connection shown in the docking manner can also be Figure 3 The communication connections shown are cascaded. It is understood that the programmable logic device 110 is not limited to... Figure 1 , Figure 2 and Figure 3The quantity can be varied, for example, the programmable logic device 110 can be 2, 3, etc., and the specific quantity can be set according to actual needs. For ease of description, the following text will use... Figure 1 Let's take the quantity in the example as an illustration.

[0028] Before mass production of chips, verification is required, which can be performed using programmable logic devices. In this application, each programmable logic device 110 is configured with a simulation logic module for simulating the function of the target chip, and verification is performed based on the simulation logic module configured on the programmable logic device 110. (Reference) Figure 5 The simulation logic module 150 may include a SoC unit, one or more service modules (BE_0, BE_1, BE_2, BE_3), and one or more interface units (INTF_0, INTF_1). The SoC unit is used for unified scheduling and management of the various functional modules within the simulation logic module. The service modules correspond to different simulation functions or application scenarios and are configured to execute specific processing tasks. The interface units are used to realize data interaction and control information transmission between the simulation logic module and external devices. Compared with other verification methods, verification using programmable logic devices has the advantages of low verification cost and a simulation frequency closer to that of real chips.

[0029] Simulation logic modules can be configured on the programmable logic device 110 using a hardware description language (HDL), such as Verilog. Different functions of the target chip can be distributed and configured on multiple programmable logic devices 110, or different target chips can be configured on different programmable logic devices 110.

[0030] refer to Figure 1 The host 120 is communicatively connected to four programmable logic devices 110 to enable data transmission. This "communication connection" can be wired (e.g., fiber optic) or wireless. The host 120 is configured to transmit data with the four programmable logic devices 110 via an Ethernet communication interface at the Ethernet Media Access Control (MAC) layer, thereby enabling data transmission and reception between the host 120 and the four programmable logic devices 110 at the Ethernet MAC layer.

[0031] In one embodiment, data transmission between the host 120 and the four programmable logic devices 110 employs raw socket communication, constructing and sending custom Ethernet frames at the Ethernet Media Access Control (MAC) layer. Specifically, the host 120 constructs and sends custom Ethernet frames at the Ethernet MAC layer using raw sockets, and parses the custom Ethernet frames from the programmable logic devices 110 to achieve data transmission with them. Due to limitations in production costs, manufacturer strategies, and device resources, programmable logic devices 110 typically lack a complete network protocol stack and do not support complex communication based on the TCP / IP protocol. This application uses an inter-chip interconnect module to establish communication connections between programmable logic devices. By adopting raw socket communication and designing custom Ethernet frames, it bypasses the TCP / IP protocol and directly transmits data at the Ethernet MAC layer. This solves the problem that programmable logic devices 110 do not support a complete protocol stack, reduces verification costs, and decreases dependence on hardware resources and protocol stacks.

[0032] Furthermore, in one embodiment, the Ethernet frame includes a type field (TYPE) that indicates the authentication item and / or authenticator corresponding to the Ethernet frame. Figure 1 As shown, due to the access of switch 130, multiple protocol messages from different verification items and verifiers are simultaneously transmitted within the local area network where host 120 and programmable logic device 110 reside. Without identification and filtering, the data used for verification may be mixed with other service data. In this application, by setting a type field in the Ethernet frame and using the type field to identify the verification item and verifier to which the Ethernet frame belongs, host 120 and programmable logic device 110 identify and filter the received Ethernet frames according to the type field. Thus, even if a large number of irrelevant protocol messages exist in the local area network, Ethernet frames can still be accurately filtered to distinguish different verification items and verifiers.

[0033] For ease of understanding, a non-restrictive example of a custom Ethernet frame is provided here. In this example, the custom Ethernet frame consists of a Layer 2 header and a payload. The header is 14 bytes long, and the payload is 46 bytes long. In the payload, the first 12 bytes are valid service fields, and the remaining bytes are automatically filled in by the network interface card (NIC). The Layer 2 header includes: a 6-byte source MAC address field (SMAC) to identify the sender, a 6-byte destination MAC address field (DMAC) to identify the target programmable logic device (PLD) 110, and a 2-byte type field.

[0034] The payload data includes a 4-byte command field (cmd), an address field (address), and a value field (value). The command field indicates the register access type and status information. The command field may include: an opcode field (to indicate the operation type, such as read, write, or interrupt trigger), a task_id field (to distinguish different tasks), and a status field (to indicate whether an error occurred during register access).

[0035] In this example, each programmable logic device 110 is assigned a unique hardware coded address, and the software establishes a device mapping relationship based on the MAC address. When the host needs to access the registers of a programmable logic device 110, the software constructs the aforementioned custom Ethernet frame based on the target MAC address, access type, and register information, and sends it to the corresponding programmable logic device 110. After receiving the message, the programmable logic device 110 parses the frame, confirms the task number and operation type, and performs the corresponding register read / write operation.

[0036] In another embodiment, data transmission between the host 120 and the four programmable logic devices also employs raw socket communication. However, unlike the previous embodiment, this embodiment constructs and parses custom network layer messages carried over Ethernet. Specifically, the host 120 constructs and sends custom network layer messages using raw sockets and parses custom network layer messages from the programmable logic devices 110, thereby enabling data transmission with the four programmable logic devices 110.

[0037] Furthermore, in one embodiment, a type field is set in the custom network layer message. The type field is used to indicate the verification project and / or verifier to which the custom network layer message belongs. By carrying the type field at the network layer, both the host 120 and the programmable logic device 110 can identify and filter the received messages according to the type field, processing only the messages that match the current verification task. In this way, even if multiple verification projects and multiple verifiers exist simultaneously in the same local area network, message identification and filtering can still be achieved.

[0038] In one embodiment, the programmable logic device 110 integrates a Gigabit Media Independent Interface (GMII) module. This GMII module is configured to transmit and receive custom messages between the programmable logic device 110 and the network interface card (NIC) 121, and to parse and encapsulate these messages. Specifically, the GMII module receives messages forwarded by the NIC 121 from the host 120, performs protocol parsing on the message content, extracts fields such as command (cmd), register address (address), and register value (value), and determines the register read / write operation type and access parameters of the target chip based on the parsing results. The GMII module can also re-encapsulate information returned by the target chip (e.g., acknowledgment information, interrupt information) according to the protocol format and send it to the host 120.

[0039] This section provides a non-restrictive example illustrating the message processing flow of a gigabit media-independent interface module. (Reference) Figure 4 As shown, in step S110, the Gigabit Media Independent Interface (GMI) module receives the configuration message; in step S120, the Gigabit Media Independent Interface (GMI) module parses the configuration message and determines the read / write type. If it is determined to be a write operation, step S130 is executed: data is written to the target register. After the write operation is completed, step S140 is executed: an acknowledgment message is sent. If it is determined to be a read operation, step S150 is executed: data is read from the target register. After the read operation is completed, step S140 is executed: an acknowledgment message is sent. After the process is completed, the system returns to standby mode, waiting for the next configuration message.

[0040] refer to Figure 5 Each programmable logic device 110 is equipped with a corresponding inter-chip interconnect module 140, and each programmable logic device 110 is equipped with an emulation logic module 150. Each inter-chip interconnect module 140 is communicatively connected to the Ethernet communication interface of the corresponding programmable logic device 110. For ease of description, ... Figure 5The two programmable logic devices 110 are designated as the first programmable logic device 111 and the second programmable logic device 112, respectively. The two inter-chip interconnect modules 140 are designated as the first inter-chip interconnect module 141 and the second inter-chip interconnect module 142, respectively. The two simulation logic modules 150 are designated as the first simulation logic module 151 and the second simulation logic module 152, respectively. The first inter-chip interconnect module 141 is configured to transmit data with the second programmable logic device 112 via the Ethernet communication interface and serial-to-parallel transceiver unit of its host programmable logic device 111. Similarly, the second inter-chip interconnect module 142 is configured to transmit data with the first programmable logic device 111 via the Ethernet communication interface and serial-to-parallel transceiver unit of its host programmable logic device 112. The inter-chip interconnect modules solve the problem of inconvenient communication connections between programmable logic devices, and various types of verification scenarios can be flexibly built using these modules.

[0041] For details, please refer to Figure 5 and Figure 6 The first programmable logic device 111 has an Ethernet communication interface 111a and a serial-to-parallel transceiver unit 111b. The first inter-chip interconnect module 141 is communicatively connected to the Ethernet communication interface 111a. In one embodiment, the first inter-chip interconnect module 141 includes a data combination module 141a, which is communicatively connected to the Ethernet communication interface 111a through a transmit interface (TX) in the data combination module 141a. Further, the first inter-chip interconnect module 141 may also include a data encapsulation module 141b, a data scheduling module 141c, and a first data buffer module 141d, which are communicatively connected in sequence. The first data buffer module 141d is communicatively connected to the data combination module 141a. The data encapsulation module 141b is used to receive data sent by the first emulation logic module 151, encapsulate the data, and further transmit the data sequentially through the data scheduling module 141c, the first data buffer module 141d, the data combination module 141a, the Ethernet communication interface 111a, and the serial-to-parallel transceiver unit 111b. The data assembly module 141a is configured to assemble the received data; the data scheduling module 141c is configured to schedule the received data, and can adopt a round-robin (RR) scheduling strategy to select each data in a preset order; the first data buffer module 141d is configured to buffer and smooth the data output by the data scheduling module 141c, and can adopt an asynchronous FIFO (AFIFO) structure.

[0042] Each of the second programmable logic devices 112 has an Ethernet communication interface 112a and a serial-to-parallel transceiver unit 112b. The serial-to-parallel transceiver unit 112b is communicatively connected to the serial-to-parallel transceiver unit 111b in the first programmable logic device 111. The second inter-chip interconnect module 142 includes a data splitting module 142a, a second data buffer module 142b, and a data packet module 142c, which are connected in sequence. The second inter-chip interconnect module 142 is communicatively connected to the Ethernet communication interface 112a through the receive interface (RX) in the data splitting module 142a, and transmits data sequentially through the data packet module 142c and the second data buffer module 142b to the first emulation logic module 151 configured on the second programmable logic device 112. The data splitting module 142a is configured to split the received data; the second data buffer module 142b is configured to buffer and smooth the received data, and can adopt an asynchronous FIFO structure; the data packet module 142c is configured to group and organize the received data.

[0043] It should be noted that the first inter-chip interconnect module 141 also includes a data splitting module, a second data caching module, and a data grouping module, and the second inter-chip interconnect module 142 also includes a data combining module, a data encapsulation module, a data scheduling module, and a first data caching module. For the sake of simplicity, the diagram is provided below. Figure 6 Not shown.

[0044] During the verification process, when data transmission is required between the first simulation logic module 151 and the second simulation logic module 152, the first simulation logic module 151 transmits the data to the first inter-chip interconnect module 141 connected to it, the first inter-chip interconnect module 141 transmits the data to the second inter-chip interconnect module 142, and the second inter-chip interconnect module 142 further transmits the data to the second simulation logic module 152, thereby realizing data transmission between the two simulation logic modules.

[0045] This application also proposes a multi-chip interconnect verification method for an FPGA platform (hereinafter referred to as the "verification method"). This verification method is used to verify the functionality of a target chip based on multiple simulated logic modules. The multiple simulated logic modules are respectively configured on corresponding programmable logic devices, and each programmable logic device is communicatively connected to at least one other programmable logic device. The verification method includes... Figure 7 Steps S210 and S220 in the process.

[0046] refer to Figure 1In step S210, data is transmitted between the host 120 and multiple programmable logic devices 110 via an Ethernet communication interface at the Ethernet media access control layer. Specifically, the host 120 transmits data with four programmable logic devices 110 via an Ethernet communication interface at the Ethernet media access control layer. The host 120 can send instructions to the programmable logic devices 110 and receive data from the programmable logic devices 110 via a software development kit on the host 120.

[0047] In one embodiment, raw socket communication is used to transmit data with multiple programmable logic devices 110 at the Ethernet media access control layer to construct and parse custom Ethernet frames at the Ethernet media access control layer. Further, in one embodiment, the Ethernet frame includes a type field indicating the authentication item and / or validator corresponding to the Ethernet frame.

[0048] In another embodiment, raw socket communication is used to transmit data with multiple programmable logic devices at the Ethernet media access control layer to construct and parse custom network layer messages carried over the Ethernet. Further, in one embodiment, the custom network layer message includes a type field, which indicates the authentication item and / or validator corresponding to the custom network layer message.

[0049] refer to Figure 1 , Figure 5 and Figure 6 In step S220, the control inter-chip interconnect module 140 transmits data with at least one programmable logic device through the Ethernet communication interface and serial-to-parallel transceiver unit of its programmable logic device. The inter-chip interconnect module is communicatively connected to the Ethernet communication interface of its programmable logic device. For example, the control first inter-chip interconnect module 141 transmits data with the second programmable logic device 112 through the Ethernet communication interface and serial-to-parallel transceiver unit of its first programmable logic device 111.

[0050] For further details regarding the verification method, please refer to the preceding description of the FPGA platform multi-chip interconnect verification system; further explanation is not provided here. The verification method of this application can be executed by the verification system described above.

[0051] This application uses specific terms to describe embodiments of the application. Terms such as "an embodiment," "one embodiment," and / or "some embodiments" refer to a particular feature, structure, or characteristic associated with at least one embodiment of the application. Therefore, it should be emphasized and noted that references to "an embodiment," "one embodiment," or "an alternative embodiment" in different locations throughout this specification do not necessarily refer to the same embodiment. Furthermore, certain features, structures, or characteristics in one or more embodiments of the application can be appropriately combined.

[0052] It should be noted that, in order to simplify the description of the present application and thus aid in the understanding of one or more embodiments of the invention, the foregoing description of the embodiments of the present application sometimes combines multiple features into a single embodiment, drawing, or description thereof. However, this disclosure method does not imply that the subject matter of the application requires more features than those mentioned. In fact, the embodiments contain fewer features than all the features of the single embodiments disclosed above.

[0053] In some embodiments, numbers describing the quantity of components and attributes are used. It should be understood that such numbers used to describe embodiments are sometimes modified by the terms "approximately," "approximately," or "generally." Unless otherwise stated, "approximately," "approximately," or "generally" indicates that the numbers are allowed to vary by ±20%. Accordingly, in some embodiments, the numerical parameters used in this application are approximate values, which may be changed depending on the characteristics required by individual embodiments. In some embodiments, numerical parameters should take into account specified significant digits and employ a general method of digit reservation. Although the numerical ranges and parameters used to confirm their breadth of range in some embodiments of this application are approximate values, in specific embodiments, such values ​​are set as precisely as feasible.

Claims

1. A multi-chip interconnect verification system for an FPGA platform, comprising multiple programmable logic devices, each programmable logic device being communicatively connected to at least one programmable logic device, and each programmable logic device being configured with a simulation logic module for simulating the function of a target chip, characterized in that, Also includes: A host is communicatively connected to the plurality of programmable logic devices. The host is configured to: transmit data between the Ethernet media access control layer and the plurality of programmable logic devices via an Ethernet communication interface using a raw socket communication method, in order to construct and parse custom Ethernet frames or construct and parse custom network layer messages carried on the Ethernet at the Ethernet media access control layer. The Ethernet frame includes a type field for indicating the authentication item and / or validator corresponding to the Ethernet frame, and the custom network layer message includes a type field for indicating the authentication item and / or validator corresponding to the custom network layer message. Multiple inter-chip interconnect modules are provided, each of which is communicatively connected to an Ethernet communication interface in a corresponding programmable logic device. The inter-chip interconnect modules are configured to transmit data with at least one programmable logic device through the Ethernet communication interface and serial-to-parallel transceiver unit of the programmable logic device in which they reside.

2. The FPGA platform multi-chip interconnection verification system as described in claim 1, characterized in that, Each of the inter-chip interconnect modules includes a data encapsulation module, a data scheduling module, a first data cache module, and a data combination module that are connected in sequence, as well as a data splitting module, a second data cache module, and a data grouping module that are connected in sequence.

3. A multi-chip interconnection verification method for an FPGA platform, verifying the functionality of a target chip based on multiple simulation logic modules, wherein the multiple simulation logic modules are respectively configured on corresponding programmable logic devices, and each programmable logic device is communicatively connected to at least one programmable logic device, characterized in that, include: Data transmission is performed between the Ethernet media access control layer and the plurality of programmable logic devices via a raw socket communication method through an Ethernet communication interface. This is to construct and parse custom Ethernet frames or custom network layer messages carried on the Ethernet over the Ethernet media access control layer. The Ethernet frame includes a type field indicating the authentication item and / or validator corresponding to the Ethernet frame, and the custom network layer message includes a type field indicating the authentication item and / or validator corresponding to the custom network layer message. The control inter-chip interconnect module transmits data with at least one programmable logic device through the Ethernet communication interface and serial-parallel transceiver unit of the programmable logic device in which it resides, wherein the inter-chip interconnect module is communicatively connected to the Ethernet communication interface in the programmable logic device in which it resides.

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