Non-contact single event effect evaluation method and system for FPGA (Field Programmable Gate Array) embedded high-speed serial interface

Abstract

The invention belongs to the technical field of semiconductor device detection and analysis, and discloses a non-contact single event effect evaluation method and system for an FPGA embedded high-speed serial interface. The method comprises the following steps: configuring an FPGA high-speed serial interface link and starting data transmission, and monitoring an error rate and a clock data recovery state at the same time; a capacitive coupling type non-contact probe is suspended above the link differential wiring, and a probe gap is determined through calibration; collecting waveform, eye pattern and frequency spectrum characteristics as baseline data under a non-irradiation condition; operating a link under an irradiation condition, and setting a trigger condition based on error code mutation, lock losing or eye pattern height reduction; probe waveforms and FPGA state parameters are synchronously stored during triggering; and performing single event effect event identification and classification on the waveform data under irradiation by using a convolutional neural network model trained based on baseline data. According to the invention, non-contact and multi-dimensional evaluation of the single event effect of the high-speed serial interface is realized.

Description

Technical Field

[0001] This application belongs to the field of semiconductor device testing and analysis technology, specifically relating to a non-contact single-event effect evaluation method and system with an embedded high-speed serial interface in an FPGA. Background Technology

[0002] Field-programmable gate arrays (FPGAs), as a type of reconfigurable integrated circuit, play a crucial role in space electronic systems due to their flexible design and short development cycle. With the continuous growth in spacecraft communication bandwidth requirements, high-speed serial transceivers (Gigabyte Transceivers, GTs) embedded in FPGAs have been widely used in onboard high-speed data links, and their transmission rates have gradually increased from the MHz level to hundreds of GHz and above.

[0003] In space radiation environments, high-speed serial interfaces are susceptible to single-event effects (SEE), which can lead to increased bit error rates, clock data recovery (CDR) circuit lockout, and even communication interruptions, seriously threatening link reliability. Therefore, conducting SEE assessments on FPGA high-speed serial interfaces under irradiation conditions is of significant engineering importance.

[0004] Currently, single-event effect testing methods for high-speed serial interfaces mainly fall into two categories: one is the bit error rate statistical method based on loopback mode, which implements a closed-loop transmission and reception mechanism within the FPGA and infers device performance by statistically analyzing bit errors, but cannot obtain the actual degradation characteristics of the signal waveform; the other is the direct detection method based on an oscilloscope, which observes waveform quality by physically connecting test points, and this method is still applicable at lower speeds (such as below 20 Gb / s).

[0005] However, with communication rates further increasing to 20 Gb / s and above, traditional direct detection methods face significant limitations. Because high-speed differential links are extremely sensitive to impedance continuity, any external branch or probe connection will introduce impedance mismatch and signal integrity issues, leading to S-parameter degradation and consequently interfering with the actual transmission waveform. Furthermore, existing evaluation methods largely rely on bit error rate or logic layer metrics such as SEU / SEFI, lacking the ability to simultaneously capture transient waveform characteristics and spectral response during irradiation, thus making it difficult to deeply identify and classify the physical mechanisms of single-event effects.

[0006] Therefore, existing technologies lack a multi-dimensional single-event effect evaluation method that can simultaneously realize waveform layer, bit error layer and phase-locked state under non-contact conditions, so as to take into account both link integrity and signal observability in ultra-high rate irradiation testing. Summary of the Invention

[0007] To address the problem of signal integrity degradation caused by impedance mismatch in existing contact measurements at ultra-high speeds, this application provides a non-contact single-event effect evaluation method and system with an embedded high-speed serial interface in an FPGA. Without disrupting the link structure, it simultaneously acquires bit error rate, CDR phase-locked state, and eye diagram waveform characteristics, and combines waveform and spectrum analysis to achieve multi-dimensional classification and identification of single-event effect events.

[0008] To achieve the above technical objectives, this application specifically adopts the following technical solution: In one aspect of this application, a non-contact single-event effect evaluation method with an embedded high-speed serial interface in an FPGA is provided, comprising the following steps: S1. Configure the FPGA high-speed serial interface link and start data transmission, while monitoring the link status parameters inside the FPGA. S2. Suspend the capacitively coupled non-contact probe above the differential trace of the link, and determine the gap distance between the probe and the trace through calibration; S3. Collect the characteristic data of the link signal after filtering and amplification under non-irradiation conditions, and use it as baseline data; S4. Run the link under irradiation conditions and set trigger conditions based on the link status parameters and the signal characteristics collected by the probe; S5. When the triggering condition is met, the waveform data of the probe and the link status parameters of the FPGA are saved synchronously. S6. Using a neural network model trained based on the baseline data, identify and classify single-event effect events in the waveform data saved under irradiation.

[0009] In one embodiment, the capacitively coupled non-contact probe includes two independent electrodes, an adjustable bracket for fixing the electrodes, and an isolation plate disposed between the electrodes and the differential traces to form a coupling capacitor.

[0010] In one implementation, the calibration process involves measuring the transmission parameters of the reference differential trace using a vector network analyzer and establishing a curve showing the relationship between the probe gap distance and the signal coupling strength.

[0011] In one implementation, the link status parameters include one or more of the following: bit error rate count, clock and data recovery phase-locked loop status flag, and equalizer parameters.

[0012] In one implementation, the triggering condition is any one or more of the following conditions: (a) A sudden change occurs in the bit error rate; (b) The clock and data recovery circuits enter a unlocked state; (c) The height of the eye diagram generated based on the probe signal drops below a set threshold.

[0013] In one implementation, the synchronization is saved by aligning the probe waveform data with the FPGA link status parameters using a unified timestamp.

[0014] In one implementation, the neural network model is a convolutional neural network model.

[0015] In one implementation, the feature data includes waveforms, eye diagrams, and spectral data.

[0016] In another aspect of this application, a non-contact single-event effect evaluation system with an embedded high-speed serial interface in an FPGA is provided, comprising: A capacitively coupled non-contact probe is suspended above the differential traces of the high-speed serial interface of the FPGA under test, and is used to acquire link signals through capacitive coupling via an air gap. A signal acquisition and processing device, connected to the probe, is used to receive and process the signals coupled to the probe; The test control and data acquisition module is connected to the FPGA under test and is used to configure the FPGA high-speed serial interface link, start data transmission, and read the FPGA link status parameters in real time. The triggering and control logic module communicates with the signal acquisition and processing device and the test control and data acquisition module respectively, and is used to control data storage according to preset triggering conditions, the triggering conditions being based on the link status parameters and / or feature data extracted from the probe signal; The data analysis module is connected to the signal acquisition and processing equipment and the test control and data acquisition module. It is used to receive and store synchronously saved probe waveform data and FPGA link status parameters, and to use a pre-trained neural network model to identify and classify single-event effect events in the waveform data under irradiation.

[0017] In one embodiment, the system further includes a calibration module that uses a vector network analyzer to establish a curve relating the gap distance of the probe to the signal coupling strength by measuring the transmission parameters of the reference differential trace.

[0018] In one embodiment, the signal acquisition and processing device is a high-speed oscilloscope with a bandwidth of not less than 20 GHz and a sampling rate of not less than 20 GS / s.

[0019] In one implementation, the link status parameters read by the test control and data acquisition module include one or more of the following: bit error rate count, clock and data recovery phase-locked loop status flag, and equalizer parameters.

[0020] In one implementation, the system achieves time synchronization between the probe waveform data and the link status parameters of the FPGA through a unified timestamp.

[0021] In one implementation, the pre-trained neural network model in the data analysis module is a convolutional neural network model trained based on radiation-free baseline data.

[0022] The beneficial effects of this application are as follows: 1) By using capacitive coupling non-contact detection, direct electrical contact with high-speed signal links is avoided, effectively overcoming the impedance mismatch and signal integrity problems introduced by traditional probes, and providing a reliable waveform observation method for ultra-high rate irradiation testing above 20Gb / s.

[0023] 2) It realizes multi-dimensional synchronous acquisition of waveform characteristics and link status parameters, and can simultaneously acquire multiple types of data such as signal eye diagram, jitter characteristics and bit error rate, CDR phase-locked state, providing a more comprehensive experimental basis for the single-event effect mechanism analysis.

[0024] 3) By combining convolutional neural networks to intelligently classify irradiation waveforms, the automatic identification and statistics of different single-event effects are realized, which significantly improves the efficiency of data processing and the accuracy of classification.

[0025] 4) A quantitative relationship between probe gap and coupling strength was established by calibrating a vector network analyzer, ensuring the consistency of test conditions and the repeatability of experimental results. Attached Figure Description

[0026] Figure 1 This is a schematic diagram of the non-contact single-event effect evaluation method using an FPGA embedded high-speed serial interface according to an embodiment of this application. Figure 2 This is a schematic diagram of the test probe in an embodiment of this application; Figure 3 This is the probe signal data processing module in the embodiments of this application; Figure 4 This is a structural diagram of the test system motherboard of an embodiment of this application. Detailed Implementation

[0027] The technical solution of this application will be clearly and completely described below with reference to specific embodiments. However, those skilled in the art will understand that the embodiments described below are only some embodiments of this application, not all embodiments, and are only used to illustrate this application, and should not be regarded as limiting the scope of this application. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0028] With the continuous improvement of spacecraft communication speeds, high-speed serial transceivers embedded in FPGAs have been widely used in spaceborne communication links. However, most existing studies on single-event effects (SEE) remain at the level of bit error rate (BER) and SEU / SEFI classification, with evaluation methods mainly relying on loopback statistics or direct oscilloscope observations. When the transmission rate exceeds 20 Gb / s, traditional direct measurement methods significantly affect link integrity due to the introduction of branches, impedance mismatches, and S-parameter distortions, making it difficult to accurately capture the real behavior of high-speed interfaces under irradiation conditions. Therefore, this application proposes a non-contact SEE evaluation method and system for high-speed serial interfaces based on capacitive coupling. This method can simultaneously acquire BER, CDR phase-locked state, and eye diagram waveform characteristics without damaging the link structure, and, combined with waveform and spectrum analysis, achieve multi-dimensional classification and identification of SEE events.

[0029] In one specific embodiment of this application, a non-contact single-event effect evaluation method with an embedded high-speed serial interface in an FPGA is provided, comprising the following steps: S1. Configure the FPGA high-speed serial interface link and start data transmission, while monitoring the link status parameters inside the FPGA.

[0030] In some embodiments, configuring the FPGA high-speed serial interface link specifically involves loading a predefined test code stream, such as a pseudo-random binary sequence (PRBS), into the high-speed serial IP core embedded in the FPGA to simulate actual data transmission conditions. A reset operation is performed on the high-speed serial interface transceiver to ensure its initial state is consistent, and the link's transmission rate is set. This rate can be adjusted according to experimental requirements, for example, set to 20 GHz or higher. After the reset, the transmission process is initiated, allowing the high-speed serial interface to begin sending and receiving data.

[0031] During data transmission, on-chip monitoring is simultaneously activated to track the link's operational status in real time. In some embodiments, the link status parameters include one or more of the following: bit error rate (BER) count, clock and data recovery phase-locked loop (CDR) status flag, and equalizer parameters. The BER count is obtained through an internal FPGA counter and is used to quantify the error probability of transmitted data. The CDR status flag indicates whether the clock is synchronized with the data stream by detecting the CDR circuit's phase-locked loop status. The equalizer parameters are read from the equalizer register of the high-speed serial interface and reflect the adjustment status of the signal equalization settings. Monitoring data is output in real time through the FPGA's internal logic or a dedicated interface and recorded to an external storage device or log system for subsequent analysis.

[0032] S2. Suspend the capacitively coupled non-contact probe above the differential trace of the link, and determine the gap between the probe and the trace through calibration.

[0033] In some embodiments, the capacitively coupled non-contact probe includes two independent electrodes fixed by an adjustable bracket. This bracket allows adjustment of the probe's height and position to ensure precise suspension above the differential trace. An isolator is placed between the electrodes and the differential trace to maintain a stable air gap. The capacitively coupled non-contact probe utilizes air as a medium to form a coupling capacitor, with measured capacitance values ​​typically between 30 and 80 fF, thereby achieving non-contact signal coupling and avoiding additional load on high-speed links.

[0034] In some embodiments, the electrodes of the capacitively coupled non-contact probe are typically made of copper foil with a thickness of approximately 17 micrometers and an area of ​​approximately 1.0 square millimeter, forming an elliptical structure. The insulating sheet is typically 0.20 mm thick.

[0035] In some embodiments, signal extraction and processing of the probe are achieved by connecting the two output terminals of the probe to the signal input channel of a high-speed oscilloscope via dual micro coaxial cables. The signal amplitude coupled to the probe is extremely weak; therefore, it needs to be amplified by an internal preamplifier of the oscilloscope or an external independent broadband amplifier to ensure that the amplified signal amplitude is greater than the minimum detectable amplitude of the acquisition device, thus ensuring effective signal acquisition.

[0036] In a preferred embodiment, to further ensure signal quality, a metal foil sheet is attached to the back of the probe as a grounding shield, which is connected to the system reference ground via a single-point grounding method to suppress common-mode noise interference.

[0037] In a preferred embodiment, the microcoaxial cable has a diameter of approximately 0.86 mm, a characteristic impedance of 50 ohms, and a length controlled to within 10 cm to reduce signal transmission loss.

[0038] In some embodiments, the hardware architecture of the test system adopts a structure where the daughterboard under test (DUT) and the main control board transmit relative to each other. The main board is responsible for system control and data initiation functions, while the daughterboard serves as the DUT. To enable monitoring of bidirectional signals on the link, capacitively coupled non-contact probes are placed at the high-speed serial interface transmitter and receiver on the main board, and at the high-speed serial interface transmitter and receiver on the daughterboard, respectively.

[0039] The purpose of the calibration is to determine the optimal gap between the probe and the trace, establish a quantitative relationship between the probe gap distance and the signal coupling strength, and ensure the consistency and accuracy of the measurement.

[0040] In some embodiments, a vector network analyzer is used during calibration to test the transmission parameters of the reference linear differential trace, specifically measuring its S21 parameter, i.e., the transmission coefficient. By changing the probe gap distance, the signal attenuation values ​​at different distances are recorded, thereby plotting a curve showing the relationship between the gap distance and the signal coupling strength. For example, experimental data shows that when the gap distance is 0.20 mm, the transmission attenuation at 10 GHz is approximately -12 dB, meeting the minimum detection requirements. Based on this calibration curve, the probe position is adjusted in actual testing to maintain a stable gap distance, ensuring that the coupled signal strength remains within the usable range.

[0041] S3. Collect characteristic data of the link signal under no-irradiation conditions as baseline data.

[0042] First, with the single-particle irradiation source off, the configured FPGA high-speed serial interface link is made to operate normally at the set target rate. At this time, the bit error rate of the link is zero, and the clock and data recovery circuits are in a stable locked state.

[0043] Next, the transmitted signal of the link is acquired using the capacitively coupled non-contact probe suspended above the differential trace. This signal is transmitted to a high-speed oscilloscope via a micro-coaxial cable. On the oscilloscope, a bandwidth and sampling rate matching the link speed are set; for example, for a 20 GHz link, the oscilloscope bandwidth is set to 20 GHz or higher, and the sampling rate to 40 GS / s. Data acquisition is then initiated.

[0044] In some embodiments, the acquired feature data includes waveform data, eye diagram data, and spectrum data. Waveform data refers to the time-domain voltage sequence directly acquired via an oscilloscope, reflecting the complete shape of the signal changing over time. Eye diagram data is a statistical graph generated by superimposing a continuous waveform, used to visually assess signal quality; key parameters such as eye diagram height, eye diagram width, and jitter can be extracted from the eye diagram. Spectrum data is obtained by performing a Fast Fourier Transform on the acquired time-domain waveform, used to analyze the energy distribution of the signal in the frequency domain, and to extract the fundamental frequency and the amplitude of its harmonic components as feature parameters.

[0045] In some embodiments, to establish a reliable baseline, it is necessary to continuously acquire data for a sufficient duration at each target transmission rate. For example, continuously record the raw waveform for at least 10 seconds, with a total baseline data recording time of at least 30 minutes. Simultaneously, record link status parameters synchronized with external waveform data, including bit error rate counts, clock and data recovery phase-locked loop status flags, and equalizer parameters.

[0046] Finally, all the collected waveforms, eye diagram parameters, and spectral features are normalized and stored together with their corresponding link state parameters to form baseline data. This baseline data serves as a comparison benchmark for judging whether the signal is abnormal in subsequent irradiation experiments, and also as a training sample for the convolutional neural network in subsequent steps, allowing it to learn the signal characteristics under normal link conditions.

[0047] S4. Run the link under irradiation conditions and set trigger conditions based on the link status parameters and the signal characteristics collected by the probe.

[0048] First, the test system containing the FPGA under test is placed under a single-event irradiation source, such as the irradiation chamber of a heavy-ion accelerator. All FPGA modules except the core link of the high-speed serial interface are physically shielded to ensure that observed events are primarily caused by single-event effects of the high-speed serial interface. Then, data transmission is initiated on the link, allowing it to operate continuously under irradiation.

[0049] During this process, a multi-condition triggering mechanism is activated simultaneously. The triggering mechanism is based on the continuous link status parameters in step S1 and the signal characteristics acquired and processed in real time by the non-contact probe in step S2.

[0050] In some embodiments, the signal characteristics acquired by the probe are eye diagram parameters generated in real time based on the coupled signals.

[0051] In some embodiments, the triggering condition is specifically any one or more combinations of the following conditions: (a) Sudden change in bit error rate: When the value of the bit error rate counter inside the FPGA increases by an order of magnitude in a short period of time, exceeding the preset sudden change threshold, the trigger condition is met.

[0052] (b) Clock and data recovery circuit enters a lost-lock state: When the clock and data recovery phase-locked state flag is detected to jump from a high level indicating lock to a low level indicating lost lock, it is triggered immediately.

[0053] (c) Eye diagram height drops below a set threshold: The trigger condition is met when the eye diagram height, calculated in real time based on the probe signal, drops by more than a preset ratio compared to the non-irradiated baseline value established in step S3.

[0054] S5. When the triggering condition is met, the waveform data of the probe and the link status parameters of the FPGA are saved synchronously.

[0055] When one or more of the aforementioned triggering conditions, including sudden changes in bit error rate, loss of clock and data recovery lockout, or decrease in eye diagram height, occur simultaneously, the test system immediately initiates the data saving process. This process aims to simultaneously record two parts of data: first, external waveform data acquired by a capacitively coupled non-contact probe and digitized by an oscilloscope; and second, link status parameters provided by the FPGA's internal monitoring circuitry. The link status parameters include one or more of the following: bit error rate count, clock and data recovery phase-locked loop status flags, and equalizer parameters.

[0056] To achieve the correspondence between waveform data and FPGA link status parameters, a unified timestamp method is used for synchronization in some embodiments. Specifically, a unique timestamp is generated for each triggered event. The probe waveform data is marked with this timestamp when it is captured and saved by the oscilloscope. At the same time, the monitoring logic inside the FPGA or the external recording device also marks the data with the same timestamp when recording link status parameters, such as the instantaneous value of the bit error counter, the level transition time of the phase-locked loop (PLL) status flag, and the read value of the equalizer parameter register.

[0057] This method allows for the matching and alignment of waveform data captured by the probe over a specific time period with the corresponding state data recorded internally by the FPGA, based on a unified timestamp. For example, waveform distortion during a burst of bit errors can be correlated with the moment the FPGA's bit error counter begins to spike. This synchronization mechanism ensures the consistency of externally observed signal characteristics with changes in the chip's internal logic state along the timeline, providing a reliable data foundation for accurately analyzing the characteristics and mechanisms of single-event events.

[0058] S6. Using a neural network model trained based on the baseline data, identify and classify single-event effect events in the waveform data saved under irradiation.

[0059] In some embodiments, the neural network model is a convolutional neural network model. The data used for training comes from the baseline dataset collected and constructed under irradiation conditions in step S3.

[0060] During training, the original waveforms in the baseline dataset are first normalized to eliminate amplitude bias. Then, continuous waveform data is divided into fixed-length microsecond-level time segments. Simultaneously, the corresponding eye diagram height, jitter value, and the spectral amplitudes of the fundamental and harmonic frequencies are input into the network as associated features. Through this process, the network learns and establishes time-domain and frequency-domain characteristic benchmarks for the high-speed serial interface under normal operating conditions.

[0061] The neural network model compares and processes the input irradiated waveform segments and their features with normal feature benchmarks learned during training, and outputs a classification judgment for each waveform segment. Based on the model output, it automatically identifies abnormal waveforms that have experienced single-event events and further categorizes them.

[0062] In some embodiments, the classification categories include single-event event types such as "burst error type", "clock data recovery lockout type", and "analog front-end degradation type".

[0063] In another specific embodiment of this application, a non-contact single-event effect evaluation system with an embedded high-speed serial interface in an FPGA is provided, including a capacitively coupled non-contact probe, a signal acquisition and processing device, a test control and data acquisition module, a triggering and control logic module, and a data analysis module.

[0064] The capacitively coupled non-contact probe is suspended above the differential traces of the high-speed serial interface of the FPGA under test. The probe acquires the link signal through the principle of capacitive coupling via an air gap without physical contact with the traces.

[0065] In some embodiments, the probe comprises two separate electrodes, which are secured by an adjustable bracket. An isolator is positioned between the electrodes and the differential traces to maintain a stable air gap, thereby creating fly-level coupling capacitance.

[0066] The signal acquisition and processing device is connected to the probe via a cable and is used to receive and process the weak signals coupled to the probe.

[0067] In some embodiments, the signal acquisition and processing device is a high-speed oscilloscope with a bandwidth of not less than 20 GHz and a sampling rate of not less than 20 GS / s, to ensure that the signal characteristics of the high-speed serial interface can be accurately captured.

[0068] The test control and data acquisition module is connected to the FPGA under test. This module is used to configure the FPGA's high-speed serial interface link, initiate the data transmission process, and read the FPGA's link status parameters in real time. The link status parameters include one or more of the following: bit error rate count, clock and data recovery phase-locked loop status flags, and equalizer parameters.

[0069] The triggering and control logic module establishes communication connections with both the signal acquisition and processing device and the test control and data acquisition module. The triggering and control logic module controls the data saving action according to preset trigger conditions. These trigger conditions are based on the link status parameters and / or feature data extracted from the probe signal. Specifically, the trigger conditions include, but are not limited to, any one or more of the following: (a) a sudden change in the bit error rate; (b) the clock and data recovery circuit entering a lost-lock state; (c) the eye diagram generated based on the probe signal, whose height drops below a set threshold.

[0070] The data analysis module is connected to the signal acquisition and processing equipment and the test control and data acquisition module. The data analysis module receives and stores synchronously saved probe waveform data and FPGA link status parameters. To achieve data time synchronization, the system uses a unified timestamp to precisely align probe waveform data from different sources with the FPGA link status parameters. The data analysis module utilizes a pre-trained neural network model to identify and classify single-event events in the waveform data saved under irradiation. The pre-trained neural network model is a convolutional neural network model trained based on baseline data without irradiation.

[0071] In some embodiments, to ensure measurement consistency, the system may also include a calibration module. The calibration module employs a vector network analyzer to establish a quantitative correlation curve between the probe's gap distance and the signal coupling strength by measuring the transmission parameters of the reference differential trace (such as the S21 parameter), thereby completing the initial calibration of the system.

[0072] Example Reference Figure 1 As shown, a non-contact single-event effect evaluation method with an embedded high-speed serial interface in an FPGA includes the following implementation steps: 1) Fabrication of a capacitively coupled non-contact probe: Refer to Figure 2 and 3 As shown, in the experiment, two pieces with an area of ​​approximately 1.0 mm were fabricated using a copper sheet (0.5 oz copper foil) with a thickness of approximately 17 µm. 2 An elliptical electrode is fixed on an adjustable bracket, and a 0.20 mm thick insulating sheet is inserted between the two electrodes and the trace to be tested to maintain a stable air gap, forming a differential capacitance coupling probe. The actual measured coupling capacitance is approximately 30–80 fF.

[0073] 2) Probe and acquisition device connection: The probe's dual-channel output is connected to the oscilloscope via a 0.86 mm semi-rigid micro coaxial cable (approximately 10 cm in length). Copper foil is attached to the back of the probe for shielding, and single-point grounding is used to reduce environmental noise interference.

[0074] 3) Calibration and motherboard / daughterboard system setup: Refer to Figure 4 As shown, the test system adopts a motherboard and daughterboard structure, with the motherboard acting as the main controller and the daughterboard as the board under test. Probes are placed at the high-speed serial interface transceiver ends of the motherboard and daughterboard, respectively. A vector network analyzer is used to measure the S21 transmission parameters of the reference straight differential trace, thereby obtaining the correlation between the probe-trace gap and the signal coupling strength, and establishing a calibration curve. Experimental results show that when the gap is 0.20 mm, the probe output transmission attenuation at 10 GHz is approximately –12 dB, which is sufficient to meet the minimum detection requirements.

[0075] 4) Oscilloscope configuration: Set the bandwidth to 20 GHz and the sampling rate to 40 GS / s on the oscilloscope, and enable the 4 ms rolling buffer and the 2 ms trigger window before and after. At the same time, enable the FFT real-time monitoring function to track the amplitude of the three frequency components f_baud, 2f and 3f.

[0076] 5) FPGA Configuration and Transmission Startup: Load the pseudo-random bitstream (PRBS31) into the high-speed serial IP embedded in the FPGA, reset the GT transceiver, and then start the transmission process. The link rate is set to 20 GHz. During transmission, the FPGA simultaneously enables the bit error rate (BER) counter, CDR phase-locked loop detection signal, and equalization parameter register readout to provide monitoring data for subsequent steps.

[0077] 6) Baseline Acquisition: The link was operated under no-irradiation conditions. Probe waveforms were continuously acquired for 60 seconds at each rate point, and eye diagram height, RMS jitter, and FFT fundamental amplitude were recorded as a control baseline. Simultaneously, the acquired waveforms, eye diagrams, and spectral features were used to construct a training dataset for a convolutional neural network. After normalization and differencing, the dataset was divided into 1–2 µs time segments as learning samples under normal link conditions.

[0078] 7) Irradiation Experiment: The test system is irradiated inside the irradiation chamber of a heavy ion accelerator. All modules except the high-speed serial interface are physically shielded, exposing only the high-speed serial interface link between the motherboard and the daughterboard. During irradiation operation, a multi-condition triggering mechanism is enabled, including conditions such as BER burst, CDR loss of lock, and eye diagram height drop exceeding 30%, to capture SEE events.

[0079] 8) Event saving: When the triggering condition is met, the original waveform data of the probe is saved for ±2 ms according to the storage depth of the test system, and the BER count, CDR status and equalization parameter register value inside the FPGA are recorded simultaneously.

[0080] 9) Cyclic test: If the link transmission function is interrupted or the high-speed serial interface is automatically reset, then repeat steps 5) to 8) until the cumulative injection rate reaches the preset test value to ensure the integrity and statistical significance of the data.

[0081] 10) Data Analysis and Classification: Feature extraction is performed on the saved waveforms, including eye diagram height, aperture, jitter, and harmonic amplitude, and preliminary event classification is performed in conjunction with FPGA internal monitoring flags. After training on the baseline data in step 6), the convolutional neural network is applied to waveform recognition under irradiation to achieve automated classification and statistics of SEE events. Experiments show that this method can accurately distinguish events into "BER burst type," "CDR unlock type," and "simulated front-end degradation type," and calculate the SEE cross section at different rates accordingly.

[0082] Although the embodiments of this application have been described above in conjunction with the accompanying drawings, this application is not limited to the specific embodiments and application fields described above. The specific embodiments described above are merely illustrative and instructive, not restrictive. Those skilled in the art can make many other forms based on the guidance of this specification and without departing from the scope of protection of the claims of this application, and these are all within the scope of protection of this application.

Claims

1. A non-contact single-event effect evaluation method with an embedded high-speed serial interface in an FPGA, characterized in that, Includes the following steps: S1. Configure the FPGA high-speed serial interface link and start data transmission, while monitoring the link status parameters inside the FPGA. S2. Suspend the capacitively coupled non-contact probe above the differential trace of the link, and determine the gap distance between the probe and the trace through calibration; S3. Collect the characteristic data of the link signal after filtering and amplification under non-irradiation conditions, and use it as baseline data; S4. Run the link under irradiation conditions and set trigger conditions based on the link status parameters and the signal characteristics collected by the probe; S5. When the triggering condition is met, the waveform data of the probe and the link status parameters of the FPGA are saved synchronously. S6. Using a neural network model trained based on the baseline data, identify and classify single-event effect events in the waveform data saved under irradiation.

2. The non-contact single-event effect evaluation method according to claim 1, characterized in that, The capacitively coupled non-contact probe includes two independent electrodes, an adjustable bracket for fixing the electrodes, and an isolation plate disposed between the electrodes and the differential traces, forming a coupling capacitor.

3. The non-contact single-event effect evaluation method according to claim 1, characterized in that, The calibration process is as follows: use a vector network analyzer to measure the transmission parameters of the reference differential trace and establish the corresponding curve between the probe gap distance and the signal coupling strength.

4. The non-contact single-event effect evaluation method according to claim 1, characterized in that, The link status parameters include one or more of the following: bit error rate count, clock and data recovery phase-locked loop status flags, and equalizer parameters.

5. The non-contact single-event effect evaluation method according to claim 1, characterized in that, The triggering condition is any one or more of the following conditions: (a) A sudden change occurs in the bit error rate; (b) The clock and data recovery circuits enter a unlocked state; (c) The height of the eye diagram generated based on the probe signal drops below a set threshold.

6. The non-contact single-event effect evaluation method according to claim 1, characterized in that, The synchronization is achieved by aligning the probe waveform data with the FPGA link status parameters using a unified timestamp.

7. The non-contact single-event effect evaluation method according to claim 1, characterized in that, The neural network model is a convolutional neural network model.

8. The non-contact single-event effect evaluation method according to claim 1, characterized in that, The feature data includes waveforms, eye diagrams, and spectral data.

9. A non-contact single-event effect evaluation system with an embedded high-speed serial interface in an FPGA, characterized in that, include: A capacitively coupled non-contact probe is suspended above the differential traces of the high-speed serial interface of the FPGA under test, and is used to acquire link signals through capacitive coupling via an air gap. A signal acquisition and processing device, connected to the probe, is used to receive and process the signals coupled to the probe; The test control and data acquisition module is connected to the FPGA under test and is used to configure the FPGA high-speed serial interface link, start data transmission, and read the FPGA link status parameters in real time. The triggering and control logic module communicates with the signal acquisition and processing device and the test control and data acquisition module respectively, and is used to control data storage according to preset triggering conditions, the triggering conditions being based on the link status parameters and / or feature data extracted from the probe signal; The data analysis module is connected to the signal acquisition and processing equipment and the test control and data acquisition module. It is used to receive and store synchronously saved probe waveform data and FPGA link status parameters, and to use a pre-trained neural network model to identify and classify single-event effect events in the waveform data under irradiation.

10. The non-contact single-event effect assessment system according to claim 9, characterized in that, The system also includes a calibration module, which uses a vector network analyzer to establish a curve showing the relationship between the probe's gap distance and the signal coupling strength by measuring the transmission parameters of the reference differential trace.

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