A circuit design simulation system and method

Abstract

This application relates to a circuit design simulation system and method. In this application, by automatically parsing and transforming abstract functional requirements into structured data and instructions that drive design tools to execute, it is possible to directly and automatically generate circuit design files that meet the requirements. This achieves end-to-end automation of the hardware design process, which not only frees designers from heavy and repetitive manual drawing and translation work and significantly shortens the development cycle, but also fundamentally ensures the consistency between the design output and the original requirements, eliminates errors introduced by human interpretation and operation, and significantly improves the efficiency, quality and maintainability of hardware design.

Description

Technical Field

[0001] This application belongs to the field of electronic design automation technology, and in particular relates to a circuit design simulation system and method. Background Technology

[0002] In the field of hardware circuit development, the current mainstream design method relies heavily on manual labor. Designers need to manually convert functional requirements in text or table form into specific circuit schematics and PCB (printed circuit board) design drawings. This process is usually completed with the help of EDA (electronic design automation) software. However, the software itself is only a tool, and all analysis, decision-making and drawing operations still need to be performed by engineers one by one.

[0003] This human-driven model has obvious drawbacks: First, it is inefficient, with cumbersome and time-consuming steps from requirements to finished design; second, the quality is unstable, with the quality of the design depending entirely on the engineer's personal experience and state of mind, making it prone to errors and difficult to standardize; third, requirements and design are disconnected, with requirement changes unable to be automatically and accurately synchronized to the design files, making maintenance difficult.

[0004] While existing technologies provide automation assistance in certain local processes (such as automatic routing), they have not yet achieved end-to-end automated generation from "functional requirements" to "final design documents." There is a lack of an intelligent processing core that can automatically understand requirements, coordinate design data, and drive tools to complete the drawing between requirement input and design output. Summary of the Invention

[0005] The purpose of this application is to provide a circuit design simulation system and method. The circuit design simulation system and method provided by this application can directly and automatically generate circuit design files that meet the requirements by automatically parsing and converting abstract functional requirements into structured data and instructions that drive design tools to execute. This achieves end-to-end automation of the hardware design process as a whole.

[0006] This application provides a circuit design simulation system, the system comprising: a hardware requirement identification module, a hardware design data processing module, and a hardware design file generation module;

[0007] The hardware requirement identification module is used to acquire functional requirement information and decompose the functional requirement information to obtain decomposed functional requirement data.

[0008] The hardware design data processing module is used to generate hardware design data and hardware design control instructions based on the decomposed functional requirement data, as well as the acquired existing schematic data, printed circuit board design parameters and component parameters.

[0009] The hardware design file generation module is used to call the drawing port and generate new schematic design files and printed circuit board design files according to the hardware design control instructions and the hardware design data.

[0010] Optionally, the hardware design data includes hardware design simulation data and component specification information, and the hardware design file generation module includes a component package generation module and a hardware design simulation generation module;

[0011] The component package generation module is used to generate or call component package graphic data according to the component specification information.

[0012] The hardware design simulation generation module is used to call the drawing port and generate new schematic design files and printed circuit board design files according to the hardware design control instructions, the hardware design simulation data and the component package graphic data.

[0013] Optionally, the system further includes: a design file storage unit;

[0014] The hardware design simulation generation module is also used to store the new schematic design file and the printed circuit board design file to the design file storage unit.

[0015] Optionally, the hardware requirement identification module includes: a requirement information reader and a requirement function decomposer;

[0016] The requirement information reader is used to acquire functional requirement information;

[0017] The requirement function decomposer is used to perform structured decomposition and / or semantic parsing of the function requirement information to obtain the decomposed function requirement data.

[0018] Optionally, the hardware design data processing module includes: a hardware information extraction module, a data scheduling module, a simulation data parsing module, a simulation logic control programmer, and a simulation control module;

[0019] The hardware information extraction module is used to extract component specification information from the component parameters and to extract schematic information from the existing schematic data.

[0020] The data scheduling module is used to receive and schedule the decomposed functional requirement data and the schematic diagram information;

[0021] The simulation data parsing module is used to parse the information output by the data scheduling module and generate parsed data;

[0022] The simulation logic control programmer is used to generate control logic based on the information output by the data scheduling module;

[0023] The simulation control module is used to integrate the parsed data with the control logic to generate hardware design simulation data and hardware design control instructions.

[0024] Optionally, the hardware design data processing module further includes: a simulation fault analysis module and a simulation verification and operation module;

[0025] The simulation verification running module is used to perform simulation verification on the new schematic design file and the printed circuit board design file, and output verification failure data when verification fails.

[0026] The simulation fault analysis module is used to analyze the verification failure data and generate fault analysis results.

[0027] The simulation control module is used to receive the fault analysis results and correct the hardware design simulation data and the hardware design control instructions based on the fault analysis results.

[0028] Optionally, the hardware design data processing module further includes: a simulation data storage unit, a data classifier, and a data exporter;

[0029] The simulation verification operation module is also used to store the successful verification data to the simulation data storage unit when the verification is successful.

[0030] The data classifier is used to read the successful verification data from the simulation data storage unit and classify it to obtain the classified successful verification data.

[0031] The data exporter is used to export the categorized successful verification data to a specified storage location.

[0032] Optionally, the hardware design simulation generation module includes: a simulation tool calling module, a functional requirement control module, and multiple drawing ports;

[0033] The functional requirement control module is used to receive and parse the hardware design control instructions and generate call control signals;

[0034] The simulation tool calling module is used to receive the hardware design simulation data and the component package graphic data, and in response to the calling control signal, distribute the hardware design simulation data and the component package graphic data to one or more drawing ports that are called.

[0035] The multiple drawing ports are used to perform specific circuit design drawing operations based on the received hardware design simulation data and component package graphic data, so as to generate the new schematic design file and printed circuit board design file.

[0036] Optionally, the plurality of drawing ports include: schematic architecture drawing port, schematic module drawing port, schematic component drawing port, printed circuit board layout and package placement port, printed circuit board wiring port, and printed circuit board structure drawing port.

[0037] This application also provides a circuit design simulation method, the method comprising:

[0038] Obtain functional requirement information and decompose the functional requirement information to obtain decomposed functional requirement data;

[0039] Based on the decomposed functional requirements data, as well as the obtained existing schematic data, printed circuit board design parameters and component parameters, hardware design data and hardware design control instructions are generated.

[0040] Based on the hardware design control instructions and the hardware design data, the drawing port is invoked to generate new schematic design files and printed circuit board design files.

[0041] Compared with existing technologies, the circuit design simulation system and method provided in this application acquire functional requirement information, decompose the functional requirement information to obtain decomposed functional requirement data, and then generate hardware design data and hardware design control instructions based on the decomposed functional requirement data, as well as the acquired existing schematic data, printed circuit board design parameters and component parameters. Furthermore, based on the hardware design control instructions and hardware design data, the drawing port is invoked to generate new schematic design files and printed circuit board design files. In this application, by automatically parsing and transforming abstract functional requirements into structured data and instructions that drive design tools, compliant circuit design files can be generated directly and automatically. This achieves end-to-end automation of the hardware design process, which not only liberates designers from heavy and repetitive manual drawing and translation work, significantly shortening the development cycle, but also fundamentally ensures the consistency between the design output and the original requirements, eliminates errors introduced by human interpretation and operation, and significantly improves the efficiency, quality and maintainability of hardware design. Attached Figure Description

[0042] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0043] Figure 1 This is a first structural block diagram of a circuit design simulation system disclosed in an embodiment of this application;

[0044] Figure 2 This is a second structural block diagram of a circuit design simulation system disclosed in an embodiment of this application;

[0045] Figure 3 This is a third structural block diagram of a circuit design simulation system disclosed in an embodiment of this application;

[0046] Figure 4 This is a structural block diagram of the hardware requirement identification module disclosed in the embodiments of this application;

[0047] Figure 5 This is a structural block diagram of the hardware design data processing module disclosed in the embodiments of this application;

[0048] Figure 6 This is a structural block diagram of the hardware design simulation generation module disclosed in the embodiments of this application;

[0049] Figure 7 This is a flowchart of a circuit design simulation method disclosed in an embodiment of this application;

[0050] Figure reference numerals: 110 - Hardware requirement identification module; 120 - Hardware design data processing module; 130 - Hardware design file generation module; 140 - Design file storage unit;

[0051] 131 - Component packaging generation module; 132 - Hardware design simulation generation module;

[0052] 111 - Requirement Information Reader; 112 - Requirement Function Decomposer;

[0053] 121-Hardware Information Extraction Module; 122-Data Scheduling Module; 123-Simulation Data Parsing Module; 124-Simulation Logic Control Programmer; 125-Simulation Control Module; 126-Simulation Fault Analysis Module; 127-Simulation Verification and Operation Module; 128-Simulation Data Storage Unit; 1291-Data Classifier; 1292-Data Exporter;

[0054] 1321 - Simulation tool calling module; 1322 - Functional requirement control module; 1323 - Drawing port;

[0055] 1323-1 - Schematic architecture drawing port; 1323-2 - Schematic module drawing port; 1323-3 - Schematic component drawing port; 1323-4 - Printed circuit board layout and package placement port; 1323-5 - Printed circuit board wiring port; 1323-6 - Printed circuit board structure drawing port;

[0056] 210 - First memory; 220 - Second memory; 230 - Third memory; 240 - Fourth memory. Detailed Implementation

[0057] To enable those skilled in the art to better understand the technical solutions in this application, the technical solutions in the embodiments of this application will be clearly and completely described below. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0058] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly set on the other component; when a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to the other component.

[0059] It should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0060] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "a plurality of" or "several" means two or more, unless otherwise explicitly specified.

[0061] It should be noted that the structures, proportions, sizes, etc., shown in the accompanying drawings of this specification are only for the purpose of assisting those skilled in the art in understanding and reading the content disclosed in the specification, and are not intended to limit the conditions under which this application can be implemented. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in the proportions, or adjustments to the size should still fall within the scope of the technical content disclosed in this application, provided that they do not affect the effects and purposes that this application can produce.

[0062] like Figure 1 As shown in the figure, this application embodiment provides a circuit design simulation system, which includes: a hardware requirement identification module 110, a hardware design data processing module 120, and a hardware design file generation module 130; the hardware requirement identification module 110 is used to acquire functional requirement information and decompose the functional requirement information to obtain decomposed functional requirement data; the hardware design data processing module 120 is used to generate hardware design data and hardware design control instructions based on the decomposed functional requirement data, as well as the acquired existing schematic data, printed circuit board design parameters, and component parameters; the hardware design file generation module 130 is used to call the drawing port to generate new schematic design files and printed circuit board design files based on the hardware design control instructions and hardware design data.

[0063] In this embodiment, the hardware requirement identification module 110 first extracts key information from the user-imported functional requirement table and performs structured decomposition to form an executable functional requirement data stream. Subsequently, the hardware design data processing module 120 integrates the decomposed functional requirements with existing design resources (such as schematics, printed circuit board parameters, component libraries, etc.) and generates hardware design data and control instructions with simulation-driven capabilities through internal data scheduling, logic programming, and simulation parsing mechanisms. Finally, the hardware design file generation module 130 calls various automated drawing ports according to the instructions to realize the fully automated generation of the entire process from schematic framework construction, module and component layout to printed circuit board routing and structural design, and outputs design files that can be directly used for simulation verification or manufacturing.

[0064] This application realizes an automated pipeline from structured requirements to manufacturable design documents, transforming the traditional design process that relies on manual interpretation and drawing into a data-driven automatic generation process, greatly improving design efficiency; ensuring the consistency and standardization of design output, eliminating differences and errors caused by human factors by executing design rules through fixed algorithm modules and drawing ports; building a direct bridge between simulation and original design data, using simulation data and instructions to directly drive physical design generation, ensuring the theoretical feasibility of the design and laying a good foundation for subsequent in-depth verification; the system architecture is modular and the interfaces are clear, with the three major modules of hardware requirement identification, simulation data calculation, and document generation having separate responsibilities, facilitating independent optimization, upgrades, or replacements, and enhancing the system's maintainability and scalability.

[0065] like Figure 2 As shown, as a specific data architecture implementation example of the above system, the hardware requirement identification module 110 is connected to the first memory 210 and is used to read and decompose the functional requirement table; the hardware design data processing module 120 is connected to the second memory 220, the third memory 230, and the fourth memory 240 and is used to integrate requirement data with existing design resources to generate simulation data and control instructions; the hardware design file generation module 130 calls the drawing port according to the instructions to generate design files and outputs them to the third memory 230 and the fourth memory 240. Through the collaboration of the above modules and memory, the system realizes full automation from requirement import to design file output.

[0066] Compared with existing technologies, the circuit design simulation system and method provided in this application acquire functional requirement information, decompose the functional requirement information to obtain decomposed functional requirement data, and then generate hardware design data and hardware design control instructions based on the decomposed functional requirement data, as well as the acquired existing schematic data, printed circuit board design parameters and component parameters. Furthermore, based on the hardware design control instructions and hardware design data, the drawing port is invoked to generate new schematic design files and printed circuit board design files. In this application, by automatically parsing and transforming abstract functional requirements into structured data and instructions that drive design tools, compliant circuit design files can be generated directly and automatically. This achieves end-to-end automation of the hardware design process, which not only liberates designers from heavy and repetitive manual drawing and translation work, significantly shortening the development cycle, but also fundamentally ensures the consistency between the design output and the original requirements, eliminates errors introduced by human interpretation and operation, and significantly improves the efficiency, quality and maintainability of hardware design.

[0067] like Figure 3As shown, in one embodiment of this application, the hardware design data includes hardware design simulation data and component specification information. The hardware design file generation module 130 includes a component package generation module 131 and a hardware design simulation generation module 132. The component package generation module 131 is used to generate or call component package graphic data according to the component specification information. The hardware design simulation generation module 132 is used to call the drawing port according to the hardware design control instructions, hardware design simulation data and component package graphic data to generate new schematic design files and printed circuit board design files.

[0068] In this embodiment, the hardware design data processing module 120 first integrates and analyzes the functional requirements and existing design resources to generate a hardware design data package (including hardware design simulation data and component specification information) and control instructions containing simulation logic and physical constraints. The component package generation module 131, as the front-end unit for physical implementation, accurately matches or dynamically generates standard package graphic data based on the specification information to establish an accurate physical model for circuit layout. The hardware design simulation generation module 132, as the execution engine for automated drawing, combines the electrical connections and performance parameters defined by the simulation data with the physical forms defined by the package graphic data according to the step logic of the control instructions. By scheduling dedicated ports such as schematic architecture drawing, module instantiation, component layout, printed circuit board routing and structure definition, it drives the underlying EDA tools to complete the fully automatic conversion and generation from logic netlist to manufacturable design files, and finally outputs schematic and printed circuit board design files that are electrically correct, process-achievable and have passed data consistency verification.

[0069] This embodiment decouples and automates the design data parsing, encapsulation generation, and file drawing processes, achieving a fast and accurate conversion from design intent to physical files, significantly improving the efficiency and consistency of hardware design.

[0070] like Figure 3 As shown, in one embodiment of this application, the system further includes: a design file storage unit 140; and a hardware design simulation generation module 132, which is also used to store new schematic design files and printed circuit board design files to the design file storage unit 140.

[0071] In this embodiment, after the hardware design simulation generation module 132 completes the automated generation of design files, it automatically writes the output schematic design files and printed circuit board design files into the system-specified design file storage unit 140 with standardized naming and version identification. This storage unit serves as a phased result library and data hub for the design process, which not only realizes the persistent storage of generated files, but also provides a unified and traceable data source for subsequent simulation verification, version comparison, design release, or downstream manufacturing processes.

[0072] This embodiment achieves standardized closed-loop management of the generation process by adding a design file storage unit 140. On the one hand, it transforms volatile automated process outputs into persistent design assets, ensuring the security and reusability of design data. On the other hand, this centralized storage mechanism provides efficient and stable data access interfaces for other modules in the system (such as verification modules and data analysis modules), avoiding file scattering and path dependence, thereby improving the workflow collaboration efficiency and data consistency of the entire system.

[0073] like Figure 4 As shown, in one embodiment of this application, the hardware requirement identification module 110 includes: a requirement information reader 111 and a requirement function decomposer 112; the requirement information reader 111 is used to acquire functional requirement information; the requirement function decomposer 112 is used to perform structured decomposition and / or semantic parsing of the functional requirement information to obtain decomposed functional requirement data.

[0074] In this embodiment, the requirement information reader 111 serves as the system input interface, responsible for reading the original requirement information from the user-provided functional requirement table, natural language document, or standardized template, and converting it into a unified data format that can be processed internally by the system. The requirement function decomposer 112 serves as the core parsing engine, performing structured decomposition (such as identifying key electrical parameters, performance indicators, interface definitions, etc.) and deep semantic parsing (such as understanding the logical relationships, constraints, and implicit design intentions in the functional description) on the read original information, and finally transforming the unstructured user requirements into a precise, structured functional requirement data stream that can be directly called by the downstream hardware design data processing module 120.

[0075] This implementation method effectively solves the problems of ambiguous requirement transmission and error-prone manual interpretation in traditional hardware design through a two-level processing mechanism. It not only improves the automation and standardization of requirement input and ensures the accuracy and integrity of the design source data, but also enhances the intelligent understanding of complex requirements through semantic parsing capabilities. This lays a highly reliable data foundation for subsequent fully automated design generation, thereby ensuring a high degree of consistency between design output and user intent from the source.

[0076] like Figure 5As shown, in one embodiment of this application, the hardware design data processing module 120 includes: a hardware information extraction module 121, a data scheduling module 122, a simulation data parsing module 123, a simulation logic control programmer 124, and a simulation control module 125; the hardware information extraction module 121 is used to extract component specification information from component parameters and extract schematic information from existing schematic data; the data scheduling module 122 is used to receive and schedule the decomposed functional requirement data and schematic information; the simulation data parsing module 123 is used to parse the information output by the data scheduling module 122 and generate parsed data; the simulation logic control programmer 124 is used to generate control logic according to the information output by the data scheduling module 122; the simulation control module 125 is used to integrate the parsed data and control logic to generate hardware design simulation data and hardware design control instructions.

[0077] In this embodiment, the hardware information extraction module 121 first scans and identifies features of the input component parameter library and existing schematic database, accurately extracting the electrical and physical specifications of the components and the network topology and modular structure of the schematic, forming standardized specification information and schematic information; the data scheduling module 122, as the process hub, receives the demand data stream from upstream and the extracted information, and performs timing arrangement and data routing according to the preset scheduling strategy to ensure that key information is transmitted to the downstream processing unit in a priority and complete manner; the simulation data parsing module 123 performs in-depth analysis of the fused information after scheduling, identifies the electrical rules, performance constraints and connection relationships, and converts them into a computable parameterized model; at the same time, the simulation logic control programmer 124 automatically generates control logic and operation sequences to drive subsequent design steps based on the same information source; finally, the simulation control module 125, as the integration and decision center, dynamically matches and optimizes the parsed parameterized model and the generated control logic, outputting hardware design simulation data and hardware design control instructions that have electrical accuracy, process feasibility and clear steps, providing a complete, coordinated and directly executable data driving source for automated design generation.

[0078] This implementation method achieves efficient fusion and intelligent conversion of multi-source heterogeneous design information through modular pipeline processing and division of labor. It not only automates the traditional data preparation and instruction writing process that relies on manual experience, but also ensures a high degree of synchronization and consistency between design data, control logic and simulation intent through centralized scheduling and control. This significantly improves the reliability of design input and lays a core foundation for the stable operation and first-time success rate of fully automated design.

[0079] like Figure 5As shown, in one embodiment of this application, the hardware design data processing module 120 further includes: a simulation fault analysis module 126 and a simulation verification operation module 127; the simulation verification operation module 127 is used to perform simulation verification on new schematic design files and printed circuit board design files, and output verification failure data when verification fails; the simulation fault analysis module 126 is used to analyze the verification failure data and generate fault analysis results; the simulation control module 125 is used to receive the fault analysis results and correct the hardware design simulation data and hardware design control instructions according to the fault analysis results.

[0080] In this embodiment, after the simulation verification execution module 127 reads the newly generated file from the design file storage unit 140, it automatically calls the built-in or integrated electrical rule checking, signal integrity simulation, and thermal simulation tools to perform multi-dimensional, configurable verification tests on the design file. When the verification results do not meet the preset performance, safety, or process standards, the module will automatically capture the violations, error logs, and key performance deviation data, and encapsulate them in a structured manner into a verification failure data packet. The simulation fault analysis module 126 then performs root cause analysis on the data packet, and through rule matching, pattern recognition, or causal reasoning, locates the source of the design defect that caused the fault (such as...). The system detects and generates a fault analysis report with a clear target, identifying issues such as schematic connection errors, component parameter mismatches, layout violations, or wiring conflicts. After receiving the analysis results, the simulation control module 125 automatically or assistedly calibrates the relevant parameters and constraints in the hardware design simulation data that caused the problem, based on preset correction strategies (such as parameter adjustment, logic reconstruction, and layout optimization). It also synchronously adjusts the corresponding operation steps or rule weights in the hardware design control instructions. The corrected data and instructions are fed back to the upstream of the design process, driving the system to perform iterative optimization and forming an intelligent closed loop of "design-verification-analysis-correction".

[0081] This implementation method deeply integrates the isolated and delayed verification and debugging steps in the traditional design process into an endogenous adaptive optimization mechanism, which significantly improves the reliability and maturity of the design and reduces the cost of manual debugging and iteration cycle.

[0082] like Figure 5 As shown, in one embodiment of this application, the hardware design data processing module 120 further includes: a simulation data storage unit 128, a data classifier 1291, and a data exporter 1292; the simulation verification running module 127 is further configured to store the verification success data in the simulation data storage unit 128 when the verification is successful; the data classifier 1291 is configured to read the verification success data from the simulation data storage unit 128 and classify it to obtain the classified verification success data; the data exporter 1292 is configured to export the classified verification success data to a specified storage location.

[0083] In this embodiment, the specified storage locations can be the third memory 230 and the fourth memory 240. After confirming that the design file has passed all verification checks, the simulation verification running module 127 automatically integrates the complete simulation report, performance parameters, pass rule list, and associated design context information into a structured verification success data package and stores it in the system's dedicated simulation data storage unit 128. This storage unit serves as a trusted design knowledge base and is organized and stored according to project, version, and data type. The data classifier 1291 then performs in-depth analysis and feature extraction on the successful data stored in the database, and automatically classifies and labels it according to preset classification dimensions (such as circuit function modules, performance levels, process nodes, key signal types, etc.) to generate a classified data set with metadata index. The data exporter 1292 serves as the data interface between the system and the external environment. According to user configuration or preset rules, it exports the classified data in a standardized format to the third memory 230 and the fourth memory 240, realizing the orderly archiving and cross-system sharing of design assets.

[0084] This implementation method constructs an automated management closed loop for design verification results, transforming successful verification data from temporary process documents into traceable and reusable high-value knowledge assets. This not only ensures the integrity and historical traceability of design data, but also provides a reliable data foundation for subsequent design reuse, quality analysis, process optimization, and compliance audits through intelligent classification and standardized export. This extends the value of a single design verification to the entire product lifecycle and organizational knowledge accumulation.

[0085] like Figure 6 As shown, in one embodiment of this application, the hardware design simulation generation module 132 includes: a simulation tool calling module 1321, a functional requirement control module 1322, and multiple drawing ports 1323; the functional requirement control module 1322 is used to receive and parse hardware design control instructions and generate calling control signals; the simulation tool calling module 1321 is used to receive hardware design simulation data and component package graphic data, and in response to the calling control signals, distribute the hardware design simulation data and component package graphic data to one of the called drawing ports (such as any one of 1323-1 to 1323-6) or multiple drawing ports 1323; the multiple drawing ports 1323 are used to perform specific circuit design drawing operations according to the received hardware design simulation data and component package graphic data to generate new schematic design files and printed circuit board design files.

[0086] In this embodiment, the functional requirement control module 1322 acts as the instruction hub, receiving and parsing the hardware design control instructions sent from upstream, decoding them into specific port call sequences, execution priorities, and data dependencies, and generating precise call control signals. The simulation tool call module 1321 acts as a data routing and execution coordinator. Upon receiving the call control signal, it unpacks and matches the synchronously received hardware design simulation data (defining electrical connections and constraints) and component package graphic data (defining physical forms) according to the signal indication, and distributes them to one or more corresponding target drawing ports. Each drawing port acts as... As a dedicated actuator, it encapsulates standardized operation logic for specific design tasks (such as drawing schematic symbols, placing components, routing traces, and defining board outlines). After receiving the distributed data, the drawing port converts it into a specific sequence of operation commands that can be recognized by the underlying EDA tools (such as schematic automation design toolkits and printed circuit board automation design toolkits), driving the tools to perform precise drawing actions. The outputs of multiple ports are coordinated in timing and aggregated by the simulation tool calling module 1321, and finally synthesized into a complete new schematic design file and printed circuit board design file that conforms to the design rules in memory or workspace.

[0087] This implementation method achieves efficient and reliable conversion from design intent to tool operation through a three-level collaborative architecture of "control parsing-data distribution-port execution". It decomposes complex automated drawing tasks into standardized and parallelizable sub-tasks, and ensures data consistency and operational atomicity through centralized scheduling. This improves generation efficiency while ensuring the correctness of output files and process compliance.

[0088] like Figure 6 As shown, in one embodiment of this application, the multiple drawing ports 1323 include: schematic architecture drawing port 1323-1, schematic module drawing port 1323-2, schematic component drawing port 1323-3, printed circuit board layout and package placement port 1323-4, printed circuit board wiring port 1323-5, and printed circuit board structure drawing port 1323-6.

[0089] In this embodiment, the schematic architecture drawing port 1323-1 is responsible for automatically creating the framework of the schematic drawing, setting the drawing attributes, and dividing the functional block hierarchy according to system instructions and top-level design data; the schematic module drawing port 1323-2 instantiates predefined functional circuit module symbols within the architecture framework based on modular design data and completes the signal interface connection between modules; the schematic component drawing port 1323-3 accurately places discrete component symbols in the drawing based on the component list and connection relationship data, and automatically labels the reference designator, parameter value, and package information.

[0090] During the printed circuit board (PCB) design phase, the PCB layout and package placement port 1323-4 receives data association and layout constraints from the schematic diagram. Within the defined board frame, it executes automatic or assisted layout algorithms to arrange component packages reasonably and optimize their position and orientation. The PCB routing port 1323-5 then automatically or interactively completes the connection of signal lines, optimizes routing paths, and handles high-speed design requirements such as differential pairs and equal lengths based on the layout, according to the electrical netlist and routing rules. The PCB structure drawing port 1323-6 defines or adjusts structural elements such as the board frame shape, mounting hole positions, keep-away zones, and process edges based on mechanical and manufacturing requirements.

[0091] This implementation method covers the entire key drawing operations from circuit logic expression to physical layout implementation through a set of fine-grained, specialized ports. Each port encapsulates the best practices and design rules for the corresponding design stage. It receives data and outputs standardized design elements through standardized interfaces, and works together to seamlessly convert abstract design data into professional-grade engineering design documents that can be directly used for production and manufacturing, ensuring the integrity, standardization and high quality of the design output.

[0092] As a more specific implementation, the functions of the multiple drawing ports 1323 in the aforementioned hardware design simulation generation module 132 are defined as follows:

[0093] The schematic architecture drawing port 1323-1 is used to call the architecture drawing function in the schematic automation design toolkit according to the control instructions sent by the hardware design simulation tool calling module 1321, to create the schematic drawing frame and hierarchical structure, and output the drawing frame data to the hardware design simulation tool calling module 1321.

[0094] The schematic module drawing port 1323-2 is used to call the module instantiation function in the schematic automation design toolkit according to the control instructions sent by the hardware design simulation tool calling module 1321, place and connect predefined functional circuit modules in the schematic, and output the module placement and connection data to the hardware design simulation tool calling module 1321.

[0095] The schematic component drawing port 1323-3 is used to call the component placement function in the schematic automation design toolkit according to the control instructions sent by the hardware design simulation tool calling module 1321, place discrete component symbols and configure their attributes (value, package, reference number, etc.), and output the component list and connection relationship data to the hardware design simulation tool calling module 1321.

[0096] The printed circuit board layout and package placement port 1323-4 is used to call the layout function in the printed circuit board automated design toolkit according to the control instructions sent by the hardware design simulation tool calling module 1321, to place the component packages reasonably in the printed circuit board frame, optimize the position and orientation, and output the component position and orientation data to the hardware design simulation tool calling module 1321.

[0097] The printed circuit board wiring port 1323-5 is used to call the wiring function in the printed circuit board automation design toolkit according to the control command sent by the hardware design simulation tool calling module 1321, complete the connection and optimization of the signal network according to the electrical rules, and output the wiring path and network connection data to the hardware design simulation tool calling module 1321.

[0098] The printed circuit board structure drawing port 1323-6 is used to call the structural functions in the printed circuit board automated design toolkit according to the control instructions sent by the hardware design simulation tool calling module 1321, define the printed circuit board outline, mechanical features and manufacturing-related elements, and output the outline definition and structural constraint data to the hardware design simulation tool calling module 1321.

[0099] like Figure 7 As shown in the embodiments of this application, a circuit design simulation method is also provided, the method comprising:

[0100] S11. Obtain functional requirement information and decompose the functional requirement information to obtain decomposed functional requirement data.

[0101] S12. Based on the decomposed functional requirements data, as well as the obtained existing schematic data, printed circuit board design parameters and component parameters, generate hardware design data and hardware design control instructions.

[0102] S13. Based on the hardware design control instructions and hardware design data, call the drawing port to generate new schematic design files and printed circuit board design files.

[0103] It should be understood that the use of terms such as "system," "device," "unit," and / or "module" in this application is merely one method of distinguishing different components, elements, parts, sections, or assemblies at different levels. However, if other terms can achieve the same purpose, they may be replaced by other expressions.

[0104] The embodiments in this specification are described in a progressive manner, with each embodiment focusing on the related aspects.

[0105] For any differences between the embodiments, or for the same or similar parts between the embodiments, please refer to each other.

[0106] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A circuit design simulation system, characterized in that, The system includes: a hardware requirement identification module, a hardware design data processing module, and a hardware design document generation module; The hardware requirement identification module is used to acquire functional requirement information and decompose the functional requirement information to obtain decomposed functional requirement data. The hardware design data processing module is used to generate hardware design data and hardware design control instructions based on the decomposed functional requirement data, as well as the acquired existing schematic data, printed circuit board design parameters and component parameters. The hardware design file generation module is used to call the drawing port and generate new schematic design files and printed circuit board design files according to the hardware design control instructions and the hardware design data. The hardware design data includes hardware design simulation data and component specification information, and the hardware design file generation module includes a component package generation module and a hardware design simulation generation module. The component package generation module is used to generate or call component package graphic data according to the component specification information. The hardware design simulation generation module is used to call the drawing port and generate new schematic design files and printed circuit board design files according to the hardware design control instructions, the hardware design simulation data and the component package graphic data. The hardware design data processing module includes: a hardware information extraction module, a data scheduling module, a simulation data parsing module, a simulation logic control programmer, and a simulation control module; The hardware information extraction module is used to extract component specification information from the component parameters and to extract schematic information from the existing schematic data. The data scheduling module is used to receive and schedule the decomposed functional requirement data and the schematic diagram information; The simulation data parsing module is used to parse the information output by the data scheduling module and generate parsed data; The simulation logic control programmer is used to generate control logic based on the information output by the data scheduling module; The simulation control module is used to integrate the parsed data with the control logic to generate hardware design simulation data and hardware design control instructions. The hardware design simulation generation module includes: a simulation tool calling module, a functional requirement control module, and multiple drawing ports; The functional requirement control module is used to receive and parse the hardware design control instructions and generate call control signals; The simulation tool calling module is used to receive the hardware design simulation data and the component package graphic data, and in response to the calling control signal, distribute the hardware design simulation data and the component package graphic data to one or more drawing ports that are called. The multiple drawing ports are used to perform specific circuit design drawing operations based on the received hardware design simulation data and component package graphic data, so as to generate the new schematic design file and printed circuit board design file.

2. The system according to claim 1, characterized in that, The system also includes: a design file storage unit; The hardware design simulation generation module is also used to store the new schematic design file and the printed circuit board design file to the design file storage unit.

3. The system according to claim 2, characterized in that, The hardware requirement identification module includes: a requirement information reader and a requirement function decomposer; The requirement information reader is used to acquire functional requirement information; The requirement function decomposer is used to perform structured decomposition and / or semantic parsing of the function requirement information to obtain the decomposed function requirement data.

4. The system according to claim 1, characterized in that, The hardware design data processing module also includes: a simulation fault analysis module and a simulation verification and operation module; The simulation verification running module is used to perform simulation verification on the new schematic design file and the printed circuit board design file, and output verification failure data when verification fails. The simulation fault analysis module is used to analyze the verification failure data and generate fault analysis results. The simulation control module is used to receive the fault analysis results and correct the hardware design simulation data and the hardware design control instructions based on the fault analysis results.

5. The system according to claim 4, characterized in that, The hardware design data processing module also includes: a simulation data storage unit, a data classifier, and a data exporter; The simulation verification operation module is also used to store the successful verification data to the simulation data storage unit when the verification is successful. The data classifier is used to read the successful verification data from the simulation data storage unit and classify it to obtain the classified successful verification data. The data exporter is used to export the categorized successful verification data to a specified storage location.

6. The system according to claim 1, characterized in that, The multiple drawing ports include: schematic architecture drawing port, schematic module drawing port, schematic component drawing port, printed circuit board layout and package placement port, printed circuit board wiring port, and printed circuit board structure drawing port.

7. A circuit design simulation method, characterized in that, The method includes: Obtain functional requirement information and decompose the functional requirement information to obtain decomposed functional requirement data; Extract component specification information from the obtained component parameters, and extract schematic information from the obtained existing schematic data; Receive and schedule the decomposed functional requirements data and the schematic diagram information; The scheduled information is parsed to generate parsed data. Control logic is generated based on the scheduled information; The parsed data and the control logic are integrated to generate hardware design simulation data and hardware design control instructions. Based on the component specification information, generate or call component package graphic data; Receive and parse the hardware design control instructions, and generate a call control signal; The system receives the hardware design simulation data and the component package graphic data, and in response to the call control signal, distributes the hardware design simulation data and the component package graphic data to one or more callable drawing ports. Based on the received hardware design simulation data and component package graphic data, the drawing ports perform specific circuit design drawing operations to generate the new schematic design file and printed circuit board design file.

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