Filter and manufacturing method thereof

Abstract

The invention provides a filter and a manufacturing method thereof. The method comprises the following steps: providing a piezoelectric composite substrate comprising a base layer and a piezoelectric layer, wherein a first area and a second area are arranged on the surface of the piezoelectric composite substrate; forming an interdigital transducer on the piezoelectric layer; forming a first passivation layer on the piezoelectric layer, wherein the first passivation layer extends to cover a part of the interdigital transducer adjacent to the interdigital transducer; and forming a welding pad covering the first passivation layer in a second region on the piezoelectric composite substrate, wherein the welding pad extends to the first region to cover a part of the interdigital transducer so as to be electrically connected with the interdigital transducer. On the basis, the manufacturing process of the piezoelectric layer is advanced before the manufacturing process of the interdigital transducer, the interdigital transducer is prevented from being corroded by chemical agents during LT PRS, and therefore the LT PRS process window is effectively expanded. In addition, the piezoelectric layer can be processed by adopting a wet etching process, a PI layer does not need to be arranged, the manufacturing process can be simplified, and the cost can be saved.

Description

Technical Field

[0001] This application relates to the field of filter technology, specifically to a filter and its manufacturing method. Background Technology

[0002] With the development of wireless communication technology and the intensification of competition in the consumer market, the miniaturization and low cost of filters such as POI SAW (Piezoelectric on Insulator Surface Acoustic Wave) filters have become a mainstream trend. A filter's substrate typically contains multiple traces, a piezoelectric layer, an interdigital transducer (IDT), and multiple pads (also called contact pads). The traces on the substrate connect to the pads, the piezoelectric layer converts electrical signals into surface acoustic waves through the piezoelectric effect and transmits them to the interdigital transducer, and the pads lead the interdigital transducer to the device surface through lead-out terminals.

[0003] In existing filters, the piezoelectric layer and interdigital transducers typically have openings formed by etching processes in the area beneath each pad. These openings, also known as "LT PRS (Photo Resist Stripping) windows" or "photoresist stripping windows," prevent microcracks in the piezoelectric layer. A PI (Polyimide) layer is also placed within these openings, with the pads positioned on the corresponding PI layer. The PI layer improves the pad's climbing ability, ensuring good electrical contact between the pad and the side of the piezoelectric layer. Since the interdigital transducer fabrication process precedes the piezoelectric layer process, the LT PRS (photoresist stripping) chemicals used in the etching process can corrode the interdigital transducers, leading to insufficient LT PRS process windows and affecting filter performance. Summary of the Invention

[0004] In view of this, this application provides a filter and a method for manufacturing the same, which can at least improve the problem of insufficient process window of LT PRS caused by chemical corrosion of interdigital transducers.

[0005] This application provides a method for manufacturing a filter, comprising: A piezoelectric composite substrate is provided, the piezoelectric composite substrate comprising a substrate layer and a piezoelectric layer, and a first region and a second region are disposed on the surface of the piezoelectric composite substrate; An interdigital transducer is formed on the piezoelectric layer; A first passivation layer is formed on the piezoelectric layer, and the first passivation layer extends to cover a portion of the interdigital transducer adjacent to the second region; A bonding pad covering the first passivation layer is formed in a second region on the piezoelectric composite substrate, and the bonding pad extends into the first region to cover a portion of the interdigital transducer for electrical connection with the interdigital transducer.

[0006] Optionally, before forming the interdigitated transducer on the piezoelectric layer, the method further includes: A photoresist layer located in the first region is formed on the piezoelectric layer; Using the photoresist layer in the first region as a mask, the piezoelectric layer is first etched by a wet etching process so that the piezoelectric layer near the edge of the first region forms an angle of less than 60° with the substrate layer. Remove the photoresist layer.

[0007] Optionally, the piezoelectric composite substrate further includes: The second sub-substrate layer is located between the base layer and the piezoelectric layer; After the first etching of the piezoelectric layer using a wet etching process, the method further includes: The second sub-substrate layer is at least partially etched by the second etching process, such that the second sub-substrate layer at the edge of the first region is at an angle of less than 60° to the base layer. A bonding pad covering the first passivation layer is formed in a second region on the piezoelectric composite substrate, including: A solder pad is formed in the etched area of ​​the second sub-substrate layer and covers the first passivation layer.

[0008] Optionally, the solution used in the wet etching process includes a mixed solution of HF / HNO3.

[0009] Optionally, the piezoelectric composite substrate further includes: The first sub-substrate layer is located between the base layer and the second sub-substrate layer; The first sub-substrate layer is not etched during the second etching process.

[0010] Optionally, the method further includes, A second passivation layer is formed on the solder pad, covering the solder pad; A third passivation layer is formed on the second passivation layer, covering the second passivation layer.

[0011] This application provides a filter, which is manufactured using any of the methods described above, and the filter includes: A piezoelectric composite substrate includes a substrate layer and a piezoelectric layer. A first region and a second region are disposed on the surface of the piezoelectric composite substrate, and the piezoelectric layer is disposed in the first region. Interdigitated transducers are disposed on the piezoelectric layer; A first passivation layer is disposed on the piezoelectric layer, and the first passivation layer extends to cover a portion of the adjacent second region of the interdigital transducer; A bonding pad is disposed on a second region of the piezoelectric composite substrate and covers the first passivation layer, and extends to the first region to cover a portion of the interdigital transducer for electrical connection with the interdigital transducer.

[0012] Optionally, the piezoelectric layer near the edge of the first region forms an acute angle with the substrate layer.

[0013] Optionally, the piezoelectric composite substrate includes a second sub-substrate layer located between the base layer and the piezoelectric layer; in the second region, the bonding pad is disposed on the second sub-substrate layer, and the second sub-substrate layer and the base layer are at an acute angle near the edge of the first region.

[0014] Optionally, the acute angle is less than 60°.

[0015] Optionally, the piezoelectric composite substrate further includes a first sub-substrate layer located between the base layer and the second sub-substrate layer, wherein the first sub-substrate layer is a structural layer with uniform thickness.

[0016] As described above, this application advances the piezoelectric layer fabrication process to before the interdigital transducer fabrication process, which can avoid the chemical agents during LT PRS (photoresist stripping) from corroding the interdigital transducer, thereby effectively expanding the LT PRS process window and ensuring the performance of the filter.

[0017] In addition, this application can use a wet etching process to process the piezoelectric layer to form the piezoelectric layer morphology after LT PRS, so that the piezoelectric layer near the edge of the first region has an angle of less than 60° with the substrate layer, so that the piezoelectric layer forms a relatively gentle slope, which serves the purpose of smoothing the solder pads, ensuring good contact between the solder pads and the sides of the piezoelectric layer, and improving structural strength, etc. Therefore, there is no need to set the PI layer originally used to improve the solder pads' slope capability, that is, the PI layer is a non-essential layer, which can simplify the process and save costs. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the structure of a filter provided in an embodiment of this application; Figure 2 This is a schematic flowchart of a filter manufacturing method provided in an embodiment of this application; Figure 3 This is a schematic diagram of a process for forming a piezoelectric layer provided in an embodiment of this application.

[0019] Filter 100, piezoelectric composite substrate 1, first region Z1, second region Z2, piezoelectric layer 2, interdigital transducer 3, first passivation layer 41, pad 5, second passivation layer 42, third passivation layer 43, substrate / silicon base layer 10, first sub-substrate layer 11, second sub-substrate layer 12. Detailed Implementation

[0020] To address the aforementioned problems in the prior art, this application provides a filter and its manufacturing method, which advances the piezoelectric layer fabrication process before the interdigital transducer fabrication process. This avoids corrosion of the interdigital transducer by chemical agents during LT PRS (photoresist stripping), effectively expanding the LT PRS process window and ensuring filter performance. The type of filter and the shape, number, and size of each structural layer can be adapted according to actual needs and are not limited in this application.

[0021] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly described below in conjunction with specific embodiments and corresponding drawings. Obviously, the embodiments described below are only a part of the embodiments of this application, and not all of them. Unless otherwise specified, the following embodiments and their technical features can be combined with each other, and also belong to the technical solutions of this application.

[0022] Figure 1 This is a schematic diagram of the structure of a filter provided in an embodiment of this application. It should be noted that... Figure 1 The image shown is only a portion of the filter's cross-sectional structure, not the entirety. For example... Figure 1 As shown, the filter 100 can be a POI SAW filter, including a piezoelectric composite substrate 1, an interdigital transducer 3, a first passivation layer 41, a pad 5, a second passivation layer 42, and a third passivation layer 43, wherein the piezoelectric composite substrate 1 includes at least a base layer 10 and a piezoelectric layer 2.

[0023] A first region Z1 and a second region Z2 are disposed on the surface of the piezoelectric composite substrate 1. The first region Z1 can be regarded as the region where the piezoelectric layer 2 is formed or disposed, and the second region Z2 can be the region other than the first region Z1, or the region other than the piezoelectric layer 2.

[0024] The piezoelectric composite substrate 1 has a two-layer or more structure, such as Figure 1When the structure design with two or more layers is shown, the piezoelectric composite substrate 1 may include a first sub-substrate layer 11 and a second sub-substrate layer 12 that are sequentially stacked between the base layer 10 and the piezoelectric layer 2. The base layer 10 may be a conventional silicon substrate 10. The first sub-substrate layer 11 and the second sub-substrate layer 12 are both full-surface structural layers covering the silicon substrate 10. The first sub-substrate layer 11 may be a trap-rich layer, i.e. a substrate layer made using trap-rich technology. The second sub-substrate layer 12 may be an oxide layer, including but not limited to a silicon monoxide layer (SiO layer) or a silicon dioxide layer (SiO2 layer). The thickness of these three layers can be adapted to the actual needs of the filter 100. For example, the silicon substrate 10 is a substrate layer with uniform thickness, and the first sub-substrate layer 11 is also a structural layer with uniform thickness, which can absorb stray electrons over a wider range and ensure the device performance of the entire filter 100. However, the second sub-substrate layer 12 has a uniform thickness in the first region Z1 but a non-uniform thickness in other regions. The maximum thickness of the first sub-substrate layer 11 and the second sub-substrate layer 12 can be equal and both less than the thickness of the silicon substrate 10. Figure 1 In the example, the thickness of the second sub-substrate layer 12 in the second region Z2 is less than the thickness in the first region Z1. Specifically, at the end of the second sub-substrate layer 12 facing the first region Z1, i.e., near the edge of the first region Z1, the second sub-substrate layer 12 forms an acute angle with the silicon substrate 10. This acute angle can be less than 60°. This acute angle ensures a more uniform and gradual transition in thickness from the first region Z1 to the second region Z2. This thickness design of the second sub-substrate layer 12 can be achieved through a wet etching process.

[0025] The piezoelectric layer 2 is not a single, continuous structural layer, but is only disposed on the substrate 1 (for example, it can be directly disposed on...). Figure 1 The piezoelectric layer morphology after LT PRS is formed in the first region Z1 (shown on the second sub-substrate 12) and the second region Z2. The piezoelectric layer 2 can be a lithium tantalate (LT) layer. Figure 1 In the example, the end of the piezoelectric layer 2 furthest from the first region Z1 is also set at an acute angle, for example, less than 60°. This acute angle can be caused by the formation of the piezoelectric layer 2 through a wet etching process. This acute angle makes the piezoelectric layer 2 form a relatively gentle slope, which serves to ensure a smooth slope for the solder pad 5 during the fabrication process, ensuring good contact between the solder pad 5 and the side of the piezoelectric layer 2, and improving the structural strength of the entire filter 100. Therefore, there is no need to set the PI layer originally used to improve the slope capability of the solder pad 5, that is, the PI layer is a non-essential layer, which can simplify the process and save costs.

[0026] The interdigital transducer (IDT) 3 is disposed on the piezoelectric layer 2; the interdigital transducer 3 does not completely cover the piezoelectric layer 2, but only covers a portion of the piezoelectric layer 2, as follows: Figure 1 As shown, the end of the piezoelectric layer 2 facing the second region Z2 (in) Figure 1 The right end of the piezoelectric layer 2 shown in the diagram is not aligned with the interdigital transducer 3, and the right end of the piezoelectric layer 2 extends beyond the right end of the interdigital transducer 3.

[0027] The first passivation layer 41 is disposed on the piezoelectric layer 2, in Figure 1 As shown in the right half, the first passivation layer 41 covers the right end of the piezoelectric layer 2 beyond the interdigital transducer 3, and the first passivation layer 41 also extends to cover a portion of the adjacent second region Z2 of the interdigital transducer 3. At this time, combined with... Figure 1 As shown, the first passivation layer 41 completely covers the piezoelectric layer 2, but partially covers the interdigital transducer 3. The portion of the interdigital transducer 3 not covered by the first passivation layer 41 is for electrical connection with the subsequently prepared pad 5.

[0028] The bonding pad 5 is disposed in the second region Z2 on the piezoelectric composite substrate 1, in Figure 1 In the scenario shown, in the second region Z2, the solder pad 5 is directly disposed on the second sub-substrate layer 12.

[0029] The solder pad 5 is also covered by the first passivation layer 41, whereby the first passivation layer 41 insulates and isolates the piezoelectric layer 2 from the solder pad 5. Please continue reading. Figure 1 As shown, the pad 5 also extends to the first region Z1 and covers a portion of the interdigital transducer 3 for electrical connection with the interdigital transducer 2, and the pad 5 leads the interdigital transducer 3 to the device surface through lead-out terminals.

[0030] The second passivation layer 42 covers the solder pad 5 and, as a full-surface structural layer, also covers the first passivation layer 41. The third passivation layer 43 is also a full-surface structural layer and covers the second passivation layer 42. In one example, the second passivation layer 42 and the third passivation layer 43 are made of different materials; for example, the second passivation layer 42 can be a silicon dioxide layer, and the third passivation layer 43 can be a silicon nitride layer. By covering the aforementioned structural element layers on the substrate 1 with these two passivation layers, at least double-layer sealing protection can be provided.

[0031] This application also provides a method for manufacturing a filter 100. Please refer to [link to relevant documentation]. Figure 2 As shown, the method further includes the following steps S1 to S7: S1: Provide a piezoelectric composite substrate, the piezoelectric composite substrate including a substrate layer and a piezoelectric layer, and a first region and a second region are disposed on the surface of the piezoelectric composite substrate.

[0032] The piezoelectric composite substrate can be a two-layer or more structure, forming a structure such as... Figure 1 When the structure has two or more layers as shown, step S1 can be manifested as: forming a substrate layer 10, a first sub-substrate layer 11, and a second sub-substrate layer 12 stacked sequentially; for example, firstly by chemical vapor deposition (CVD) or atomic layer deposition (ALD). The substrate layer 10 is formed by chemical vapor deposition (ALD). Chemical vapor deposition (CVD) is a widely used thin-film deposition technique. It involves introducing a gaseous precursor containing the target material into a reaction chamber, where it decomposes and deposits on the substrate surface at high temperature to form the substrate layer 10. This process offers advantages such as good film uniformity and the ability to produce large areas of substrate layer 10. Atomic layer deposition (ALD) is a self-defined layer-by-layer growth technique. It involves alternately introducing a precursor and an oxidant to form an atomically flat thin film on the substrate surface to obtain the substrate layer 10. This process allows for precise control of the thickness and composition of the substrate layer 10, making it suitable for manufacturing high-precision filter devices. The substrate layer 10 can be made of silicon, and is therefore referred to as the silicon substrate 10. Then, a first sub-substrate layer 11 and a second sub-substrate layer 12 are formed on the silicon substrate 10 using either chemical vapor deposition or ALD. Each of these layers is used to create a complete surface structure. It should be understood that the preparation process of each layer depends on the different materials used in each layer, and the above-described chemical vapor deposition process or atomic layer deposition process is only an example.

[0033] Combination Figure 3 As shown, this application also performs wet etching on the piezoelectric layer through the following steps S21 to S23.

[0034] S21. A photoresist layer located in the first region is formed on the piezoelectric layer.

[0035] Continue to combine Figure 1As shown, a photoresist layer is formed on an entire piezoelectric layer. Then, the entire photoresist layer is exposed using a photomask. This exposure process exposes the photoresist in the second region Z2 to ultraviolet light, while the photoresist in the first region Z1 is not exposed to ultraviolet light. The photoresist exposed to ultraviolet light can react chemically with the developer and dissolve in it, while the photoresist not exposed to ultraviolet light cannot react chemically with the developer and cannot dissolve in it. Thus, the photoresist in the second region Z2 is removed by the developer, leaving only the remaining photoresist on the piezoelectric layer in the first region Z1.

[0036] S22. The piezoelectric layer is first etched using an etching solution to remove the portion of the piezoelectric layer that is not covered by the photoresist layer.

[0037] Continue reading Figure 1 As shown, the piezoelectric layer located in the first region Z1 is covered by residual photoresist and will not react with the etching solution. However, the piezoelectric layer located in the second region Z2 is in direct contact with the etching solution and therefore undergoes an etching reaction, i.e., the first etching reaction, which removes the piezoelectric layer in the second region Z2, resulting in the desired piezoelectric layer 2. It should be noted that the etching solution is a fluid and therefore flows towards the first region Z1, thus reacting with the portion of the second region Z2 adjacent to the first region Z1. Ultimately, this causes the piezoelectric layer 2 to move away from the end of the first region Z1 (i.e., the end of the first region Z1). Figure 1 The right end of the piezoelectric layer 2 shown is set at an acute angle, which can be less than 60°. In one example, the etching solution includes a mixed solution of HF / HNO3.

[0038] S23. Remove the photoresist layer.

[0039] This S23 step can be called the LT PRS (photoresist stripping) process. After removing the residual photoresist layer, the piezoelectric layer 2 is exposed and belongs to the outermost surface of the current process device.

[0040] In other words, in the piezoelectric composite substrate provided in step S1, the piezoelectric layer can be a single-surface structure layer. The method of this application then performs a patterning process on this single-surface piezoelectric layer through the following steps: First, a photoresist layer located in the first region is formed on the piezoelectric layer. Then, using the photoresist layer in the first region as a mask, a wet etching process is used to perform a first etching on the piezoelectric layer, so that the piezoelectric layer near the edge of the first region forms an angle of less than 60° with the substrate layer. Finally, the photoresist layer is removed. Thus, the desired result is obtained... Figure 1 The piezoelectric layer 2 is shown. In one example, the solution used in the wet etching process includes a mixed solution of HF / HNO3.

[0041] S2: An interdigital transducer is formed on the piezoelectric layer.

[0042] In one example of this application, a metal electrode conforming to the required pattern can be directly formed on the piezoelectric layer 2 using a vapor deposition process, thereby obtaining the interdigital transducer 3.

[0043] In other examples, this application can first use magnetron sputtering to deposit a full-surface metal electrode layer (e.g., a molybdenum / aluminum material layer) on the surface of the piezoelectric layer 2. The magnetron sputtering process can ensure the uniformity and adhesion of the metal electrode layer, providing a basis for subsequent etching processes. Then, an etching process is used to remove the unwanted areas of the full-surface metal electrode layer. The specific areas can be determined according to product requirements, but they are all located within the first region Z1. After the etching process, the final retained portion of the metal electrode layer can be used as the finally obtained interdigital transducer 3.

[0044] S3: A first passivation layer is formed on the piezoelectric layer, and the first passivation layer extends to cover a portion of the second region adjacent to the interdigital transducer.

[0045] One example of this application is that a physical vapor deposition process can be used to deposit a passivation material on the surface of a device prepared in step S2, and then an etching process can be used to remove the unwanted areas of the passivation material, and the remaining part is the first passivation layer.

[0046] The material of the first passivation layer includes, but is not limited to, at least one of silicon dioxide and silicon nitride.

[0047] S4: A bonding pad covering the first passivation layer is formed in a second region on the piezoelectric composite substrate, and the bonding pad extends to the first region to cover a portion of the interdigital transducer for electrical connection with the interdigital transducer.

[0048] Combination Figure 1 As shown, the bonding pad 5 is essentially a metal electrode layer, or metal line, disposed in a preset area. Its material is conductive metal, which can be obtained using an etching process. For example, a whole surface of conductive metal is deposited on the device surface obtained in step S3. Then, a layer of photoresist is formed on the whole surface of conductive metal. This photoresist is then exposed and developed to obtain a photoresist with a preset pattern. Next, the whole surface of conductive metal is etched using an etching solution. Alternatively, a dry etching process can be used to etch the whole surface of conductive metal to remove the portion not covered by the photoresist. The remaining portion of the whole surface of conductive metal forms as shown in the image. Figure 1 The solder pad 5 is shown.

[0049] Optionally, after step S4, the method may further include steps S5 and S6.

[0050] S5: Form a second passivation layer on the solder pad covering the solder pad.

[0051] S6: A third passivation layer is formed on the second passivation layer, covering the second passivation layer.

[0052] Combination Figure 1 In the structural design shown, both the second passivation layer 42 and the third passivation layer 43 are integral structural layers, and therefore can be fabricated using a deposition process. For example, the second passivation layer 42 can be a silicon dioxide layer, which can be fabricated using a physical vapor deposition process, and the third passivation layer 43 can be a silicon nitride layer, which can be fabricated using a chemical vapor deposition process.

[0053] The use of step designations such as S1 and S2 in this document is intended to more clearly and concisely describe the corresponding content and does not constitute a substantial restriction on the order. In specific implementation, those skilled in the art may execute S2 first and then S1, etc., but these should all be within the protection scope of this application.

[0054] As described above, this application advances the piezoelectric layer fabrication process to before the interdigital transducer fabrication process, which can avoid the chemical agents during LT PRS (photoresist stripping) from corroding the interdigital transducer, thereby effectively expanding the LT PRS process window and ensuring the performance of the filter.

[0055] In addition, this application uses a wet etching process to process the piezoelectric layer to form the morphology of the piezoelectric layer after LT PRS, so that the piezoelectric layer near the edge of the first region has an angle of less than 60° with the substrate layer, so that the piezoelectric layer forms a relatively gentle slope, which serves the purpose of smoothing the solder pads, ensuring good contact between the solder pads and the sides of the piezoelectric layer, and improving structural strength. Therefore, there is no need to set the PI layer originally used to improve the solder pads' slope capability, that is, the PI layer is a non-essential layer, which can simplify the process and save costs.

[0056] Please continue reading. Figure 1As shown, for a piezoelectric composite substrate 1 including a silicon base layer 10, a first sub-substrate layer 11, and a second sub-substrate layer 12, after the piezoelectric layer 2 is formed in the first region Z1 of the piezoelectric composite substrate 1 through the first etching, the method may further include: at least partially etching the second sub-substrate layer 12 through a second etching, such that the second sub-substrate layer 12 near the edge of the first region Z1 forms an angle of less than 60° with the base layer 10, that is, the portion of the second sub-substrate layer 12 not covered by the piezoelectric layer 2 is partially etched by the second etching to thin it. In other words, the portion of the second sub-substrate layer 12 located in the second region Z2 is etched. Here, in step S4, a bonding pad 5 is formed in the etched area of ​​the second sub-substrate layer 12, and the bonding pad 5 covers the first passivation layer 41. Therefore, the lower part of the solder pad 5 contacts the second sub-substrate layer 12 of the silicon oxide layer, resulting in better adhesion. If it directly contacts the first sub-substrate layer 11, there is a risk of peeling later. When the second sub-substrate layer 12 is partially etched, the etched surface becomes rough, which is more conducive to improving adhesion. At the same time, the second sub-substrate layer 12 and the piezoelectric layer 2 form a relatively gentle slope on the same side, which is more conducive to the smooth slope of the solder pad 5 during the preparation of the solder pad 5, further ensuring good contact between the solder pad 5 and the side of the piezoelectric layer 2.

[0057] In this example, within the second region Z2, the silicon substrate 10 of the substrate 1 is still covered by the first sub-substrate layer 11 and the second sub-substrate layer 12 and is not directly exposed, so it will not directly contact the solder pad 5, thereby avoiding the risk of leakage caused by the solder pad 5 directly contacting the silicon substrate 10.

[0058] In the above example, both the second etching and the first etching use a photoresist layer as an etching barrier layer, which is used to prepare the etching process. Figure 1 The photoresist layer shown in piezoelectric layer 2 can specifically be the photoresist layer formed on the piezoelectric layer in the first region Z1 in the aforementioned step S21.

[0059] Combination Figure 1 As shown, the first sub-substrate layer 11 is not etched during the second etching process. Since the first sub-substrate 11 has the function of absorbing stray electrons, it can absorb more stray electrons over a wider range without being etched, thus ensuring the device performance of the entire filter 100.

[0060] The above description is only a part of the embodiments of this application and does not limit the patent scope of this application. For those skilled in the art, any equivalent structural transformations made using the content of this specification and drawings are similarly included within the patent protection scope of this application.

[0061] In the description of the embodiments of this application, the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing the technical solutions of the corresponding embodiments, and are not intended to indicate or imply that the device or element must have a specific orientation, or be constructed and operated in a specific orientation. They should not be construed as limitations on this application.

[0062] Although this document uses terms such as "first," "second," etc., to describe various types of information, this information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. Furthermore, the singular forms "a," "an," and "the" are intended to also include the plural forms. The terms "or" and "and / or" are interpreted as inclusive, or meaning either one or any combination thereof. Exceptions to this definition only arise when combinations of elements, functions, steps, or operations are inherently mutually exclusive in some way.

Claims

1. A method for manufacturing a filter, characterized in that, include: A piezoelectric composite substrate is provided, the piezoelectric composite substrate comprising a substrate layer and a piezoelectric layer, and a first region and a second region are disposed on the surface of the piezoelectric composite substrate; An interdigital transducer is formed on the piezoelectric layer; A first passivation layer is formed on the piezoelectric layer, and the first passivation layer extends to cover a portion of the interdigital transducer adjacent to the second region; A bonding pad covering the first passivation layer is formed in a second region on the piezoelectric composite substrate, and the bonding pad extends into the first region to cover a portion of the interdigital transducer for electrical connection with the interdigital transducer.

2. The method according to claim 1, characterized in that, Before forming the interdigitated transducer on the piezoelectric layer, the method further includes: A photoresist layer located in the first region is formed on the piezoelectric layer; Using the photoresist layer in the first region as a mask, the piezoelectric layer is first etched by a wet etching process so that the piezoelectric layer near the edge of the first region forms an angle of less than 60° with the substrate layer. Remove the photoresist layer.

3. The method according to claim 2, characterized in that, The piezoelectric composite substrate further includes: The second sub-substrate layer is located between the base layer and the piezoelectric layer; After the first etching of the piezoelectric layer using a wet etching process, the method further includes: The second sub-substrate layer is at least partially etched by the second etching process, such that the second sub-substrate layer at the edge of the first region is at an angle of less than 60° to the base layer. A bonding pad covering the first passivation layer is formed in a second region on the piezoelectric composite substrate, including: A solder pad is formed in the etched area of ​​the second sub-substrate layer and covers the first passivation layer.

4. The method according to claim 2 or 3, characterized in that, The wet etching process uses a solution comprising a mixture of HF and HNO3.

5. The method according to claim 3, characterized in that, The piezoelectric composite substrate further includes: The first sub-substrate layer is located between the base layer and the second sub-substrate layer; The first sub-substrate layer is not etched during the second etching process.

6. The method according to claim 1, characterized in that, It also includes, A second passivation layer is formed on the solder pad, covering the solder pad; A third passivation layer is formed on the second passivation layer, covering the second passivation layer.

7. A filter, characterized in that, The filter is prepared by the method described in any one of claims 1 to 6, and comprises: A piezoelectric composite substrate includes a substrate layer and a piezoelectric layer. A first region and a second region are disposed on the surface of the piezoelectric composite substrate, and the piezoelectric layer is disposed in the first region. Interdigitated transducers are disposed on the piezoelectric layer; A first passivation layer is disposed on the piezoelectric layer, and the first passivation layer extends to cover a portion of the adjacent second region of the interdigital transducer; A bonding pad is disposed on a second region of the piezoelectric composite substrate and covers the first passivation layer, and extends to the first region to cover a portion of the interdigital transducer for electrical connection with the interdigital transducer.

8. The filter according to claim 7, characterized in that, The piezoelectric layer near the edge of the first region forms an acute angle with the substrate layer.

9. The filter according to claim 7, characterized in that, The piezoelectric composite substrate includes a second sub-substrate layer located between the base layer and the piezoelectric layer; In the second region, the pad is disposed on the second sub-substrate layer, and the second sub-substrate layer and the base layer are at an acute angle near the edge of the first region.

10. The filter according to claim 8 or 9, characterized in that, The acute angle is less than 60°.

11. The filter according to claim 9, characterized in that, The piezoelectric composite substrate further includes a first sub-substrate layer located between the base layer and the second sub-substrate layer, wherein the first sub-substrate layer is a structural layer with uniform thickness.

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