Foreground calibration circuit of SARADC comparator input offset voltage

Abstract

The invention discloses a foreground calibration circuit for an input offset voltage of an SAR ADC comparator. The foreground calibration circuit comprises a power supply input circuit, an input geminate transistor circuit, a latch comparator, an SAR successive approximation register and a Res DAC resistance voltage division type digital-to-analog converter. The output end of the power input circuit is electrically connected with the power end of the input geminate transistor circuit; an analog input signal VIN and a reference voltage signal VREF are input into the input end of the input geminate transistor circuit, and the output end of the input geminate transistor circuit is electrically connected with two input ends of the latch comparator; the two output ends of the latch comparator are electrically connected with the input end of the SAR successive approximation register, and the output end of the SAR successive approximation register is electrically connected with the input end of the Res DAC resistance voltage division type digital-to-analog converter; the output end of the Res DAC resistance voltage division type digital-to-analog converter outputs a CALIP signal and a CALIN signal to a grid electrode of an adjusting tube in the input geminate transistor circuit, so that the adjusting tube generates compensation current to compensate the current difference of two input geminate transistors in the input geminate transistor circuit, and offset voltage is calibrated.

Description

Technical Field

[0001] This invention relates to the field of power electronics technology, and in particular to a foreground calibration circuit for the input offset voltage of a SARADC comparator. Background Technology

[0002] The input offset voltage VOS of a SAR ADC comparator is one of the core factors limiting the conversion accuracy of a SAR ADC, affecting both its static accuracy and dynamic performance. The comparator's input offset voltage is the "inherent bias voltage" that causes the output to flip. In a SAR ADC, the comparator is used to determine the relative magnitude of the input signal and the reference signal. VOS directly causes the comparator's decision threshold to shift; the comparator, which should flip at the input voltage VIN, will actually flip at VIN ± VOS. Traditional calibration structures include foreground calibration and background calibration. Foreground calibration involves changing the capacitors or current at the pull-up and pull-down positions of the latch comparator to compensate for the offset voltage. However, the comparator offset voltage is greatly affected by the input pair threshold voltage, and the adjustable range at the output is small; large-scale adjustment is costly. Background calibration typically uses autozero calibration, which is divided into IOS and OOS. IOS cannot completely eliminate the offset voltage, and OOS easily causes intermediate stage output overflow because autozero requires clock input, introducing additional noise that affects ADC performance. Summary of the Invention

[0003] Purpose of the invention: In order to overcome the shortcomings of the prior art, the present invention provides a foreground calibration circuit for the input offset voltage of a SARADC comparator. By introducing a feedback loop, offset detection, polarity determination, gate voltage adjustment and iterative convergence are automatically realized, thereby calibrating the offset voltage of the SAR ADC comparator.

[0004] Technical Solution: To achieve the above objectives, the present invention provides a foreground calibration circuit for the input offset voltage of a SARADC comparator, comprising a power input circuit, an input transistor pair circuit, a latch comparator, a SAR successive approximation register, and a Res DAC resistor divider digital-to-analog converter. The input terminal of the power input circuit is electrically connected to the output terminal of the IB current source, and the output terminal of the power input circuit is electrically connected to the power supply terminal of the input transistor pair circuit. The input terminal of the input transistor pair circuit receives an analog input signal VIN and a reference voltage signal VREF, and the output terminal of the input transistor pair circuit is electrically connected to the two input terminals of the latch comparator. The two output terminals of the latch comparator are electrically connected to the input terminals of the SAR successive approximation register, and the output terminal of the SAR successive approximation register is electrically connected to the input terminal of the Res DAC resistor divider digital-to-analog converter. The output terminal of the Res DAC resistor divider digital-to-analog converter outputs CALIP and CALIN signals to the gate of the regulating transistor in the input transistor pair circuit, causing the regulating transistor to generate a compensation current to compensate for the current difference between the two input transistors in the input transistor pair circuit, thereby calibrating the offset voltage.

[0005] Furthermore, the power input circuit includes transistors M3, M4, M5, M6, M7, and M8; the drain of transistor M3 serves as the input terminal of the power input circuit and is electrically connected to the output terminal of the IB current source; the source of transistor M3 is electrically connected to the drain of transistor M5; the gates of transistors M5 and M6 are both electrically connected to the drain of transistor M3; the gate of transistor M3 is electrically connected to the gate of transistor M4; the source of transistor M4 is electrically connected to the drain of transistor M6; the drain of transistor M4 is electrically connected to the drain of transistor M7, the gate of transistor M7, and the gate of transistor M8; and the drain of transistor M8 serves as the output terminal of the power input circuit.

[0006] Furthermore, the input transistor circuit includes an M1 input transistor pair, an M2 input transistor pair, an M9 transistor, and an M10 transistor; the gates of both the M1 and M2 input transistor pairs serve as the input terminals of the SAR ADC comparator, and the sources of both the M1 and M2 input transistor pairs serve as the power supply terminals of the input transistor circuit; the drain of the M1 input transistor pair is electrically connected to the drain of the M9 transistor, and the drain of the M2 input transistor pair is electrically connected to the drain of the M10 transistor; the drain of the M1 input transistor pair is electrically connected to the gates of the M9 and M10 transistors through a resistor R1, and the drain of the M2 input transistor pair is electrically connected to the gates of the M9 and M10 transistors through a resistor R2.

[0007] Furthermore, the input transistor circuit also includes an M11 regulating transistor and an M22 regulating transistor; the source of the M11 regulating transistor is electrically connected to the source of the M1 input transistor, and the drain of the M11 regulating transistor is electrically connected to the drain of the M1 input transistor; the source of the M22 regulating transistor is electrically connected to the source of the M2 input transistor, and the drain of the M22 regulating transistor is electrically connected to the drain of the M2 input transistor.

[0008] Furthermore, the gate of the M1 input transistor pair serves as the DACP terminal of the input transistor pair circuit, inputting the analog input signal VIN; the gate of the M2 input transistor pair serves as the DACN terminal of the input transistor pair circuit, inputting the reference voltage signal VREF; the drain of the M1 input transistor pair serves as the output terminal of the input transistor pair circuit, outputting the VIN_PRE signal; and the drain of the M2 input transistor pair serves as the output terminal of the input transistor pair circuit, outputting the VIP_PRE signal.

[0009] Furthermore, the positive input terminal of the latch comparator is electrically connected to the drain of the M2 input pair to receive the VIP_PRE signal, and the negative input terminal of the latch comparator is electrically connected to the drain of the M1 input pair to receive the VIN_PRE signal; the control terminal of the latch comparator receives the CLKC clock signal, the negative output terminal of the latch comparator outputs the CMP_OUTN signal, and the positive output terminal of the latch comparator outputs the CMP_OUTP signal.

[0010] Furthermore, the Res DAC resistor divider digital-to-analog converter includes a voltage divider resistor group; the two ends of the voltage divider resistor group are respectively input to voltages V_calmax and V_calmin; the voltage divider resistor group includes resistors R11 to R18, which are connected in series; the connection point of each pair of resistors is electrically connected to CAL_P through a control switch. <1> The terminals are connected, and each pair of resistors is electrically connected to CAL_N via a control switch. <1> Terminal, the CAL_P <1> End and CAL_N <1> All terminals serve as output terminals of the Res DAC resistor divider digital-to-analog converter.

[0011] Furthermore, the CAL_P <1> The terminal is electrically connected to the gate of the M11 regulating transistor, via CAL_P. <1> The gate of the M11 regulating transistor receives the CALIP signal; the CAL_N <1> The terminal is electrically connected to the gate of the M22 regulating transistor, via CAL_N. <1> A CALIN signal is input to the gate of the M22 regulating transistor.

[0012] Beneficial effects: The foreground calibration circuit for the input offset voltage of a SARADC comparator of the present invention, after processing the output of the latch comparator through the logic of the SAR successive approximation register, controls the control switch in the Res DAC resistor divider type digital-to-analog converter to input a voltage signal to the regulating transistor in the input pair circuit, generating a compensation current. The compensation current compensates for the current difference between the two input pairs to calibrate the offset voltage. Compared with the background calibration auto-zero calibration method, the calibration of the present invention does not introduce clock noise during normal operation. Compared with the foreground calibration method of applying current to the pull-up and pull-down transistors, the present invention moves the calibration offset voltage from the output terminal to the input terminal, resulting in a larger adjustment range and lower adjustment cost. Attached Figure Description

[0013] Figure 1 This is a circuit diagram of a single-stage SAR ADC comparator.

[0014] Figure 2 The circuit diagram shows a two-stage SAR ADC comparator.

[0015] Figure 3 Circuit diagram of the foreground calibration circuit for the input offset voltage of the SARADC comparator;

[0016] Figure 4 This is a structural diagram of the voltage divider resistor group in a Res DAC resistor divider digital-to-analog converter;

[0017] Figure 5 This is a diagram showing the change in the gate voltage of the two regulating transistors in the input transistor circuit.

[0018] Figure 6 The circuit diagram shows the foreground calibration circuit for the input offset voltage of the comparator of a SARADC with four regulating transistors. Detailed Implementation

[0019] The invention will now be further described with reference to the accompanying drawings.

[0020] like Figure 1 As shown, the offset voltage of the comparator has different effects on SAR ADCs with different structures. The core of a single-stage SAR ADC comparator is a single comparator plus a bit-by-bit iterative structure of a DAC (digital-to-analog converter), as shown in the figure. Figure 1 As shown, the comparator needs to determine the difference between the input signal and the output of the DAC digital-to-analog converter in each round of comparison; at this time, the offset voltage V OS This will directly cause a threshold shift in each round of comparisons, and this shift will accumulate in the final output. If the offset voltage V OS If the value is greater than 1 LSB, the least significant bit will be directly corrupted; if the offset voltage V OSA value of 0.5 LSB, while not causing code errors, will worsen the differential nonlinearity DNL, ​​shift the overall transfer characteristic curve, and introduce fixed zero-point error and nonlinearity error INL.

[0021] like Figure 2 As shown, the two-stage SAR ADC comparator adopts a cascaded structure of "coarse quantization + fine quantization", as shown in the figure. Figure 2 As shown, the preamplifier performs a coarse high-order measurement, and the subsequent stage performs a fine low-order measurement based on the residual from the preamplifier. A residual amplifier RA is typically included in between. At this time, the offset voltage V of the preamplifier comparator... OS More significant impact: pre-amplifier offset voltage V OS This will cause a deviation of 1 coarse code in the coarse quantization result, and the voltage range corresponding to the coarse code is relatively large. If the offset voltage of the preceding stage V OS Exceeding 1 LSB in coarse quantization will cause direct errors in the residual amplifier calculations, which cannot be corrected by even precise fine quantization in subsequent stages. Furthermore, the residual amplifier will amplify the offset of the preceding stage, with the amplification factor equal to the inter-stage gain, further worsening the effective offset of the input to the subsequent stage. The offset voltage V of the subsequent comparator... OS The impact is relatively limited because the subsequent stage only processes the residual signal, and its offset error is limited to the finely quantized LSB range, as long as the offset voltage V... OS A finer quantization of less than 1 LSB only affects the lowest few bits, and its impact on overall accuracy is far less than that of the preceding stage. The offset voltage V between the preceding and following stages is also significantly smaller. OS Individual calibration is required, which greatly increases the difficulty of calibration. Therefore, this invention proposes a foreground calibration circuit for the input offset voltage of a SAR ADC comparator to calibrate the offset voltage of the SAR ADC comparator.

[0022] like Figure 3As shown, a foreground calibration circuit for the input offset voltage of a SARADC comparator includes a power input circuit, an input transistor pair circuit, a latch comparator 1, a SAR successive approximation register 2, and a Res DAC resistor divider digital-to-analog converter 3. The input terminal of the power input circuit is electrically connected to the output terminal of an IB current source, and the output terminal of the power input circuit is electrically connected to the power supply terminal of the input transistor pair circuit. The input terminal of the input transistor pair circuit serves as the input terminal of the SAR ADC comparator, receiving an analog input signal VIN and a reference voltage signal VREF. The output terminal of the input transistor pair circuit is electrically connected to the two input terminals of the latch comparator 1. The two output terminals of the latch comparator 1 serve as the output terminals of the SAR ADC comparator, and the two output terminals of the latch comparator 1 are electrically connected to the input terminals of the SAR successive approximation register 2. The output terminal of the SAR successive approximation register 2 is electrically connected to the input terminal of the Res DAC resistor divider digital-to-analog converter 3. The output of the DAC resistor divider digital-to-analog converter 3 outputs CALIP and CALIN signals to the gate of the regulating transistor in the input transistor pair circuit. This causes the regulating transistor to generate a compensation current to compensate for the current difference between the two input transistors in the input transistor pair circuit, thereby calibrating the offset voltage. The two outputs of the latch comparator 1 are electrically connected to the two inputs of the SAR successive approximation register 2. The two outputs of the SAR successive approximation register 2 are electrically connected to the two inputs of the Res DAC resistor divider digital-to-analog converter 3. In other words, the outputs of the two outputs of the SAR successive approximation register 2 control all the control switches in the Res DAC resistor divider digital-to-analog converter 3.

[0023] The latch comparator 1 is the LTCH COMP in the figure, and the SAR successive approximation register is the SARLogic in the figure. SAR Logic represents successive approximation register logic. A preamplifier is added before the LTCH latch comparator 1. Before the ADC analog-to-digital converter starts working, the input terminal of the comparator is short-circuited. The comparator output result is fed back to the series resistor group in the Res DAC resistor divider type digital-to-analog converter 3 to adjust the gate voltage of the two input transistor pairs, thereby changing the current across the NP terminals of the SAR ADC comparator and compensating for the offset voltage equivalent to the input terminal of the SAR ADC comparator; thus, offset voltage calibration is achieved. The SAR ADC comparator is the comparator in the SAR ADC successive approximation register type analog-to-digital converter; the input transistor pair circuit is the preamplifier. For example, the M1 input transistor pair and the M2 input transistor pair are connected to the upper plate of the capacitor array in the SAR ADC successive approximation register type analog-to-digital converter, with the M1 input transistor pair as the P terminal and the M2 input transistor pair as the N terminal.

[0024] like Figure 3As shown, the power input circuit includes transistors M3, M4, M5, M6, M7, and M8. The drain of transistor M3 serves as the input terminal of the power input circuit and is electrically connected to the output terminal of the IB current source. The source of transistor M3 is electrically connected to the drain of transistor M5. The gates of transistors M5 and M6 are both electrically connected to the drain of transistor M3. The gate of transistor M3 is electrically connected to the gate of transistor M4. The source of transistor M4 is electrically connected to the drain of transistor M6. The drain of transistor M4 is electrically connected to the drain, gate, and gate of transistor M7 and transistor M8. The drain of transistor M8 serves as the output terminal of the power input circuit. The gate of transistor M3 and the gate of transistor M4 are biased by voltage VBN. The sources of transistors M5 and M6 are grounded, i.e., electrically connected to VSS. The sources of transistors M7 and M8 are electrically connected to the output of the power supply, i.e., electrically connected to the VDD power supply. Transistors M3, M4, M5, and M6 are all NMOS transistors, while transistors M7 and M8 are both PMOS transistors.

[0025] like Figure 3 As shown, the input transistor circuit includes an M1 input transistor pair, an M2 input transistor pair, an M9 transistor, and an M10 transistor. The gates of the M1 and M2 input transistor pairs serve as the input terminals of the SAR ADC comparator, and the sources of the M1 and M2 input transistor pairs serve as the power supply terminals of the input transistor circuit. The sources of the M1 and M2 input transistor pairs are electrically connected to the drain of the M8 transistor. The drain of the M1 input transistor pair is electrically connected to the drain of the M9 transistor, and the drain of the M2 input transistor pair is electrically connected to the drain of the M10 transistor. The drain of the M1 input transistor pair is electrically connected to the gates of the M9 and M10 transistors through a resistor R1, and the drain of the M2 input transistor pair is electrically connected to the gates of the M9 and M10 transistors through a resistor R2. The drain of the M1 input pair is electrically connected to one end of the resistor R1, the drain of the M2 input pair is electrically connected to one end of the resistor R2, and the other ends of the resistors R1 and R2 are electrically connected; the source of the M9 transistor and the source of the M10 transistor are grounded, which is electrically connected to VSS; the M1 input pair, M2 input pair, M11 regulating transistor, and M22 regulating transistor can all be PMOS transistors, while the M9 transistor and M10 transistor are both NMOS transistors.

[0026] like Figure 3As shown, the input transistor circuit further includes an M11 regulating transistor and an M22 regulating transistor; the source of the M11 regulating transistor is electrically connected to the source of the M1 input transistor, and the drain of the M11 regulating transistor is electrically connected to the drain of the M1 input transistor; the source of the M22 regulating transistor is electrically connected to the source of the M2 input transistor, and the drain of the M22 regulating transistor is electrically connected to the drain of the M2 input transistor; the sources of the M11 and M22 regulating transistors are electrically connected to the drain of the M8 transistor. This results in the M11 regulating transistor being connected in parallel with the M1 input transistor, and the M22 regulating transistor being connected in parallel with the M2 input transistor.

[0027] The gate of the M1 input transistor pair serves as the DACP terminal of the input transistor pair circuit, inputting the analog input signal VIN. The gate of the M2 input transistor pair serves as the DACN terminal of the input transistor pair circuit, inputting the reference voltage signal VREF, which is a successive approximation reference voltage. The DACP and DACN terminals of the input transistor pair circuit serve as the two input terminals of the SAR ADC comparator. The drain of the M1 input transistor pair serves as the output terminal of the input transistor pair circuit, outputting the VIN_PRE signal, and the drain of the M2 input transistor pair serves as the output terminal of the input transistor pair circuit, outputting the VIP_PRE signal.

[0028] The positive input of latch comparator 1 is electrically connected to the drain of the M2 input pair to receive the VIP_PRE signal, and the negative input of latch comparator 1 is electrically connected to the drain of the M1 input pair to receive the VIN_PRE signal. The control terminal of latch comparator 1 receives the CLKC clock signal, the negative output terminal of latch comparator 1 outputs the CMP_OUTN signal, and the positive output terminal of latch comparator 1 outputs the CMP_OUTP signal. Both the positive and negative output terminals of latch comparator 1 serve as output terminals of the SAR ADC comparator, and the CMP_OUTN and CMP_OUTP signals output by latch comparator 1 serve as output signals of the SAR ADC comparator. Simultaneously, the output CMP_OUTN and CMP_OUTP signals are input to the input terminals of the SAR successive approximation register 2.

[0029] like Figure 4As shown, the Res DAC resistor divider digital-to-analog converter 3 includes a voltage divider resistor group; the two ends of the voltage divider resistor group are respectively input to voltages V_calmax and V_calmin, where V_calmax is the VDD voltage and V_calmin is the VSS voltage; the voltage divider resistor group includes resistors R11 to R18, which are connected in series; the connection point of each pair of resistors is electrically connected to CAL_P through a control switch. <1> The terminals are connected, and each pair of resistors is electrically connected to CAL_N via a control switch. <1> Terminal, the CAL_P <1> End and CAL_N <1> All terminals are used as output terminals of the Res DAC resistor divider digital-to-analog converter 3.

[0030] like Figure 4 As shown, one end of resistor R11 serves as one end of a voltage divider resistor group, receiving the input voltage V_calmax; the other end of resistor R11 is electrically connected to one end of resistor R12, the other end of resistor R12 is electrically connected to one end of resistor R13, the other end of resistor R13 is electrically connected to one end of resistor R14, the other end of resistor R14 is electrically connected to one end of resistor R15, the other end of resistor R15 is electrically connected to one end of resistor R16, the other end of resistor R16 is electrically connected to one end of resistor R17, the other end of resistor R17 is electrically connected to one end of resistor R18, and the other end of resistor R18 serves as the other end of a voltage divider resistor group, receiving the input voltage V_calmin; the connection point between the other end of resistor R11 and one end of resistor R12 is electrically connected to CAL_P via a control switch. <1> The connection point between the other end of resistor R11 and one end of resistor R12 is electrically connected to CAL_N via a control switch. <1> Terminal; similarly, the other end of resistor R17 is electrically connected to one end of resistor R18, and the connection point is electrically connected to CAL_P via a control switch. <1> One end of resistor R17 is electrically connected to one end of resistor R18, and the connection point is electrically connected to CAL_N via a control switch. <1> Terminal. All control switches in the Res DAC resistor divider digital-to-analog converter 3 are controlled to close or open via the output signal of the SAR successive approximation register 2.

[0031] The CAL_P <1> The terminal is electrically connected to the gate of the M11 regulating transistor, via CAL_P. <1> A CALIP voltage signal is input to the gate of the M11 regulating transistor, and the gate voltage of the M11 regulating transistor is changed by changing the CALIP voltage signal; the CAL_N <1> The terminal is electrically connected to the gate of the M22 regulating transistor, via CAL_N. <1> A CALIN voltage signal is input to the gate of the M22 regulating transistor, and the gate voltage of the M22 regulating transistor is changed by changing the CALIN voltage signal.

[0032] The input offset voltage V of the SAR ADC comparatorOS Defined as the compensation voltage that needs to be applied to the input terminal to make the output zero or the flip threshold centered. Its core source is the process mismatch of the input differential pair transistors, and the process mismatch of the load transistor equivalent to the input, specifically manifested as mismatch in threshold voltage, width-to-length ratio, and channel resistance. These mismatches will cause the drain currents of the two NP input pairs in the SAR ADC comparator to be unequal when the two input pairs have the same input voltage. The calculation process for the difference in drain current between the two input pairs is as follows:

[0033]

[0034] In the formula, I is the difference between the drain currents of the two input transistor pairs. D1 I is the drain current of the input pair of transistors M1. D2 The drain current of the input pair of transistors is M2; after being amplified by the load, the output deviates from the ideal state. At this time, a voltage V needs to be applied to the input terminal. GS Only then can the difference in drain current between the two input transistor pairs be offset. .

[0035] The difference in drain current between the two input transistor pairs The transconductance of the input pair transistors generates an offset voltage V. OS Offset voltage V OS The calculation process is as follows:

[0036]

[0037] In the formula, gm is the transconductance of the two differential input pairs, namely the transconductance of input pairs M1 and M2; the more severe the mismatch, the greater the offset voltage V. OS The larger the value, typically in the mV range, the more precise the comparator needs to calibrate the mismatch voltage to the μV level.

[0038] To compensate for the difference in drain current between the two input pairs of transistors Small-sized regulating transistors M11 and M22 are connected in parallel next to the input pairs M1 and M2. These two regulating transistors are of the same type as the two input pairs, and their gates are connected to an adjustable voltage V. G1a and V G2a The adjustable voltage V G1a and V G2a The CALIP and CALIN voltage signals are output from the Res DAC resistor divider digital-to-analog converter 3; the adjustable voltage V G1a and voltage V G2a The stepped voltage output from the Res DAC resistor divider digital-to-analog converter 3 controls the Res DAC resistor divider digital-to-analog converter 3 as follows: Figure 4 As shown; the current generated by the two regulating transistors compensates for the current difference between the two input transistor pairs. Assume the current difference between the input transistor pairs... At this time, two regulating tubes are needed to generate reverse compensation current. This makes the total current difference zero; the process is shown below:

[0039]

[0040]

[0041] In the formula, I D1a I is the drain current of the M11 regulating transistor. D2a This refers to the drain current of the M22 regulating transistor; The reverse compensation current is obtained by combining the drain currents of the M11 and M22 regulating transistors. The M1 and M2 input pairs have the same dimensions, as do the M11 and M22 regulating transistors. A larger width-to-length ratio for the M11 and M22 regulating transistors results in a larger current change for the same gate voltage variation. A larger width-to-length ratio also results in a wider adjustment range for Vos, but lower adjustment accuracy; conversely, a smaller width-to-length ratio results in a smaller adjustment range for Vos, but higher adjustment accuracy. The selection of the dimensions of the M11 and M22 regulating transistors primarily considers the adjustment range and accuracy of Vos and the range of the voltage generated by the Res DAC resistor divider digital-to-analog converter 3.

[0042] The drain current of the two regulating transistors can be changed by altering the gate voltages of regulating transistors M11 and M22. The gate voltages of the two regulating transistors are controlled by the CALIN and CALIP voltage signals output from the Res DAC resistor divider digital-to-analog converter 3. The magnitudes of the CALIN and CALIP voltage signals are generated by controlling the closing or opening of the control switch in the Res DAC resistor divider digital-to-analog converter 3 through the output signal of the SAR successive approximation register 2. The SAR successive approximation register 2 obtains its output signal based on the signals output from the two output terminals of the receive latch comparator 1 through successive approximation register logic processing.

[0043] like Figure 5As shown, a foreground calibration circuit for the input offset voltage of a SAR ADC comparator is presented. Actual calibration requires a feedback loop for automation, involving four steps: offset detection, polarity determination, gate voltage adjustment, and iterative convergence. When the two inputs of the SAR ADC comparator are shorted, the ideal output should randomly flip or stabilize at a mid-level. However, due to mismatch, the output will stabilize at either a high or low level. The output state is recorded by a latch in the SAR successive approximation register 2 for polarity determination. This register then controls the control switch in the Res DAC resistor divider digital-to-analog converter to close or open, achieving fixed compensation for each adjustment. Each time the gate voltages of the two regulating transistors are adjusted, the comparator's output state is re-detected until the output randomly flips or jitters near a threshold when the input is shorted, thus reducing the offset voltage V. OS It is calibrated to the minimum, at this time .

[0044] like Figure 5 As shown in the diagram, the left figure illustrates that when the input equivalent Voss difference is relatively small, the gate voltage of the regulating transistor is initially set to two voltages with a significant phase difference. Because the equivalent Voss is small, the two gate voltages gradually converge. The comparison stops when the results of two consecutive flips are different. At this point, the reverse Voss caused by the difference in gate voltage is approximately considered as the input equivalent Voss. The right figure illustrates that when the input equivalent Voss difference is relatively large, the gate voltage of the regulating transistor will not converge to the same value and will fluctuate around a certain voltage. At this point, the reverse Voss caused by the difference in gate voltage is approximately considered as the input equivalent Voss.

[0045] Example

[0046] like Figure 6 As shown, the output terminal of the Res DAC resistor divider digital-to-analog converter 3 outputs CALIP and CALIN signals to the gates of the four regulating transistors in the input transistor pair circuit, so that the four regulating transistors generate compensation current to compensate the current difference between the two input transistors in the input transistor pair circuit, thereby achieving calibration of the offset voltage.

[0047] The input transistor circuit includes an M1 input transistor pair, an M2 input transistor pair, an M9 transistor, an M10 transistor, an M11 regulating transistor, an M22 regulating transistor, an M33 regulating transistor, and an M44 regulating transistor. The gates of the M1 and M2 input transistor pairs serve as the input terminals of the SARADC comparator, and the sources of the M1 and M2 input transistor pairs serve as the power supply terminals of the input transistor circuit. The sources of the M1 and M2 input transistor pairs are electrically connected to the drain of the M8 transistor. The drain of the M1 input transistor pair is electrically connected to the drain of the M9 transistor, and the drain of the M2 input transistor pair is electrically connected to the drain of the M10 transistor. The drain of the M1 input transistor pair is electrically connected to the gates of the M9 and M10 transistors through a resistor R1, and the drain of the M2 input transistor pair is electrically connected to the gates of the M9 and M10 transistors through a resistor R2. The drain of the M1 input pair is electrically connected to one end of the resistor R1, the drain of the M2 input pair is electrically connected to one end of the resistor R2, and the other ends of the resistors R1 and R2 are electrically connected; the source of the M9 transistor and the source of the M10 transistor are grounded, which is electrically connected to VSS.

[0048] The source of the M11 regulating transistor is electrically connected to the source of the M1 input pair, and the drain of the M11 regulating transistor is electrically connected to the drain of the M1 input pair. The source of the M22 regulating transistor is electrically connected to the source of the M2 input pair, and the drain of the M22 regulating transistor is electrically connected to the drain of the M2 input pair. The source of the M33 regulating transistor is electrically connected to the drain of the M9 transistor, and the drain of the M33 regulating transistor is electrically connected to the source of the M9 transistor. The source of the M44 regulating transistor is electrically connected to the drain of the M10 transistor, and the drain of the M44 regulating transistor is electrically connected to the source of the M10 transistor. The sources of the M11 and M22 regulating transistors are electrically connected to the drain of the M8 transistor. This results in the M11 regulating transistor being connected in parallel with the M1 input pair, the M22 regulating transistor being connected in parallel with the M2 input pair, the M33 regulating transistor being connected in parallel with the M9 transistor, and the M44 regulating transistor being connected in parallel with the M10 transistor. The input pair M1, input pair M2, regulating transistor M11, regulating transistor M22, regulating transistor M33, and regulating transistor M44 can all be PMOS transistors, while transistors M9 and M10 are both NMOS transistors.

[0049] The CAL_P <1> The gates of the M11 and M33 regulating transistors are electrically connected via CAL_P. <1> A CALIP voltage signal is input to the gates of the M11 and M33 regulating transistors, and the gate voltages of the M11 and M33 regulating transistors are changed by changing the CALIP voltage signal; the CAL_N <1> The gates of the M22 and M44 regulating transistors are electrically connected by CAL_N. <1> A CALIN voltage signal is input to the gates of the M22 and M44 regulating transistors. By changing the CALIN voltage signal, the gate voltages of the M22 and M44 regulating transistors are changed. At this time, the ResDAC resistor divider type digital-to-analog converter 3 can control whether to input voltage signals to the gates of the M11, M22, M33, and M44 regulating transistors. For example, only the M11 regulating transistor can be input, while the M22, M33, and M44 regulating transistors are not; or only the M11 and M22 regulating transistors can be input, while the M33 and M44 regulating transistors are not. A control switch can be installed on the connecting wire between the output terminal of the ResDAC resistor divider type digital-to-analog converter 3 and the gates of the M11, M22, M33, and M44 regulating transistors to control whether to input voltage signals to their gates.

[0050] To compensate for the difference in drain current between the two input pairs of transistors Small-sized regulating transistors M11 and M22 are connected in parallel next to input transistors M1 and M2. These regulating transistors are of the same type as the two input transistor pairs. Small-sized regulating transistors M33 and M44 are connected in parallel next to transistors M9 and M10. These regulating transistors are of the same type as transistors M9 and M10. Transistors M9 and M10 both serve as load transistors. The gates of all four regulating transistors are connected to different potentials at the output of the Res DAC resistor divider digital-to-analog converter 3. The current generated by the regulating transistors compensates for the current difference between the two input transistor pairs. Assuming the current difference between the input transistor pairs… At this time, four regulating transistors are needed to generate reverse compensation current. This makes the total current difference zero.

[0051] Four regulating transistors, M11 to M44, are connected in parallel across the input pair and the load transistor, respectively. The gate voltage of the regulating transistors is generated by the Res DAC resistor divider digital-to-analog converter 3. Changes in the gate voltage alter their conduction current, thereby affecting the current balance of the amplifier's input stage, thus compensating for the current difference between the two input pairs and achieving offset compensation. The larger the gate voltage, the stronger the compensation capability of the regulating transistor and the greater the compensation amount. To simultaneously consider compensation accuracy and compensation range, a hierarchical compensation logic is proposed. The four regulating transistors are designed according to "range from large to small, accuracy from low to high," forming a hierarchical system of "coarse adjustment - medium adjustment - fine adjustment - micro adjustment." This is because a single regulating transistor cannot simultaneously meet the requirements of wide range and high accuracy. The larger the range, the larger the minimum step size, and the lower the accuracy. However, using them in combination can balance both. The larger regulating transistor quickly reduces large offsets, while the smaller regulating transistor precisely eliminates residual errors.

[0052] The selection of the regulating tube size should comprehensively consider both the regulating range and the regulating accuracy. The regulating range and regulating step size should be set as follows: M11 regulating tube: regulating range ±30mV, minimum step size 5mV, coarse adjustment covering the maximum error; M22 regulating tube: regulating range ±15mV, minimum step size 2mV, medium-coarse adjustment; M33 regulating tube: regulating range ±8mV, minimum step size 1mV, fine adjustment; M44 regulating tube: regulating range ±3mV, minimum step size 0.2mV, fine adjustment, highest accuracy.

[0053] When performing graded offset measurements, the initial offset is first measured using the coarse-adjustment M11 regulating transistor. All other three regulating transistors are disconnected. The original offset voltage, denoted as Vos_raw, is calculated using the codeword generated during the M11 regulating transistor calibration process; this represents the range of the coarse-adjustment measurement. For example, if the measurement result is Vos_raw = +42mV, it means that a compensation of -42mV is needed to bring the offset to zero. The compensation direction of the M11 regulating transistor is determined based on the polarity of Vos_raw: if Vos_raw is positive, the M11 regulating transistor needs to output negative compensation; if it is negative, the M11 regulating transistor needs to output positive compensation.

[0054] Based on the output codeword of the M11 regulating transistor, select a combination of regulating transistors whose total adjustment range covers the value and whose minimum step size meets the target accuracy. Specifically, there are four cases: 1. When the coarse adjustment measurement range is greater than the range that the M22 regulating transistor can measure, select a combination of M22 and M33 regulating transistors. 2. When the coarse adjustment measurement range is greater than the range that the M33 regulating transistor can measure but less than the range that the M22 regulating transistor can measure, select a combination of M22, M33, and M44 regulating transistors, with the M44 regulating transistor used to precisely cover the remaining error. 3. When the coarse adjustment measurement range is greater than the range that the M44 regulating transistor can measure but less than the range that the M33 regulating transistor can measure, select a combination of M33 and M44 regulating transistors. 4. When the coarse adjustment measurement range is less than the range that the M44 regulating transistor can measure, select a combination of M33 and M44 regulating transistors or separate compensation for the M44 regulating transistor. Write the final determined regulating transistor combination parameters and the DAC control code of the regulating transistors into the latch. Maintain the calibration codeword before the next power-on, ensuring the circuit maintains a low offset during normal operation.

[0055] The above description is merely a preferred embodiment of the present invention. Those skilled in the art can make several modifications and optimizations based on the above disclosure without departing from the basic principles described above. These modifications and optimizations should be considered within the scope of protection as understood by the present invention.

Claims

1. A foreground calibration circuit for the input offset voltage of a SARADC comparator, characterized in that: The circuit includes a power input circuit, an input transistor pair circuit, a latch comparator (1), a SAR successive approximation register (2), and a Res DAC resistor divider digital-to-analog converter (3). The input terminal of the power input circuit is electrically connected to the output terminal of the IB current source, and the output terminal of the power input circuit is electrically connected to the power supply terminal of the input transistor pair circuit. The input terminal of the input transistor pair circuit receives the analog input signal VIN and the reference voltage signal VREF, and the output terminal of the input transistor pair circuit is electrically connected to the two input terminals of the latch comparator (1). The two output terminals of the latch comparator (1) are electrically connected to the input terminals of the SAR successive approximation register (2), and the output terminal of the SAR successive approximation register (2) is electrically connected to the input terminal of the Res DAC resistor divider digital-to-analog converter (3). The output terminal of the Res DAC resistor divider digital-to-analog converter (3) outputs the CALIP signal and the CALIN signal to the gate of the regulating transistor in the input transistor pair circuit, so that the regulating transistor generates a compensation current to compensate the current difference between the two input transistors in the input transistor pair circuit, thereby calibrating the offset voltage.

2. The foreground calibration circuit for the input offset voltage of a SARADC comparator according to claim 1, characterized in that: The power input circuit includes transistors M3, M4, M5, M6, M7, and M8. The drain of transistor M3 serves as the input terminal of the power input circuit and is electrically connected to the output terminal of the IB current source. The source of transistor M3 is electrically connected to the drain of transistor M5. The gates of transistors M5 and M6 are both electrically connected to the drain of transistor M3. The gate of transistor M3 is electrically connected to the gate of transistor M4. The source of transistor M4 is electrically connected to the drain of transistor M6. The drain of transistor M4 is electrically connected to the drain, gate, and gate of transistor M7 and transistor M8. The drain of transistor M8 serves as the output terminal of the power input circuit.

3. The foreground calibration circuit for the input offset voltage of a SARADC comparator according to claim 1, characterized in that: The input transistor circuit includes an M1 input transistor pair, an M2 input transistor pair, an M9 transistor, and an M10 transistor. The gates of both the M1 and M2 input transistor pairs serve as the input terminals of the SAR ADC comparator, and the sources of both the M1 and M2 input transistor pairs serve as the power supply terminals of the input transistor circuit. The drain of the M1 input transistor pair is electrically connected to the drain of the M9 transistor, and the drain of the M2 input transistor pair is electrically connected to the drain of the M10 transistor. The drain of the M1 input transistor pair is electrically connected to the gates of the M9 and M10 transistors through a resistor R1, and the drain of the M2 input transistor pair is electrically connected to the gates of the M9 and M10 transistors through a resistor R2.

4. The foreground calibration circuit for the input offset voltage of a SARADC comparator according to claim 3, characterized in that: The input transistor circuit further includes an M11 regulating transistor and an M22 regulating transistor; the source of the M11 regulating transistor is electrically connected to the source of the M1 input transistor, and the drain of the M11 regulating transistor is electrically connected to the drain of the M1 input transistor; the source of the M22 regulating transistor is electrically connected to the source of the M2 input transistor, and the drain of the M22 regulating transistor is electrically connected to the drain of the M2 input transistor.

5. The foreground calibration circuit for the input offset voltage of a SARADC comparator according to claim 3, characterized in that: The gate of the M1 input transistor pair serves as the DACP terminal of the input transistor pair circuit, inputting the analog input signal VIN. The gate of the M2 input transistor pair serves as the DACN terminal of the input transistor pair circuit, inputting the reference voltage signal VREF. The drain of the M1 input transistor pair serves as the output terminal of the input transistor pair circuit, outputting the VIN_PRE signal. The drain of the M2 input transistor pair serves as the output terminal of the input transistor pair circuit, outputting the VIP_PRE signal.

6. The foreground calibration circuit for the input offset voltage of a SARADC comparator according to claim 5, characterized in that: The positive input terminal of the latch comparator (1) is electrically connected to the drain of the M2 input pair to receive the VIP_PRE signal, and the negative input terminal of the latch comparator (1) is electrically connected to the drain of the M1 input pair to receive the VIN_PRE signal; the control terminal of the latch comparator (1) receives the CLKC clock signal, the negative output terminal of the latch comparator (1) outputs the CMP_OUTN signal, and the positive output terminal of the latch comparator (1) outputs the CMP_OUTP signal.

7. The foreground calibration circuit for the input offset voltage of a SARADC comparator according to claim 1, characterized in that: The Res DAC resistor divider digital-to-analog converter (3) includes a voltage divider resistor group; the two ends of the voltage divider resistor group are respectively input to the voltage V_calmax and the voltage V_calmin; the voltage divider resistor group includes resistors R11 to R18, which are connected in series; the connection point of each pair of resistors is electrically connected to CAL_P through a control switch. <1> The terminals are connected, and each pair of resistors is electrically connected to CAL_N via a control switch. <1> Terminal, the CAL_P <1> End and CAL_N <1> All terminals are used as output terminals of the Res DAC resistor divider digital-to-analog converter (3).

8. The foreground calibration circuit for the input offset voltage of a SARADC comparator according to claim 7, characterized in that: The CAL_P <1> The terminal is electrically connected to the gate of the M11 regulating transistor, via CAL_P. <1> The gate of the M11 regulating transistor receives the CALIP signal; the CAL_N <1> The terminal is electrically connected to the gate of the M22 regulating transistor, via CAL_N. <1> A CALIN signal is input to the gate of the M22 regulating transistor.

Images