Multi-format image acquisition device based on FPGA and gigabit network image transmission method

Abstract

The invention provides a multi-format image acquisition device based on an FPGA (Field Programmable Gate Array) and a gigabit network image transmission method. The device comprises a power supply module, a video acquisition module, a video processing module, a network communication module and an upper computer software module, the power supply module converts a 5V direct-current power supply into multi-path voltage for power supply; the video acquisition module receives video signals in various formats and converts the video signals into parallel signals; the video processing module takes an FPGA as a core, processes a video and packages the video into a UDP data packet; the network communication module is used for converting the RGMII signal into a gigabit Ethernet signal; and the upper computer software module is used for receiving, analyzing and displaying video data and sending a control instruction so as to realize acquisition and transmission of multi-format video signals. According to the invention, video signals in various formats can be acquired simultaneously, and the system has the advantages of abundant interfaces, stable performance, low cost, high data bandwidth, flexible use scene and the like.

Description

Technical Field

[0001] This invention relates to the field of video testing equipment technology, and more specifically, to an FPGA-based multi-format image acquisition device and a gigabit network image transmission method. Background Technology

[0002] There are various types of existing image capture cards, such as HDMI image capture cards, PAL image capture cards, and Cameralink image capture cards, which are used for video signal acquisition, simulation, and testing. Most of these capture cards use dedicated video chips or CPUs for processing, resulting in relatively simple signal processing strategies, insufficient expandability, limited output interfaces, large size, and lack of flexibility.

[0003] In implementing the embodiments of the present invention, the prior art has at least the following problems or defects: it cannot simultaneously acquire multiple video signals of various formats, which requires the use of multiple acquisition cards, increasing cost and complexity; the processing latency is high, which cannot meet the requirements of high real-time scenarios; and most acquisition cards require the installation of additional driver devices, making them inconvenient to use. Summary of the Invention

[0004] This invention provides a multi-format image acquisition device based on FPGA and a gigabit network image transmission method.

[0005] In a first aspect of the present invention, an FPGA-based multi-format image acquisition device is provided, comprising: Power supply module, video acquisition module, video processing module, network communication module, and host computer software module; The power module has an input terminal connected to an external 5V DC power supply, and an output terminal connected to the video acquisition module, video processing module, and network communication module, respectively, for converting the 5V DC power supply into 3.3V, 2.5V, and 1.2V voltages. The input end of the video acquisition module receives video signals of various formats, and the output end is connected to the video processing module to convert the received video signals into parallel video signals. The video processing module is based on an FPGA, with its input end connected to the video acquisition module and its output end connected to the network communication module. It is used to process video signals and encapsulate them into UDP data packets. The input end of the network communication module is connected to the video processing module, and the output end is connected to the host computer via a network cable, which is used to convert the RGMII signal into a gigabit Ethernet signal. The host computer software module is connected to the network communication module via a network and is used for receiving, parsing, displaying, and sending control commands for video data.

[0006] Furthermore, the video acquisition module includes a DVI video interface circuit, a Cameralink video interface circuit, an SDI video interface circuit, a PAL video interface circuit, and a CML video interface circuit; The DVI video interface circuit uses a TFP401 chip to convert DVI signals into RGB parallel signals; The Cameralink video interface circuit uses the DS90CR288 chip to convert Cameralink signals into RGB parallel signals. The SDI video interface circuit uses the LMH0387 chip to convert the SDI signal into a differential signal. The PAL video interface circuit uses the ADV7282 chip to convert PAL signals into BT656 parallel signals. The CML video interface circuit uses the TLK2711 chip to convert CML signals into parallel signals.

[0007] Furthermore, the output terminals of the DVI video interface circuit, Cameralink video interface circuit, SDI video interface circuit, PAL video interface circuit, and CML video interface circuit are respectively connected to different I / O banks of the FPGA; The clock signal, data signal, and control signal of each video interface circuit are connected to dedicated pins on the FPGA.

[0008] Furthermore, the video processing module includes: The video input interface unit is used to receive parallel video signals from the video acquisition module; The video processing unit is used for scaling, cropping, splicing, and overlaying video signals; The frame buffer unit uses DDR3 SDRAM for buffering video data; The UDP protocol encapsulation unit is used to encapsulate the processed video data into UDP packets; The network interface unit is used to output RGMII signals to the network communication module.

[0009] Furthermore, the video processing unit adopts a multi-channel parallel pipeline architecture, and the processing delay of each video channel satisfies the formula: in Delay the video input. To delay video processing, Delay the video output.

[0010] Furthermore, the network communication module includes a network PHY chip and a network transformer; The network PHY chip is an RTL8211FI-CG, with its RGMII interface connected to the FPGA and its MDIO interface connected to the FPGA. The network transformer uses a G2401CE, with the primary winding connected to the network PHY chip and the secondary winding connected to an RJ45 interface.

[0011] Furthermore, the host computer software module includes: The self-test module is used for network connection self-test and device function self-test. The video information module is used to display video format, video resolution, and video frame rate information; The image display module is used to display video images in real time. The instruction sending module is used to send video stream switching instructions and control parameters.

[0012] Furthermore, the power module includes: The first DC-DC converter is used to convert 5V to 3.3V to power the video acquisition module; The second DC-DC converter is used to convert 5V to 2.5V to power the FPGA's bank voltage; The third DC-DC converter is used to convert 5V to 1.2V to power the FPGA core voltage; Each DC-DC converter is equipped with a π-type filter circuit at its output. The inductance L and capacitance C of the filter circuit satisfy the formula: in Where L is the cutoff frequency, L is the inductance of the filter circuit, and C is the capacitance of the filter circuit.

[0013] Furthermore, the device supports the simultaneous acquisition and transmission of multiple video signal formats. When multiple video inputs are received simultaneously, the video processing module selects one video for processing and transmission according to the instructions of the host computer software module, with a switching time of less than one frame period.

[0014] In a second aspect of the invention, a gigabit network-based image transmission method is provided, comprising: Video acquisition steps: Receive video signals of at least one format through the video acquisition module and convert the video signals into parallel video signals; Video processing steps: Parallel video signals are processed using an FPGA, including at least one of the following operations: scaling, cropping, splicing, and overlaying. Data encapsulation step: The processed video data is encapsulated into UDP packets. The structure of a UDP packet includes an IP header, a UDP header, and a video data payload. Network transmission steps: The UDP data packets are converted into gigabit Ethernet signals through the network communication module and transmitted to the host computer via a network cable; Data parsing steps: Receive network data through the host computer software module, parse UDP packets, and extract video data; Image display steps: Display the parsed video data in real time on the host computer interface; Command interaction steps: Send control commands through the host computer interface to control the working status and video processing parameters of the video acquisition device.

[0015] The embodiments of the present invention have at least the following beneficial effects: 1. This invention uses an FPGA as the core processing unit, enabling flexible acquisition and processing of various video formats. This solves the problems of limited signal processing strategies and insufficient scalability caused by the use of dedicated chips or CPUs in existing technologies. The programmability of the FPGA allows the device to flexibly adjust its processing strategy according to different video formats and usage scenarios, improving its versatility and adaptability, and meeting the needs of various video signal acquisition and processing.

[0016] 2. By employing a multi-channel parallel pipeline architecture for its video processing unit, this invention enables efficient processing of video signals, including operations such as scaling, cropping, splicing, and overlaying. This effectively solves the problems of high processing latency and inability to meet high real-time requirements in existing technologies. This architecture optimizes the processing latency of each video channel, ensuring rapid processing and transmission of video data, improving the overall system performance, and making it particularly suitable for video acquisition and transmission scenarios with high real-time requirements.

[0017] 3. This invention uses the UDP protocol to encapsulate video data and transmits it via a gigabit network, solving the problems of limited export interfaces and inconvenient use in existing technologies. The use of the UDP protocol makes host computer software development more convenient, eliminating the need for additional driver installations and achieving plug-and-play functionality. Simultaneously, the high-speed transmission capability of the gigabit network ensures stable video data transmission, reduces transmission latency, and improves data transmission efficiency and reliability, enabling the device to perform excellently in various application scenarios and enhancing the user experience. Attached Figure Description

[0018] The above and other objects, features, and advantages of exemplary embodiments of the present invention will become readily apparent from the following detailed description taken in conjunction with the accompanying drawings. Several embodiments of the invention are illustrated in the drawings by way of example and not limitation, wherein: Figure 1 This is a schematic diagram of the structure of a multi-format image acquisition device based on FPGA provided in an embodiment of the present invention; Figure 2 This is a data flow diagram provided in one embodiment of the present invention; Figure 3 A circuit block diagram provided for an embodiment of the present invention; Figure 4 This is a schematic diagram of a Cameralink video interface circuit provided in an embodiment of the present invention; Figure 5 This is a schematic diagram of an SDI video interface circuit provided in an embodiment of the present invention; Figure 6 This is a schematic diagram of a PAL video interface circuit provided in an embodiment of the present invention; Figure 7 This is a schematic diagram of a CML video interface circuit provided in an embodiment of the present invention; Figure 8 This is a schematic diagram of a network PHY chip provided in an embodiment of the present invention; Figure 9 This is a schematic diagram of a power module provided in an embodiment of the present invention. Detailed Implementation

[0019] The principles and spirit of the invention will now be described with reference to several exemplary embodiments. It should be understood that these embodiments are provided merely to enable those skilled in the art to better understand and implement the invention, and are not intended to limit the scope of the invention in any way. Rather, these embodiments are provided to make the invention more thorough and complete, and to fully convey the scope of the invention to those skilled in the art.

[0020] Those skilled in the art will recognize that embodiments of the present invention can be implemented as a system, apparatus, device, method, or computer program product. Therefore, the present invention can be specifically implemented in the following forms: entirely hardware, entirely software (including firmware, resident software, microcode, etc.), or a combination of hardware and software.

[0021] It should be noted that the number of any elements in the accompanying drawings is for illustrative purposes only and not as a limitation, and any naming is for distinction only and has no limiting meaning.

[0022] The following is for reference. Figure 1 , Figure 1 This is a schematic diagram of the structure of a multi-format image acquisition device based on FPGA provided in an embodiment of the present invention. Figure 1 As shown, an FPGA-based multi-format image acquisition device includes: Power supply module, video acquisition module, video processing module, network communication module, and host computer software module; The power module has an input terminal connected to an external 5V DC power supply, and an output terminal connected to the video acquisition module, video processing module, and network communication module, respectively, for converting the 5V DC power supply into 3.3V, 2.5V, and 1.2V voltages. The input end of the video acquisition module receives video signals of various formats, and the output end is connected to the video processing module to convert the received video signals into parallel video signals. The video processing module is based on an FPGA, with its input end connected to the video acquisition module and its output end connected to the network communication module. It is used to process video signals and encapsulate them into UDP data packets. The input end of the network communication module is connected to the video processing module, and the output end is connected to the host computer via a network cable, which is used to convert the RGMII signal into a gigabit Ethernet signal. The host computer software module is connected to the network communication module via a network and is used for receiving, parsing, displaying, and sending control commands for video data.

[0023] It should be noted that the image acquisition device of this invention mainly consists of a power supply module, a video acquisition module, a video processing module, a network communication module, and a host computer software module. The power supply module converts the external 5V DC power supply into power supplies of different voltage levels to meet the power supply requirements of each module in the device. The video acquisition module is responsible for receiving video signals of various formats and converting them into parallel video signals for subsequent processing. The video processing module uses an FPGA (Field-Programmable Gate Array) as its core to process the video signals and encapsulate the processed video data into UDP data packets. The network communication module is responsible for converting the RGMII signal output by the video processing module into a gigabit Ethernet signal and transmitting it to the host computer via a network cable. The host computer software module is used to receive and parse video data and send display and control commands. An FPGA is a programmable integrated circuit that can be logically configured according to different needs, possessing high flexibility and scalability.

[0024] Specifically, the power supply module includes a first DC-DC converter, a second DC-DC converter, and a third DC-DC converter. The first DC-DC converter converts 5V DC power to 3.3V, primarily powering the video acquisition module; the second DC-DC converter converts 5V to 2.5V, powering the FPGA's bank voltage; and the third DC-DC converter converts 5V to 1.2V, powering the FPGA's core voltage. Each DC-DC converter's output is equipped with a π-type filter circuit to filter out high-frequency noise in the power supply, ensuring its stability. The video acquisition module includes various video interface circuits, such as DVI, Cameralink, SDI, PAL, and CML video interface circuits. These interface circuits use different chips to convert the corresponding video signals into parallel signals before inputting them into the FPGA. For example, the DVI video interface circuit uses the TFP401 chip to convert DVI signals into RGB parallel signals; the Cameralink video interface circuit uses the DS90CR288 chip to convert Cameralink signals into RGB parallel signals. The FPGA in the video processing module is the core of the entire device. It processes video signals through a multi-channel parallel pipeline architecture, including operations such as scaling, cropping, splicing, and overlaying. The processed video data is encapsulated into UDP packets and transmitted to the host computer via the network communication module.

[0025] Preferably, the FPGA in the video processing module adopts a multi-channel parallel pipeline architecture, where the processing delay of each video channel consists of three parts: video input delay, video processing delay, and video output delay. This architecture can effectively improve the efficiency of video processing and ensure fast processing and transmission of video data. In the power supply module, the inductance value L and capacitance value C of the π-type filter circuit are based on the cutoff frequency. The selection process is based on filtering requirements. The outputs of various interface circuits in the video acquisition module are connected to different I / O banks of the FPGA, ensuring stable signal transmission. The network PHY chip in the network communication module uses the RTL8211FI-CG, whose RGMII interface connects to the FPGA to convert RGMII signals into Gigabit Ethernet signals. The host computer software module includes a self-test module, a video information module, an image display module, and a command sending module. These modules work together to receive, parse, display, and send control commands for video data.

[0026] In some embodiments, the video acquisition module includes a DVI video interface circuit, a Cameralink video interface circuit, an SDI video interface circuit, a PAL video interface circuit, and a CML video interface circuit. The DVI video interface circuit uses a TFP401 chip to convert DVI signals into RGB parallel signals; The Cameralink video interface circuit uses the DS90CR288 chip to convert Cameralink signals into RGB parallel signals. The SDI video interface circuit uses the LMH0387 chip to convert the SDI signal into a differential signal. The PAL video interface circuit uses the ADV7282 chip to convert PAL signals into BT656 parallel signals. The CML video interface circuit uses the TLK2711 chip to convert CML signals into parallel signals.

[0027] like Figure 2 , 3 As shown, the video acquisition module of the image acquisition device of the present invention includes various video interface circuits. These interface circuits can receive video signals of different formats and convert them into RGB parallel signals or other signal formats suitable for FPGA processing. The DVI video interface circuit uses a TFP401 chip, which can convert DVI signals into RGB parallel signals; for example... Figure 4 As shown, the CameraLink video interface circuit uses the DS90CR288 chip, which can convert CameraLink signals into RGB parallel signals; as Figure 5 As shown, the SDI video interface circuit uses the LMH0387 chip, which can convert SDI signals into differential signals; for example... Figure 6 As shown, the PAL video interface circuit uses the ADV7282 chip, which can convert PAL signals into BT656 parallel signals; as Figure 7 As shown, the CML video interface circuit uses the TLK2711 chip, which can convert CML signals into parallel signals. The selection and configuration of these chips are to ensure that video signals of different formats can be effectively converted and processed, thereby meeting the needs of various video signal acquisition.

[0028] Specifically, the DVI, Cameralink, SDI, PAL, and CML video interface circuits in the video acquisition module correspond to different video signal formats. DVI is a common digital video interface; the TFP401 chip decodes the video data in the DVI signal and converts it into an RGB parallel signal for further processing by the FPGA. Cameralink is a high-speed serial interface commonly used in industrial cameras; the DS90CR288 chip converts Cameralink signals into RGB parallel signals, suitable for FPGA processing. SDI is a serial digital interface; the LMH0387 chip converts SDI signals into differential signals, a format suitable for long-distance transmission and with strong anti-interference capabilities. PAL is an analog television broadcasting standard; the ADV7282 chip converts PAL signals into BT656 parallel signals, a format suitable for digital processing. CML is a high-speed serial interface; the TLK2711 chip converts CML signals into parallel signals, suitable for FPGA processing. The design of these interface circuits enables the device to receive video signals of various formats, improving its versatility and flexibility.

[0029] Preferably, each interface circuit in the video acquisition module is meticulously designed to ensure signal integrity and processing efficiency. For example, the TFP401 chip in the DVI video interface circuit can automatically detect the format and parameters of the input signal and perform corresponding decoding and conversion operations. The DS90CR288 chip in the Cameralink video interface circuit supports multiple data rates and signal formats, flexibly adapting to different Cameralink devices. The LMH0387 chip in the SDI video interface circuit has signal equalization and clock recovery functions, effectively improving signal transmission quality and stability. The ADV7282 chip in the PAL video interface circuit supports multiple PAL standards and signal formats, automatically identifying and converting input signals. The TLK2711 chip in the CML video interface circuit has high-speed data transmission capabilities and low latency characteristics, meeting the processing requirements of high-speed video signals. The design and configuration of these interface circuits enable the device to efficiently receive and process video signals of various formats, providing a solid foundation for subsequent video processing and transmission.

[0030] In some embodiments, the outputs of the DVI video interface circuit, Cameralink video interface circuit, SDI video interface circuit, PAL video interface circuit, and CML video interface circuit are respectively connected to different I / O banks of the FPGA; The clock signal, data signal, and control signal of each video interface circuit are connected to dedicated pins on the FPGA.

[0031] It should be noted that in this invention, the output terminals of the various video interface circuits of the video acquisition module are respectively connected to different I / O banks of the FPGA. This design ensures that video signals of different formats can be independently and efficiently transmitted to the FPGA for processing. An I / O bank is an area on the FPGA used for inputting and outputting signals. Each I / O bank can be configured with different voltage levels and electrical characteristics to adapt to the signal requirements of different interface circuits. The clock signal, data signal, and control signal of each video interface circuit are respectively connected to dedicated pins on the FPGA. This connection method ensures signal integrity and processing accuracy, avoids interference between signals, and improves the stability and reliability of the system.

[0032] Specifically, an FPGA's I / O bank is a configurable input / output interface area that can be flexibly configured according to different signal requirements. For example, the output signal of a DVI video interface circuit may require a specific voltage level and electrical characteristics, so it is connected to a suitably configured I / O bank. Similarly, the output signals of Cameralink, SDI, PAL, and CML video interface circuits are also connected to their respective suitably configured I / O banks. The clock, data, and control signals of each video interface circuit are connected to dedicated pins on the FPGA. These pins are configured according to the signal type and requirements to ensure correct signal transmission and processing. For example, clock signals typically require high precision and low jitter transmission, so they are connected to dedicated clock pins; data signals are connected to the corresponding data pins based on the data width and transmission rate; and control signals, used to control the acquisition and processing of video signals, are also connected to dedicated control pins.

[0033] Preferably, to further optimize signal transmission and processing efficiency, the configuration parameters of each I / O bank can be adjusted according to specific application requirements. For example, the drive strength, input delay, and output delay of the I / O bank can be adjusted based on the frequency and voltage range of the video signal to ensure signal integrity and stability. Simultaneously, the dedicated pins of the FPGA can be precisely configured using a Hardware Description Language (HDL) to achieve precise control and processing of different signals. For instance, the electrical characteristics of each pin, such as voltage level and current drive capability, can be set through HDL code, and signal synchronization and timing control can also be achieved. Furthermore, to improve the system's anti-interference capability, appropriate filtering and shielding measures can be added to the signal transmission path to further ensure signal quality and system reliability.

[0034] In some embodiments, the video processing module includes: The video input interface unit is used to receive parallel video signals from the video acquisition module; The video processing unit is used for scaling, cropping, splicing, and overlaying video signals; The frame buffer unit uses DDR3 SDRAM for buffering video data; The UDP protocol encapsulation unit is used to encapsulate the processed video data into UDP packets; The network interface unit is used to output RGMII signals to the network communication module.

[0035] It should be noted that the video processing module of this invention is the core component of the image acquisition device. Based on an FPGA, it includes a video input interface unit, a video processing unit, a frame buffer unit, a UDP protocol encapsulation unit, and a network interface unit. These units work together to receive, process, buffer, encapsulate, and output video signals. The video input interface unit receives parallel video signals from the video acquisition module. The video processing unit performs various processing operations on the video signals, such as scaling, cropping, splicing, and overlaying. The frame buffer unit temporarily stores video data. The UDP protocol encapsulation unit encapsulates the processed video data into UDP data packets. The network interface unit outputs the encapsulated data packets to the network communication module. This modular design improves the system's flexibility and scalability, enabling it to adapt to different video processing needs.

[0036] Specifically, each unit of the video processing module has a clear function and physical meaning. The video input interface unit is the entry point for video signals into the FPGA, receiving and transmitting the parallel video signals output from the video acquisition module to the FPGA. The video processing unit is the logic processing section inside the FPGA, employing a multi-channel parallel pipeline architecture to process data from multiple video channels simultaneously, improving processing efficiency. The frame buffer unit uses DDR3 SDRAM, a high-speed dynamic random access memory used for temporary storage of video data to handle data bursts and timing adjustments during video processing. The UDP protocol encapsulation unit is responsible for encapsulating the processed video data according to the UDP protocol format, enabling its transmission over the network. The network interface unit is the interface that outputs the encapsulated UDP packets to the network communication module; it supports the RGMII signal format, a high-speed serial interface suitable for Gigabit Ethernet communication. The parameter settings and configurations of these units can be adjusted according to the specific video format and processing requirements to ensure optimal processing results.

[0037] Preferably, the multi-channel parallel pipeline architecture of the video processing unit can be further refined. The processing latency of each video channel consists of three parts: video input latency, video processing latency, and video output latency. Video input latency mainly depends on the transmission speed of the video signal and the receiving capability of the FPGA; video processing latency is related to the complexity of the logic processing within the FPGA and can be reduced through algorithm and logic design optimization; video output latency is related to the efficiency of data encapsulation and the output interface. To improve processing efficiency, multi-level caching and preprocessing mechanisms can be implemented within the FPGA. For example, multiple buffer areas can be set in the frame buffer unit to store video data at different stages, thereby enabling fast data reading, writing, and processing. The UDP protocol encapsulation unit can dynamically adjust the size and transmission rate of data packets according to network conditions to ensure stable data transmission. Furthermore, the network interface unit can support various network configurations, such as auto-negotiation and flow control, to adapt to different network environments and requirements. These optimization measures can further improve the performance and reliability of the video processing module.

[0038] In some embodiments, the video processing unit employs a multi-channel parallel pipeline architecture, and the processing latency of each video channel satisfies the formula: in Delay the video input. To delay video processing, Delay the video output.

[0039] It should be noted that the multi-channel parallel pipeline architecture employed by the video processing unit is designed for efficient video signal processing. This architecture allows the video processing module to process data from multiple video channels simultaneously. Each channel's processing includes receiving the video signal, performing necessary processing such as scaling and cropping, and outputting the processed data. This design improves video processing efficiency, reduces processing latency, and ensures that video data can be processed and transmitted quickly and accurately. Processing latency consists of three parts: video input latency, video processing latency, and video output latency. The sum of these three parts determines the overall response time of the video processing module.

[0040] Specifically, each video channel in a multi-channel parallel pipeline architecture comprises three main delay components: video input delay, video processing delay, and video output delay. Video input delay refers to the time from when the video signal enters the FPGA to when processing begins; it primarily depends on the video signal transmission rate and the size of the FPGA's input buffer. Video processing delay refers to the time required for the FPGA to process the video signal, such as scaling and cropping; this delay is related to the complexity of the processing algorithm and the FPGA's processing power. Video output delay refers to the time from when the processed video data is output from the FPGA to the network communication module; it primarily depends on the data encapsulation speed and the network interface's transmission rate. These delay parameters can be configured and optimized using a hardware description language (HDL) to adapt to different video processing needs and performance requirements.

[0041] Preferably, to further optimize the performance of the video processing unit, the multi-channel parallel pipeline architecture can be finely tuned. For example, increasing the size of the input buffer can reduce video input latency, which helps in processing high-resolution or high-frame-rate video signals. Regarding video processing latency, more efficient algorithms or optimized existing algorithm logic can be employed to reduce processing time. For example, for video scaling operations, a fast bilinear interpolation algorithm can be used instead of a more complex one, thereby improving processing speed. For video output latency, latency can be reduced by optimizing the UDP packet encapsulation process, for example, by reducing redundant information in the packet header or employing a more efficient encapsulation algorithm. Furthermore, hardware acceleration technologies, such as using dedicated DSP modules or hardware accelerators, can further improve processing speed. These optimizations can significantly improve the performance of the video processing unit, enabling it to better meet the demands of real-time video processing.

[0042] In some embodiments, the network communication module includes a network PHY chip and a network transformer; The network PHY chip is an RTL8211FI-CG, with its RGMII interface connected to the FPGA and its MDIO interface connected to the FPGA. The network transformer uses a G2401CE, with the primary winding connected to the network PHY chip and the secondary winding connected to an RJ45 interface.

[0043] It should be noted that the network communication module is a key component of the image acquisition device. Its main function is to convert the RGMII signal output from the FPGA into a gigabit Ethernet signal and transmit it to the host computer via a network cable. The network communication module includes a network PHY chip and a network transformer, such as... Figure 8As shown, the network PHY chip is responsible for converting the RGMII signal into an electrical signal suitable for network transmission, while the network transformer is used for signal isolation and transmission, ensuring signal stability and anti-interference capability. This design enables video data to be transmitted efficiently via standard Gigabit Ethernet, meeting the requirements for high-speed and stable video data transmission.

[0044] Specifically, the network PHY chip in the network communication module uses the RTL8211FI-CG model, a high-performance Ethernet physical layer chip. Its RGMII interface connects to the FPGA to receive the RGMII signal output by the FPGA and convert it into a Gigabit Ethernet signal. The MDIO interface is used for management and configuration communication with the FPGA, enabling parameter setting and status monitoring of the network PHY chip. The network transformer uses the G2401CE model, with its primary winding connected to the network PHY chip and its secondary winding connected to the RJ45 interface. This provides electrical isolation and impedance matching for the signal, ensuring signal integrity and stability during transmission. The RGMII signal is a high-speed serial interface signal suitable for high-speed data transmission between the FPGA and the network PHY chip; while the RJ45 interface is a standard Ethernet interface used to connect a network cable for network transmission of video data.

[0045] Preferably, to further improve the performance and reliability of the network communication module, optimizations can be made in both hardware design and software configuration. In terms of hardware design, high-quality network transformers and well-shielded network cables can be used to reduce electromagnetic interference during signal transmission. Simultaneously, appropriate signal integrity design, such as differential routing and impedance matching, can be added between the network PHY chip and the FPGA to ensure stable signal transmission. In terms of software configuration, the network PHY chip can be finely configured using the FPGA's configuration software, such as setting link speed, duplex mode, and flow control parameters, to adapt to different network environments and transmission requirements.

[0046] Furthermore, an auto-negotiation function can be implemented in the network communication module, enabling the device to automatically detect and configure optimal network parameters, thereby improving system compatibility and reliability. These optimizations enhance the performance of the network communication module, ensuring efficient and stable transmission of video data.

[0047] In some embodiments, the host computer software module includes: The self-test module is used for network connection self-test and device function self-test. The video information module is used to display video format, video resolution, and video frame rate information; The image display module is used to display video images in real time. The instruction sending module is used to send video stream switching instructions and control parameters.

[0048] It should be noted that the host computer software module is a crucial component of the image acquisition device. Connected to the network communication module via a network, it is responsible for receiving and parsing video data, displaying the video images in real-time on the host computer interface, and sending control commands to regulate the operating status and video processing parameters of the video acquisition device. The host computer software module includes a self-test module, a video information module, an image display module, and a command sending module. These modules work together to provide users with an intuitive and convenient operating interface, enabling easy video acquisition, display, and control operations.

[0049] Specifically, the self-test module automatically checks the network connection status and the device's functional integrity during system startup, ensuring the device is in normal working order. The video information module displays key information such as the format, resolution, and frame rate of the currently acquired video, providing users with detailed video parameters. The image display module displays the parsed video data on the host computer screen in real time, allowing users to intuitively observe the acquired video content. The command sending module allows users to send various control commands through the host computer interface, such as switching video streams and adjusting video processing parameters, thereby achieving remote control of the video acquisition device. These modules are implemented based on host computer software programming, typically using C++ or other high-level programming languages, combined with network programming and graphical user interface (GUI) development technologies.

[0050] Preferably, to improve the performance and user experience of the host computer software module, several optimization measures can be incorporated into the software design. For example, in the self-test module, timeout and retry mechanisms can be set to ensure network connection reliability, while periodically testing key functions of the device to promptly identify and report potential problems. In the video information module, automatic recognition of multiple video formats can be added to automatically adjust display parameters for optimal display effects when different video signal formats are input. The image display module can reduce display latency and improve video smoothness by optimizing image rendering algorithms. The command sending module can provide a user-friendly interface, allowing users to easily select and send control commands, while adding a command feedback mechanism to allow users to understand the execution status of commands in real time. These optimization measures can enhance the functionality and usability of the host computer software module, providing users with a more efficient and convenient operating experience.

[0051] In some embodiments, the power module includes: The first DC-DC converter is used to convert 5V to 3.3V to power the video acquisition module; The second DC-DC converter is used to convert 5V to 2.5V to power the FPGA's bank voltage; The third DC-DC converter is used to convert 5V to 1.2V to power the FPGA core voltage; Each DC-DC converter is equipped with a π-type filter circuit at its output. The inductance L and capacitance C of the filter circuit satisfy the formula: in Where L is the cutoff frequency, L is the inductance of the filter circuit, and C is the capacitance of the filter circuit.

[0052] like Figure 9 As shown, the power supply module is a fundamental component of the image acquisition device. It is responsible for converting the external 5V DC power supply into various voltage levels to meet the power requirements of the different modules within the device. The power supply module includes three DC-DC converters, each responsible for converting the 5V DC power supply to specific voltage values: 3.3V, 2.5V, and 1.2V. These voltage values ​​are used to power the video acquisition module, the FPGA's bank voltage, and the FPGA core voltage, respectively. Each DC-DC converter has an output terminal equipped with... A filter circuit is used to filter out high-frequency noise in the power supply, ensuring its stability. This design ensures a stable and efficient power supply for the entire device, guaranteeing the normal operation of each module.

[0053] Specifically, the first DC-DC converter in the power module converts 5V DC power to 3.3V. This voltage primarily powers the video acquisition module, ensuring stable acquisition and conversion of video signals. The second DC-DC converter converts 5V to 2.5V, which powers the FPGA's bank voltage. The bank voltage is the power supply voltage used for the FPGA's internal I / O banks, ensuring the FPGA can correctly receive and transmit signals. The third DC-DC converter converts 5V to 1.2V, which powers the FPGA's core voltage. The core voltage is the power supply voltage for the FPGA's internal logic circuits, ensuring the FPGA can operate normally. A type-2 filter circuit is a common type of filter circuit, composed of an inductor and a capacitor, used to filter out high-frequency noise in a power supply. The parameters of the filter circuit, such as the inductor value L and the capacitor value C, are set according to the cutoff frequency. The cutoff frequency is selected to ensure effective filtering. The calculation formula is: Where L is the inductance of the filter circuit and C is the capacitance of the filter circuit. By properly selecting the values ​​of L and C, the stability and reliability of the power supply can be ensured.

[0054] Preferably, to further improve the performance and reliability of the power module, optimizations can be made in hardware design and parameter settings. For example, when selecting a DC-DC converter, conversion efficiency and output stability can be considered, and a high-efficiency, low-ripple converter can be selected. For this type of filter circuit, the optimal inductor and capacitor values ​​can be determined experimentally to achieve the best filtering effect.

[0055] In addition, overvoltage and undervoltage protection circuits can be added to the power supply module to prevent damage to the device from abnormal power supply voltage. In practical applications, the parameters of the power supply module can be adjusted and optimized according to the specific needs of the device and the working environment to ensure the stable operation of the entire image acquisition device.

[0056] In some embodiments, the device supports the simultaneous acquisition and transmission of multiple video signals in various formats. When multiple video inputs occur simultaneously, the video processing module selects one video signal for processing and transmission according to the instructions of the host computer software module, with a switching time of less than one frame period.

[0057] It should be noted that the image acquisition device of this invention supports the simultaneous acquisition and transmission of video signals in multiple formats. This allows the device to adapt to input from various video sources, improving its flexibility and versatility in different application scenarios. When multiple video inputs occur simultaneously, the video processing module can select one video stream for processing and transmission according to instructions from the host computer software module, ensuring efficient switching and processing capabilities in multi-video source environments. The switching time is less than one frame period, meaning that the switching of the video stream is almost imperceptible, guaranteeing the continuity and smoothness of video display.

[0058] Specifically, multi-channel video input refers to the device's ability to simultaneously receive signals from different video sources. These signals can be in different formats, such as DVI, Cameralink, SDI, PAL, and CML. After receiving instructions from the host computer software module, the video processing module can quickly identify and select the specified video signal for processing. The processing includes decoding, format conversion, and data encapsulation of the video signal to ensure that the video signal is correctly transmitted to the host computer. The switching time should be less than one frame period, meaning that the time for switching video sources during video display will not exceed the display time of a video frame. This typically means the switching time is within a few milliseconds, depending on the video's frame rate. For example, for a 30 frames per second video, one frame period is approximately 33.3 milliseconds, therefore the switching time should be less than 33.3 milliseconds.

[0059] Preferably, to achieve fast video stream switching, the video processing module can employ a preloading mechanism, that is, preloading a portion of the video data into a buffer before receiving the switching command. This way, when the switching command arrives, the video processing module can immediately read the data from the buffer for processing, thereby reducing switching time. Simultaneously, latency in the signal processing process can be reduced by optimizing the internal logic design of the FPGA. For example, more efficient algorithms or optimized implementations of existing algorithms can be used to improve processing speed.

[0060] Furthermore, switching speed can be further improved by increasing hardware resources, such as more cache space or faster processing units. In practical applications, the size of the preloaded data and the parameters of the processing algorithm can be adjusted according to the specific video format and frame rate to ensure that the switching time meets the requirement of less than one frame period.

[0061] The above embodiments of the present invention have the following beneficial effects: 1. This invention uses an FPGA as the core processing unit, enabling flexible acquisition and processing of various video formats. This solves the problems of limited signal processing strategies and insufficient scalability caused by the use of dedicated chips or CPUs in existing technologies. The programmability of the FPGA allows the device to flexibly adjust its processing strategy according to different video formats and usage scenarios, improving its versatility and adaptability, and meeting the needs of various video signal acquisition and processing.

[0062] 2. By employing a multi-channel parallel pipeline architecture for its video processing unit, this invention enables efficient processing of video signals, including operations such as scaling, cropping, splicing, and overlaying. This effectively solves the problems of high processing latency and inability to meet high real-time requirements in existing technologies. This architecture optimizes the processing latency of each video channel, ensuring rapid processing and transmission of video data, improving the overall system performance, and making it particularly suitable for video acquisition and transmission scenarios with high real-time requirements.

[0063] 3. This invention uses the UDP protocol to encapsulate video data and transmits it via a gigabit network, solving the problems of limited export interfaces and inconvenient use in existing technologies. The use of the UDP protocol makes host computer software development more convenient, eliminating the need for additional driver installations and achieving plug-and-play functionality. Simultaneously, the high-speed transmission capability of the gigabit network ensures stable video data transmission, reduces transmission latency, and improves data transmission efficiency and reliability, enabling the device to perform excellently in various application scenarios and enhancing the user experience.

[0064] One embodiment of an image transmission method based on gigabit network includes: Video acquisition steps: Receive video signals of at least one format through the video acquisition module and convert the video signals into parallel video signals; Video processing steps: Parallel video signals are processed using an FPGA, including at least one of the following operations: scaling, cropping, splicing, and overlaying. Data encapsulation step: The processed video data is encapsulated into UDP packets. The structure of a UDP packet includes an IP header, a UDP header, and a video data payload. Network transmission steps: The UDP data packets are converted into gigabit Ethernet signals through the network communication module and transmitted to the host computer via a network cable; Data parsing steps: Receive network data through the host computer software module, parse UDP packets, and extract video data; Image display steps: Display the parsed video data in real time on the host computer interface; Command interaction steps: Send control commands through the host computer interface to control the working status and video processing parameters of the video acquisition device.

[0065] It should be noted that the image transmission method of this invention is implemented based on an FPGA-based multi-format image acquisition device. This method includes a series of steps such as video acquisition, processing, encapsulation, transmission, parsing, display, and command interaction. This method achieves efficient video data acquisition and transmission by converting video signals of different formats into unified UDP data packets for network transmission. The host computer software module is responsible for receiving and parsing UDP data packets, extracting video data, and displaying it in real time on the host computer interface. Simultaneously, it sends control commands to control the working status of the video acquisition device and video processing parameters, thereby achieving flexible control over the video acquisition and processing process.

[0066] Specifically, in the video acquisition step, the video acquisition module receives video signals of various formats, such as DVI, Cameralink, SDI, PAL, and CML, and converts these signals into parallel video signals. In the video processing step, the FPGA processes the parallel video signals, including operations such as scaling, cropping, stitching, and overlaying. In the data encapsulation step, the processed video data is encapsulated into UDP packets, the structure of which includes an IP header, a UDP header, and a video data payload. In the network transmission step, the UDP packets are converted into gigabit Ethernet signals by the network communication module and transmitted to the host computer via a network cable. In the data parsing step, the host computer software module receives network data, parses the UDP packets, and extracts the video data. In the image display step, the parsed video data is displayed in real time on the host computer interface. In the command interaction step, control commands are sent through the host computer interface to control the working status of the video acquisition device and the video processing parameters.

[0067] Preferably, to further optimize the performance of the image transmission method, refinements can be made in the following aspects: In the video acquisition step, preprocessing of video signals of different formats can be performed, such as reducing noise and improving signal quality through hardware filters. In the video processing step, more efficient algorithms can be employed, such as using hardware-accelerated bilinear interpolation algorithms for video scaling to reduce processing time. In the data encapsulation step, the size of UDP packets can be dynamically adjusted according to network conditions to improve transmission efficiency. In the network transmission step, flow control and congestion avoidance algorithms can be used to ensure stable transmission of video data over the network. In the data parsing step, parsing time can be reduced and real-time performance improved by optimizing the parsing algorithm. In the image display step, advanced image rendering techniques can be used to reduce display latency and improve video smoothness. In the command interaction step, a command feedback mechanism can be added to allow users to understand the execution status of commands in real time, improving user experience. These optimization measures can significantly improve the performance of the image transmission method, enabling it to better meet the needs of real-time video transmission.

[0068] Furthermore, the storage medium in the embodiments of this application stores program instructions capable of implementing all the above methods. These program instructions can be stored in the storage medium in the form of a software product, including several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) or processor to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks, or terminal devices such as computers, servers, mobile phones, and tablets.

[0069] The above description is merely an explanation of some preferred embodiments of the present invention and the technical principles employed. Those skilled in the art should understand that the scope of the invention as described in the embodiments of the present invention is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the above-described inventive concept. For example, technical solutions formed by substituting the above-described features with (but not limited to) technical features with similar functions disclosed in the embodiments of the present invention.

Claims

1. A multi-format image acquisition device based on FPGA, characterized in that, include: Power supply module, video acquisition module, video processing module, network communication module, and host computer software module; The power module has an input terminal connected to an external 5V DC power supply, and an output terminal connected to the video acquisition module, video processing module, and network communication module, respectively, for converting the 5V DC power supply into 3.3V, 2.5V, and 1.2V voltages. The input end of the video acquisition module receives video signals of various formats, and the output end is connected to the video processing module to convert the received video signals into parallel video signals. The video processing module is based on an FPGA, with its input end connected to the video acquisition module and its output end connected to the network communication module. It is used to process video signals and encapsulate them into UDP data packets. The input end of the network communication module is connected to the video processing module, and the output end is connected to the host computer via a network cable, which is used to convert the RGMII signal into a gigabit Ethernet signal. The host computer software module is connected to the network communication module via a network and is used for receiving, parsing, displaying, and sending control commands for video data.

2. The FPGA-based multi-format image acquisition device according to claim 1, characterized in that: The video acquisition module includes a DVI video interface circuit, a Cameralink video interface circuit, an SDI video interface circuit, a PAL video interface circuit, and a CML video interface circuit. The DVI video interface circuit uses a TFP401 chip to convert DVI signals into RGB parallel signals; The Cameralink video interface circuit uses the DS90CR288 chip to convert Cameralink signals into RGB parallel signals. The SDI video interface circuit uses the LMH0387 chip to convert the SDI signal into a differential signal. The PAL video interface circuit uses the ADV7282 chip to convert PAL signals into BT656 parallel signals. The CML video interface circuit uses the TLK2711 chip to convert CML signals into parallel signals.

3. The FPGA-based multi-format image acquisition device according to claim 2, characterized in that: The outputs of the DVI video interface circuit, Cameralink video interface circuit, SDI video interface circuit, PAL video interface circuit, and CML video interface circuit are respectively connected to different I / O banks of the FPGA. The clock signal, data signal, and control signal of each video interface circuit are connected to dedicated pins on the FPGA.

4. The FPGA-based multi-format image acquisition device according to claim 1, characterized in that: The video processing module includes: The video input interface unit is used to receive parallel video signals from the video acquisition module; The video processing unit is used for scaling, cropping, splicing, and overlaying video signals; The frame buffer unit uses DDR3 SDRAM for buffering video data; The UDP protocol encapsulation unit is used to encapsulate the processed video data into UDP packets; The network interface unit is used to output RGMII signals to the network communication module.

5. The FPGA-based multi-format image acquisition device according to claim 4, characterized in that: The video processing unit adopts a multi-channel parallel pipeline architecture, and the processing delay of each video channel satisfies the formula: in Delay the video input. To delay video processing, Delay the video output.

6. The FPGA-based multi-format image acquisition device according to claim 1, characterized in that: The network communication module includes a network PHY chip and a network transformer; The network PHY chip is an RTL8211FI-CG, with its RGMII interface connected to the FPGA and its MDIO interface connected to the FPGA. The network transformer uses a G2401CE, with the primary winding connected to the network PHY chip and the secondary winding connected to an RJ45 interface.

7. The FPGA-based multi-format image acquisition device according to claim 1, characterized in that: The host computer software module includes: The self-test module is used for network connection self-test and device function self-test. The video information module is used to display video format, video resolution, and video frame rate information; The image display module is used to display video images in real time. The instruction sending module is used to send video stream switching instructions and control parameters.

8. The FPGA-based multi-format image acquisition device according to claim 1, characterized in that: The power module includes: The first DC-DC converter is used to convert 5V to 3.3V to power the video acquisition module; The second DC-DC converter is used to convert 5V to 2.5V to power the FPGA's bank voltage; The third DC-DC converter is used to convert 5V to 1.2V to power the FPGA core voltage; Each DC-DC converter is equipped with a π-type filter circuit at its output. The inductance L and capacitance C of the filter circuit satisfy the formula: in Where L is the cutoff frequency, L is the inductance of the filter circuit, and C is the capacitance of the filter circuit.

9. The FPGA-based multi-format image acquisition device according to claim 1, characterized in that: The device supports the simultaneous acquisition and transmission of multiple video signal formats. When multiple video inputs are available simultaneously, the video processing module selects one video for processing and transmission according to the instructions of the host computer software module, with a switching time of less than one frame period.

10. A gigabit network-based image transmission method, applied to the FPGA-based multi-format image acquisition device as described in any one of claims 1-9, characterized in that, Includes the following steps: Video acquisition steps: Receive video signals of at least one format through the video acquisition module and convert the video signals into parallel video signals; Video processing steps: Parallel video signals are processed using an FPGA, including at least one of the following operations: scaling, cropping, splicing, and overlaying. Data encapsulation step: The processed video data is encapsulated into UDP packets. The structure of a UDP packet includes an IP header, a UDP header, and a video data payload. Network transmission steps: The UDP data packets are converted into gigabit Ethernet signals through the network communication module and transmitted to the host computer via a network cable; Data parsing steps: Receive network data through the host computer software module, parse UDP packets, and extract video data; Image display steps: Display the parsed video data in real time on the host computer interface; Command interaction steps: Send control commands through the host computer interface to control the working status and video processing parameters of the video acquisition device.

Images