Device structure and forming method thereof

Abstract

A phase change memory device may be provided by forming a bottom electrode, a dielectric material layer, and a via opening extending through the dielectric material layer such that a top surface segment of the bottom electrode is exposed below the via opening; forming a tubular dielectric spacer in a peripheral region of the via opening; depositing a continuous layer stack over the dielectric material layer and the tubular dielectric spacer, the continuous layer stack comprising a heater liner layer, a phase change material layer comprising a phase change material, and a top electrode material layer; and patterning the continuous layer stack into a layer stack comprising a heater liner, a phase change material portion, and a top electrode. The embodiment of the invention also provides a device structure and a forming method thereof.

Description

Technical Field

[0001] Embodiments of this disclosure relate to device structures and methods of forming the same. Background Technology

[0002] Phase change material (PCM) devices are suitable for memory-based computing applications due to their scalability and non-volatility. However, the fabrication process for PCM devices requires numerous processing steps. One time-consuming and expensive step involves forming the bottom electrode and heater element using a chemical mechanical polishing process. Summary of the Invention

[0003] Some embodiments of this disclosure provide a method of forming a device structure, the method comprising: forming a bottom electrode, a dielectric material layer, and a via opening extending through the dielectric material layer such that a top surface segment of the bottom electrode is exposed below the via opening; forming a tubular dielectric spacer in a peripheral region of the via opening such that a central portion of the top surface segment is exposed below a void laterally surrounded by the tubular dielectric spacer; depositing a continuous layer stack over the dielectric material layer and the tubular dielectric spacer, the continuous layer stack including a heater pad layer, a phase change material layer including a phase change material, and a top electrode material layer; and patterning the continuous layer stack into a layer stack including a heater pad, a phase change material portion, and a top electrode.

[0004] Other embodiments of this disclosure provide a method of forming a device structure, the method comprising: forming a bottom electrode, a dielectric material layer, and a via opening extending through the dielectric material layer such that a top surface segment of the bottom electrode is exposed below the via opening; depositing a heater pad layer within a portion of the via opening and over the dielectric material layer; vertically recessing a horizontal extension of the heater pad layer; depositing a phase change material layer and a top electrode material layer over the horizontal extension of the heater pad layer, the phase change material layer comprising a phase change material; and patterning the top electrode material layer, the phase change material layer, and the heater pad layer into a layer stack comprising a heater pad, a phase change material portion, and a top electrode.

[0005] Another embodiment of this disclosure provides a device structure comprising: a tubular dielectric spacer located within a through-hole opening in a dielectric material layer; a heater pad including a vertically extending portion laterally surrounded by the tubular dielectric spacer and a horizontally extending portion disposed above a top surface segment of the dielectric material layer; a phase change material portion including a phase change material contacting the top surface of the heater pad; and a top electrode contacting the top surface of the phase change material portion. Attached Figure Description

[0006] The aspects of this disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, the various components are not drawn to scale. In fact, the dimensions of the various components may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1 This is a vertical cross-sectional view of the intermediate structure in the first embodiment after forming the field-effect transistor, the metal interconnect structure, and the dielectric material layer, according to an embodiment of the present disclosure.

[0008] Figure 2 This is a vertical cross-sectional view of the intermediate structure in the first embodiment according to an embodiment of the present disclosure after forming a through-hole opening through the dielectric material layer.

[0009] Figure 3 This is a vertical cross-sectional view of the intermediate structure in the first embodiment after the formation of the dielectric spacer material layer, according to an embodiment of the present disclosure.

[0010] Figure 4 This is a vertical cross-sectional view of the intermediate structure in the first embodiment after the tubular dielectric spacer has been formed, according to an embodiment of the present disclosure.

[0011] Figure 5 This is a vertical cross-sectional view of the intermediate structure in the first embodiment after forming a continuous stack of layers including a heater liner layer, a phase change material layer and a top electrode material layer, according to an embodiment of the present disclosure.

[0012] Figure 6 This is a vertical cross-sectional view of the intermediate structure in the first embodiment after patterning a continuous layer stack into each in-process layer stack that includes a heater pad, a phase change material portion, and a top electrode, according to an embodiment of the present disclosure.

[0013] Figure 7 This is a vertical cross-sectional view of the intermediate structure in the first embodiment after the formation of the sidewall liner layer, according to an embodiment of the present disclosure.

[0014] Figure 8 This is a vertical cross-sectional view of the intermediate structure in the first embodiment after the sidewall liner in the forming process according to an embodiment of the present disclosure.

[0015] Figure 9 This is a vertical cross-sectional view of the intermediate structure in the first embodiment after patterning the process stack into each stack comprising a heater pad, a phase change material portion and a top electrode, and patterning the process sidewall pads into sidewall pads, according to an embodiment of the present disclosure.

[0016] Figure 10 This is a vertical cross-sectional view of the structure of the first embodiment after removing the patterned etched mask layer according to the present disclosure.

[0017] Figures 11A to 11C It shows in Figures 8 to 10 An ordered top view of the region of the first configuration of the structure in the first embodiment during the processing steps.

[0018] Figures 12A to 12C It shows in Figures 8 to 10 An ordered top view of the second configuration region of the embodiment structure during the processing steps.

[0019] Figures 13A to 13C It shows in Figures 8 to 10 An ordered top view of the third configuration region of the embodiment structure during the processing steps.

[0020] Figure 14 It shows in Figure 8 The processing steps are followed by a top-down view of the fourth configuration area of ​​the embodiment structure.

[0021] Figure 15 This is a vertical cross-sectional view of the structure of a first embodiment after the formation of the sealing dielectric layer and the additional metal interconnect structure according to the present disclosure.

[0022] Figures 16A to 16D These are the various configurations of phase-change memory cells in various programming resistor states according to embodiments of the present disclosure.

[0023] Figure 17 This is a vertical cross-sectional view of the intermediate structure in a second embodiment following the deposition heater liner layer, according to an embodiment of the present disclosure.

[0024] Figure 18 This is a vertical cross-sectional view of the intermediate structure in a second embodiment according to an embodiment of the present disclosure after the heater liner layer is vertically recessed.

[0025] Figure 19 This is a vertical cross-sectional view of the intermediate structure in a second embodiment according to an embodiment of the present disclosure, after the deposition of a phase change material layer and a top electrode material layer.

[0026] Figure 20 This is a vertical cross-sectional view of the intermediate structure in the second embodiment after forming an intermediate layer stack, each of which includes a process heater pad, a process phase change material portion, and a process top electrode, according to an embodiment of the present disclosure.

[0027] Figure 21 This is a vertical cross-sectional view of a second embodiment structure after the formation of the sealing dielectric layer and the additional metal interconnect structure according to the present disclosure.

[0028] Figure 22This is a vertical cross-sectional view of the intermediate structure in a third embodiment following the deposition heater liner layer, according to an embodiment of the present disclosure.

[0029] Figure 23 This is a vertical cross-sectional view of the intermediate structure in a third embodiment according to an embodiment of the present disclosure, after the deposition of a phase change material layer and a top electrode material layer.

[0030] Figure 24 This is a vertical cross-sectional view of the intermediate structure in the third embodiment after forming an intermediate layer stack, each of which includes a process heater pad, a process phase change material portion, and a process top electrode, according to an embodiment of the present disclosure.

[0031] Figure 25 This is a vertical cross-sectional view of a third embodiment structure after the formation of the sealing dielectric layer and the additional metal interconnect structure according to the present disclosure.

[0032] Figure 26 This is a first flowchart illustrating the general processing steps for manufacturing a device structure according to an embodiment of the present disclosure.

[0033] Figure 27 This is a second flowchart illustrating the general processing steps for manufacturing a device structure according to an embodiment of the present disclosure. Detailed Implementation

[0034] The following disclosure provides numerous different embodiments or instances of various components for implementing the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. These are merely examples and not intended to be limiting. The drawings are not to scale. Unless explicitly stated otherwise, elements with the same reference numerals refer to the same elements and are assumed to have the same material composition and the same thickness range. Unless explicitly disclosed otherwise, it is assumed that all features of the original embodiment are present in any derivative embodiment. Therefore, the features described with reference to the relevant embodiments in the drawings and / or specification provide support for the features in the embodiments. Unless explicitly described otherwise, embodiments in which multiple instances of any said element are repeated are explicitly contemplated. Embodiments in which unnecessary elements are omitted, even if such embodiments are not explicitly disclosed but are known in the art, are explicitly contemplated.

[0035] Furthermore, for ease of description, spatially relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the geometric features between the elements shown in the figures. The first physical element is “embedded” by the second physical element if the entire volume of the first physical element lies within a hypothetical volume defined by a set of hypothetical surfaces, and this set of hypothetical surfaces has the smallest total surface area among all hypothetical surfaces containing the entire outer surface of the second physical element, and is topologically isomorphic to a sphere. Such a set of hypothetical surfaces would cover every opening (if present) in the outer surface, having the smallest surface area segment among all possible unopened surface segments. Spatially relative terms are intended to encompass different orientations of the device in use or operation, except for those shown in the figures. The device may be positioned in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly. Unless otherwise expressly stated, each element with the same reference number is assumed to have the same material composition and is assumed to have a thickness within the same thickness range.

[0036] Phase-change memory (PCM) devices can be used in a variety of applications due to their scalability and non-volatility. However, the complexity of PCM device manufacturing processes can pose challenges. For example, the fabrication of heater elements is often affected by the use of chemical mechanical polishing (CMP) processes. CMP processes not only require expensive equipment and consumables but also demand stringent process control, which can lead to increased production time and / or yield losses.

[0037] Various embodiments of this disclosure provide a sequence of manufacturing steps for fabricating phase-change memory (PCM) devices while reducing complexity and processing costs. Specifically, the disclosed sequence of manufacturing steps provides a method for fabricating PCM devices without using CMP processes. Specifically, a heater pad is used to provide the phase-change material portion with the dual function of a heater element and a heater pad, contacting the bottom surface of the phase-change material portion. The heater pad can be formed by providing narrow via openings in a dielectric material layer, filling the entire or peripheral area of ​​the via openings with a heater pad layer, and subsequently patterning the heater pad layer. A phase-change material layer and a top electrode material layer can be deposited over the heater material layer, and the same masking pattern can be used to pattern the heater pad layer, the phase-change material layer, and the top electrode material layer. The heater pad includes a vertical extension formed in the via opening and a horizontal extension positioned above the dielectric material layer. Sidewall pads can be formed on each layer stack of the heater pad, the phase-change material portion, and the top electrode to provide a phase-change memory cell. Therefore, a phase-change memory cell can be fabricated without using expensive CMP processes.

[0038] Before forming the heater pad, a tubular dielectric spacer can be formed in the via opening. In one embodiment, the void in the tubular dielectric spacer can be narrow enough to be completely filled during the deposition of the heater pad layer. In another embodiment, the void in the tubular dielectric spacer can be wider than twice the target thickness of the horizontal extension of the subsequently formed heater pad, and a combination of over-deposition and recessed etching can be used to provide the target thickness of the horizontal extension of the heater pad while filling the void in the via opening. In yet another embodiment, the void in the tubular dielectric spacer can be wider than twice the target thickness of the heater pad, and the remaining portion of the void can be filled with the vertical extension of the phase change material portion. Various embodiments of the present disclosure will now be described with reference to the accompanying drawings.

[0039] refer to Figure 1 The diagram illustrates a structure according to a first embodiment of the present disclosure. The first embodiment structure includes a substrate 8, which may be a semiconductor substrate, such as a commercially available silicon substrate. The substrate 8 may include a semiconductor material layer 9, at least in its upper portion. The semiconductor material layer 9 may be a surface portion of a bulk semiconductor substrate, or it may be a top semiconductor layer of a semiconductor-on-insulator (SOI) substrate. In one embodiment, the semiconductor material layer 9 comprises a single-crystal semiconductor material, such as single-crystal silicon. In another embodiment, the substrate 8 may comprise a single-crystal silicon substrate containing single-crystal silicon material.

[0040] A shallow trench isolation structure 720 containing a dielectric material (such as silicon oxide) can be formed in the upper part of the semiconductor material layer 9. Suitable doped semiconductor wells, such as p-type wells and n-type wells, can be formed in each region laterally surrounded by a portion of the shallow trench isolation structure 720.

[0041] A semiconductor device 700 may be formed on the semiconductor material layer 9. The semiconductor device 700 may include complementary metal-oxide-semiconductor (CMOS) transistors and optional additional semiconductor devices (such as resistors, diodes, capacitor structures, etc.). The semiconductor device 700 may include a programming transistor 701 formed in the memory array region 100 and a peripheral transistor 702 formed in the peripheral region 300. Each field-effect transistor (701, 702) may include a source region, a drain region, a channel region, a gate dielectric, and a gate electrode. In one embodiment, the channel region may include a portion of the semiconductor material layer 9 and may include a single-crystal semiconductor material. Each programming transistor 701 may be configured to provide a set of programming pulses for a subsequently formed corresponding phase-change memory cell. The peripheral transistor 702 may be formed as a component of peripheral circuitry that controls the operation of the programming transistor 701 and interfaces with input / output (I / O) circuitry (not shown).

[0042] In one embodiment, substrate 8 may comprise a monocrystalline silicon substrate, and field-effect transistors (701, 702) may include corresponding portions of the monocrystalline silicon substrate as semiconductor channels. As used herein, a "semiconductor" element refers to an element having a dielectric constant of 1.0 x 10⁻⁶. -6 S / cm up to 1.0x10 5 Components with conductivity in the range of S / cm. As used herein, "semiconductor material" refers to a component having conductivity in the absence of electrical dopants, with a conductivity in the range of 1.0 x 10⁻⁶ S / cm. -6 S / cm up to 1.0x10 5 Materials with electrical conductivity in the range of S / cm can be produced when appropriately doped with an electrical dopant, exhibiting conductivity from 1.0 S / cm to 1.0 x 10⁻⁶. 5 Doped materials with conductivity in the range of S / cm.

[0043] Various metal interconnect structures can be formed within a dielectric material layer, which can subsequently be formed over the substrate 8 and the semiconductor device. In the illustrated example, the dielectric material layer may include, for example, a first dielectric material layer 601, a first interconnect-level dielectric material layer 610, a second interconnect-level dielectric material layer 620, a third interconnect-level dielectric material layer 630, and a fourth interconnect-level dielectric material layer 640. The first dielectric layer 601 may be a layer surrounding contact structures connected to the source and drain (sometimes referred to as the contact-level dielectric material layer 601). The metal interconnect structure may include a device contact via structure 612, a first metal line structure 618, a first metal via structure 622, a second metal line structure 628, a second metal via structure 632, and a third metal line structure 638. The device contact via structure 612 is formed in the first dielectric material layer 601 and contacts a corresponding component of the semiconductor device 700. The first metal line structure 618 is formed in the first interconnect-level dielectric material layer 610. The first metal via structure 622 is formed in the lower part of the second interconnect-level dielectric material layer 620. The second metal line structure 628 is formed in the upper part of the second interconnect-level dielectric material layer 620. The second metal via structure 632 is formed in the lower part of the third interconnect-level dielectric material layer 630, and the third metal line structure 638 is formed in the upper part of the third interconnect-level dielectric material layer 630. An additional dielectric material layer may be formed above the third interconnect-level dielectric material layer 630; this additional dielectric material layer is referred to herein as the lower fourth interconnect-level dielectric material layer 641.

[0044] Each dielectric layer (601, 610, 620, 630, 641) may include a dielectric material such as undoped silicate glass, doped silicate glass, organosilicon glass, amorphous fluorinated carbon, porous variants thereof, or combinations thereof. Each metal interconnect structure (612, 618, 622, 628, 632, 638) may include at least one conductive material, which may be a combination of a metal pad (such as a metal nitride or metal carbide) and a metal filler material. Each metal pad may include TiN, TaN, WN, TiC, TaC, and WC, and each metal filler portion may include W, Cu, Al, Co, Ru, Mo, Ta, Ti, alloys thereof, and / or combinations thereof. In one embodiment, the first metal via structure 622 and the second metal wire structure 628 may be formed as an integrated wire and via structure using a dual damascene process. Typically, any connected assembly of metal wire structures (628, 638) and at least one underlying metal via structure (622, 632) can be formed as an integrated wire and via structure.

[0045] Typically, semiconductor devices (such as field-effect transistors (701, 702)) can be formed on substrate 8, and metal interconnect structures (612, 618, 622, 628, 632, 638) and dielectric material layers (601, 610, 620, 630, 641) can be formed above the semiconductor devices. The metal interconnect structures (612, 618, 622, 628, 632, 638) can be formed in the dielectric material layers (601, 610, 620, 630, 641) and can be electrically connected to the semiconductor devices.

[0046] A subset of the metal interconnect structures (612, 618, 622, 628, 632, 638) located within a dielectric material layer below the topmost dielectric layer may include the bottom electrode 38 (formed as a portion of the metal interconnect structure 638) of the phase-change memory cells to be subsequently formed. In the illustrated example, a subset of the third metal line structure 638 may include a two-dimensional array of bottom electrodes 38 for the subsequent phase-change memory cell array. The bottom electrode 38 may be formed within a dielectric material layer (such as a third interconnect level dielectric material layer 630) located below the topmost dielectric material layer (such as a lower fourth interconnect level dielectric material layer 641). The bottom electrode 38 includes at least one metal having high conductivity. For example, the bottom electrode 38 may include a metal portion containing copper, aluminum, or tungsten. Optionally, the bottom electrode 38 may include a metal barrier pad containing a metal barrier material such as TiN, TaN, WN, and / or MoN.

[0047] In summary, the programmable transistor 701 can be formed on the substrate 8. Metal interconnect structures (612, 618, 622, 628, 632, 638) formed within interconnect dielectric material layers (601, 610, 620, 630, 641) can be formed above the programmable transistor 701. The metal interconnect structures (612, 618, 622, 628, 632, 638) can be configured to be electrically connected to the heater elements of the phase-change memory cells to be subsequently formed.

[0048] According to aspects of this disclosure, the programming transistor 701 can be configured to program a corresponding phase-change memory cell into at least two different resistance states, and preferably into at least three different resistance states, and more preferably into at least four different resistance states. Programming each phase-change memory cell into a different resistance state can be influenced by pulse modes selected from a set of pre-programmed pulse modes that can be applied to each programming transistor 701. The pulse modes differ from each other in the duration of the pulse mode and the peak voltage of the pulse mode. In one embodiment, the total number of resistance states that a phase-change memory cell can be programmed into can be in the range of 2 to 64, such as in the range of 3 to 16, and / or in the range of 4 to 8; however, a greater number of resistance states can be programmed as needed by changing the pulse modes generated by each programming transistor 701.

[0049] refer to Figure 2 The via opening 41 can be formed through the topmost dielectric layer (such as the lower fourth interconnect dielectric layer 641). Each via opening 41 can be formed above a corresponding one of the underlying metal interconnect structures (such as a subset of the third metal line structure 638), thereby physically exposing the top surface segment of the underlying metal interconnect structure. The dielectric layer through which the via opening 41 is formed includes a heat-resistant dielectric material, such as undoped or doped silicate glass. The thickness of the dielectric layer can range from 200 nm to 1,000 nm, however, smaller or larger thicknesses can also be used. The lateral dimension (such as diameter) at the bottom of each via opening 41 can range from 50 nm to 400 nm, however, smaller or larger lateral dimensions can also be used.

[0050] Typically, a bottom electrode 38, a dielectric material layer (such as a lower fourth interconnect dielectric material layer 641), and via openings 41 extending through the dielectric material layer can be formed such that the top surface segment of the corresponding bottom electrode 38 is exposed below each via opening 41.

[0051] refer to Figure 3A dielectric spacer material can be conformally deposited in the peripheral region of the via opening 41 and over a dielectric material layer (such as the lower fourth interconnect level dielectric material layer 641) surrounding the via opening 41, forming a dielectric spacer material layer 42L. The dielectric spacer material of the dielectric spacer material layer 42L can have a thermal conductivity of less than 40 W / m·K. For example, the dielectric spacer material layer 42L can include silicon oxide, silicon nitride, aluminum oxide, silicon carbonitride, or combinations thereof. In one embodiment, the dielectric spacer material of the dielectric spacer material layer 42L can be substantially composed of silicon oxide, having a thermal conductivity in the range of 1.1 W / m·K to 1.4 W / m·K. Typically, the material composition of the dielectric spacer material layer 42L can be the same as or different from the material composition of the dielectric material layer through which the via opening 41 extends perpendicularly. The dielectric spacer material layer 42L can be deposited using a conformal deposition process (such as chemical vapor deposition). Due to the isotropic deposition process of forming the dielectric spacer layer 42L, the top surface of the dielectric spacer layer 42L may include an annular raised surface segment formed around the top edge of the via opening 41.

[0052] According to aspects of this disclosure, the thickness of the dielectric spacer layer 42L is selected such that the difference between the bottom width of each via opening 41 and twice the thickness of the dielectric spacer layer 42L is within a target range of the bottom width of each vertical extension of the subsequently formed heater pad layer. In an exemplary example, where the bottom width of each via opening 41 is in the range of 50 nm to 400 nm, and in an example where the target range of the bottom width of each vertical extension of the subsequently formed heater pad layer is in the range of 20 nm to 100 nm, the thickness of the dielectric spacer layer 42L can be in the range of 15 nm to 150 nm, such as in the range of 30 nm to 80 nm, but smaller or larger thicknesses can also be used.

[0053] refer to Figure 4 An anisotropic etching process can be performed to anisotropically etch the horizontal extensions of the dielectric spacer material layer 42L. Each remaining vertical extension of the dielectric spacer material layer 42L retained in the peripheral region of the corresponding via opening 41 constitutes a tubular dielectric spacer 42 with a tubular configuration. According to an aspect of this disclosure, the central portion of the top surface segment of the bottom electrode 38 can be exposed beneath each void laterally surrounded by the corresponding tubular dielectric spacer 42.

[0054] Each tubular dielectric spacer 42 may include an outer cylindrical sidewall having an outer cone angle ranging from 0 to 15 degrees (e.g., 1 to 5 degrees) relative to the vertical direction. As used herein, "cylindrical sidewall" refers to any sidewall that has a closed perimeter in a horizontal cross-sectional view and may or may not have a cone angle relative to the vertical direction. Each tubular dielectric spacer 42 may include an inner cylindrical sidewall having an inner cone angle ranging from 0 to 15 degrees (e.g., 1 to 5 degrees) relative to the vertical direction. The inner cone angle may be the same as or substantially the same as the outer cone angle. In one embodiment, each tubular dielectric spacer 42 includes an annular raised surface segment abutting the top periphery of the inner cylindrical sidewall of the through-hole opening 41.

[0055] refer to Figure 5 Metal heater material can be deposited in the gaps laterally surrounded by tubular dielectric spacers 42 and over dielectric material layers (such as the lower fourth interconnect level dielectric material layer 641) extending vertically through the via openings 41. The deposited metal heater material forms a heater pad layer 52L, which is a pad layer containing the metal heater material. The metal heater material has a higher conductivity than the metal material of the bottom electrode 38. In one embodiment, the heater pad layer 52L comprises a first metal nitride material, which can be a stoichiometric or near-stoichiometric metal nitride material. For example, the heater pad layer 52L can include TaN, TiN, WN, and / or MoN. In one embodiment, the conductivity of the metal material of the heater pad layer 52L can be 1.0 x 10⁻⁶. 3 S / cm to 1.0x10 5 Within the range of S / cm. Metal heater materials can be deposited by chemical vapor deposition or physical vapor deposition. In one embodiment, the metal heater material may include stoichiometric or near-stoichiometric metal nitride materials, such as stoichiometric or near-stoichiometric TiN, TaN, WN, and / or MoN.

[0056] In one embodiment, a conformal deposition process (such as chemical vapor deposition) can be used to deposit the metallic heater material of the heater pad layer 52L. According to aspects of this disclosure, the duration of the deposition process for the heater pad layer 52L can be selected such that the predominant portion and / or the entire volume of each void within the via opening 41 is filled with the deposited material of the heater pad layer 52L. The thickness of the horizontally extending portion of the heater pad layer 52L is selected such that the patterned portion of the heater pad layer 52L can provide resistance during operation of the subsequent phase memory cell to be formed. The thickness of the horizontally extending portion of the heater pad layer 52L deposited above the top surface of the dielectric material layer extending vertically through the via opening 41 can range from 10 nm to 80 nm, such as from 20 nm to 50 nm, but smaller or larger thicknesses can also be used.

[0057] Typically, the heater pad layer 52L can be deposited within a portion of the volume of each via opening 41 of a dielectric material layer (such as the lower fourth interconnect level dielectric material layer 641) and deposited above the horizontal top surface of the dielectric material layer. In depositing the heater pad layer 52L, the heater pad layer 52L includes a flat horizontal surface segment PHSS disposed above the dielectric material layer, and also includes an annular raised surface segment ACSS that abuts the periphery of a corresponding opening in the flat horizontal surface segment PHSS and is disposed above a corresponding via opening 41. The formation of the annular raised surface segment ACSS is due to the isotropic nature of the deposition process used to deposit the heater pad layer 52L.

[0058] The heater pad layer 52L includes a vertically extending portion deposited in a void within the tubular dielectric spacer 42, and a horizontally extending portion deposited above the top surface of a dielectric material layer (such as the lower fourth interconnect level dielectric material layer 641). The heater pad layer 52L at least partially fills each void within the via opening 41. In one embodiment, the maximum width of each void (such as the width at a horizontal plane encompassing the top surface of the dielectric material layer) may be less than half the thickness of the heater pad layer 52L, which is measured at the horizontally extending portion of the heater pad layer 52L positioned above the dielectric material layer. In one embodiment, a vertically extending seam S is formed at the center of each void, each void being filled by the corresponding vertically extending portion of the heater pad layer 52L. Each vertically extending seam S may be formed at the center of the corresponding vertically extending portion of the heater pad layer 52L. In one embodiment, the heater pad layer 52L is deposited on the central portion of each physically exposed portion of the top surface segment of the bottom electrode 38.

[0059] The phase change material layer 54L can be deposited over the entire physically exposed surface of the heater liner layer 52L. Therefore, the phase change material layer 54L is deposited directly on the flat horizontal surface segment PHSS of the heater liner layer 52L, and directly on each annular raised surface segment ACSS of the heater liner layer 52L, which is situated above a horizontal plane containing the top surface of a dielectric material layer (such as the lower fourth interconnect level dielectric material layer 641).

[0060] The phase change material layer 54L includes a phase change material and / or is substantially composed of a phase change material. As used herein, "phase change material" refers to a material having at least two distinct phases, thus providing different resistivities. A phase change material (PCM) can be used to store information as the resistivity states of a material, which can be in different resistivity states corresponding to different phases of the material. The different phases can include an amorphous state with high resistivity and a crystalline state with low resistivity (i.e., a resistivity lower than that of the amorphous state). In the first part of the programming process, a transition between the amorphous and crystalline states can be induced by controlling the cooling rate after applying an electrical pulse that amorphizes the phase change material. The second part of the programming process involves controlling the cooling rate of the phase change material. In embodiments where rapid quenching occurs, the phase change material can be cooled to an amorphous, high-resistivity state. In embodiments where slow cooling occurs, the phase change material can be cooled to a crystalline, low-resistivity state.

[0061] Exemplary phase change materials include, but are not limited to, germanium antimony telluride (GST) compounds (such as Ge2Sb2Te5 or GeSb2Te4), germanium antimony compounds, indium germanium telluride compounds, aluminum selenide telluride compounds, indium selenide telluride compounds, and aluminum indium selenide telluride compounds. In one embodiment, the phase change material of the phase change material layer 54L may include a doped GST compound (such as N-doped GST, Si-doped GST, C-doped GST, Ge-doped GST, Ru-doped GST, or Al-doped GST) or a doped GeTe compound (such as N-doped GeTe, Si-doped GeTe, C-doped GeTe, or Ge-doped GeTe). The phase change material layer 54L can be deposited by physical vapor deposition. The thickness of the phase change material layer 54L can be in the range of 30 nm to 200 nm, such as in the range of 50 nm to 90 nm, but smaller or larger thicknesses can also be used. In one embodiment, the phase change material of the phase change material layer can be selected such that the electrical conductivity of the amorphous phase of the phase change material is 1.0 x 10⁻⁶. -8 S / cm up to 1.0x10 - 3 The conductivity of the phase change material is in the range of S / cm, while the conductivity of the crystalline phase is in the range of 1.0 x 10⁻⁶. -1 S / cm up to 1.0x10 3Within the range of S / cm.

[0062] The top electrode material layer 56L comprises a metallic material, such as W, Ta, Ti, Mo, WN, TiN, or MoN. The top electrode material layer 56L can have a thickness ranging from 100 nm to 200 nm, but smaller or larger thicknesses are also possible. The top electrode material layer 56L can be deposited by chemical vapor deposition or physical vapor deposition.

[0063] Typically, a continuous layer stack (52L, 54L, 56L) can be deposited over a dielectric material layer (such as a lower fourth interconnect level dielectric material layer 641) and a tubular dielectric spacer 42. This continuous layer stack (52L, 54L, 56L) includes a heater pad layer 52L, a phase change material layer 54L comprising a phase change material, and a top electrode material layer 56L. The heater pad layer 52L can be deposited directly on the dielectric material layer through which the via opening 41 extends vertically, and directly on the tubular dielectric spacer 42 located in the peripheral region of the via opening 41.

[0064] refer to Figure 6 A first patterning process can be performed to pattern the consecutive layer stacks (52L, 54L, 56L) into in-process layer stacks (52', 54', 56'). Specifically, a first patterned etch mask layer 77 can be formed over the consecutive layer stacks (52L, 54L, 56L). For example, the first patterned etch mask layer 77 can be formed by applying a photoresist layer over the consecutive layer stacks (52L, 54L, 56L) and photolithographically patterning the photoresist layer into a discrete array of patterned photoresist material portions. In one embodiment, the first patterned etch mask layer 77 may comprise a two-dimensional array, such as a two-dimensional rectangular periodic array, of patterned photoresist material portions located in the memory array region 100. In one embodiment, each patterned photoresist material portion may have a rectangular horizontal cross-sectional shape. In one embodiment, the lateral dimension of each patterned photoresist material portion can be selected to provide patterning of at least two phase-change memory cells in subsequent processing steps. Optionally, the lateral dimension of each patterned photoresist material portion can be selected to provide patterning of individual phase-change memory cells in subsequent processing steps.

[0065] A first anisotropic etching process can be performed to etch portions of the continuous layer stack (52L, 54L, 56L) that are not masked by the first patterned etching mask layer 77. The etching chemistry of the first anisotropic etching process selectively etches the material of the continuous layer stack (52L, 54L, 56L) relative to the material of the dielectric material layer (such as the lower fourth interconnect level dielectric material layer 641) in which the tubular dielectric spacers 42 are embedded. The continuous layer stack (52L, 54L, 56L) is patterned into in-process layer stacks (52', 54', 56'), each in-process layer stack (52', 54', 56') comprising an in-process heater pad 52', an in-process phase change material portion 54', and an in-process top electrode 56'. As used herein, "in-process" elements refer to elements whose structure and / or composition are changed in subsequent process steps. Each in-process heater pad 52' may be a patterned portion of the heater pad layer 52L. In each process, the phase change material portion 54' can be a patterned portion of the phase change material layer 54L. In each process, the top electrode 56' can be a patterned portion of the top electrode material layer 56L. For each layer stack (52', 54', 56'), the sidewalls of the heater pad 52' in the process can be perpendicularly aligned with the sidewalls of the phase change material portion 54' in the process, and can be perpendicularly aligned with the sidewalls of the top electrode 56' in the process. The first surface and the second surface are "perpendicularly aligned" as used herein, wherein the second surface is positioned above or below the first surface, and the first surface and the second surface lie in the same vertical plane, which can be flat or curved in a horizontal cross-sectional view. The first patterned etch mask layer 77 can subsequently be removed, for example, by ashing.

[0066] refer to Figure 7 According to aspects of this disclosure, sidewall liner layers 58L can be deposited on the physically exposed surfaces of the layer stacks (52', 54', 56') and on the physically exposed top surfaces of dielectric material layers (such as the lower fourth interconnect level dielectric material layer 641) in which the bottom electrode 38 and tubular dielectric spacers 42 are embedded. In one embodiment, the sidewall liner layer 58L may comprise a metal nitride material layer deposited by a conformal deposition process (such as chemical vapor deposition). In one embodiment, the sidewall liner layer 58L may comprise a second metal nitride material, which may comprise TiN, TaN, WN, and / or MoN, and / or substantially composed of TiN, TaN, WN, and / or MoN. The thickness of the sidewall liner layer 58L may be in the range of 1 nm to 20 nm, such as in the range of 2 nm to 4 nm, but smaller or larger thicknesses may also be used.

[0067] According to aspects of this disclosure, the electrical conductivity of the second metal nitride material can be reduced by incorporating carbon or nitrogen atoms into the metal nitride material layer through in-situ or out-of-situ doping (i.e., incorporating carbon or nitrogen atoms during or after the deposition of the sidewall liner layer 58L). For example, during the chemical vapor deposition of the sidewall liner layer 58L, carbon or nitrogen atoms can be provided by a reactive carbon-containing gas (such as acetylene or ethylene) or a reactive nitrogen-containing gas (such as ammonia). Optionally, after the deposition process of the sidewall liner layer 58L, the sidewall liner layer 58L can be exposed to an environment containing reactive carbon-containing or reactive nitrogen-containing substances at elevated temperatures. Alternatively, after the deposition process of the sidewall liner layer 58L, an ion implantation process or a plasma doping process can be performed.

[0068] Carbon or nitrogen atoms can be incorporated into the second metal nitride material of the sidewall liner layer 58L at a certain atomic concentration, such that the conductivity of the doped metal nitride material of the sidewall liner layer 58L after incorporation of carbon or nitrogen atoms is less than 1 / 3 of the conductivity of the second metal nitride material before incorporation. In an exemplary example, the conductivity of the sidewall liner layer 58L after incorporation of carbon or nitrogen atoms can reach 1.0 x 10⁻⁶. 1 S / cm to 1.0x10 5 Within the range of S / cm.

[0069] Typically, the ratio of metal atoms to nitrogen atoms in the stoichiometric metal compound MN is 1:1, where M is Ta, Ti, Mo, or W. In embodiments using nitrogen doping, when nitrogen atoms are doped into the stoichiometric metal compound to form the sidewall liner layer 58L of this disclosure, the ratio of metal atoms to nitrogen atoms in the sidewall liner layer 58L can be in the range of 1:1.02 to 1:1.05. In embodiments using carbon doping, when carbon atoms are doped into the stoichiometric metal compound to form the sidewall liner layer 58L of this disclosure, the ratio of metal atoms, nitrogen atoms, and carbon atoms in the sidewall liner layer 58L can be in the range of 1:1:0.02 to 1:1:0.05. Typically, the atomic concentration of additional nitrogen atoms in a nitrogen-doped metal nitride material can be in the range of 0.02 times to 0.05 times the atomic concentration of metal atoms. Similarly, the atomic concentration of carbon atoms in carbon-doped metal nitride materials can range from 0.02 times to 0.05 times the atomic concentration of metal atoms.

[0070] In one embodiment, after the doping process, the conductivity of the second metal nitride material of the sidewall liner layer 58L may be less than 1 / 3, and preferably less than 1 / 10, of the conductivity of the first metal nitride material of the heater liner 52' ​​in the process. In other words, the conductivity of the material comprising the heater liner 52' ​​in the process is at least 3 times, and preferably at least 10 times, the conductivity of the sidewall liner material of the sidewall liner layer 58L.

[0071] Typically, the first metal nitride material of the heater pad layer 52L (and the heater pad 52' in the process) and the second metal nitride material (which is a doped metal nitride material) of the sidewall pad layer 58L can be selected such that the resistance of the phase change memory material cell with a high resistance value is determined by the resistance of the heater pad patterned from the heater pad 52' in the process and the resistance of the sidewall pad patterned from the sidewall pad layer 58L. This resistance state includes a high resistance state and a first resistance state with a relatively high resistance value. In this embodiment, the resistance of the amorphous volume of the phase change material portion does not determine the resistance of the phase change memory cell in the high resistance state. Therefore, the phase change memory cell can operate without being affected by any resistance drift of the phase change material.

[0072] refer to Figure 8 An anisotropic etching process can be performed to remove the horizontally extending portions of the sidewall liner layer 58L. The anisotropic etching process can be selective for the material of the dielectric material layer (such as the lower fourth interconnect level dielectric material layer 641) in which the tubular dielectric spacer 42 is embedded. Each remaining vertically extending portion of the sidewall liner layer 58L constitutes a process sidewall liner 58' laterally surrounding the respective process layer stack (52', 54', 56'). Each process sidewall liner 58' contacts each sidewall of the respective process layer stack (52', 54', 56') of the process heater liner 52', the process phase change material portion 54', and the process top electrode 56'. In one embodiment, the upper surface segment of each sidewall of the process top electrode 56' may be physically exposed. Typically, the process sidewall liner 58' can be formed around the layer stack (52', 54', 56') in each process by conformally depositing and anisotropically etching layers of sidewall liner material.

[0073] refer to Figure 9A second patterning process can be performed to pattern the in-process layer stack (52', 54', 56') and the in-process sidewall pad 58'. The second patterned etch mask layer 79 can be formed over the in-process layer stack (52', 54', 56') and the in-process sidewall pad 58' in such a way that it covers a first region of the in-process layer stack (52', 54', 56') and the in-process sidewall pad 58', but does not cover a second region of the in-process layer stack (52', 54', 56') and the in-process sidewall pad 58'. For example, a photoresist layer (not shown) can be applied over the in-process layer stack (52', 54', 56') and the in-process sidewall pad 58', and the photoresist layer can be photolithographically patterned into a two-dimensional array of patterned photoresist material, such as a rectangular array. In one embodiment, the second patterned etch mask layer 79 may cover at least two non-interconnected discrete regions of the layer stack (52', 54', 56') in each process, i.e., discrete regions separated by gaps not covered by the second patterned etch mask layer 79.

[0074] A second anisotropic etching process can be performed to etch the unmasked portions of the layer stacks (52', 54', 56') and the sidewall pads 58' in the process, that is, to etch the portions of the layer stacks (52', 54', 56') and the sidewall pads 58' that are not masked by the second patterned etch mask layer 79. The etching chemistry of the second anisotropic etching process selectively etches the material of the layer stacks (52', 54', 56') and the sidewall pads 58' in the process relative to the material of the dielectric material layer (such as the lower fourth interconnect level dielectric material layer 641) in which the tubular dielectric spacers 42 are embedded.

[0075] In one embodiment, the second patterning process can pattern each successive combination of the in-process stack (52', 54', 56') and the in-process sidewall pad 58' into a plurality of discrete material portions that are not adjacent to each other. In one embodiment, each patterned portion of the in-process stack (52', 54', 56') includes a corresponding stack comprising a heater pad 52, a phase change material portion 54, and a top electrode 56. According to embodiments of the present disclosure, each patterned portion of the in-process sidewall pad 58' constitutes a sidewall pad 58. The in-process stack (52', 54', 56') can be patterned into a plurality of stacks (52, 54, 56). The in-process sidewall pad 58' can be patterned into a plurality of sidewall pads 58. For each layer stack (52, 54, 56), the lateral distance between the sidewall of the layer stack (52, 54, 56) and the proximal sidewall of the lower heater element 52 can be in the range of 30 nm to 200 nm, such as in the range of 50 nm to 150 nm, but smaller or larger lateral distances can also be used.

[0076] Typically, at least one sidewall pad 58 can be formed on the sidewalls of each layer stack (52, 54, 56) by depositing and patterning a sidewall pad material, each layer stack (52, 54, 56) being a patterned portion of a continuous layer stack (52L, 54L, 56L). The sidewall pad material of at least one sidewall pad 58 comprises a material having a higher conductivity than that of the amorphous phase of the phase change material. The sidewall pad material may comprise a metal nitride material formed by doping it with carbon or nitrogen atoms, such that the metal nitride material has a lower conductivity than that of a stoichiometric metal nitride material. Therefore, in embodiments where the amorphous phase portion of the phase change material and the sidewall pad 58 provide two parallel conductive paths, the sidewall pad 58 provides a lower resistance path and primarily determines the total resistance of the two parallel conductive paths during operation of the phase change memory cell of this disclosure. Because the resistance drift effect of the phase change material is suppressed during the operation of the phase change memory cell, this aspect is particularly useful for the operation of phase change memory cells used in computing in memory (CIM) applications.

[0077] refer to Figure 10 The second patterned etched mask layer 79 can be removed, for example, by ashing. Each successive combination of the bottom electrode 38, heater pad 52, phase change material portion 54, top electrode 56, and at least one sidewall pad 58 constitutes a phase change memory cell 50. The vertically extending portion of the heater pad 52 serves as a heating element for the phase change memory cell 50 and provides various types of thermal pulses required to program the phase change material portion 54 to a target resistive state after a suitable programming pulse (i.e., a current pulse) is applied between the bottom electrode 38 and the top electrode 56.

[0078] In one embodiment, each phase change memory cell 50 includes: a tubular dielectric spacer 42 located within a via opening 41 in a dielectric material layer (such as a lower fourth interconnect dielectric material layer 641); a heater pad 52 including a vertical extension laterally surrounded by the tubular dielectric spacer 42 and a horizontal extension positioned above a top surface segment of the dielectric material layer (such as the lower fourth interconnect dielectric material layer 641); a phase change material portion 54 including a phase change material contacting the top surface of the heater pad layer 52L; and a top electrode 56 contacting the top surface of the phase change material portion 54.

[0079] In one embodiment, the heater pad 52 includes a flat horizontal surface segment PHSS disposed on a dielectric material layer (such as the lower fourth interconnect level dielectric material layer 641), and also includes an annular raised surface segment ACSS adjacent to the periphery of an opening in the flat horizontal surface segment PHSS and disposed on the via opening 41; and the phase change material portion 54 contacts the annular raised surface segment ACSS.

[0080] In one embodiment, the vertically extending portion of the heater pad 52 includes a vertically extending seam S; and the top surface of the heater pad 52 includes an annular raised surface segment ACSS having a bottom tip abutting the top of the vertically extending seam S. In one embodiment, the phase change material portion 54 includes a vertically extending portion located in the central region of the through-hole opening 41; and the vertically extending portion of the heater pad 52 includes a cylindrical inner sidewall that contacts the vertically extending portion of the phase change material portion 54.

[0081] In one embodiment, the phase change memory unit 50 includes at least one sidewall liner 58 located on at least one sidewall of the phase change material portion 54, contacting the sidewall of a horizontally extending portion of the heater liner 52, and comprising a material having a higher conductivity than the amorphous phase of the phase change material.

[0082] Typically, reference Figure 8 The first patterning process described and reference Figure 9 The second patterning process described herein can use various pattern combinations to provide an array of phase-change memory cells 50 with different configurations. Figures 11A to 11C It shows in Figures 8 to 10 An ordered top view of the first configured region of the embodiment structure during the processing steps. Figures 12A to 12C It shows in Figures 8 to 10 An ordered top view of the second configuration region of the embodiment structure during the processing steps. Figures 13A to 13C It shows in Figures 8 to 10 An ordered top view of the third configuration region of the embodiment structure during the processing steps. Figure 14 It shows in Figure 8 A top view of the fourth configuration area of ​​the embodiment structure after the processing steps. Figures 11A to 14 The various configurations shown are merely descriptions of specific configurations and do not limit the scope of this disclosure.

[0083] refer to Figure 11A , showed Figure 8 The region at the process step includes the first configuration of the embodiment structure comprising the in-process layer stack (52', 54', 56') and the in-process sidewall gasket 58'. The in-process layer stack (52', 54', 56') may include a first sidewall parallel to a first horizontal direction hd1 and a second sidewall parallel to a second horizontal direction hd2. The second horizontal direction hd2 may be perpendicular to the first horizontal direction hd1.

[0084] refer to Figure 11B The diagram illustrates a region of a first configuration of an embodiment structure after the formation of the second patterned etch mask layer 79 and before the execution of the second anisotropic etching process. The second patterned etch mask layer 79 may include a two-dimensional array (e.g., a 2xN array) of patterned discrete etch mask material portions (such as patterned photoresist material portions) covering 2N segments of the first sidewalls of the layer stack (52', 54', 56') in the process. In the illustrated example, the integer N is 4. Typically, the integer N can be any positive integer. As described above, the layer stack (52', 54', 56') in the process includes a first sidewall extending laterally along a first horizontal direction hd1 and a second sidewall extending laterally along a second horizontal direction hd2. The masking material portions of the second patterned etch mask layer 79 extend laterally along the second horizontal direction hd2 and may be laterally spaced from each other along the first horizontal direction hd1.

[0085] refer to Figure 11C You can refer to, for example Figure 9 The described process involves performing a second anisotropic etching process. This second anisotropic etching process removes unmasked portions of the layer stacks (52', 54', 56') not covered by the second patterned etch mask layer 79. Each patterned portion of the layer stacks (52', 54', 56') includes a layer stack (52, 54, 56) containing a corresponding heater pad 52, a corresponding phase change material portion 54, and a corresponding top electrode 56. Typically, multiple patterned portions of each layer stack (52', 54', 56') may include at least one row of patterned portions arranged along a first horizontal direction hd1. Figure 11CIn the first configuration shown, at least one patterned row may include two rows of patterned portions of the in-process layer stack (52', 54', 56'), i.e., two rows of layer stacks (52, 54, 56) constituting a 2xN array of layer stacks (52, 54, 56). Typically, a PxQ array of in-process layer stacks (52', 54', 56') can be used, and can be achieved by using... Figures 11A to 11C The first configuration shown forms a phase-change memory cell 50 in a 2PxQN array.

[0086] Generally, at least one sidewall pad 58 may be formed on each layer stack (52, 54, 56) within each phase change memory cell 50. In a first configuration, at least one sidewall pad 58 within each phase change memory cell 50 may consist of a single sidewall pad 58 formed directly on the sidewall of the layer stack (52, 54, 56) of the phase change memory cell 50, which is a patterned portion of a continuous layer stack (52L, 54L, 56L).

[0087] refer to Figure 12A , showed Figure 8 The region at the process step includes a second configuration of an embodiment structure comprising two in-process layer stacks (52', 54', 56') and two in-process sidewall gaskets 58'. Each in-process layer stack (52', 54', 56') may include a first sidewall parallel to a first horizontal direction hd1 and a second sidewall parallel to a second horizontal direction hd2. The second horizontal direction hd2 may be perpendicular to the first horizontal direction hd1.

[0088] refer to Figure 12BThe diagram illustrates a region of a second configuration of an embodiment structure after the formation of the second patterned etch mask layer 79 and before the execution of the second anisotropic etch process. The second patterned etch mask layer 79 may include a 1xN array of patterned discrete etch mask material portions (such as patterned photoresist material portions) covering 2N segments of the first sidewall of each layer stack (52', 54', 56') in the process. Each patterned discrete etch mask material portion may include a strip of photoresist material extending laterally along a second horizontal direction hd2 and having a uniform width along a first horizontal direction hd1. In the illustrated example, the integer N is 4. Typically, the integer N can be any positive integer. As described above, each layer stack (52', 54', 56') in the process includes a first sidewall extending laterally along the first horizontal direction hd1 and a second sidewall extending laterally along the second horizontal direction hd2. The masking material portion of the second patterned etched mask layer 79 extends laterally along the second horizontal direction hd2 and can be laterally spaced apart from each other along the first horizontal direction hd1.

[0089] refer to Figure 12C You can refer to, for example Figure 9 The described process involves performing a second anisotropic etching process. This second anisotropic etching process removes unmasked portions of the layer stacks (52', 54', 56') not covered by the second patterned etch mask layer 79. Each patterned portion of the layer stacks (52', 54', 56') includes a layer stack (52, 54, 56) containing a corresponding heater pad 52, a corresponding phase change material portion 54, and a corresponding top electrode 56. Typically, multiple patterned portions of each layer stack (52', 54', 56') may include at least one row of patterned portions arranged along a first horizontal direction hd1. Figure 12C In the second configuration shown, at least one patterned row may include a row of patterned portions of the layer stacks (52', 54', 56') in the process, that is, rows of the layer stacks (52, 54, 56) constituting a 1xN array of layer stacks (52, 54, 56). Typically, a PxQ array of layer stacks (52', 54', 56') in the process can be used, and can be achieved by using... Figures 12A to 12C The second configuration shown forms the phase-change memory cell 50 of the PxQN array.

[0090] Generally, at least one sidewall pad 58 may be formed on each layer stack (52, 54, 56) within each phase change memory cell 50. In a second configuration, at least one sidewall pad 58 within each phase change memory cell 50 may include two sidewall pads 58 formed directly on a pair of sidewalls of the layer stack (52, 54, 56) of the phase change memory cell 50, which are patterned portions of a continuous layer stack (52L, 54L, 56L). The pair of sidewalls may be parallel to each other, and the two sidewall pads 58 may be laterally spaced from each other in a horizontal direction (such as a second horizontal direction hd2).

[0091] refer to Figure 13A , showed Figure 8 The region at the process step includes the third configuration of the embodiment structure comprising process layer stacks (52', 54', 56') and process sidewall gaskets 58'. Each process layer stack (52', 54', 56') may include a first sidewall parallel to a first horizontal direction hd1 and a second sidewall parallel to a second horizontal direction hd2. The second horizontal direction hd2 may be perpendicular to the first horizontal direction hd1.

[0092] refer to Figure 13B The diagram illustrates a region of a third configuration of an embodiment structure after the formation of the second patterned etch mask layer 79 and before the execution of the second anisotropic etching process. The second patterned etch mask layer 79 may include pairs of patterned discrete etch mask material portions (such as patterned photoresist material portions) that cover all second sidewalls of the in-process layer stacks (52', 54', 56') and a segment of each first sidewall adjacent to a corresponding second sidewall of the in-process layer stacks (52', 54', 56'). Each first sidewall of the in-process layer stacks (52', 54', 56') includes a central segment not covered by the second patterned etch mask layer 79. As described above, each in-process layer stack (52', 54', 56') includes a first sidewall extending laterally along a first horizontal direction hd1 and a second sidewall extending laterally along a second horizontal direction hd2. The two masking material portions of the second patterned etch mask layer 79 extend laterally along the second horizontal direction hd2 and can be laterally spaced apart from each other along the first horizontal direction hd1, so that the central segment of each first sidewall of the layer stack (52', 54', 56') in the process is not covered by the second patterned etch mask layer 79.

[0093] refer to Figure 13C You can refer to, for example Figure 9The described process involves performing a second anisotropic etching process. This second anisotropic etching process removes unmasked portions of the layer stacks (52', 54', 56') not covered by the second patterned etch mask layer 79. Each patterned portion of the layer stacks (52', 54', 56') includes a layer stack (52, 54, 56) containing a corresponding heater pad 52, a corresponding phase change material portion 54, and a corresponding top electrode 56. Typically, multiple patterned portions of each layer stack (52', 54', 56') may include at least one row of patterned portions arranged along a first horizontal direction hd1. Figure 13C In the third configuration shown, at least one patterned row may include rows of two patterned portions of the process stack (52', 54', 56'), i.e., rows of the stack (52, 54, 56) constituting a 1x2 array of the stack (52, 54, 56). Typically, a PxQ array of the process stack (52', 54', 56') can be used, and can be achieved by using... Figures 13A to 13C The third configuration shown forms the phase-change memory cell 50 of the Px2Q array.

[0094] Generally, at least one sidewall pad 58 may be formed on each layer stack (52, 54, 56) within each phase change memory cell 50. In a third configuration, at least one sidewall pad 58 within each phase change memory cell 50 may consist of a single sidewall pad 58 formed directly on the three sidewalls of the layer stack (52, 54, 56) of the phase change memory cell 50, which is a patterned portion of a continuous layer stack (52L, 54L, 56L).

[0095] refer to Figure 14 , showed Figure 8 The fourth configuration of the embodiment structure following the process steps. In the fourth configuration, modifications were made. Figure 8 The masking pattern of the first patterned etch mask layer 77 used in the processing step is such that the pattern of the first patterned etch mask layer 77 is the same as the target pattern of the layer stack (52, 54, 56) array of the phase change memory cell array 50. In this embodiment, reference is made to... Figure 6 The described first anisotropic etching process directly patterns the continuous layer stack (52L, 54L, 56L) into an array of layer stacks (52, 54, 56). Furthermore, during the execution of the reference... Figure 7 and Figure 8 In the described processing steps, the sidewall liner layer 58L can be directly patterned as the sidewall liner 58. Therefore, if the fourth configuration of the embodiment structure is used, the reference can be omitted. Figure 9 and Figure 10 The described processing steps.

[0096] Generally, at least one sidewall pad 58 can be formed on each layer stack (52, 54, 56) within each phase change memory cell 50. In a fourth configuration, at least one sidewall pad 58 within each phase change memory cell 50 can have a ring-shaped configuration. In other words, at least one sidewall pad 58 within each phase change memory cell 50 can consist of a single sidewall pad 58 that is topologically co-fibered with the toroidal surface, i.e., it can be continuously deformed without forming new holes and without eliminating any pre-existing holes in the toroidal surface. The single sidewall pad 58 can be formed directly on each sidewall of the corresponding layer stack (52, 54, 56), which is a patterned portion of a continuous layer stack (52L, 54L, 56L).

[0097] refer to Figure 15 A sealing dielectric layer 643 and additional metal interconnect structures (62, 642, 648) may be formed above the phase-change memory cell 50. The sealing dielectric layer 643 includes at least one interlayer dielectric material, such as silicon oxide, silicon nitride, and / or silicon carbonitride. The sealing dielectric layer 643 constitutes an upper fourth interconnect level dielectric material layer. The combination of the lower fourth interconnect level dielectric material layer 641 and the sealing dielectric layer 643 constitutes a fourth interconnect level dielectric material layer 640. The additional metal interconnect structures (62, 642, 648) may include: a top contact via structure 62 in contact with the top surface of a corresponding top electrode 56; a third metal via structure 642 formed to pass through the lower part of the fourth interconnect level dielectric material layer 640; and a fourth metal line structure 648 formed in the upper part of the fourth interconnect level dielectric material layer 640 on the top contact via structure 62 and the third metal via structure 642. The top surface of the fourth metal wire structure 648 may be coplanar with the horizontal top surface of the sealing dielectric layer 643. Additional dielectric material layers (not shown) and additional metal interconnect structures may be formed as needed to provide electrical connections between the top electrode 56 of the phase change memory cell 50 and the respective semiconductor devices 700 located beneath the dielectric material layers (601, 610, 620, 630, 640).

[0098] Typically, a programmable transistor 701 can be provided on a substrate 8. Metal interconnect structures (612, 618, 622, 628, 632, 638) embedded within interconnect-level dielectric material layers (601, 610, 620, 630, 641) can be formed above the programmable transistor 701. A bottom electrode 38 and tubular dielectric spacers 42 can be formed within dielectric material layers (such as a lower fourth interconnect-level dielectric material layer 641). Each heater pad 52 can be electrically connected to an electrical node of the corresponding programmable transistor 701, such as an output node. A continuous layer stack (52L, 54L, 56L) comprising a heater pad layer 52L, a phase change material layer 54L including a phase change material, and a top electrode material layer 56L can be deposited and patterned to form a layer stack (52, 54, 56) of heater pad 52, phase change material portion 54, and top electrode 56. Sidewall liner layer 58L can be formed and patterned to form sidewall liner 58. At least one sidewall liner 58 can be formed on at least one sidewall of each layer stack (52, 54, 56).

[0099] Each sidewall liner 58 comprises a material having a higher conductivity than the amorphous phase of the phase change material in the phase change material portion 54. For each phase change memory cell 50, a sealing dielectric layer 643 may be directly deposited on at least one sidewall of the stacked layers (52, 54, 56) (which are patterned portions of a continuous stacked layer (52L, 54L, 56L), directly deposited on the outer sidewall of each of the at least one sidewall liner 58, and directly deposited on the top surface of the stacked layers (52, 54, 56). Thus, for each phase change memory cell 50, the sealing dielectric layer 643 is in contact with at least one sidewall of the stacked layers, the outer sidewall of each of the at least one sidewall liner 58, and the top surface of the stacked layers (52, 54, 56).

[0100] For each phase change memory cell 50 electrically connected to the programming transistor 701, the programming transistor 701 is configured to program the phase change memory cell 50 to at least three different resistance states by applying at least three different programming pulse modes to the heater pad 52. Figures 16A to 16D These are the various configurations of the phase change material portions 54 in various programmed resistor states according to embodiments of this disclosure.

[0101] refer to Figure 16AThe diagram illustrates a phase change memory cell 50 in a low-resistance state. In this embodiment, at least 99% of the entire volume of the phase change material portion 54 is in a polycrystalline phase. In one embodiment, the entire phase change material portion 54 may be a crystalline phase change material portion 54C comprising the polycrystalline phase change material. The electrical conductivity of the crystalline phase change material is higher than that of the materials of the heater pad 52 and at least one sidewall pad 58. Therefore, the main conductive path extends vertically between the heater pad 52 and the top electrode 56.

[0102] refer to Figure 16B The diagram illustrates a phase change memory cell 50 in a first intermediate state. In this embodiment, the phase change material portion 54 includes a first volume having an amorphous phase and a second volume having a crystalline phase. The first volume includes an amorphous phase change material portion 54A, and the second volume includes a crystalline phase change material portion 54C. The first volume is not in direct contact with at least one sidewall liner 58. The conductivity of the amorphous phase change material is lower than that of the materials of the heater liner 52 and at least one sidewall liner 58. Therefore, the main conductive path extends laterally within the heater liner 52 below the amorphous phase change material portion 54A and extends at an angle relative to the vertical direction through the crystalline phase change material portion 54C between the peripheral portion of the heater liner 52 and the top electrode 56.

[0103] refer to Figure 16C The diagram illustrates a phase change memory cell 50 in a second intermediate state, which provides a higher resistance than the first intermediate state. In this embodiment, the phase change material portion 54 includes a first volume having an amorphous phase and a second volume having a crystalline phase. The first volume includes an amorphous phase change material portion 54A, and the second volume includes a crystalline phase change material portion 54C. The first volume is in direct contact with at least one sidewall liner 58 but not with the top electrode 56. The conductivity of the amorphous phase change material is lower than that of the materials of the heater liner 52 and at least one sidewall liner 58. Therefore, the main conductive path extends laterally within the heater liner 52 below the amorphous phase change material portion 54A, extends vertically through the lower portion of each sidewall liner 58, and extends at an angle relative to the vertical direction through the middle portion of each sidewall liner 58 and the crystalline phase change material portion 54C between the top electrode 56.

[0104] refer to Figure 16D The diagram illustrates a phase change memory cell 50 in a high-resistivity state. In this embodiment, at least 99% of the entire volume of the phase change material portion 54 is in the amorphous phase.

[0105] Although Figures 16A to 16DThe diagram illustrates four resistance states of the phase change memory cell 50, but pulse patterns derived from programming pulses from programming transistor 701 can be pre-programmed to select from multiple programming pulse patterns stored in the programming circuitry of the phase change memory cell 50. The total number of pre-programmed pulse patterns can range from 2 to 210, such as 3 to 28, and / or 4 to 26. The total number of programmable resistance states in each phase change memory cell 50 can be the same as the total number of pre-programmed pulse patterns. In one embodiment, each programming transistor 701 can be configured to apply at least four different programming pulse patterns to a corresponding heater pad 52. The programming pulses can have corresponding durations and / or voltage drop rates to provide a controlled cooling rate for the molten region of the phase change material portion 54. The duration of the programming pulses can range from 10 nanoseconds to 500 nanoseconds, with longer programming pulses typically corresponding to the formation of large crystalline regions in the phase change material portion 54.

[0106] refer to Figure 17 The diagram illustrates a second embodiment structure according to an embodiment of the present disclosure. The second embodiment structure can be viewed from... Figure 1 The structure shown is derived from the first embodiment, by forming a through-hole opening 41 with a larger lateral dimension, and by performing a reference... Figure 3 and Figure 4 The described processing steps, and the deposition of a higher standard than the reference... Figure 5 The heater liner layer 52L described is a heater liner layer 52L with a larger thickness.

[0107] For example, such as Figure 2 The lateral dimension (such as diameter) of the bottom of each via opening 41 formed at the corresponding processing step can be in the range of 80 nm to 400 nm, but smaller or larger lateral dimensions can also be used. (Selection as...) Figure 3 The thickness of the dielectric spacer layer 42L deposited at the corresponding process step is such that the difference between the bottom width of each via opening 41 and twice the thickness of the dielectric spacer layer 42L is greater than the target range of the bottom width of each vertical extension of the subsequently formed heater pad layer. In an exemplary example, if the bottom width of each via opening 41 is in the range of 80 nm to 400 nm, and if the target range of the bottom width of each vertical extension of the heater pad layer 52L is in the range of 20 nm to 100 nm, then the thickness of the dielectric spacer layer 42L can be in the range of 15 nm to 150 nm, such as 30 nm to 80 nm, but smaller or larger thicknesses can also be used. Thus, the lateral distance between the inner cylindrical sidewall and the outer cylindrical sidewall of each tubular dielectric spacer 42 can be approximately in the range of 15 nm to 150 nm, for example, in the range of 30 nm to 80 nm, but smaller or larger lateral distances can also be used.

[0108] A heater pad layer 52L of sufficient thickness can be deposited to fill the main part and / or all of the volume of each void within the via opening 41 with the deposited material of the heater pad layer 52L. The thickness of the horizontally extending portion of the heater pad layer 52L formed above the top surface of a dielectric material layer (such as the lower fourth interconnect level dielectric material layer 641) can be in the range of 25 nm to 120 nm, such as in the range of 50 nm to 80 nm, but smaller or larger thicknesses can also be used.

[0109] As in the first embodiment, a vertically extending seam S can be formed within each vertical extension of the heater liner layer 52L, each vertical extension of the heater liner layer 52L being deposited within a portion of the volume of a respective through-hole opening 41. Another portion of the volume of the corresponding through-hole opening 41 can be occupied by a tubular dielectric spacer 42. As in the first embodiment, the heater liner layer 52L is formed with a flat horizontal surface segment PHSS disposed on a dielectric material layer (e.g., the lower fourth interconnect level dielectric material layer 641), and an annular raised surface segment ACSS, each annular raised surface segment ACSS abutting the periphery of a corresponding opening in the flat horizontal surface segment PHSS and including a corresponding bottom tip abutting the top of the vertically extending seam S.

[0110] refer to Figure 18 The heater liner layer 52L can be vertically recessed by performing a back-etching process, which is a recessed etching process that etches the material of the heater liner layer 52L. The back-etching process vertically recesses the horizontal extension of the heater liner layer 52L. Simultaneously, the back-etching process also vertically recesses the annular raised surface segment ACSS of the heater liner layer 52L. In other words, the back-etching process simultaneously etches both the annular raised surface segment ACSS and the flat horizontal surface segment PHSS of the heater liner layer 52L.

[0111] The etch-back process can include a wet etching process or a reactive ion etching process. The duration of the etch-back process can be selected so that the thinned horizontal extension of the heater pad layer 52L has a thickness within a target thickness range, which can be in the range of 1 nm to 50 nm, such as in the range of 3 nm to 20 nm, but smaller or larger thicknesses can also be used. Typically, this is achieved by referring to... Figure 17 and Figure 18The thickness of the horizontal extension of the heater liner 52L formed by the described processing steps can be less than the thickness of the horizontal extension of the heater liner 52L in the first embodiment structure, and the horizontal extension of the heater liner 52L in the second embodiment structure can provide higher resistance than the horizontal extension of the heater liner 52L in the first embodiment structure.

[0112] refer to Figure 19 Reference can be executed Figure 5 A subset of the processing steps described are used to deposit a phase change material layer 54L and a top electrode material layer 56L over a horizontally extended portion of the heater liner layer 52L.

[0113] refer to Figure 20 Reference can be executed Figure 6 The described processing steps are for patterning continuous layer stacks (52L, 54L, 56L) into a two-dimensional array of process layer stacks (52', 54', 56').

[0114] refer to Figure 21 Reference can be executed Figures 7 to 15 The described processing steps form a two-dimensional array of phase-change memory devices 50. Each phase-change memory cell 50 of the second embodiment structure may have a larger bottom width for the vertical extension of the heater pad 52 and / or a smaller thickness for the horizontal extension of the heater pad 52, which can advantageously provide enhanced resistance distribution characteristics for the various programming states of the phase-change memory cells 50.

[0115] refer to Figure 22 This illustrates a third embodiment structure according to an embodiment of the present disclosure after the formation of the heater liner layer 52L. The third embodiment structure can be derived from... Figure 1 The structure shown is derived from the first embodiment, by forming a through-hole opening 41 with a larger lateral dimension, and by performing a reference... Figure 3 and Figure 4 The described process steps, and the deposition having the same characteristics as the reference Figure 5 The heater liner layer 52L described is a heater liner layer 52L with the same thickness range. The heater liner layer 52L can be deposited by a conformal deposition process.

[0116] As described above, voids may exist within each volume laterally surrounded by the tubular dielectric spacer 42. In the third embodiment, the maximum width of each void within the via opening 41 volume is greater than half the thickness of the heater liner layer 52L. Therefore, the voids within the via opening 41 volume are not completely filled by the heater liner layer 52L. In other words, after the heater liner layer 52L is formed, there are unfilled portions of voids that may exist within each volume of the via opening 41. In one embodiment, the inner cylindrical sidewall of the tubular portion of the heater liner layer 52L and the top surface segment of the horizontal extension of the corresponding lower bottom electrode 38 of the heater liner layer 52L may be physically exposed to each unfilled void existing within the volume of the corresponding via opening 41 through a dielectric material layer (such as the lower fourth interconnect level dielectric material layer 641).

[0117] As in the first embodiment, the heater liner layer 52L is formed with a flat horizontal surface segment PHSS and an annular raised surface segment ACSS placed on a dielectric material layer (such as the lower fourth interconnect level dielectric material layer 641). Each annular raised surface segment ACSS is adjacent to the periphery of a corresponding opening in the flat horizontal surface segment PHSS and includes a corresponding bottom tip point adjacent to the top of the vertically extending seam S.

[0118] refer to Figure 23 Reference can be executed Figure 5 A subset of the processing steps are described for depositing a phase change material layer 54L and a top electrode material layer 56L. In the third embodiment structure, the phase change material layer 54L includes vertically extending portions, each having a cylindrical sidewall that contacts a corresponding inner cylindrical sidewall of a tubular dielectric spacer 42 within the volume of a corresponding via opening 41, which extends vertically through a dielectric material layer (such as a lower fourth interconnect level dielectric material layer 641). Each vertically extending portion of the phase change material layer 54L may be deposited within an unfilled portion of a corresponding void, which is laterally surrounded by a corresponding tubular portion of the heater liner layer 52L. A subsequent top electrode material layer 56L is deposited over the phase change material layer 54L.

[0119] refer to Figure 24 Reference can be executed Figure 6 The described processing steps are for patterning continuous layer stacks (52L, 54L, 56L) into a two-dimensional array of process layer stacks (52', 54', 56').

[0120] refer to Figure 25 Reference can be executed Figures 7 to 15The described processing steps form a two-dimensional array of phase-change memory devices 50. Each phase-change memory cell 50 of the third embodiment may have a tubular vertical extension of a heater pad 52. In one embodiment, the lateral thickness (measured between the inner and outer cylindrical walls) of the tubular vertical extension of the heater pad 52 may be the same as the vertical thickness of the horizontal extension of the heater pad 52 (which lies above the dielectric material layer through which the via opening 41 extends vertically).

[0121] Common reference Figures 1 to 25 Furthermore, according to various embodiments of the present disclosure, a device structure is provided comprising: a tubular dielectric spacer 42 located within a via opening 41 in a dielectric material layer (such as a lower fourth interconnect dielectric material layer 641); a heater pad 52 including a vertical extension laterally surrounded by the tubular dielectric spacer 42 and a horizontal extension disposed above a top surface segment of the dielectric material layer (such as the lower fourth interconnect dielectric material layer 641); a phase change material portion 54 including a phase change material contacting the top surface of the heater pad layer 52L; and a top electrode 56 contacting the top surface of the phase change material portion 54.

[0122] In one embodiment, the heater pad 52 includes a flat horizontal surface segment PHSS disposed on a dielectric material layer (such as the lower fourth interconnect level dielectric material layer 641), and also includes an annular raised surface segment ACSS adjacent to the periphery of an opening in the flat horizontal surface segment PHSS and disposed on the via opening 41; and the phase change material portion 54 contacts the annular raised surface segment ACSS.

[0123] In one embodiment, the vertically extending portion of the heater pad 52 includes a vertically extending seam S; and the top surface of the heater pad 52 includes an annular raised surface segment ACSS having a bottom tip abutting the top of the vertically extending seam S.

[0124] In one embodiment, the phase change material portion 54 includes a vertically extending portion located in the central region of the through-hole opening 41; and the vertically extending portion of the heater liner 52 includes a cylindrical inner sidewall that contacts the vertically extending portion of the phase change material portion 54.

[0125] In one embodiment, the device structure includes at least one sidewall liner 58 located on at least one sidewall of the phase change material portion 54, contacting the sidewall of a horizontal extension of the heater liner 52, and the included material has a higher conductivity than the amorphous phase of the phase change material.

[0126] Figure 26This is a first flowchart illustrating the general processing steps for manufacturing a device structure according to an embodiment of the present disclosure.

[0127] Refer to step 2610 and Figures 1 to 2 , Figure 17 and Figure 22 A bottom electrode 38, a dielectric material layer (such as a lower fourth interconnect dielectric material layer 641), and a via opening 41 extending through the dielectric material layer (such as a lower fourth interconnect dielectric material layer 641) can be formed such that the top surface segment of the bottom electrode 38 is exposed below the via opening 41.

[0128] Refer to step 2620 and Figure 3 , Figure 4 , Figure 17 and Figure 22 A tubular dielectric spacer 42 can be formed in the peripheral region of the through-hole opening 41, such that the central portion of the top surface segment is exposed below the gap that is laterally surrounded by the tubular dielectric spacer 42.

[0129] Refer to step 2630 and Figure 5 , Figures 16A to 17 ,as well as Figure 22 and Figure 23 A continuous stack of layers (52L, 54L, 56L) can be formed over a dielectric material layer (such as the lower fourth interconnect dielectric material layer 641) and a tubular dielectric spacer 42. The continuous stack of layers (52L, 54L, 56L) includes a heater pad layer 52L, a phase change material layer 54L including a phase change material, and a top electrode material layer 56L.

[0130] Refer to step 2640 and Figures 6 to 16D , Figures 19 to 21 ,as well as Figure 24 and Figure 25 The continuous layer stack (52L, 54L, 56L) can be patterned into a layer stack (52, 54, 56) including heater pad 52, phase change material portion 54 and top electrode 56.

[0131] Figure 27 This is a second flowchart illustrating the general processing steps for manufacturing a device structure according to an embodiment of the present disclosure.

[0132] Refer to step 2710 and Figure 1 , Figure 2 and Figure 17 A bottom electrode 38, a dielectric material layer (such as a lower fourth interconnect dielectric material layer 641), and a via opening 41 extending through the dielectric material layer (such as a lower fourth interconnect dielectric material layer 641) can be formed such that the top surface segment of the bottom electrode 38 is exposed below the via opening 41.

[0133] Refer to step 2720 and Figures 3 to 5 and Figure 17 A heater pad layer 52L can be deposited within a portion of the volume of the via opening 41 and above a dielectric material layer (such as the lower fourth interconnect level dielectric material layer 641).

[0134] Refer to step 2730 and Figure 18 This allows the horizontal extension of the heater liner 52L to be recessed vertically.

[0135] Refer to step 2740 and Figure 19 A phase change material layer 54L and a top electrode material layer 56L, comprising a phase change material, can be deposited above the horizontal extension of the heater liner layer 52L.

[0136] Refer to step 2750 and Figures 6 to 16D , Figure 20 and Figure 21 The top electrode material layer 56L, the phase change material layer 54L, and the heater pad layer 52L can be patterned into a layer stack (52, 54, 56) including the heater pad 52, the phase change material portion 54, and the top electrode 56.

[0137] Within each phase-change memory cell, heater pads 52 and sidewall pads 58 are used to set the resistance level of the high-resistivity state of the phase-change memory cell. The combination of heater pads 52 and sidewall pads 58 suppresses the resistance drift effect of the phase change material portion 54, reduces the power consumption of the phase-change memory cell, reduces the error rate during phase-change memory cell operation, and provides for a reduction in the cell size of the phase-change memory cell. Typically, the thickness of heater pads 52 and sidewall pads 58 can be optimized to provide a wide range of resistance variations for the various resistance states of the phase-change memory cell and to facilitate efficient multi-level cell (MLC) operation, i.e., programming the cell to operate with three or more resistance states. Therefore, a larger programming window can be provided for MLC operation using the phase-change memory cell 50.

[0138] The embodiments of this disclosure provide an advancement in process technology for manufacturing phase-change memory devices by eliminating the need for a chemical mechanical polishing (CMP) process during the formation of heater elements, including the vertically extending portions of heater pads 52. In one embodiment, each heater pad 52 is formed within a via opening 41 and is laterally surrounded by a tubular dielectric spacer 42. The horizontally extending portions of the heater pads 52 are positioned over a dielectric material layer through which the via opening 41 extends vertically. A phase-change material portion 54 is disposed above the heater pads 52, and a top electrode 56 contacts the top surface of the phase-change material portion 54. The sequence of processing steps for forming the phase-change memory cell 50 reduces manufacturing complexity while improving thermal efficiency and cost-effectiveness. The phase-change memory cell 50 of this disclosure minimizes heat loss by using a low thermal conductivity material as the tubular dielectric spacer 42, which laterally surrounds the vertically extending portions of the heater pads 52 that serve as heater elements. Enhanced thermal isolation of the heater elements can enhance device performance for memory computing (CIM) applications.

[0139] According to one aspect of this application, a method of forming a device structure is provided, the method comprising: forming a bottom electrode, a dielectric material layer, and a via opening extending through the dielectric material layer such that a top surface segment of the bottom electrode is exposed below the via opening; forming a tubular dielectric spacer in a peripheral region of the via opening such that a central portion of the top surface segment is exposed below a void laterally surrounded by the tubular dielectric spacer; depositing a continuous layer stack over the dielectric material layer and the tubular dielectric spacer, the continuous layer stack comprising a heater pad layer, a phase change material layer including a phase change material, and a top electrode material layer; and patterning the continuous layer stack as a layer stack comprising a heater pad, a phase change material portion, and a top electrode. In some embodiments, the heater pad layer includes a vertically extending portion deposited in a void within the tubular dielectric spacer and a horizontally extending portion deposited above the top surface of the dielectric material layer. In some embodiments, a vertically extending seam is formed at the center of the vertically extending portion of the heater pad layer. In some embodiments, the phase change material layer includes a vertically extending portion having cylindrical sidewalls that contact the inner cylindrical sidewalls of a tubular dielectric spacer. In some embodiments, the method of forming the device structure further includes: depositing a dielectric spacer layer in a peripheral region of a via opening and over the dielectric material layer; and anisotropically etching the dielectric spacer layer, wherein the remaining vertically extending portion of the dielectric spacer layer filling the peripheral region of the via opening constitutes a tubular dielectric spacer. In some embodiments, a heater pad layer is deposited on a central portion of a top surface segment of a bottom electrode; and a phase change material layer is deposited on a flat horizontal surface segment of the heater pad layer, the flat horizontal surface segment being positioned above a horizontal plane containing the top surface of the dielectric material layer. In some embodiments, when depositing the heater pad layer, the heater pad layer includes a flat horizontal surface segment positioned above the dielectric material layer, and also includes an annular raised surface segment adjacent to the periphery of an opening in the flat horizontal surface segment and positioned above the via opening; and the phase change material layer is deposited directly on the annular raised surface segment. In some embodiments, a heater liner layer is deposited using a conformal deposition process; the maximum width of the voids is less than half the thickness of the heater liner layer; and a vertically extending seam is formed at the center of the voids filled by the vertically extending portion of the heater liner layer. In some embodiments, a heater liner layer is deposited using a conformal deposition process; the maximum width of the voids is greater than half the thickness of the heater liner layer; after the heater liner layer is formed, there is an unfilled portion of the voids within the volume of the via opening; and a vertically extending portion of the phase change material layer is deposited within the unfilled portion of the voids. In some embodiments, the method of forming a device structure further includes forming at least one sidewall liner by depositing and patterning a sidewall liner material, wherein at least one sidewall liner is formed on at least one sidewall of a layer stack, wherein the material comprising the at least one sidewall liner has a higher conductivity than the conductivity of the amorphous phase of the phase change material.

[0140] According to another aspect of this application, a method of forming a device structure is provided, the method comprising: forming a bottom electrode, a dielectric material layer, and a via opening extending through the dielectric material layer such that a top surface segment of the bottom electrode is exposed below the via opening; depositing a heater pad layer within a portion volume of the via opening and over the dielectric material layer; vertically recessing a horizontally extending portion of the heater pad layer; depositing a phase change material layer and a top electrode material layer over the horizontally extending portion of the heater pad layer, the phase change material layer comprising a phase change material; and patterning the top electrode material layer, the phase change material layer, and the heater pad layer into a layer stack comprising a heater pad, a phase change material portion, and a top electrode. In some embodiments, the method of forming the device structure further comprises forming a tubular dielectric spacer in a peripheral region of the via opening such that a central portion of the top surface segment is exposed below a void laterally surrounded by the tubular dielectric spacer, wherein a portion volume of the via opening includes the volume of the void within the tubular dielectric spacer. In some embodiments, vertically recessing the horizontally extending portion of the heater pad layer comprises performing an etch-back process that etches the material of the heater pad layer. In some embodiments, a vertically extending seam is formed within a vertically extending portion of a heater liner layer deposited within a portion of the via opening. In some embodiments, the heater liner layer has a flat horizontal surface segment and an annular raised surface segment, the flat horizontal surface segment being disposed above a dielectric material layer, the annular raised surface segment abutting the periphery of an opening in the flat horizontal surface segment, and including a bottom tip abutting the top of the vertically extending seam; and vertically recessing the horizontally extending portion of the heater liner layer includes performing an etch-back process that, while vertically recessing the horizontally extending portion of the heater liner layer, simultaneously vertically recesses the annular raised surface segment of the heater liner layer.

[0141] According to another aspect of this application, a device structure is provided, comprising: a tubular dielectric spacer located within a via opening in a dielectric material layer; a heater pad including a vertically extending portion laterally surrounded by the tubular dielectric spacer and a horizontally extending portion disposed above a top surface segment of the dielectric material layer; a phase change material portion including a phase change material contacting the top surface of the heater pad; and a top electrode contacting the top surface of the phase change material portion. In some embodiments, the heater pad includes a flat horizontal surface segment disposed above the dielectric material layer, and further includes an annular raised surface segment abutting the periphery of the opening in the flat horizontal surface segment and disposed above the via opening; and the phase change material portion contacting the annular raised surface segment. In some embodiments, the vertically extending portion of the heater pad includes a vertically extending seam; and the top surface of the heater pad includes an annular raised surface segment having a bottom tip abutting the top of the vertically extending seam. In some embodiments, the phase change material portion includes a vertically extending portion located in the central region of the via opening; and the vertically extending portion of the heater pad includes a cylindrical inner sidewall that contacts the vertically extending portion of the phase change material portion. In some embodiments, the device structure further includes at least one sidewall pad located on at least one sidewall of the phase change material portion, contacting the sidewall of the horizontally extending portion of the heater pad, and the included material has a higher electrical conductivity than the amorphous phase of the phase change material.

[0142] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand aspects of this disclosure. Unless explicitly disclosed otherwise herein, each embodiment described using the term "comprising" also inherently discloses that in some embodiments the term "comprising" may be replaced by "substantially consisting of" or "consisting of". When two or more elements are listed as alternatives in the same or different paragraphs, a Markush group comprising the list of two or more elements is also implicitly disclosed. When the auxiliary verb "able to" is used in this disclosure to describe the execution of a step in the formation or processing of an element, embodiments in which such an element or such step is not performed are also explicitly contemplated, provided that the resulting apparatus or device can provide equivalent results. Therefore, the auxiliary verb "able to" applied to the execution of a step in the formation or processing of an element should also be interpreted as "can" or "can or can not," provided that omitting such a step in the formation or processing of an element can provide the same or equivalent results, with equivalent results including slightly better and slightly worse results. Those skilled in the art should understand that they can readily use this disclosure as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and alterations can be made to them herein without departing from the spirit and scope of this disclosure.

Claims

1. A method for forming a device structure, comprising: A bottom electrode, a dielectric material layer, and a via opening extending through the dielectric material layer are formed such that the top surface segment of the bottom electrode is exposed below the via opening; A tubular dielectric spacer is formed in the peripheral region of the through-hole opening, such that the central portion of the top surface segment is exposed below the gap laterally surrounded by the tubular dielectric spacer; A continuous layer stack is deposited over the dielectric material layer and the tubular dielectric spacer, the continuous layer stack comprising a heater pad layer, a phase change material layer including a phase change material, and a top electrode material layer; as well as The continuous layer stack is patterned into a layer stack comprising a heater pad, a phase change material portion, and a top electrode.

2. The method according to claim 1, wherein, The heater liner includes a vertical extension deposited in the voids within the tubular dielectric spacer and a horizontal extension deposited above the top surface of the dielectric material layer.

3. The method according to claim 2, wherein, A vertically extending seam is formed at the center of the vertically extending portion of the heater liner layer.

4. The method according to claim 2, wherein, The phase change material layer includes a vertically extending portion having cylindrical sidewalls that contact the inner cylindrical sidewalls of the tubular dielectric spacer.

5. The method according to claim 1, further comprising: A dielectric spacer material layer is deposited in the peripheral region of the via opening and over the dielectric material layer; as well as The dielectric spacer material layer is anisotropically etched, wherein the remaining vertical extension of the dielectric spacer material layer that fills the peripheral region of the via opening constitutes the tubular dielectric spacer.

6. The method according to claim 1, wherein: The heater liner layer is deposited on the central portion of the top surface segment of the bottom electrode; and The phase change material layer is deposited on a flat horizontal surface segment of the heater liner layer, the flat horizontal surface segment being positioned above a horizontal plane containing the top surface of the dielectric material layer.

7. The method according to claim 1, wherein: When depositing the heater liner layer, the heater liner layer includes a flat horizontal surface segment disposed above the dielectric material layer, and also includes an annular raised surface segment adjacent to the periphery of an opening in the flat horizontal surface segment and disposed above the through-hole opening; and The phase change material layer is deposited directly on the annular protrusion surface segment.

8. The method according to claim 7, wherein: The heater liner layer is deposited using a conformal deposition process; The maximum width of the gap is less than half the thickness of the heater liner layer; and A vertically extending seam is formed at the center of the gap filled by the vertically extending portion of the heater liner layer.

9. A method for forming a device structure, comprising: A bottom electrode, a dielectric material layer, and a via opening extending through the dielectric material layer are formed such that the top surface segment of the bottom electrode is exposed below the via opening; A heater liner layer is deposited within a portion of the volume of the through-hole opening and above the dielectric material layer; The horizontal extension of the heater liner is recessed vertically; A phase change material layer and a top electrode material layer are deposited over the horizontal extension of the heater liner layer, the phase change material layer comprising a phase change material; as well as The top electrode material layer, the phase change material layer, and the heater pad layer are patterned into a layer stack comprising a heater pad, a phase change material portion, and a top electrode.

10. A device structure, comprising: A tubular dielectric spacer located within a through-hole opening in a dielectric material layer; The heater liner includes a vertical extension that is laterally surrounded by the tubular dielectric spacer and a horizontal extension that is positioned above the top surface section of the dielectric material layer. The phase change material portion includes the phase change material in contact with the top surface of the heater liner; as well as The top electrode contacts the top surface of the phase change material portion.

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