Manufacturing method of gate-all-around transistor
By doping the edge region of the sacrificial layer with an etching aid and using isotropic etching to form the inner sidewall, the problem of the inner sidewall tip of the gate-around transistor is solved, thereby improving device performance and yield.
Patent Information
- Application Number
- CN202511440537.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-10-09
- Publication Date
- 2026-02-17
AI Technical Summary
In existing manufacturing methods, the inner walls of the gate-around transistor have sharp points at the top and bottom, which leads to abnormal discharge between the gate stack structure and the source-drain regions, affecting device performance.
Etching aids are doped into the edge region of the sacrificial layer, and a dielectric filling region is formed by isotropic etching, so that the inner wall extends along the thickness direction of the semiconductor substrate, avoiding the formation of sharp points.
This prevents abnormal discharge between the gate stack structure and the source/drain regions, improving the operating performance and yield of the gate-around transistor.
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Figure CN121548065A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and in particular to a method for manufacturing a gate-around transistor. Background Technology
[0002] With the development of semiconductor technology, higher-performance semiconductor devices such as gate-around transistors (GMT-A) have emerged. Compared with planar transistors and fin field-effect transistors, GMT-A has higher gate control capability, which is beneficial for suppressing short-channel effects. In addition, in the actual manufacturing process, before forming the source and drain regions, etching and deposition processes are often used to form inner sidewalls at both ends of the sacrificial layer along its length to isolate the subsequently formed gate stack structure from the source and drain regions, thereby reducing leakage current.
[0003] However, the performance of gate-ring transistors manufactured using existing methods is not improved. Summary of the Invention
[0004] The purpose of this invention is to provide a method for manufacturing a gate ring transistor, which extends the inner sidewall near the inner side of the sacrificial layer along the thickness direction of the semiconductor substrate, prevents the top and bottom portions of the gate stack structure corresponding to the inner sidewall from having sharp points, avoids abnormal discharge between the gate stack structure and the source / drain regions, and improves the operating performance of the gate ring transistor.
[0005] To achieve the above objectives, the present invention provides a method for manufacturing a gate-around transistor (GMT). The method includes: first, forming a fin structure on a semiconductor substrate. Along the thickness direction of the semiconductor substrate, the fin structure includes alternately stacked sacrificial layers and channel layers, and in each sacrificial layer, at least two first edge regions along the thickness direction are doped with an etching aid. Next, forming a mask structure spanning the fin structure; and removing the portion of the fin structure exposed outside the mask structure. Next, using isotropic etching, removing the second edge regions at both ends of the sacrificial layer along its length direction to form a dielectric filling region. The etching aid is used to extend the dielectric filling region along the thickness direction of the semiconductor substrate near the inner surface of the sacrificial layer. Next, forming inner sidewalls within the dielectric filling region.
[0006] In the manufacturing method provided by the present invention, in the fin-like structure formed on a semiconductor substrate, the sacrificial layer is doped with an etching aid in at least the first edge regions on both sides along the thickness direction. This etching aid can accelerate the etching rate of the etchant at the top and bottom of the second edge regions of the sacrificial layer during isotropic etching of the second edge regions at both ends along the length direction, and reduce the etching rate difference between different regions of the second edge regions along the thickness direction. This allows the dielectric filling region formed by isotropic etching to extend along the thickness direction of the semiconductor substrate near the inner surface of the sacrificial layer. Correspondingly, this facilitates the extension of the inner sidewalls formed in the dielectric filling region along the thickness direction of the semiconductor substrate, preventing sharp points from appearing at the top and bottom of the inner sidewalls corresponding to the gate stack structure, avoiding abnormal discharge between the gate stack structure and the source / drain regions, and improving the operating performance and yield of the gate-around transistor.
[0007] In one example, the channel layer is made of silicon, the sacrificial layer is made of germanium silicon, and the germanium content in the germanium silicon is greater than or equal to 15%.
[0008] In one example, the sacrificial layer includes a first central region and first edge regions located on either side of the first central region in the thickness direction of the semiconductor substrate. In the above case, after forming the mask structure spanning the fin structure and before forming the dielectric filling region, the germanium content in the first central region is greater than the germanium content in the first edge region; and / or, along the direction from the first central region to the first edge region, the germanium content in the first edge region of the sacrificial layer gradually decreases.
[0009] In one example, a remote plasma etching process is employed, and the second edge regions at both ends of the sacrificial layer along its length are removed using a mixed gas. The mixed gas is NF3, NH3, O2, and He, or CF4, O2, and He.
[0010] In one example, a vapor phase etching process is used, and the second edge regions at both ends of the sacrificial layer along the length direction are removed by F2 and / or ClF3.
[0011] In one example, the sacrificial layer includes a first central region and first edge regions located on either side of the first central region in the thickness direction of the semiconductor substrate. Along the direction from the first central region to the first edge regions, the doping concentration of the etching aid in the first edge regions of the sacrificial layer gradually increases.
[0012] In one example, the etching aid includes an N-type dopant.
[0013] In one example, an in-situ doping process is used to dope etching aids into the sacrificial layer.
[0014] In one example, the etching aid includes at least one of phosphorus, arsenic, oxygen, and carbon.
[0015] In one example, forming inner sidewalls within the dielectric-filled region includes: conformally depositing dielectric material within the dielectric-filled region and on the fin structure and mask structure using an atomic layer deposition process. Next, an etching process is used to remove the dielectric material outside the dielectric-filled region, leaving the dielectric material within the dielectric-filled region to form the inner sidewalls.
[0016] In one example, the longitudinal section of the inner wall along the length of the fin structure is rectangular.
[0017] In one example, after forming inner sidewalls within the dielectric-filled region, the fabrication method of the gate-around transistor further includes forming source-drain regions on both sides of the remaining fin structure. Next, at least a portion of the mask structure is removed, and the remaining sacrificial layer is removed to allow the remaining channel layer to form the channel region. Next, a gate stack structure is formed around the outer periphery of the channel region. Attached Figure Description
[0018] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings: Figure 1 This is a longitudinal cross-sectional view of a gate-ring transistor formed using related technologies; Figure 2 A flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention; Figure 3 This is a schematic diagram of the structure of the semiconductor device formed in the manufacturing process of the embodiments of the present invention. Figure 1 ; Figure 4 This is a schematic diagram of the structure of the semiconductor device formed in the manufacturing process of the embodiments of the present invention. Figure 2 ; Figure 5 This is a schematic diagram of the structure of the semiconductor device formed in the manufacturing process of the embodiments of the present invention. Figure 3 ; Figure 6 This is a schematic diagram of the structure of the semiconductor device formed in the manufacturing process of the embodiments of the present invention. Figure 4 ; Figure 7 This is a schematic diagram of the structure of the semiconductor device formed in the manufacturing process of the embodiments of the present invention. Figure 5 ; Figure 8 This is a schematic diagram of the structure of the semiconductor device formed in the manufacturing process of the embodiments of the present invention. Figure 6 ; Figure 9 This is a schematic diagram of the structure of the semiconductor device formed in the manufacturing process of the embodiments of the present invention. Figure 7 ; Figure 10 This is a schematic diagram of the structure of the semiconductor device formed in the manufacturing process of the embodiments of the present invention. Figure 8 ; Figure 11 This is a schematic diagram of the structure of the semiconductor device formed in the manufacturing process of the embodiments of the present invention. Figure 9 ; Figure 12 This is a schematic diagram of the structure of the semiconductor device formed in the manufacturing process of the embodiments of the present invention. Figure 10 ; Figure 13 This is a schematic diagram of the structure of the semiconductor device formed in the manufacturing process of the embodiments of the present invention. Figure 10 one; Figure 14 This is a schematic diagram of the structure of the semiconductor device formed in the manufacturing process of the embodiments of the present invention. Figure 10 two; Figure 15 This is a schematic diagram of the structure of the semiconductor device formed in the manufacturing process of the embodiments of the present invention. Figure 10 three.
[0019] Reference numerals: 11 is semiconductor substrate, 12 is fin structure, 13 is sacrificial layer, 14 is channel layer, 15 is shallow trench isolation structure, 16 is mask structure, 17 is sacrificial gate, 18 is gate sidewall, 19 is first edge region, 20 is first central region, 21 is second edge region, 22 is dielectric filling region, 23 is inner sidewall, 24 is source / drain region, 25 is insulating dielectric layer, 26 is channel region, and 27 is gate stack structure. Detailed Implementation
[0020] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely exemplary and not intended to limit the scope of the invention. Furthermore, descriptions of well-known structures and techniques are omitted in the following description to avoid unnecessarily obscuring the concept of the invention.
[0021] The accompanying drawings illustrate various structural schematic diagrams according to embodiments of the present invention. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.
[0022] In the context of this invention, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or there may be an intermediate layer / element between them. Furthermore, if a layer / element is "on" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element. To make the technical problems, technical solutions, and beneficial effects of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
[0023] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified. "Several" means one or more, unless otherwise explicitly specified.
[0024] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.
[0025] With the development of semiconductor technology, higher-performance semiconductor devices such as gate-around transistors (GMT-A) have emerged. Compared with planar transistors and fin field-effect transistors, GMT-A has higher gate control capability, which is beneficial for suppressing short-channel effects. Furthermore, in actual manufacturing processes, before forming the source and drain regions, etching and deposition processes are often used to form inner sidewalls at the edges of the sacrificial layer along its length to isolate the subsequently formed gate stack structure from the source and drain regions, reducing leakage current. However, the operating performance of GMT-A formed using existing manufacturing methods is not improved.
[0026] Specifically, taking SiGe as the sacrificial layer and Si as the channel layer as an example: a SiGe / Si superlattice stack can be epitaxially formed on a semiconductor substrate. Next, the SiGe / Si superlattice stack is patterned to form a fin-like structure. After forming a mask structure spanning the fin-like structure, the portion of the fin-like structure exposed outside the mask structure is selectively removed. At this point, both the channel layer and the sacrificial layer are exposed along their length. Then, a portion of the SiGe sacrificial layer is selectively etched to form an inner sidewall cavity. Subsequently, a deposition and etching process is used to form inner sidewalls within the inner sidewall cavity. However, in existing techniques for epitaxially forming SiGe / Si supercrystalline silicon stacks on semiconductor substrates, to reduce the impact on the Si channel layer, a gradient change in Ge concentration exists at the interface between the two, meaning that the Ge content is lower in the region of the SiGe sacrificial layer near the channel layer. Furthermore, during the fabrication of shallow trench isolation structures, processes such as high-temperature annealing cause Ge to easily diffuse into the Si channel layer in regions near the SiGe sacrificial layer, further reducing the Ge content in these regions. During the etching of the inner sidewall cavity, the etching rate of the SiGe sacrificial layer is related to its Ge concentration. The reduced Ge content in these regions leads to a decreased etching rate of the etchant in these areas. Figure 1 As shown, the resulting inner sidewall cavity has a crescent shape, which in turn causes the inner sidewall within the inner sidewall cavity to also have a crescent shape. The crescent-shaped inner sidewall causes the gate stack structure 27 to have sharp points at the top and bottom of the inner sidewall, which can easily lead to abnormal discharge between the source / drain region 24 and the gate, thus causing the gate ring transistor to fail.
[0027] To address the aforementioned technical problems, embodiments of the present invention provide a method for manufacturing a gate-around transistor. In this method, an etching aid is used to extend the inner surface of the dielectric filling region near the sacrificial layer along the thickness direction of the semiconductor substrate. Consequently, this facilitates the extension of the inner sidewalls formed within the dielectric filling region, near the inner surface of the sacrificial layer, along the thickness direction of the semiconductor substrate, preventing sharp points from appearing at the top and bottom of the inner sidewalls of the gate stack structure and avoiding abnormal discharge between the gate stack structure and the source / drain regions.
[0028] like Figure 2 As shown, this embodiment of the invention provides a method for manufacturing a gate-ring transistor. The following will describe a method based on... Figures 3 to 15 The illustrated perspective view or cross-sectional view describes the manufacturing process. Specifically, the manufacturing method of this gate-ring transistor includes the following steps: First, such as Figures 3 to 6As shown, a fin structure 12 is formed on a semiconductor substrate 11. Along the thickness direction of the semiconductor substrate 11, the fin structure 12 includes sacrificial layers 13 and channel layers 14 that are alternately stacked, and in each sacrificial layer 13, at least the first edge regions 19 on both sides along the thickness direction are doped with etching aids.
[0029] It is understandable that the channel layer in the fin structure is used to manufacture the channel region included in the gate-around transistor. Therefore, the material and number of the channel layer included in the fin structure can be determined based on the material and number of the nanostructures included in the channel region. No specific limitation is made here.
[0030] The sacrificial layer included in the fin structure will be partially removed to release the gaps used to fill part of the gate stack structure. Therefore, the thickness of the sacrificial layer can be determined according to the thickness of the gate stack structure included in the ring gate transistor. The material of the sacrificial layer can be any material different from the channel layer, as long as it can be applied to the manufacturing method provided in the embodiments of the present invention.
[0031] For example, the channel layer material may include silicon, and the sacrificial layer material may include germanium-silicon, with the germanium content in the germanium-silicon being greater than or equal to 15%. This configuration ensures compatibility with more mature semiconductor processes, reduces the manufacturing difficulty of gate-around transistors, and helps improve the yield of gate-around transistors. In addition, the germanium content in the germanium-silicon being greater than or equal to 15% increases the material difference between the channel layer and the sacrificial layer, facilitating the subsequent removal of part of the sacrificial layer to obtain space for filling the gate stack structure.
[0032] In addition, in practical applications, in the fin structure, the bottom layer of the membrane is the sacrificial layer, and the top layer of the membrane can be either the sacrificial layer or the channel layer.
[0033] In the actual manufacturing process, such as Figure 3 and Figure 4 As shown, a semiconductor stack including a sacrificial layer 13 and a channel layer 14 can be formed on a semiconductor substrate 11 using processes such as epitaxy. The specific structure of this semiconductor stack can be determined based on the specific structure of the fabricated fin structure. Furthermore, an in-situ doping process can be used to dope etching aids into the sacrificial layer 13 to simplify the fabrication process of the gate-around transistor and improve its fabrication efficiency. Next, processes such as deposition and etching can be used to form a corresponding mask structure located on a portion of the semiconductor stack. And as shown... Figure 5 As shown, under the protection of this mask structure, the semiconductor stack and a portion of the semiconductor substrate 11 are patterned to obtain a Fin structure. Then, as... Figure 6As shown, shallow trench isolation structures 15 for defining active regions can be formed on semiconductor substrate 11 using processes such as deposition and etching. The top height of the shallow trench isolation structure 15 is less than or equal to the bottom height of the sacrificial layer 13 located at the bottom layer.
[0034] It should be noted that if the manufactured gate-around transistor does not include a shallow trench isolation structure, only the semiconductor stack can be patterned without etching the semiconductor substrate. After patterning, a fin-like structure can be obtained.
[0035] Furthermore, to minimize the impact on the channel layer, the material difference between the channel layer and the sacrificial layer is minimized at the interface (for example, when the sacrificial layer material includes germanium and silicon, there is a gradient change in Ge concentration, with a lower Ge content in the region near the channel layer within the SiGe sacrificial layer). Moreover, during the fabrication of shallow trench isolation structures, processes such as high-temperature annealing can easily cause elements like Ge in the region near the channel layer within the sacrificial layer to diffuse into the channel layer, further reducing the Ge content in that region.
[0036] For example, such as Figure 4 As shown, in the thickness direction of the semiconductor substrate 11, the sacrificial layer 13 includes a first central region 20 and first edge regions 19 located on both sides of the first central region 20. Furthermore, when the channel layer 14 is made of silicon and the sacrificial layer 13 is made of germanium-silicon, the germanium content in the first central region 20 is greater than the germanium content in the first edge regions 19; and / or, along the direction from the first central region 20 to the first edge regions 19, the germanium content in the first edge regions 19 of the sacrificial layer 13 gradually decreases.
[0037] Secondly, it is understandable that in each sacrificial layer, at least the first edge regions along both sides of the thickness direction are doped with etching aids. These etching aids can accelerate the etching rate of the etchant at the top and bottom of the second edge regions of the sacrificial layer during subsequent isotropic etching of the second edge regions at both ends of the length direction, and reduce the etching rate difference between different regions of the second edge regions along the thickness direction. This allows the dielectric filling region formed by isotropic etching to extend along the thickness direction of the semiconductor substrate near the inner surface of the sacrificial layer. In this case, the type of etching aid and its distribution in the sacrificial layer can be determined based on the material of the sacrificial layer, the distribution of elements such as Ge in the sacrificial layer that cause the etching rate difference between the sacrificial layer and the channel layer, and the type of etchant used to etch the sacrificial layer.
[0038] The etching aid may be distributed only in the first edge region of the sacrificial layer. Alternatively, the etching aid may be distributed in both the first edge region and the first middle region of the sacrificial layer, with the doping concentration of the etching aid in the first edge region of the sacrificial layer being greater than the doping concentration in the first middle region.
[0039] For example, such as Figure 4 As shown, along the direction from the first central region 20 to the first edge region 19, the doping concentration of the etching aid in the first edge region 19 of the sacrificial layer 13 can be gradually increased. This helps to compensate for the problem of reduced etching rate difference caused by the gradual decrease in the material difference between the sacrificial layer 13 and the channel layer 14 due to the gradual decrease in the element such as Ge in the sacrificial layer 13 along the direction from the first central region 20 to the first edge region 19. This ensures that the dielectric filling region extends along the thickness direction of the semiconductor substrate 11 near the inner side of the sacrificial layer 13, so that the inner sidewalls can also extend along the thickness direction of the semiconductor substrate 11 near the inner side of the sacrificial layer 13. This prevents sharp points from appearing at the bottom and top of the gate stack structure.
[0040] For example, etching aids may include N-type dopants. For instance, etching aids may include phosphorus and / or arsenic.
[0041] For example, etching aids may include oxygen and / or carbon.
[0042] Next, as Figure 7 and Figure 8 As shown, a mask structure 16 spanning the fin structure 12 can be formed using processes such as deposition and etching. The specific structure and material of the mask structure 16 can be set according to actual needs, as long as it can provide mask protection in the future.
[0043] For example: Figure 7 and Figure 8 As shown, the mask structure 16 may include a sacrificial gate 17 and a gate sidewall 18, with the gate sidewall 18 located at least on both sides of the sacrificial gate 17 along its width direction. The material of the sacrificial gate 17 may include an easily removable material such as polysilicon.
[0044] Alternatively, the mask structure described above may also include a gate oxide layer, a sacrificial gate located on the gate oxide layer, and gate sidewalls located on both sides of the sacrificial gate and the gate oxide layer. The material of the gate oxide layer may include silicon oxide or similar materials.
[0045] Alternatively, the mask structure may consist of only a sacrificial gate.
[0046] Next, as Figure 9 As shown, dry etching or wet etching processes can be used to remove the portion of the fin structure 12 exposed outside the mask structure 16.
[0047] Next, as Figure 9 and Figure 10 As shown, isotropic etching is used to remove the second edge regions 21 at both ends of the sacrificial layer 13 along its length to form dielectric filling regions 22. An etching aid is used to extend the dielectric filling regions 22 along the thickness direction of the semiconductor substrate 11 close to the inner surface of the sacrificial layer 13.
[0048] The type of etchant used to remove the second edge region can be determined based on the materials of the sacrificial layer and the channel layer, as well as actual needs; no specific limitations are made here.
[0049] For example, a remote plasma etching process can be used to remove the second edge regions at both ends of the sacrificial layer along its length using a mixed gas. The mixed gas can be NF3, NH3, O2, and He, or it can be CF4, O2, and He. Specifically, the ratio of the different gases in the mixed gas can be set according to actual needs. For example, when the mixed gas is NF3, NH3, O2, and He, the ratio of NF3, NH3, O2, and He can be 1:2:5:20. When the mixed gas is CF4, O2, and He, the ratio of CF4, O2, and He in the mixed gas can be 1:5:1.
[0050] For example, a vapor phase etching process can be used, and the second edge regions at both ends of the sacrificial layer along the length direction can be removed by F2 and / or ClF3.
[0051] Next, as Figure 11 As shown, processes such as deposition and etching can be used to form inner sidewalls 23 within the medium-filled area.
[0052] For example, atomic layer deposition (ALD) can be used to conformally deposit dielectric material in the dielectric-filled region, as well as on the fin structure and mask structure, to ensure that the inner sidewalls formed in the dielectric-filled region, near the inner surface of the sacrificial layer, also extend along the thickness direction of the semiconductor substrate, thereby preventing sharp points from appearing at the top and bottom of the inner sidewalls corresponding to the gate stack structure. Next, as... Figure 11 As shown, an etching process is used to remove the dielectric material located outside the dielectric filling area, and the remaining dielectric material within the dielectric filling area forms the inner sidewall 23. At this time, as... Figure 11 As shown, along the length of the fin-like structure, the longitudinal cross-sectional shape of the inner wall 23 can be rectangular. Alternatively, the inner surface can be straight, while the outer surface can be arc-shaped or curved.
[0053] For example, when the material of the inner wall includes silicon nitride, the inner wall can be formed by using three-dimensional processes such as inductive coupling and applying a combination of CH4 / CH2F2 / O2 / Ar gases to etch back the dielectric material.
[0054] Next, as Figure 12 As shown, source / drain regions 24 can be formed on both sides of the remaining fin structure using epitaxial growth or other processes. The material of the source / drain regions 24 can be selected according to the conductivity type of the gate-ring transistor and actual requirements.
[0055] For example, when the gate-ring transistor is an N-type transistor, the material of the source and drain regions may include Si.
[0056] For example, when the gate-ring transistor is a P-type transistor, the material of the source and drain regions can include SiGe.
[0057] Next, as Figure 13 As shown, processes such as deposition and planarization can be used to form an insulating dielectric layer 25 on the existing structure. The top of the insulating dielectric layer 25 is flush with the top of the mask structure 16. The material of the insulating dielectric layer 25 can include any insulating material such as silicon oxide, silicon nitride, and silicon oxynitride, as long as it can be applied to the manufacturing method provided in the embodiments of the present invention.
[0058] Next, as Figure 14 As shown, dry etching or wet etching processes can be used to remove at least part of the mask structure and the remaining sacrificial layer 13, so that the remaining channel layer 14 forms the channel region 26.
[0059] It should be noted that because the sacrificial layer is doped with etching aids at least in the first edge region, the etching rate of the sacrificial layer by the etchant is accelerated, thereby reducing the damage to the channel region caused by the etchant when releasing the channel region and improving the yield of the gate-around transistor. Furthermore, after forming the channel region, the oxide layer around the outer periphery of the channel region can be selectively removed using a DHF (100:1) solution or a BOE solution, further improving the yield of the gate-around transistor.
[0060] Furthermore, the specific structure of the mask structure can be used to determine whether to remove the entire mask structure or only a portion of it. For example, if the mask structure only includes a sacrificial gate or only includes a sacrificial gate and a gate oxide layer, the entire mask structure needs to be removed. If the mask structure includes a sacrificial gate and a gate sidewall, the gate sidewall needs to be retained, meaning only a portion of the mask structure needs to be removed.
[0061] Next, as Figure 15As shown, a gate stack structure 27 surrounding the channel region 26 can be formed using processes such as atomic layer deposition. The specific structure and materials of the gate stack structure 27 can be set according to actual needs, and are not specifically limited here.
[0062] For example, the gate stack structure may include a gate dielectric layer and a gate. The gate dielectric layer at least surrounds the outer periphery of each nanowire / sheet included in the channel region. The gate is disposed on the gate dielectric layer. The material of the gate dielectric layer may include any insulating material such as HfO2, ZrO2, TiO2, or Al2O3. The material of the gate may include any conductive material such as TiN, TaN, or TiSiN.
[0063] As can be seen from the above, such as Figures 3 to 15 As shown, in the manufacturing method provided in this embodiment of the invention, in the fin structure 12 formed on the semiconductor substrate 11, the sacrificial layer 13 is doped with an etching aid in at least the first edge regions 19 on both sides along the thickness direction. This etching aid can accelerate the etching rate of the etchant at the top and bottom of the second edge regions 21 in the sacrificial layer 13 during isotropic etching of the second edge regions 21 at both ends along the length direction, and reduce the etching rate difference between different regions of the second edge regions 21 along the thickness direction. This allows the dielectric filling region 22 formed by isotropic etching to extend along the thickness direction of the semiconductor substrate 11 near the inner surface of the sacrificial layer 13. Correspondingly, this facilitates the extension of the inner sidewall 23 formed in the dielectric filling region 22 along the thickness direction of the semiconductor substrate 11 near the inner surface of the sacrificial layer 13, preventing sharp points from appearing on the top and bottom portions of the gate stack structure 27 corresponding to the inner sidewall 23, avoiding abnormal discharge between the gate stack structure 27 and the source / drain regions 24, and improving the operating performance and yield of the gate-around transistor.
[0064] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.
[0065] The embodiments of the present invention have been described above. However, these embodiments are merely for clarity and are not intended to limit the scope of the invention. The scope of the invention is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of the invention, and all such substitutions and modifications should fall within the scope of the invention.
Claims
1. A method of manufacturing a gate-all-around transistor, characterized by, The method comprises: forming a fin structure on a semiconductor substrate; the fin structure comprises alternately stacked sacrificial layers and channel layers along a thickness direction of the semiconductor substrate, and each of the sacrificial layers is doped with an etching assistant in at least a first edge region on both sides in the thickness direction; forming a mask structure across the fin structure; removing a part of the fin structure exposed outside the mask structure; using an isotropic etching method, removing a second edge region at both ends of the sacrificial layer in the length direction to form a dielectric filling region; the etching assistant is used to make the dielectric filling region extend along the thickness direction of the semiconductor substrate close to the inner side of the sacrificial layer; forming an inner side wall in the dielectric filling region.
2. The method of manufacturing a gate-all-around transistor according to claim 1, wherein The material of the channel layer comprises silicon, the material of the sacrificial layer comprises germanium silicon, and the content of germanium in the germanium silicon is greater than or equal to 15%.
3. The method of manufacturing a gate-all-around transistor according to claim 2, wherein In the thickness direction of the semiconductor substrate, the sacrificial layer comprises a first middle region and the first edge region on both sides of the first middle region; After forming the mask structure across the fin structure, the content of germanium in the first middle region is greater than that in the first edge region before forming the dielectric filling region; And / or, the content of germanium in the first edge region of the sacrificial layer gradually decreases in the direction from the first middle region to the first edge region.
4. The method of manufacturing a gate-all-around transistor according to claim 2 or 3, wherein Using a remote plasma etching process, and removing the second edge region at both ends of the sacrificial layer in the length direction by using a mixed gas; wherein the mixed gas is NF3, NH3, O2 and He, or the mixed gas is CF4, O2 and He; Or, using a gas phase etching process, and removing the second edge region at both ends of the sacrificial layer in the length direction by using F2 and / or ClF3.
5. The method of manufacturing a gate-all-around transistor according to claim 1, wherein In the thickness direction of the semiconductor substrate, the sacrificial layer comprises a first middle region and the first edge region on both sides of the first middle region; In the direction from the first middle region to the first edge region, the doping concentration of the etching assistant in the first edge region of the sacrificial layer gradually increases.
6. The method of manufacturing a gate-all-around transistor according to claim 1, wherein The etching assistant comprises an N-type dopant; And / or, using an in-situ doping process, the etching assistant is doped into the sacrificial layer.
7. The method of manufacturing a gate-all-around transistor according to claim 1, wherein The etching assistant comprises at least one of phosphorus, arsenic, oxygen and carbon.
8. The method of manufacturing a gate-all-around transistor according to claim 1, wherein Forming the inner side wall in the dielectric filling region comprises: using an atomic layer deposition process, conformally depositing a dielectric material in the dielectric filling region, and on the fin structure and the mask structure; using an etching process, removing the dielectric material outside the dielectric filling region, and the dielectric material remaining in the dielectric filling region forms the inner side wall.
9. The method of manufacturing a gate-all-around transistor according to claim 1, wherein In the length direction of the fin structure, the longitudinal cross-sectional shape of the inner side wall is rectangular.
10. The method of manufacturing a gate-all-around transistor according to any one of claims 1 to 9, wherein After forming the inner side wall in the dielectric filling region, the method for manufacturing the ring gate transistor further comprises: forming source-drain regions on both sides of the remaining fin structure; removing at least part of the mask structure, and removing the remaining sacrificial layer to form a channel region with the remaining channel layer; A gate stack structure is formed around the periphery of the channel region.