Semiconductor structure and forming method thereof

Abstract

A method for forming a semiconductor structure is provided. The method includes alternately stacking channel layers and sacrificial layers on a substrate in a vertical direction to form a semiconductor stack, patterning the semiconductor stack to form a fin-shaped structure protruding from the substrate, forming source / drain trenches in the fin-shaped structure, laterally recessing the sacrificial layers in the fin-shaped structure to form a first recess, and forming a second recess in the fin-shaped structure. And enlarging the first groove to form a second groove. After enlarging the first recess, one of the second recesses has a vertical dimension greater than a thickness of the sacrificial layer. The method further includes forming an internal spacer in the second recess, and forming a source / drain feature in the source / drain trench. The embodiment of the invention also relates to a semiconductor structure.

Description

Technical Field

[0001] Embodiments of this disclosure relate to semiconductor structures and methods of forming the same. Background Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advancements in IC materials and design have resulted in multiple generations of ICs, each featuring smaller and more complex circuitry than the previous generation. In the evolution of ICs, functional density (i.e., the number of interconnect devices per chip area) typically increases, while geometry (i.e., the smallest component (or line) that can be created using manufacturing processes) decreases. This scaling down process generally provides benefits through increased production efficiency and reduced associated costs. However, this scaling down also increases the complexity of handling and manufacturing ICs.

[0003] Recently, multi-gate transistors have been introduced to improve gate control by increasing gate-channel coupling, reducing off-state current, and mitigating short-channel effect (SCE). One such multi-gate transistor that has been introduced is the FinFET (Fin Field-Effect Transistor). The name FinFET comes from the fin-shaped structure that extends from the substrate, is formed on the substrate, and is used to form the FET channel. Another type of multi-gate transistor (introduced in part to address some of the performance challenges associated with FinFET configurations) is the gate-all-around (GAA) device, such as the gate-all-around (GAA) transistor. The name GAA comes from the gate structure that extends completely around the channel region, providing access to the channel on all four sides. The channel of a GAA device has multiple vertically spaced horizontal nanowires, nanosheets, and / or nanostrips. GAA devices are compatible with conventional complementary metal-oxide-semiconductor (CMOS) processes, and their structure allows them to be scaled up massively while maintaining gate control and mitigating SCE.

[0004] In multi-gate devices, such as gate-all-around devices, internal spacers have been used to reduce capacitance and leakage between the gate structure and the source / drain components. While current methods for forming gate-all-around devices with internal spacers are generally sufficient for their intended purposes, they continue to present challenges in device fabrication and performance, and are not satisfactory in every aspect. Summary of the Invention

[0005] Embodiments of this disclosure provide a method for forming a semiconductor structure, comprising: alternately stacking a channel layer and a sacrificial layer on a substrate in a vertical direction to form a semiconductor stack; patterning the semiconductor stack to form a fin structure protruding from the substrate; forming a source / drain trench in the fin structure; laterally recessing the sacrificial layer in the fin structure to form a first groove, wherein the first groove at opposite ends of one of the sacrificial layers is spaced apart from each other along a direction; widening the first groove to form a second groove, wherein, after widening the first groove, one of the second grooves has a vertical dimension larger than the thickness of the sacrificial layer; forming an internal spacer in the second groove; forming a source / drain component in the source / drain trench; forming a contact etch stop layer over the source / drain component; and forming an interlayer dielectric (ILD) layer over the contact etch stop layer, wherein the thickness of the contact etch stop layer along the direction is smaller than the thickness of the interlayer dielectric layer.

[0006] Another embodiment of this disclosure provides a method for forming a semiconductor structure, comprising: forming a fin structure, the fin structure including a stack on top of a substrate, the stack including a channel layer interleaved with a sacrificial layer, the substrate protruding from a substrate, the fin structure including a channel region and a source / drain region; forming a dummy gate stack over the channel region of the fin structure; depositing a gate spacer layer over the dummy gate stack; forming a source / source trench by recessing the source / drain region of the fin structure, wherein the source / drain trench exposes the sidewalls of the sacrificial layer and the channel layer; and making the sacrificial layer... Selectively and partially recessed to form a first groove; widening the first groove to form a second groove, wherein one of the second grooves has a vertical dimension larger than the thickness of the sacrificial layer; forming an internal spacer in the second groove; forming a source / drain component in the source / drain trench, wherein a gap is formed between the source / drain component and one of the internal spacers; forming a contact etch stop layer above the source / drain component; and forming an interlayer dielectric (ILD) layer above the contact etch stop layer, wherein the dielectric constant of the contact etch stop layer is greater than the dielectric constant of the interlayer dielectric layer.

[0007] Another embodiment of this disclosure provides a semiconductor structure including: a channel member suspended above a substrate; internal spacers interleaved with the channel member; a gate structure enclosing the channel member; source / drain members adjacent to the channel member, wherein the internal spacers extend into an end portion of the channel member adjacent to the internal spacers, and one of the internal spacers has a vertical dimension larger than that of the channel member; a contact etch stop layer located above the source / drain members; and an interlayer dielectric (ILD) layer located above the contact etch stop layer, wherein the source / drain members are partially embedded in the substrate and located below the interlayer dielectric layer. Attached Figure Description

[0008] When read in conjunction with the accompanying drawings, aspects of this disclosure are best understood from the following detailed description. It should be noted that, in accordance with standard industry practice, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the individual components may be arbitrarily increased or decreased.

[0009] Figure 1 This is a flowchart illustrating a method for forming a semiconductor structure from a workpiece according to some embodiments of the present disclosure.

[0010] Figure 2 This is a partial perspective view of a semiconductor structure at an intermediate stage according to some embodiments of the present disclosure.

[0011] Figure 3A , Figure 3B , Figure 3C , Figure 3D , Figure 3E-1 , Figure 3E-2 , Figure 3E-3 , Figure 3E-4 , Figure 3F , Figure 3G , Figure 3H , Figure 3I , Figure 3J , Figure 3K and Figure 3L It shows the basis Figure 1 Partial cross-sectional views of the fabrication of semiconductor structures at various intermediate stages in some embodiments of the method described herein.

[0012] Figure 4 Some embodiments according to this disclosure are shown. Figure 3J The semiconductor structure in it.

[0013] Figure 5A , Figure 5B , Figure 5C , Figure 5D , Figure 5E , Figure 5F , Figure 5G , Figure 5H , Figure 5I , Figure 5J , Figure 5K and Figure 5L This is a partial cross-sectional view illustrating the fabrication of a semiconductor structure at various intermediate stages according to some embodiments of the present disclosure.

[0014] Figure 6A Some embodiments according to this disclosure are shown. Figure 3F The semiconductor structure in it.

[0015] Figure 6B Some embodiments according to this disclosure are shown. Figure 5F The semiconductor structure in it.

[0016] Figure 7 This is a partial cross-sectional view of a semiconductor structure at an intermediate stage according to some other embodiments of this disclosure.

[0017] Figure 8A , Figure 8B , Figure 8C , Figure 8D , Figure 8E , Figure 8F and Figure 8G This is a partial cross-sectional view of a semiconductor structure being manufactured at various intermediate stages according to some embodiments of the present disclosure.

[0018] Figure 9A It is a graph depicting the distribution of germanium concentration on a sacrificial layer according to some embodiments of the present disclosure.

[0019] Figure 9B This is another diagram depicting the distribution of germanium concentration on the sacrificial layer according to some embodiments of the present disclosure. Detailed Implementation

[0020] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include embodiments where the first and second components are in direct contact, and may also include embodiments where an additional component may be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0021] Additionally, for ease of description, spatial relative terms such as “below,” “lower,” “above,” and “upper” may be used herein to describe the relationship between one element or component and another, as shown in the figures. Besides the orientations shown in the figures, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be positioned in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0022] As used herein, terms such as “first,” “second,” and “third” describe various elements, components, regions, layers, and / or parts, but these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms may only be used to distinguish one element, component, region, layer, or part from another. Unless the context clearly indicates otherwise, terms such as “first,” “second,” and “third” as used herein do not imply order or sequence.

[0023] While the numerical ranges and parameters set forth in this disclosure are approximate, the numerical values ​​described in the specific examples are reported as precisely as possible. However, any numerical value inherently contains some error, which is necessarily caused by the standard deviation found in the corresponding test measurement. Furthermore, as used herein, the terms “substantially,” “approximately,” or “about” generally mean a value or range that would be expected by one of ordinary skill in the art. Alternatively, the terms “substantially,” “approximately,” or “about” mean within an acceptable standard error of the mean when considered by one of ordinary skill in the art. One of ordinary skill in the art will understand that an acceptable standard error can vary depending on the technology. Except in the operational / working examples, or unless expressly stated otherwise, all numerical ranges, quantities, values, and percentages disclosed herein (such as those relating to material quantities, durations, temperatures, operating conditions, ratios of quantities, etc.) should in all cases be understood to be modified by the terms “substantially,” “approximately,” or “about.” Therefore, unless otherwise stated, the numerical parameters set forth in this disclosure and the appended claims are approximate values ​​that may vary as needed. At a minimum, each numerical parameter should be interpreted based at least on the reported significant figures and by applying ordinary rounding techniques. A range may be expressed in this document as a distance from one endpoint to another or between two endpoints. Unless otherwise stated, all ranges disclosed herein include endpoints.

[0024] This disclosure generally relates to multi-gate transistors and manufacturing methods, and more specifically, to the formation of internal spacers during the fabrication of gate-all-around (GAA) transistors. In a gate-all-around transistor, the gate of the transistor completely surrounds the channel, such that the channel is surrounded or enclosed by the gate. Such transistors have the advantage of improved electrostatic control of the channel through the gate, which also mitigates leakage current. Gate-all-around transistors include internal spacers and external gate sidewall spacers (or simply gate spacers). The internal spacers are formed by additional processes of the gate spacers. The internal spacers are formed between the channel layers and serve to reduce capacitance and leakage between the gate structure and the source / drain components. The purpose of this disclosure is to design methods for forming robust internal spacers, thereby preventing undesired leakage paths between the gate structure and the source / drain components. Depending on the context, source / drain components may refer individually or collectively to the source or drain.

[0025] Various aspects of this disclosure will now be described in more detail with reference to the accompanying drawings. In this regard, Figure 1 This is a flowchart illustrating a method 100 for forming a semiconductor structure from a workpiece according to an embodiment of the present disclosure. Figure 2 This is a partial perspective view of a semiconductor structure at an intermediate stage according to some embodiments. A nanosheet field-effect transistor is illustrated to show the semiconductor structure in some embodiments; however, this disclosure is not limited to nanosheet field-effect transistors.

[0026] Method 100 is merely an example and is not intended to limit this disclosure to what is expressly shown in method 100. Additional steps may be provided before, during, and after method 100, and some of the described steps may be replaced, eliminated, or rearranged for additional embodiments of the method. For simplicity, not all steps are described in detail herein. The following is in conjunction with... Figure 2 Description method 100, Figure 2 This is a perspective view of workpiece 200. Because workpiece 200 will be manufactured into a semiconductor structure, it can be referred to herein as semiconductor structure 200. Furthermore, Figure 2 , Figures 3A to 3L , Figure 4 , Figures 5A to 5L , Figure 6A , Figure 6B , Figure 7 and Figures 8A to 8G The directions D1, D2, and D3 are perpendicular to each other. In this disclosure, unless otherwise stated, the same reference numerals denote the same parts.

[0027] In some embodiments, such as Figure 2As shown, the semiconductor structure 200 includes fin structures 210 protruding from a substrate 202. Each fin structure 210 includes a sacrificial layer 206 and a channel layer 208 alternately stacked over the substrate 202. A plurality of dummy gate stacks 215 extend across the fin structure 210 and are longitudinally oriented along direction D2. In some embodiments, the extension direction of the fin structure 210 is perpendicular to the extension direction of the dummy gate stacks 215. Source / drain regions are formed on opposite sides of the dummy gate stacks 215. A channel layer 208 is formed between the source / drain regions over the substrate 202. An isolation member 211 is formed on opposite sides of the fin structure 210. The isolation member 211 may be flush with the top surface of the fin substrate 210B. Each dummy gate stack 215 may include a dummy dielectric layer 212 on the fin structure 210 and a dummy electrode layer 214 on the dummy dielectric layer 212.

[0028] Figure 2 A reference cross-section used in subsequent figures is also shown. Cross-section AA is along the longitudinal axis of fin structure 210 (e.g., in direction D1), for example, perpendicular to the direction along the longitudinal axis of dummy gate stack 215 (e.g., in direction D2). For clarity, subsequent figures refer to reference cross-section AA.

[0029] Figures 3A to 3L It shows the basis Figure 1 Partial cross-sectional views of the fabrication of semiconductor structures at various intermediate stages in some embodiments of method 100. Figure 3A It is along Figure 2 The cross-sectional view taken from section AA, which extends along the length of fin structure 210. (Reference) Figure 1 , Figure 2 and Figure 3A Method 100 includes a block 102, wherein a workpiece 200 is provided with a plurality of fin structures 210 protruding from a substrate 202, and a plurality of dummy gate stacks 215 are positioned across the fin structures 220. In some embodiments, the fin structures 210 are longitudinally oriented along direction D1, and the dummy gate stacks 215 are longitudinally oriented along direction D2. Direction D1 may be perpendicular to direction D2. The fin structure 210 may include two fins, one in an n-type region (where an n-type transistor will be formed) and the other in a p-type region (where a p-type transistor will be formed). Optionally, the fin structure 210 may include two fins, both of which may be located in the n-type region or both of which may be located in the p-type region.

[0030] In some embodiments, substrate 202 may be a semiconductor substrate, such as a silicon (Si) substrate. Depending on design requirements known in the art, substrate 202 may include various doping configurations. In embodiments where the semiconductor device is p-type, an n-well (not shown) may be formed on a portion of substrate 202 in a p-type region. In some embodiments, the n-type dopant used to form the n-well may include phosphorus (P) or arsenic (As). In embodiments where the semiconductor device is n-type, a p-well may be formed on a portion of substrate 202 in an n-type region. In some embodiments, the p-type dopant used to form the p-well may include boron (B) or gallium (Ga). Suitable doping methods may include ion implantation and / or diffusion processes of the dopant. Substrate 202 may also include other semiconductors, such as germanium (Ge), silicon carbide (SiC), silicon germanium (SiGe), or diamond. Optionally, substrate 202 may include compound semiconductors and / or alloy semiconductors. Additionally, the substrate 202 may include an epitaxial layer (epi layer) that can be strained for performance enhancement, may include a silicon-on-insulator (SOI) or germanium-on-insulator (GeOI) structure, and / or may have other suitable enhancement components.

[0031] In some embodiments, each fin structure 210 includes alternating layers located on top of the fin substrate 210B. The formation of the fin structure 210 may include depositing a stack (not shown) on the substrate 202 in an epitaxial growth process, and patterning the stack and the top portion of the substrate 202 to form a plurality of stacks 205. Each stack 205 includes the fin structure 210. Since the fin substrate 210B is formed by patterning the top portion of the substrate 202, the fin substrate 210B can still be considered as the top portion of the substrate 202, depending on the context.

[0032] The stack 205 includes sacrificial layers 206 interleaved with channel layers 208. The sacrificial layers 206 and channel layers 208 comprise different material compositions. In some embodiments, the sacrificial layer 206 comprises a semiconductor composition, such as silicon germanium (SiGe) or another suitable semiconductor material. In some embodiments, the sacrificial layer 206 comprises a dielectric composition, such as an oxide or another suitable interposer material, and the sacrificial layer 206 may be referred to as a sacrificial dielectric interposer. In some embodiments, the channel layer 208 comprises the semiconductor composition silicon (Si). Although three sacrificial layers 206 and three channel layers 208 are arranged alternately in the exemplary embodiments, this is for illustrative purposes only and is not intended to limit the specific references in the claims. It will be understood that any number of epitaxial layers (i.e., sacrificial layers 206 and channel layers 208) can be formed in the stack 205. The number of layers depends on the desired number of channel components for the semiconductor structure 200. In some embodiments, the number of channel layers 208 is between 1 and 20.

[0033] In some embodiments, all sacrificial layers 206 may have a substantially uniform thickness between about 3 nm and about 10 nm, and all channel layers 208 may have a substantially uniform thickness between about 3 nm and about 15 nm. The thicknesses of the sacrificial layers 206 and the channel layers 208 may be the same or different. As described in more detail below, the channel layer 208 or portions thereof may be used as channel members for subsequently formed multi-gate devices, and the thickness of the channel layer 108 may be determined based on device performance considerations. In some embodiments, the sacrificial layer 206 in the channel region is ultimately removed and used to define the vertical distance between adjacent channel layers 208 of the subsequently formed multi-gate device. The thickness of the sacrificial layer 206 is determined based on device performance considerations.

[0034] The layers in the stack 205 can be deposited using molecular beam epitaxy (MBE), vapor deposition (VPE), and / or another suitable epitaxial growth process. Therefore, the stack 205 is also referred to as an epitaxial stack 205. As described above, in at least some embodiments, the sacrificial layer 206 comprises an epitaxially grown silicon-germanium (SiGe) layer, and the channel layer 208 comprises an epitaxially grown silicon (Si) layer. In some embodiments, the sacrificial layer 206 and the channel layer 208 are substantially dopant-free. That is, the sacrificial layer 206 and the channel layer 208 may have a diameter from about 0 cm⁻¹. -3 Up to 1x10 17 cm -3 The concentration of exogenous dopants. Intentional doping is not performed during the epitaxial growth process used to form the sacrificial layer 206 and the channel layer 208.

[0035] In some embodiments, the fin structure 210 can be patterned from the stack 205 and the substrate 202 using photolithography and etching processes. The photolithography process may include photoresist coating (such as spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (such as spin drying and / or hard baking), other suitable photolithography techniques, and / or combinations thereof. In some embodiments, the etching process may include dry etching (such as reactive ion etching (RIE)), wet etching, and / or another etching method. In some embodiments, dual patterning or multiple patterning processes may be used to define the fin structure 210, for example, where the pitch of the fin structure 210 is smaller than that achievable using a single direct photolithography process. For example, in one embodiment, a material layer (not shown) is formed over the substrate 202, and the material layer is patterned using a photolithography process. Spacers are formed alongside the patterned material layer using a self-aligned process. The material layer is then removed, and the remaining spacers or mandrels can be used to pattern the fin structure 210 by etching the top portions of the stack 205 and the substrate 202. In some embodiments, the width of each fin structure 210 along direction D2 is measured to be between about 6 nm and about 80 nm, and the distance between the opposite sidewalls of two adjacent fin structures 210 along direction D2 is measured to be between about 10 nm and about 115 nm.

[0036] Furthermore, the workpiece 200 (or semiconductor structure 200) includes an isolation component 211 deposited in a trench between the opposing sidewalls of two adjacent fin structures 210. Figure 2 In some embodiments, isolation member 211 is formed in a trench to isolate fin structure 210 from adjacent fin structures. Isolation member 211 may also be referred to as shallow trench isolation (STI) member 211. In some exemplary methods for forming isolation member 211, a dielectric layer is first deposited over substrate 202 to fill the trench. In some embodiments, the dielectric layer may include silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), a low-k dielectric material, another suitable material, and / or combinations thereof. In various examples, the dielectric layer may be deposited by chemical vapor deposition (CVD), subatmospheric pressure CVD (SACVD), flowable CVD, spin coating, and / or another suitable process. The deposited dielectric material is then thinned and planarized, for example, by chemical mechanical polishing (CMP). The planarized dielectric layer is further recessed or pulled back by dry etching, wet etching, and / or combinations thereof to form STI member 211. After the planarized dielectric layer is recessed, the fin structure 210 rises above the STI component 211. The recessed top surface of the STI component 211 can be flush with the top surface of the fin substrate 210B.

[0037] After defining the fin structure 210, a plurality of dummy gate stacks 215 are formed over the fin structure 210. The dummy gate stacks 215 may include a dummy dielectric layer 212 and a dummy electrode layer 214 located on the dummy dielectric layer 212. The formation of the dummy gate stacks 215 may include depositing layers of the dummy gate stacks 215 and patterning these layers. In some embodiments, a dummy dielectric material, a dummy electrode material, and a gate-top hard mask layer (not shown) may be blanket-deposited over the substrate 202, covering the fin structure 210 and the isolation member 211. In some embodiments, the dummy dielectric material may be formed on the fin structure 210 using a CVD process, an atomic layer deposition (ALD) process, an oxygen plasma oxidation process, or another suitable process. The dummy dielectric material may include silicon oxide or another suitable dielectric material. In some embodiments, a dummy electrode material may be deposited over the dummy dielectric material using a CVD process, an ALD process, or another suitable process. The dummy electrode material may include polysilicon. For patterning purposes, a gate-top hard mask layer can be deposited on the dummy electrode material using a CVD process, an ALD process, or another suitable process. The gate-top hard mask layer can then be used as a patterning mask to pattern the dummy electrode material and the dummy dielectric material to form a dummy gate stack 215. For example, the patterning process may include photolithography processes (such as photolithography or electron beam lithography), which may further include photoresist coating (such as spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (such as spin drying and / or hard baking), another suitable photolithography technique, and / or combinations thereof. In some embodiments, the etching process may include dry etching (such as RIE etching), wet etching, and / or another etching method.

[0038] A dummy gate stack 215 is formed over a corresponding channel region 210C of the fin structure 210. In some embodiments, a gate replacement process (or post-gate process) is employed, wherein the dummy gate stack 215 serves as a placeholder to undergo various processes and is removed and replaced by a functional gate structure. A transistor is formed at the intersection of the fin structure 210 and the functional gate structure. In an exemplary embodiment, where the dummy gate stack 215 is formed over the fin structure 210, the fin structure 21 is divided into a channel region 210C below the dummy gate stack 215 and source / drain regions 210S / D located between the channel regions 210. Figure 3A As shown, the channel region 210C is disposed between the two source / drain regions 210S / D along the D1 direction. Furthermore, the dummy gate stacks 215 are spaced apart from each other by the gate pitch GS along the D1 direction. Figure 3AThe diagram also depicts the gate width Wg of the dummy gate stack 215 in direction D1 and the pitch Pgd between adjacent dummy gate stacks 215. The dummy gate stacks 215 formed in the channel region 210C can have a uniform gate width Wg.

[0039] refer to Figure 1 and Figure 3B Method 100 includes block 104, wherein a gate spacer layer 218 is deposited on the sidewall of a dummy gate stack 215. The gate spacer layer 218 may be a single layer or multiple layers. In some embodiments, one layer of the gate spacer layer 218 may include silicon carbonitride, silicon carbon oxide, silicon carbonitride, or silicon nitride. The gate spacer layer 218 may be deposited over the dummy gate stack 215 using processes such as CVD, subatmospheric pressure CVD (SACVD), ALD, or another suitable process.

[0040] In some embodiments, such as Figure 3B As shown, the gate spacer layer 218 includes a first gate spacer 216 and a second gate spacer 217 disposed above the first gate spacer 216. The first gate spacer 216 may comprise silicon oxynitride, and the second gate spacer 217 may comprise silicon nitride. The formation of the gate spacer layer 218 may include conformal deposition of a first gate spacer material (not shown) and a second gate spacer material (not shown) disposed on the first gate spacer material, followed by patterning of these gate spacer materials. For ease of description of a layer having a substantially uniform thickness over various regions, the term "conformal" may be used herein. In some embodiments, the patterning process may include removing excess portions of the second gate spacer material and the first gate spacer material, including a top portion above the top surface 214a of the dummy electrode layer 214 and a bottom portion above the topmost channel layer 208. Figure 3B As shown, the remaining portions of the first gate spacer material and the second gate spacer material can be referred to as the first gate spacer 216 and the second gate spacer 217, respectively. In some embodiments, after the patterning process, the top surface 214a of the dummy electrode layer 214 and the top surface 208a of the topmost sacrificial layer 208 are exposed. The gate spacer layer 218 can also be referred to as the gate spacer 218.

[0041] refer to Figure 1 and Figure 3CMethod 100 includes block 106, wherein a fin structure 210 in the source / drain region 210S / D is recessed to form a source / drain trench 220'. In some embodiments, the source / drain region 210S / D not covered by the dummy gate stack 215 and the gate spacer layer 218 is etched by a dry etching process or another suitable etching process to form the source / drain trench 220'. For example, the dry etching process may utilize oxygen-containing gases, fluorine-containing gases (such as CF4, SF6, CH2F2, CHF3 and / or C2F6), chlorine-containing gases (such as Cl2, CHCl3, CCl4 and / or BCl3), bromine-containing gases (such as HBr and / or CHBr3), iodine-containing gases, another suitable gas, plasma, and / or combinations thereof. In some embodiments, the fin structure 210 is recessed to expose the sidewalls 206s of the sacrificial layer 206 and the sidewalls 208s of the channel layer 208. In some implementations, the source / drain trench 220' extends into the fin substrate 210B below the stack 205.

[0042] refer to Figure 1 and Figure 3D Method 100 includes block 108, wherein a sacrificial layer 206 is laterally recessed to form a first groove 223 in the fin structure 210. In some embodiments, the operation at block 108 may include selectively and partially removing the sacrificial layer 206 to form the first groove 223 between adjacent channel layers 208. The first groove 223 exposes opposing ends 208E of the channel layers 208. In some embodiments, the sacrificial layer 206 exposed in the source / drain trench 220' is selectively and laterally recessed to form the first groove 223, while the exposed portions of the gate spacer layer 218, the fin substrate 210B (substrate 202), and the channel layers 208 are substantially unetched. Figure 3D As shown, the first grooves 223 located at opposite ends of each sacrificial layer 206 are separated from each other along the first direction D1.

[0043] In embodiments where the channel layer 208 is primarily composed of silicon (Si) and the sacrificial layer 206 is primarily composed of silicon germanium (SiGe), selective wet etching or selective dry etching processes can be used to selectively recess the sacrificial layer 206. In some embodiments, a single etching process is performed to laterally recess the sacrificial layer 206. In some embodiments, selective and partial recessing of the sacrificial layer 206 includes a SiGe oxidation process and subsequent SiGe oxide removal. In this embodiment, the SiGe oxidation process may include the use of ozone. In some other embodiments, the selective dry etching process may include the use of one or more fluorine-based etchants, such as fluorine gas or hydrofluorocarbons. The selective wet etching process may include APM etching (e.g., an ammonium hydroxide-hydrogen peroxide-water mixture). In some embodiments, the shape of the first groove 223 may be non-uniform due to etching capability, and the sacrificial layer 206 may have a thinner portion at the ends. For example, a recessed region 2061 may be formed between the first groove 223 and the sacrificial layer 206. If the first recess 223 is filled with a suitable material to form an internal spacer (not shown), etching can be performed through the channel layer 208 to form an undesirable gap above and / or below the internal spacer during the channel release process. After the gate replacement is formed, defects may occur where metal is squeezed through the undesired gap, creating one or more leakage paths between the metal gate and the source / drain components.

[0044] refer to Figure 1 and Figure 3E-4 Method 100 includes block 110, wherein a first recess 223 is enlarged to form a second recess 240. Operation at block 110 may include selectively etching the channel layer 208 to enlarge the first recess 223, while the gate spacer layer 218 and sacrificial layer 206 are substantially unetched. In some embodiments, the exposed ends 208E of the channel layer 208 may be formed by oxidizing the surface of the channel layer 208 to form an oxide layer, and by removing the oxide layer, for example, through one or more etching processes. The oxidation and removal processes may be cyclically repeated to enlarge the first recess 223. Figure 3D (), until the second groove 240 is formed with the desired shape and size.

[0045] Figure 3E-1 , Figure 3E-2 , Figure 3E-3 and Figure 3E-4Enlarged cross-sectional views of the fabrication of the second groove and S / D trench at various intermediate stages according to some other embodiments of the present disclosure are shown. In some embodiments, directional oxidation and selective etching may be employed to control the reshaping of the first groove 223 and the source / drain trench 220'. In some embodiments, the second groove 240 is formed by cyclic oxidation and removal processes until a second groove 240 with a predetermined shape is obtained. The oxidation process may be directionally controlled and performed by one or more gases in a dry etching chamber or tool to oxidize the exposed surface of the channel layer 208 in a selected portion of the target material layer. An exemplary embodiment is described below.

[0046] refer to Figure 3E-1 For example, the exposed ends 208E and the first groove 223 of the channel layer 208 are selectively oxidized using one or more suitable dry etching gases to form an oxide portion 281. The oxide portion 281 may include an oxide portion 282 grown on the channel layer 208 and an oxide portion 283 grown on the bottom of the source / drain trench 220'. The oxidation process may consume portions of the channel layer 208 and the substrate 202. In some embodiments, oxide portions 282 and 283 comprise silicon dioxide.

[0047] Directional oxidation can be used, wherein the portion 2821 of oxide portion 282 facing the first groove 223 grows at a higher rate than the other portions 2822 of oxide portion 282 at the sidewall 208s of the channel layer 208. Therefore, the amount of grown oxide portion 282 can be selectively controlled. For example, by using a dry etching gas, the amount of portion 2821 of oxide portion 282 generated within the first groove 223 can be controlled to be greater than the amount of portion 2822 of oxide portion 282 generated at the sidewall 208s. Furthermore, the formation of oxide portions 282 and 283 (e.g., collectively referred to as oxide portion 281) can be performed by rapid thermal oxidation (RTO), radical oxidation, plasma oxidation, any suitable anisotropic oxidation process, or a combination thereof.

[0048] refer to Figure 3E-2 One or more etching processes are performed to remove oxide portions 281, thereby forming the bottom of the first groove 223 and the source / drain trench 220'. For example, oxide portions 282 are removed to form the groove 223', and oxide portions 283 are removed to form the source / drain trench 220'. In some embodiments, oxide portions 281 are removed by wet or dry chemical etching, reactive ion etching, any suitable etching, or a combination thereof. Furthermore, cycles comprising one or more dry etching processes and one or more wet etching processes can be repeated continuously to form the groove 223' and the source / drain trench 220'.

[0049] Figure 3E-1 The oxidation process shown can be called the first oxidation process, and Figure 3E-2 The removal process shown can be referred to as the first removal process. The first oxidation process and the first removal process can be collectively referred to as the first cycle operation. After performing the first cycle operation ( Figure 3E-2 The vertical dimension of the first groove 223' is larger than that before the first cycle operation was performed. Figure 3D The vertical dimension of the first recess 233. In some embodiments, one or more etching processes are performed to selectively etch oxide portions 282 and 283, while the dummy gate stack 215 and gate spacer layer 218 remain substantially unetched.

[0050] Next, in some embodiments, reference will be made to Figure 3E-3 The remaining portion of the end 208E of the channel layer 208 is subjected to another oxidation process to form an oxide portion 285. The oxide portion 285 may include an oxide portion 286 grown on the remaining portion of the channel layer 208 and an oxide portion 287 grown on the bottom of the source / drain trench 220". The oxidation process may consume portions of the channel layer 208 and the substrate 202. Oxide portions 286 and 287 may include silicon dioxide.

[0051] Directional oxidation can be used to allow the portion 2861 of oxide portion 286 facing the first groove 223' to grow at a higher rate than the other portions 2862 of oxide portion 286 at the sidewall 208s of the channel layer 208. Therefore, the amount of grown oxide portion 286 can be selectively controlled. For example, by using a directional dry etching gas, the amount of portion 2861 of oxide portion 286 generated within the first groove 223' can be controlled to be greater than the amount of portion 2862 of oxide portion 286 generated on the sidewall 208s. The formation of oxide portions 286 and 287 (e.g., collectively referred to as oxide portion 285) can be performed by rapid thermal oxidation (RTO), radical oxidation, plasma oxidation, any suitable anisotropic oxidation process, or a combination thereof.

[0052] Next, refer to Figure 3E-4One or more etching processes are performed to remove oxide portions 285, thereby forming the bottom of the first recess 223' and the source / drain trench 220". In some embodiments, oxide portions 286 are removed to form the second recess 240, while oxide portions 287 are removed to form the source / drain trench 220. The oxide portions 285 can be removed by, for example, wet or dry chemical etching, reactive ion etching, any suitable etching, or a combination thereof. Furthermore, a cycle comprising one or more dry etching processes and one or more wet etching processes can be repeated continuously until the second recess 240 and the source / drain trench 220 with the desired shape and size are obtained. After performing the cyclic operation, viewed from a top view, the sidewalls 218s of the gate spacer 218 can shield the channel layer 208.

[0053] Figure 3E-3 The oxidation process shown can be called the second oxidation process, and Figure 3E-4 The removal process shown can be referred to as the second removal process. The second oxidation process and the second removal process can be collectively referred to as the second cycle operation. During the execution of the second cycle operation ( Figure 3E-4 After that, the vertical dimension of the second groove 240 is larger than that after the first cycle operation is performed. Figure 3E-2 The vertical dimension of the first recess 223'. In some embodiments, one or more etching processes are performed to selectively etch oxide portions 286 and 287, while the dummy gate stack 215 and gate spacer layer 218 remain substantially unetched.

[0054] While two cyclic operations of the oxidation and removal processes are provided in this exemplary embodiment, the present disclosure is not limited thereto. The oxidation and removal processes may be repeated cyclically until the second groove 240 and the source / drain trench 220 are formed with the desired shape.

[0055] In some embodiments, the first groove 223 is enlarged to form a second groove 240, each second groove 240 having a larger vertical dimension than the first groove 233. For example... Figure 3E-4 As shown, the maximum vertical dimension T2 of the second groove 240 is greater than the thickness T1 of the sacrificial layer 206. This occurs after the internal spacer 250 is subsequently formed in the second groove 240. Figure 3F For the sake of simplicity, the maximum vertical dimension T2 may also be referred to as the thickness T2 of the internal spacer 250 in the following text.

[0056] Each of the second grooves 240 may have a substantially flat top surface and a curved bottom surface. The cross-section of the second groove 240 may be trimmed to have a desired shape, for example, using exemplary methods such as the described cyclic oxidation and removal processes. In some embodiments, the top surface 240a and the bottom surface 240b include curved surfaces, such as... Figure 3E-4As shown. One (or each) of the top surfaces 240a of the second groove 240 may include a first portion 240a-1 and a second portion 240a-2 with different curvatures in cross-section. The curvature of the first portion 240a-1 may be greater than, equal to, or less than the curvature of the second portion 240a-2. In some embodiments, the curvature of the first portion 240a-1 is greater than the curvature of the second portion 240a-2. Similarly, one (or each) of the bottom surfaces 240b of the second groove 240 may include a first portion 240b-1 and a second portion 240b-2 with different curvatures in cross-section. For example, the curvature of the first portion 240b-1 of the bottom surface 240b may be greater than the curvature of the second portion 240b-2.

[0057] refer to Figure 1 and Figure 3F Method 100 includes block 112, wherein an internal spacer 250 is formed in a second recess 240. The operation at block 112 may include depositing an internal spacer material (not shown) over a substrate 202. In some embodiments, the internal spacer material is deposited in a source / drain trench 220 and fills the second recess 240. The internal spacer material is then etched back to form the internal spacer 250 in the second recess 240.

[0058] One or each of the top surface 250a and bottom surface 250b of the internal spacer 250 may include a curved surface with different curvatures or an inclined surface with different slopes in cross-section. The top surface 250a of the internal spacer 250 may include a first portion 250a-1 adjacent to the sacrificial layer 206 (i.e., subsequently formed by...). Figure 3L The gate structure 274 shown is replaced by a second portion 250a-2 adjacent to the source / drain trench 220. In some embodiments, the first portion 250a-1 and the second portion 250a-2 have different curvatures in cross-section. For example, the curvature of the first portion 250a-1 of the top surface 250a may be greater than the curvature of the second portion 250a-2. Similarly, the bottom surface 250b of the internal spacer 250 may include a first portion 250b-1 and a second portion 250b-2, wherein the curvature of the first portion 250b-1 may be greater than the curvature of the second portion 250b-2. In some embodiments, the first portion 250a-1 and the second portion 250a-2 of the top surface 250a are inclined at different angles. The first portion 250b-1 and the second portion 250b-2 of the bottom surface 250b are inclined at different angles. The first section 250a-1 (or 250b-1) may be more inclined relative to the horizontal plane than the second section 250a-2 (or 250b-2) relative to the horizontal plane (i.e., the channel layer 208 along the extended D1-D2 plane). For example, as Figure 3FAs shown, the angle θ1 between the first part 250a-1 and direction D1 is greater than the angle θ2 between the second part 250a-2 and direction D1.

[0059] In some embodiments, after the second groove 240 and the inner spacer 250 are formed, the inner spacer 250 on the opposite side of the sacrificial layer 206 is thicker than the sacrificial layer 206. For example... Figure 3F As shown, the thickness T2 of the inner spacer 250 is greater than the thickness T1 of the sacrificial layer 206. Furthermore, after the second groove 240 and the inner spacer 250 are formed, each of the remaining portions of the channel layer (also indicated as 208) has a different thickness. Figure 3F As shown, portions of the channel layers 208 between the sacrificial layers 206 have a thickness T3. Each of the opposite ends 208E of the channel layers 208 between the inner spacers 250 has a thickness T4. Thickness T4 is less than thickness T3.

[0060] The internal spacer material may include metal oxides, silicon oxide, silicon carbonitride, silicon nitride, silicon oxynitride, carbon-rich silicon carbonitride, or low-k dielectric materials. Metal oxides may include aluminum oxide, zirconium oxide, tantalum oxide, yttrium oxide, titanium oxide, lanthanum oxide, or other suitable metal oxides. Although not explicitly shown, the internal spacer material may be a single layer or multiple layers. In some embodiments, the internal spacer material may be deposited using CVD, PECVD, SACVD, ALD, or another suitable method.

[0061] In some embodiments, internal spacer material is deposited in the second recess 240 and over the sidewalls 218s of the gate spacer 218 exposed in the source / drain trench 220 and the sidewalls 208s of the channel layer 208. The deposited internal spacer material is then etched back to remove it from the sidewalls 208s of the channel layer 208 and the sidewalls 218s of the gate spacer 218, thereby forming an internal spacer 250 in the second recess 240.

[0062] In some embodiments, the etch-back operation may include the use of hydrogen fluoride (HF), fluorine (F2), hydrogen (H2), ammonia (NH3), nitrogen trifluoride (NF3), or another fluorine-based etchant. In some embodiments, each internal spacer 250 contacts (e.g., in direct contact) a recessed sacrificial layer 206 and is disposed between two adjacent channel layers 208. In some embodiments, each internal spacer 250 has a sidewall 250s that is substantially flush with the sidewalls 208s of the channel layer 208. In an exemplary embodiment, the sidewalls 250s of the internal spacer 250 are not flush with the sidewalls 218s of the gate spacer 218. Optionally, the sidewalls 250s of the internal spacer 250 may be concave (i.e., bent inward toward the corresponding sacrificial layer 206 adjacent to the internal spacer 250) or convex (i.e., bent outward toward the corresponding source / drain trench 220).

[0063] According to an embodiment, the length of the sacrificial layer 206 along direction D1 (i.e., the distance between the internal spacers 250 at the two opposite ends of the sacrificial layer 206) is the channel length of the gate structure 274 subsequently formed in the replacement gate process (in... Figure 3L (represented as Lc1). Therefore, by increasing the vertical dimension of the first groove 223 to form the second groove 240, sufficient channel length is ensured for the semiconductor structure.

[0064] refer to Figure 1 , Figure 3G and Figure 3H Method 100 includes block 114, wherein a source / drain component 264 is formed in a source / drain trench 220. Operations at block 114 may include suitable epitaxial processes for growing a substrate epitaxial layer 262 and the source / drain component 264 above the substrate epitaxial layer 262, which will be described in more detail below.

[0065] refer to Figure 3G In some embodiments, after forming internal spacers 250 at opposite ends of the sacrificial layer 206, a substrate epitaxial layer 262 is deposited in the bottom of each source / drain trench 220. The formation of the substrate epitaxial layer 262 reduces the depth of the source / drain trench 220 and facilitates the growth of the source / drain components 264 in subsequent processes.

[0066] In some embodiments, the substrate epitaxial layer 262 comprises the same material as the substrate 202 and the channel layer 208, such as silicon (Si), except for the doping conditions (doping elements and / or doping concentration). For example, the substrate epitaxial layer 262 is made of undoped silicon, the substrate 202 is made of doped silicon, and the channel layer 208 is made of undoped or doped silicon. In some embodiments, the substrate epitaxial layer 262 comprises the same material as the sacrificial layer 206, such as silicon germanium (SiGe), but with a different germanium (Ge) content. In some other embodiments, the substrate epitaxial layer 262, the channel layer 208, and the sacrificial layer 206 are made of different semiconductor materials. In various embodiments, the substrate epitaxial layer 262 is dopant-free, wherein, for example, no intentional doping is performed during the epitaxial growth process. By comparison, the substrate 202 may be lightly doped and have a higher doping concentration than the substrate epitaxial layer 262.

[0067] Furthermore, the epitaxial layer 262 provides a high-resistance path from the source / drain region to the substrate 202, thereby suppressing leakage current in the substrate 202 (i.e., through the finned substrate 210B). The inner spacer 250 restricts the vertical growth of the epitaxial layer 262 because epitaxial growth may not occur from the dielectric surface. The epitaxial layer 262 can exhibit facet growth as it reaches the bottom inner spacer 250. Therefore, in some embodiments, the epitaxial layer 262 may partially overlap with the bottom portion of the bottom inner spacer 250, but will not grow vertically beyond the top surface of the bottom inner spacer 250. For simplicity and clarity, the epitaxial layer 262 flush with the bottom surface of the bottom inner spacer 250 is depicted in the figures.

[0068] Suitable epitaxial processes for growing the substrate epitaxial layer 262 may include vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), selective CVD, and / or another suitable process. Various deposition parameters (such as deposition gas composition, carrier gas composition, deposition gas flow rate, carrier gas flow rate, deposition time, deposition pressure, deposition temperature, source power, RF bias voltage, DC bias voltage, RF bias power, DC bias power, other suitable deposition parameters, or combinations thereof) can be adjusted to selectively deposit semiconductor material on the exposed semiconductor surface in the source / drain trench 220. In some embodiments, when forming the substrate epitaxial layer 262, the structure is exposed to a deposition mixture comprising DCS and / or SiH4 (silicon-containing precursor), H2 (carrier precursor), and HCl (etchant-containing precursor). In some embodiments, the selective CVD process employs a deposition temperature of about 600°C to about 750°C. In some embodiments, the selective CVD process employs a deposition pressure of about 10 Torr to about 100 Torr. In some embodiments, a bottom-up deposition process is performed such that the substrate epitaxial layer 262 grows from the exposed semiconductor surface at the bottom of the source / drain trench 220, but not from the exposed end portions of the channel layer 208. In some embodiments, post-deposition etching is performed after a selective CVD process to remove any semiconductor material (if any) that may remain on the end portions of the substrate epitaxial layer 262 on the channel layer 208. Post-deposition etching includes dry etching, wet etching, other suitable etching processes, or combinations thereof.

[0069] refer to Figure 3H In some embodiments, the source / drain component 264 is formed in the source / drain trench 220. In some embodiments, the source / drain component 264 may also be referred to as the doped epitaxial layer 264. Sometimes, the term "source / drain component" includes the doped epitaxial layer 264 and the underlying substrate epitaxial layer 262.

[0070] In some embodiments, forming the source / drain component 264 includes epitaxially growing a semiconductor layer using an MBE process, a chemical vapor deposition process, and / or other suitable epitaxial growth processes. The source / drain component 264 may include phosphorus- or arsenic-doped silicon for n-type transistors. The source / drain component 264 may include boron-doped silicon-germanium for p-type transistors. The source / drain component 264 covers the substrate epitaxial layer 262 and contacts the internal spacer 250. Furthermore, the source / drain component 264 contacts the sidewalls 208s of the channel layer 208. In some embodiments, the source / drain component 264 is grown vertically beyond the top surface of the topmost internal spacer 250 and the topmost channel layer 208.

[0071] Next, refer to Figure 1 , Figure 3I , Figure 3J , Figure 3K and Figure 3L Method 100 includes block 116, in which further processes are performed. Such further processes may include, for example, depositing a contact etch stop layer (CESL) 266 over the structure, and depositing an interlayer dielectric (ILD) layer 268 (such as...) over the CESL 266. Figure 3I As shown), remove the dummy gate stack 215 (as shown). Figure 3J (As shown), selectively remove the sacrificial layer 206 in the trench region to release the trench layer 208 as a trench component (e.g. Figure 3K (as shown) and a gate structure 274 is formed above the channel region (as shown) Figure 3L (As shown). The components, materials, and manufacturing methods in some exemplary embodiments will be described in more detail below.

[0072] In some embodiments, CESL 266 is formed prior to the formation of ILD layer 268. CESL 266 may comprise silicon nitride, silicon oxynitride, and / or another material known in the art. CESL 266 can be formed by an ALD process, a plasma-enhanced chemical vapor deposition (PECVD) process, and / or another suitable deposition process. Figure 3I As shown, CESL 266 is formed on the top surface 264a of the source / drain component 264.

[0073] An ILD layer 268 is then deposited over the CESL 266. In some embodiments, the thickness of the CESL 266 along the first direction D1 is less than the thickness of the ILD layer 268. Furthermore, source / drain components comprising a doped epitaxial layer 264 and an underlying substrate epitaxial layer 262 are partially embedded in the substrate 202 and located below the ILD layer 268. The ILD layer 268 may comprise materials such as tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide, such as borosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silicon glass (BSG), and / or another suitable dielectric material. In some embodiments, the dielectric constant of the ILD layer 268 is less than the dielectric constant of the CESL 266. The ILD layer 268 can be deposited using a PECVD process or another suitable deposition technique. In some embodiments, the structure may be annealed after the formation of the ILD layer 268 to improve the integrity of the ILD layer 268. After depositing CESL 266 and ILD layer 268, a planarization process is performed on ILD layer 268 and CESL 266 to remove excess portions above the top surface of dummy gate stack 215, thereby exposing dummy gate stack 215. The planarization process may include a chemical mechanical planarization (CMP) process. The exposure of dummy gate stack 215 allows for the removal of dummy gate stack 215 and the release of channel layer 208.

[0074] In some embodiments, such as Figure 3J As shown, the exposed dummy gate stack 215 is removed to form a gate trench 270 over the channel layer 208. Removal of the dummy gate stack 215 may include one or more etching processes selectively targeting the material of the dummy gate stack 215. For example, selective wet etching, selective dry etching, or a combination thereof may be used to remove the dummy gate stack 215. After removal of the dummy gate stack 215, the sidewalls of the channel layer 208 and the sacrificial layer 206 in the channel region are exposed to the gate trench 270.

[0075] In some embodiments, such as Figure 3K As shown, after removing the dummy gate stack 215, method 100 may include selectively removing the sacrificial layer 206 between the channel layers 208. Selectively removing the sacrificial layer 206 releases the channel layers 208 to form channel members (also designated 208). Furthermore, selectively removing the sacrificial layer 206 leaves spaces 272 between the channel members 208. The selective removal of the sacrificial layer 206 can be achieved by selective dry etching, selective wet etching, or another selective etching process. A selective dry etching process may include using one or more fluorine-based etchants, such as fluorine gas or hydrofluorocarbons. A selective wet etching process may include APM etching (e.g., an ammonium hydroxide-hydrogen peroxide-water mixture).

[0076] In some embodiments, such as Figure 3L As shown, method 100 may include further operations to form a gate structure 274 to enclose each channel member 208. In some embodiments, the gate structure 274 is formed within a gate trench 270 and in a space 272 left by removing the sacrificial layer 206. According to an embodiment, the thickness T2 of one or each internal spacer 250 is greater than the thickness Tg of the portion of the gate structure 274 between two adjacent channel members 208.

[0077] In some embodiments, the gate structure 274 includes a gate dielectric layer 275 and a gate electrode layer 277 located above the gate dielectric layer 275. Although not explicitly shown in the figures, the gate dielectric layer 275 may include an interface layer and a high-k gate dielectric layer. The interface layer may include a dielectric material such as silicon oxide, hafnium silicate, or silicon oxynitride. The interface layer may be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and / or another suitable method.

[0078] The high-K dielectric material used to form the gate dielectric layer 275 may include a dielectric material with a high dielectric constant (approximately 3.9), which is larger than that of silicon oxide with a specific heat. High-k gate dielectric layers may include hafnium oxide, titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O5), hafnium silicon oxide (HfSiO4), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSiO2), lanthanum oxide (La2O3), aluminum oxide (Al2O3), zirconium oxide (ZrO), yttrium oxide (Y2O3), SrTiO3 (STO), BaTiO3 (BTO), BaZrO, hafnium lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), (Ba,Sr)TiO3 (BST), silicon nitride (SiN), silicon oxynitride (SiON), combinations thereof, or other suitable materials. High-k gate dielectric layers can be formed by ALD, physical vapor deposition (PVD), CVD, oxidation, and / or another suitable method. In one embodiment, a highly conformal deposition process such as ALD is used to form the gate dielectric layer 275 to ensure that a gate dielectric layer with a uniform thickness is formed around each channel layer 208.

[0079] The gate electrode layer 277 of the gate structure 274 may include one or more layers of conductive materials, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, another suitable material, and / or combinations thereof. The gate electrode layer 277 may be formed by ALD, PVD, CVD, electron beam evaporation, or another suitable process. In some embodiments, the gate dielectric material layer and the gate electrode material layer are deposited over the top surface 266a of the CESL 266 and the top surface 268a of the ILD layer 268. The excess gate dielectric material layer and the gate electrode material layer formed over the ILD layer 268 are then planarized using, for example, a CMP process until the CESL 266 and the ILD layer 268 are exposed. Thus, the gate structure 274 can provide a substantially flat top surface. Furthermore, the gate structure 274 includes portions between channel members 208 in the channel region.

[0080] In some embodiments, the gate structure 274 further includes a work function adjustment layer 276 disposed between the gate dielectric layer 275 and the gate electrode layer 277 to enhance device performance. The work function adjustment layer 276 may include one or more work function metal layers. In some embodiments, the work function adjustment layer 276 is made of one or more conductive materials, such as a single layer of TiN, TaN, TaAlC, TiC, TaC, Co, Al, TiAl, HfTi, TiSi, TaSi, or TiAlC, or a multilayer of two or more of these materials. The work function adjustment layer 276 can be formed by ALD, PVD, CVD, electron beam evaporation, or another suitable process.

[0081] According to some embodiments of the semiconductor structure 200A, each of the internal spacers 250 has an enlarged vertical dimension, which effectively prevents the formation of cracks that typically occur during the removal of the sacrificial layer 206, thereby solving the conventional problem of metal extrusion through cracks to form leakage paths after the formation of the replacement gate.

[0082] Figure 4 Some embodiments according to this disclosure are shown. Figure 3J The semiconductor structure in it.

[0083] like Figure 4 As shown, in some embodiments, the thickness T2 of the inner spacer 250 is greater than the thickness T1 of the sacrificial layer 206. For example, the top surface 206a of the sacrificial layer 206 is located at a lateral level lower than the top surface 250a of the inner spacer 250. The bottom surface 206b of the sacrificial layer 206 is located at a lateral level higher than the bottom surface 250b of the inner spacer 250. When the sacrificial layer 206 has a thinner end and a recessed region 2061 is formed between the inner spacer 250 and the sacrificial layer 206, the inner spacer 250 acts as a solid barrier to effectively stop lateral etching during selective removal of the sacrificial layer 206 (e.g., as indicated by arrow Eb), thereby preventing leakage paths from forming after the replacement gate is formed.

[0084] In some (but not limited to) embodiments, the thickness T1 of the sacrificial layer 206 is in the range of about 8.5 nm to 10.5 nm, and the difference Td between the top surface 250a of the inner spacer 250 (e.g., the second portion 250a-2) and the top surface 206a of the sacrificial layer 206 is in the range of about 0.5 nm to 1.5 nm. In some (but not limited to) embodiments, the difference Td is in the range of about 4.5% to 20% of the thickness T2. In some (but not limited to) embodiments, the difference Td is in the range of about 5% to 15% of the thickness T2. These values ​​are provided for illustrative purposes only and are not intended to be limiting.

[0085] Figures 5A to 5LThis is a partial cross-sectional view illustrating the fabrication of a semiconductor structure at various intermediate stages according to some embodiments of the present disclosure. Figures 3A to 3L The parts / components are similar or the same Figures 5A to 5L The parts / components in the reference are represented by similar or identical reference numbers. Figures 5A to 5L Details and references regarding the arrangement, materials, and manufacturing methods of those similar or identical parts / assemblies shown. Figures 3A to 3L The points discussed are essentially the same, and will not be repeated here.

[0086] According to some aspects of the embodiments, in addition to Figures 5A to 5J Each sacrificial layer 506 in the process is an additional component of the membrane stack used to form... Figure 5L The method for forming the semiconductor structure 200B is similar to that used for... Figure 3L A method for a semiconductor structure 200A, wherein the lateral recess of the intermediate film of the stack is different from the lateral recess of the other films of the stack.

[0087] refer to Figure 2 and Figure 5A In some embodiments, a plurality of fin structures 210 protruding from a substrate 202 are provided, and a plurality of dummy gate stacks 215 are formed across the fin structures 210. Each fin structure 210 includes alternating layers located on top of the fin substrate 210B. The formation of the fin structures 210 may include depositing stacks (not shown) on the substrate 202 in an epitaxial growth process. The stacks and top portions of the substrate 202 are patterned to form a plurality of stacks 205. Each stack 205 includes the fin structure 210, and the fin structure 210 includes a sacrificial layer 506 interleaved with the channel layer 508.

[0088] In some embodiments, each sacrificial layer 506 includes a sacrificial intermediate film 5062 disposed between two sacrificial outer films 5061 and 5063. The sacrificial intermediate film 5062 and the sacrificial outer films 5061 and 5063 comprise different semiconductor compositions, such that the sacrificial intermediate film 5062 and the sacrificial outer films 5061 and 5063 have different etch rates. Furthermore, in some embodiments, the sacrificial intermediate film 5062 and the sacrificial outer films 5061 and 5063 have substantially the same thickness. In some embodiments, the sacrificial intermediate film 5062 is thicker than one of the sacrificial outer films 5061 and 5063. In some embodiments, the sacrificial intermediate film 5062 is thinner than one of the sacrificial outer films 5061 and 5063.

[0089] In some embodiments, the sacrificial layer 506 comprises silicon germanium (SiGe), and the germanium concentration of the sacrificial intermediate film 5062 is greater than the germanium concentration of the sacrificial outer films 5061 and 5063. In some (but not limited to) examples, the germanium concentration of the sacrificial intermediate film 5062 of the SiGe sacrificial layer 506 is greater than about 25%, and the germanium concentration of the sacrificial outer film 5061 (or sacrificial outer film 5063) of the SiGe sacrificial film 506 is less than about 25%. The etch rate of the sacrificial outer films 5061 and 5063 is lower than the etch rate of the sacrificial intermediate film 5062. Therefore, the sacrificial outer films 5061 and 5063 have less lateral etch in subsequent processes and can be referred to as sacrificial hard films.

[0090] The dummy gate stack 215 may include a dummy dielectric layer 212 and a dummy electrode layer 214 located on the dummy dielectric layer 212. The dummy gate stack 215 serves as a placeholder to withstand various processes and will be removed and replaced by a functional gate structure. A transistor is formed at the intersection of the fin structure 210 and the functional gate structure. In an exemplary embodiment, where the dummy gate stack 215 is formed above the fin structure 210, the fin structure 21 is divided into a channel region 210C below the dummy gate stack 215 and a source / drain region 210S / D between the channel region 210.

[0091] Furthermore, the dummy gate stacks 215 are spaced apart from each other by the gate pitch GS in the direction D1. Figure 5A The diagram depicts the gate width Wg of one of the dummy gate stacks 215 in direction D1 and the pitch Pgd between adjacent dummy gate stacks 215. The dummy gate stacks 215 in the channel region 210C can have a uniform gate width Wg.

[0092] refer to Figure 5B In some embodiments, a gate spacer layer 218 is deposited on the sidewalls of the dummy gate stack 215. The gate spacer layer 218 may be a single layer or multiple layers. In some embodiments, the gate spacer layer 218 includes a first gate spacer 216 and a second gate spacer 217 disposed above the first gate spacer 216.

[0093] refer to Figure 5C In some embodiments, the fin structure 210 in the source / drain region 210S / D is recessed to form a source / drain trench 220. The source / drain trench 220 exposes the sidewalls 508s of the channel layer 508 and the sidewalls 506s of the sacrificial layer 506.

[0094] refer to Figure 5DIn some embodiments, the sacrificial layer 506 is laterally recessed to form a first groove 523 in the fin structure 210. In some embodiments, the sacrificial layer 506 exposed in the source / drain trench 220 is selectively etched to form the first groove 523, while the exposed portions of the gate spacer layer 218, the fin substrate 210B (substrate 202), and the channel layer 508 are substantially unetched.

[0095] In some embodiments, the sacrificial intermediate film 5062 (e.g., with a higher Ge concentration) and the sacrificial outer films 5061 and 5063 (e.g., with a lower germanium concentration) have different etch selectivity. For example, when a single etch process is performed to laterally recess the sacrificial layer 506, the etch rate for each of the sacrificial intermediate films 5062 with a higher Ge concentration is greater than the etch rate for each of the sacrificial outer films 5061 and 5063 with a lower Ge concentration. Therefore, a first groove 523 including different recess amounts can be obtained by a single etch process. In some embodiments, after etching, the lateral recess amount of the sacrificial intermediate film 5062 is greater than the lateral recess amount of one of the sacrificial outer films 5061 and 5063. Figure 5D As shown, one of the first grooves 523 includes an outer groove 5231 of the sacrificial outer membrane 5061, an intermediate groove 5232 of the sacrificial intermediate membrane 5062, and an outer groove 5233 of the sacrificial outer membrane 5063. The intermediate groove 5232 in the D1 direction is larger than the outer grooves 5231 and 5233 in the D1 direction.

[0096] refer to Figure 5E In some embodiments, the first groove 523 is enlarged to form the second groove 540. In this exemplary embodiment, the outer grooves 5231 and 5233 are further reshaped by one or more selective etching processes. Figure 5D This forms outer grooves 5241 and 5243 with larger vertical dimensions, while the intermediate groove 5232 extends neither vertically nor laterally. The formation of the second groove 540 can be referenced in [reference needed]. Figures 3E-1 to 3E-4 The methods discussed will not be repeated here. In some embodiments, each of the second grooves 540 has a T-shaped cross-section.

[0097] refer to Figure 5FIn some embodiments, an internal spacer 550 is formed in a second recess 540. For example, an internal spacer material (not shown) is deposited in the source / drain trench 220 and fills the second recess 540. The internal spacer material is then etched back to form the internal spacer 550 in the second recess 540. In some embodiments, one of the internal spacers 550 may be divided into a body 550M and a protrusion 550P projecting from the body 550M. The protrusion 550P projects toward the sacrificial layer 506 (i.e., away from the source / drain trench 220). In some embodiments, the thickness T2 (e.g., the maximum vertical dimension) of the body 550M of the internal spacer 550 is greater than the thickness T1 of the sacrificial layer 506. Since the protrusion 550P fills the intermediate recess 5232, the thickness of the protrusion 550P is substantially equal to the thickness of the sacrificial intermediate film 5062.

[0098] In some embodiments, such as Figure 5F As shown, the main body 550M of the internal spacer 550 has a lateral length L1 between its opposing side surfaces 550s2 and 550s1. The intermediate portion 550c of the internal spacer 550 has a lateral length L2 between the side surface 550s2 of the main body 550M and the side surface 550P-s of the protrusion 550P. Therefore, the protrusion 550P of the internal spacer 550 increases the volume of the intermediate portion 550c of the internal spacer 550, thereby providing a robust internal spacer 55. Figure 5F As shown, the lateral length L2 is greater than the lateral length L1. Furthermore, in this exemplary embodiment, the side surface 550s2 of the inner spacer 550 is a substantially flat surface; however, this disclosure is not limited thereto.

[0099] Next, refer to Figure 5G to Figure 5L It can execute with Figures 3G to 3L Further processes similar to those described above. Such further processes may include, for example, depositing an epitaxial layer 262 on the substrate (e.g., ...). Figure 5G As shown), source / drain components 264 are formed in the source / drain trench 220 (e.g., Figure 5H As shown), a contact etch stop layer (CESL) 266 is deposited and an ILD layer 268 is deposited on top of the CESL 266 (as shown). Figure 5I As shown), remove the dummy gate stack 215 (as shown). Figure 5J As shown), the sacrificial layer 506 in the trench region is selectively removed to release the trench layer 508 as the trench component 508 (as shown). Figure 5K As shown), and a gate structure 574 is formed above the channel region (as shown). Figure 5L (As shown).

[0100] The gate structure 574 may include a gate dielectric layer 575, a power function adjustment layer 576, and a gate electrode layer 577. In some embodiments, the body 550M of the internal spacer 550 contacts the channel member 508 and the side surface 574s of the gate structure 574. In some embodiments, a protrusion 550P is located between the body 550M and the gate structure 574 (e.g., along the D1 direction). In some embodiments, the protrusion 550P is perpendicularly spaced from the adjacent channel member 508 (e.g., along the D3 direction).

[0101] According to some embodiments of the semiconductor structure 200B, the internal spacer 550 with an enlarged vertical dimension effectively prevents the formation of cracks that typically occur during the removal of the sacrificial layer 506, thereby solving the conventional problem of metal extrusion through cracks that forms leakage paths when forming replacement gates (e.g., gate structure 574). Furthermore, in some embodiments, the channel length of the semiconductor structure 200B can be increased by requiring less etching on the sacrificial outer films 5061 and 5063 of the sacrificial layer 506 than on the intermediate sacrificial film 5062 of the sacrificial layer 506. Therefore, the reliability and electrical performance of the semiconductor structure can be improved.

[0102] Figure 6A Some embodiments according to this disclosure are shown. Figure 3F The semiconductor structure in it. Figure 6B Some embodiments according to this disclosure are shown. Figure 5F The semiconductor structure in it.

[0103] like Figure 6A As shown, one of the internal spacers 250 has a length L1', and the gate structure 274 deposited to enclose the channel layer 208 has a channel length Lc1. That is, the channel length Lc1 is defined as the lateral length between the opposing internal spacers 250 in the direction D1. Figure 6B As shown, one of the bodies 550M of the internal spacer 550 has a length L1, and the gate structure 574 deposited as a wrapping channel layer 508 has a channel length Lc2. That is, the channel length Lc2 is defined as the lateral length in the direction D1 between the relative bodies 550M of the internal spacer 250.

[0104] refer to Figure 6A and Figure 6B In some embodiments where the sacrificial layer 206 and the sacrificial intermediate film 5062 comprise the same material, the sacrificial layer 206 ( Figure 3D The lateral concavity is approximately equal to that of the sacrificial intermembrane 5062. Figure 5DThe lateral recess of the inner spacer 250 is greater than that of the sacrificial outer membranes 5061 and 5063. Therefore, the length L1' of the inner spacer 250 is greater than the length L1 of the body 550M of the inner spacer 550. The selective removal of the sacrificial layer 506 leaves a space 572 between the channel layers 508. Figure 5K Following this, a gate structure (e.g., comprising a metal gate) 574 is deposited to enclose the channel layer 508. The smaller lateral recess of the sacrificial outer films 5061 and 5063 results in a larger contact area between the subsequently formed gate structure 574 and the channel layer 508, which improves the electrical performance of the semiconductor structure. In some embodiments, the channel length Lc2 of the semiconductor structure 200B (e.g., ...) is... Figure 6B As shown) a channel distance Lc1 greater than 200A in the semiconductor structure (e.g.) Figure 6A (As shown).

[0105] Figure 7 This is a partial cross-sectional view of a semiconductor structure at an intermediate stage according to some other embodiments of this disclosure. Figure 7 The structure can be similar to Figures 5A to 5L The method of operation is formed. In some embodiments, when, for example, internal spacer material is deposited in the source / drain trench 220 and the second groove 540 by ALD ( Figure 5F The internal spacer material may not completely fill the second groove 540, and after the source / drain component 264 is subsequently formed in the source / drain trench 220, the semiconductor structure may include a gap 560 (also referred to as an air gap or air pocket) located in some or all of the internal spacers 550. The gap 560 is located between the source / drain component 264 and the internal spacers 550.

[0106] In some embodiments, each internal spacer 550 includes a body 550M and a protrusion 550P projecting toward the gate structure 574. Furthermore, the protrusion 550P and the gap 560 may be positioned relative to the intermediate portion 550c of the internal spacer 550. In some embodiments, the body 550M of one of the internal spacers 550 has opposing side surfaces 550s2 and 550s1. The side surface 550s2 may include a recess 550r located in the intermediate portion 550c of the internal spacer 550. The remaining portion of the side surface 550s2 of the internal spacer 550 may be substantially flush with the sidewall 508s of the channel layer 508. The recess 550r of the side surface 550s2 of the internal spacer 550 and the source / drain component 264 adjacent to the internal spacer 550 define the gap 560. Figure 7 As shown, one of the gaps 560 has a vertical dimension Da. These gaps 560 may have substantially the same dimension or different dimensions.

[0107] In some embodiments, although the body 550M has a recessed portion 550r, the volume of the middle portion 550c of the internal spacer 550 can be increased when a protrusion 550P is formed.

[0108] Specifically, such as Figure 7 As shown, the body 550M of the internal spacer 550 has a lateral length L1 in the D1 direction between the side surfaces 550s2 and 550s1. The intermediate portion 550c of the internal spacer 550 has a lateral length L2 in the D1 direction between the side surface 550P-s of the protrusion 550P and the recessed portion 550r of the side surface 550s2 of the body 550M. In some embodiments, the thickness Tp of the protrusion 550P is substantially equal to or greater than the dimension Da of the gap 560. In some embodiments, the lateral length L1 and the lateral length L2 are substantially the same. In some embodiments, the lateral length L2 is greater than the lateral length L1. According to an embodiment, the formation of the protrusion 550P compensates for the volume loss of the internal spacer 550 due to the formation of the gap 560. Therefore, the protrusion 550P of the internal spacer 550, which increases the volume of the intermediate portion 550c of the internal spacer 550, provides a robust internal spacer 550.

[0109] according to Figure 5L and Figure 7 In the structure, each of the internal spacers 550 has a T-shaped cross-section. After depositing the gate structure 574 to enclose the channel layer 508, as described above, the T-shaped internal spacers 550 result in a larger contact area between the gate structure 574 and the channel layer 508. Furthermore, when the sacrificial layer 506 is removed (e.g., ...), Figure 5K Each of the internal spacers 550 has an enlarged vertical dimension, effectively preventing etching through the channel layer 508 above the top of the internal spacer 550 and / or below the bottom of the internal spacer 550. Furthermore, the semiconductor structure includes one or more voids 560 (e.g., Figure 7 In some embodiments, these voids may be unintentionally formed through the deposition of internal spacer material, the protrusions 550M of the internal spacer 550 thickening the middle portion 550c of the internal spacer 550 and preventing etching through the middle portion 550c during the removal of the sacrificial layer 506 (e.g., forming undesirable cracks). Therefore, it is possible to effectively improve... Figure 5L and Figure 7 The reliability and electrical performance of semiconductor structures.

[0110] According to some other embodiments of this disclosure, the internal spacer with protrusions can be manufactured by another method.

[0111] Figures 8A to 8GThis is a partial cross-sectional view of a semiconductor structure being manufactured at various intermediate stages according to some embodiments of this disclosure. Figures 5C to 5L The parts / components are similar or the same Figures 8A to 8G The parts / components in the document are represented by similar or identical reference numbers. Figures 8A to 8G Details and references regarding the arrangement, materials, and manufacturing methods of those similar or identical parts / assemblies shown. Figures 5C to 5L and Figures 3C to 3L The points discussed are essentially the same, and will not be repeated here.

[0112] refer to Figure 2 and Figure 8A In some embodiments, a plurality of fin structures 210 protruding from a substrate 202 and a plurality of dummy gate stacks 215 positioned across the fin structures 210 are provided. Each fin structure 210 includes alternating layers located on top of a fin substrate 210B. Formation of the fin structures 210 may include depositing stacks (not shown) on the substrate 202 via an epitaxial growth process. The stacks and top portions of the substrate 202 are patterned to form a plurality of stacks. Each stack includes a fin structure 210. Furthermore, each stack includes a sacrificial layer 606 interleaved with a channel layer 608.

[0113] Furthermore, the dummy gate stack 215 may include a dummy dielectric layer 212 and a dummy electrode layer 214 located on the dummy dielectric layer 212. When the dummy gate stack 215 is formed over the fin structure 210, the fin structure 210 is divided into a channel region 210C below the dummy gate stack 216 and source / drain regions 210S / D located between the channel regions 210. Then, in some embodiments, a gate spacer layer 218 (including a first gate spacer 216 and a second gate spacer 217) is deposited on the sidewalls of the dummy gate stack 215. The bottom portion of the gate spacer layer 218 and the fin structure 210 in the source / drain regions 210S / D are then removed to form a source / drain trench 220.

[0114] In this exemplary embodiment, each sacrificial layer 606 includes a sacrificial intermediate film 6062 located between two sacrificial outer films 6061 and 6063. The sacrificial intermediate film 6062 and the sacrificial outer films 6061 and 6063 exhibit different etch rates. In some embodiments, the sacrificial layer 606 comprises silicon germanium (SiGe), and the germanium concentration of the sacrificial intermediate film 6062 is greater than the average germanium concentration in either of the sacrificial outer films 6061 and 6063. In some embodiments, each of the sacrificial outer films 6061 and 6063 has a germanium concentration gradient that decreases from the sacrificial intermediate film 6062 to the channel layer 608.

[0115] Figure 9AThis is a diagram depicting the germanium concentration distribution on a sacrificial layer 606 according to some embodiments of the present disclosure. In some embodiments, the sacrificial intermediate film 6062 of the sacrificial layer 606 has a uniform germanium concentration C2, while each of the sacrificial outer films 6061 and 6063 has a germanium concentration that decreases with increasing distance from the sacrificial intermediate film 6062.

[0116] Specifically, such as Figure 8A and Figure 9A As shown, the sacrificial outer film 6061 has a lower surface S1 in contact with the channel layer 608 and an upper surface S2 in contact with the sacrificial intermediate film 6062. Curve (I) represents the distribution of germanium concentration in the sacrificial outer film 6061. The germanium concentration in the sacrificial outer film 6061 varies from a maximum value C2 at the upper surface S2 to a minimum value C1 at the lower surface S1. Curve (II) represents the distribution of germanium concentration in the sacrificial intermediate film 6062, which is uniform at the maximum value C2. Furthermore, the sacrificial outer film 6063 has a lower surface S3 in contact with the sacrificial intermediate film 6062 and an upper surface S4 in contact with the channel layer 608. Curve (III) represents the distribution of germanium concentration in the sacrificial outer film 6063. The germanium concentration in the sacrificial outer film 6061 varies from a maximum value C2 at the lower surface S3 to a minimum value C1 at the upper surface S4.

[0117] Figure 9B This is another diagram depicting the germanium concentration distribution on the sacrificial layer 606 according to some embodiments of the present disclosure. Figure 9A and Figure 9B The germanium concentration distribution in the samples showed a similar trend, except that... Figure 9A Curves (I) and (III) in the figure decrease exponentially with increasing distance from the sacrificial intermediate membrane 6062, while Figure 9B Curves (I') and (III') in the diagram decrease linearly with distance from the sacrificial intermediate film 6062. Therefore, in this exemplary embodiment, the sacrificial layer 606 has the lowest germanium concentration at the interface (i.e., surfaces S1 and S4) between the sacrificial layer 606 and the channel layer 608. In some embodiments, the minimum germanium concentration C1 can be substantially zero.

[0118] For a GAA nanosheet transistor where the channel layer 608 is a silicon (Si) layer and the sacrificial layer 606 is a silicon-germanium (SiGe) layer, Ge diffuses from the SiGe layer into the Si channel layer due to the high thermal budget of subsequent processes (e.g., shallow trench isolation (STI) oxide annealing, S / D epitaxial growth, etc.). Unwanted germanium diffusion leads to a range of problems, including, for example, a shift in the gate threshold voltage and poor SiGe indentation profiles for internal spacer formation operations. Therefore, according to this embodiment, the germanium concentration distribution in the sacrificial layer 606 (including the highest germanium concentration in the middle portion and the germanium concentration decreasing with increasing distance from the middle portion) effectively reduces germanium diffusion, thereby improving the reliability and electrical performance of the semiconductor structure.

[0119] Next, refer to Figure 8B In some embodiments, the sacrificial layer 606 is laterally recessed to form a first groove 623 in the fin structure 210. In some embodiments, the etch rate of the sacrificial intermediate film 6062 with a higher Ge concentration is greater than the etch rate of the sacrificial outer films 6061 and 6063. Furthermore, the lateral recess amount of the sacrificial intermediate film 6062 is greater than the lateral recess amount of the sacrificial outer films 6061 and 6063. Figure 8B As shown, one of the first grooves 623 includes an outer groove 6231 of a sacrificial outer film 6061, an intermediate groove 6232 of a sacrificial intermediate film 6062, and an outer groove 6233 of a sacrificial outer film 6063. Since each of the sacrificial outer films 6061 and 6063 includes a germanium concentration that decreases with increasing distance from the intermediate portion, the sacrificial outer films 6061 and 6063 have curved surfaces defining the outer grooves 6231 and 6233 after etching. In some embodiments, the sacrificial outer films 6061 and 6063 exhibit curved surfaces after performing a single etching process.

[0120] Next, refer to Figure 8C In some embodiments, the first groove 623 is enlarged to form a second groove 624. In this exemplary embodiment, the outer grooves 6231 and 6233 ( Figure 8B Further reshaping is used to form outer recesses 6241 and 6243, each of which has a larger vertical dimension. The operation for forming the second recess 624 may include a cyclic oxidation and removal process performed on the channel layer 608 to enlarge the first recess 623 while the gate spacer layer 218 and the sacrificial intermediate film 6062 are substantially unetched. The formation of the second recess 624 can be referenced in [reference needed]. Figures 3E-1 to 3E-4 The methods discussed will not be repeated here. In some embodiments, the removal process may include one or more consecutively repeated dry etching processes and one or more wet etching processes until a second groove 624 with the desired size is formed.

[0121] refer to Figure 8D In some embodiments, an internal spacer 650 is formed in a second recess 624. The internal spacer 650 includes a body 650M and a protrusion 650P projecting toward the sacrificial layer 606. Furthermore, the protrusion 650P projects from a side surface 650s1 of the body 650M. In some embodiments, the side surface 650P-s of one of the protrusions 650Ps in the internal spacer 650 is convex in cross-sectional view (i.e., curved outward toward the corresponding sacrificial layer 606).

[0122] The internal spacer 650 can be formed by CVD, ALD, or any suitable method. In one embodiment, the internal spacer 650 is formed using a highly conformal deposition process such as ALD to form multiple spacer films, each spacer film having a uniform thickness along the sidewall of the second recess 624. However, using ALD deposition, the second recess 624 may not be completely filled with the internal spacer material. After the source / drain components 264 are formed in subsequent processes, such as... Figure 8E As shown, a gap 660 (also referred to as an air gap or air bag) can be formed in the second groove 624, and the gap 660 is located between the inner spacer 650 and the source / drain component 264.

[0123] Furthermore, in some embodiments, the protrusion 650P and the subsequently formed gap 660 (e.g., in...) Figure 8E The protrusion 650P can be positioned relative to the middle portion 650c of the internal spacer 650. Specifically, the body 650M of the internal spacer 650 includes side surfaces 650s2 and 650s1. The side surface 650s2 includes a recess 650r located in the middle portion 650c of the internal spacer 650. The remaining portion of the side surface 650s2 of the internal spacer 650 is substantially flush with the sidewall 608s of the channel layer 608. Although the side surface 650s2 of the body 650M includes the recess 650r, the volume of the middle portion 650c of the internal spacer 650 can increase with the formation of the protrusion 650P. Figure 8D As shown, the intermediate portion 650c between the side surface 650P-s of the protrusion 650P and the recessed portion 650r of the side surface 650s2 of the body 650M has a lateral length L3 in the D1 direction. With the protrusion 650P, the volume of the intermediate portion 650c of the internal spacer 650 can be increased, thereby providing a robust internal spacer 650.

[0124] Next, refer to Figures 8E to 8G In some embodiments, it is possible to perform with Figure 5G to Figure 5LFurther processes similar to those described above. Such further processes may include, for example, depositing a substrate epitaxial layer 262, forming source / drain components 264 in the source / drain trench 220, depositing a contact etch stop layer (CESL) 266 and an ILD layer 268 over the CESL 266, and removing dummy gate stacks 215 (such as...). Figure 8E (as shown); selectively remove the sacrificial layer 606 in the trench region to release the trench layer 608 as trench member 608 (as shown). Figure 8F (as shown) and a gate structure 674 formed above the channel region (as shown) Figure 8G (As shown). The gate structure 674 may include a gate dielectric layer 675, a power function adjustment layer 676, and a gate electrode layer 677. In some embodiments, in a cross-sectional view, a protrusion 650P of one of the internal spacers 650 has a convex side surface 650P-s that contacts the gate structure 674. During the formation of the gate structure 674 enclosing the channel region, the convex side surface 650P-s of the protrusion 650P may facilitate conformal deposition of the gate structure 674 on the protrusion 650P to enclose the channel region.

[0125] According to some embodiments of the semiconductor structure 200C, the internal spacer 650 with an enlarged vertical dimension effectively prevents the formation of cracks that typically occur during the removal of the sacrificial layer 606, thereby solving the conventional problem of leakage paths through cracks by metal extrusion during the formation of replacement gates (e.g., gate structure 674). Furthermore, in some embodiments, the channel length Lc3 of the semiconductor structure 200C can be increased by having a smaller etching amount on the sacrificial outer films 6061 and 6063 of the sacrificial layer 606 than on the intermediate sacrificial film 6062 of the sacrificial layer 606. Furthermore, according to some embodiments of the semiconductor structure 200C, the protrusion 650M of the internal spacer 650 thickens the middle portion 650c of the internal spacer 650c and prevents etching through the internal spacer during the removal of the sacrificial layer 606 (e.g., the formation of undesirable cracks). Furthermore, according to some embodiments of the method for forming the semiconductor structure 200C, there is a [missing information - likely a measurement or feature] from the middle portion of the sacrificial layer 606 to the channel layer 608 ([missing information - likely a measurement or feature]). Figure 8A The reduced germanium concentration gradient of the sacrificial layer 606 effectively reduces germanium diffusion with high thermal budgets in subsequent processes.

[0126] While not intended to be limiting, one or more embodiments of this disclosure provide numerous benefits for semiconductor structures and their formation. For example, embodiments of this disclosure provide internal spacers interleaved with channel components, and the internal spacers have enlarged dimensions to prevent leakage paths from forming between the metal gate and source / drain components. Furthermore, in some embodiments, robust internal spacers can be provided by forming protrusions in the middle portions of the internal spacers. In some embodiments, internal spacers with protrusions compensate for volume losses when one or more gaps are formed between the internal spacers and the source / drain components. Additionally, in some embodiments, by forming internal spacers with protrusions, a larger contact area between the gate structure and the channel layer can be achieved, which improves the performance of the semiconductor structure (e.g., a transistor). Therefore, the reliability and electrical performance of the semiconductor structures of the embodiments are significantly improved.

[0127] In one exemplary aspect, this disclosure relates to a method. The method includes: alternately stacking channel layers and sacrificial layers on a substrate in a vertical direction to form a semiconductor stack; patterning the semiconductor stack to form a fin structure protruding from the substrate; forming source / drain trenches in the fin structure; laterally recessing the sacrificial layers in the fin structure to form a first trench; and widening the first trench to form a second trench. The method also includes forming a contact etch stop layer over source / drain components and forming an interlayer dielectric (ILD) layer over a CESL. The first trenches at opposite ends of one of the sacrificial layers are spaced apart from each other along a direction. The thickness of the CESL along the direction is less than the thickness of the ILD layer. After widening the first trench, one of the second trenches has a vertical dimension larger than the thickness of the sacrificial layer. The method also includes forming internal spacers in the second trench and forming source / drain components in the source / drain trench.

[0128] In some embodiments, anisotropic etching is performed to increase the vertical dimension of the first groove. In some embodiments, the first groove exposes opposite ends of the channel layer, and forming the second groove includes partially etching the exposed portion of the channel layer to form the second groove. In some embodiments, one of the sacrificial layers includes a sacrificial intermediate film disposed between two sacrificial outer films, and when the sacrificial layer is laterally recessed, the lateral recess of the sacrificial intermediate film is greater than the lateral recess of one of the sacrificial outer films. In some embodiments, the sacrificial layer is laterally recessed by etching, and the etching rate of the sacrificial intermediate film is higher than the etching rate of the sacrificial outer films. In some embodiments, the sacrificial intermediate film and the sacrificial outer film of the sacrificial layer are laterally recessed using a single etching process to form the first groove. In some embodiments, the germanium concentration of the sacrificial intermediate film is greater than the germanium concentration of the sacrificial outer films. In some embodiments, one of the sacrificial outer films has a germanium concentration gradient that decreases from the sacrificial intermediate film to the channel layer adjacent to the sacrificial outer film.

[0129] In another exemplary aspect, this disclosure relates to a method. The method includes: forming a fin structure including a stack on top of a substrate, the stack including a channel layer interleaved with a sacrificial layer. The substrate protrudes from a substrate, and the fin structure includes a channel region and a source / drain region. The method further includes forming a dummy gate stack over the channel region of the fin structure, depositing a gate spacer layer over the dummy gate stack, and forming a source / source trench by recessing the source / drain region of the fin structure. The source / drain trench exposes the sidewalls of the channel layer and the sacrificial layer. The method further includes selectively and partially recessing the sacrificial layer to form a first trench, and widening the first trench to form a second trench. One of the second trenches has a vertical dimension larger than the thickness of the sacrificial layer. The method further includes forming an internal spacer in the second trench, and forming a source / drain component in the source / drain trench, wherein a gap is formed between the source / drain component and one of the internal spacers. The method also includes forming a contact etch stop layer over the source / drain components and an interlayer dielectric (ILD) layer over the CESL, wherein the dielectric constant of the CESL is greater than that of the ILD layer.

[0130] In some embodiments, the sacrificial layer is partially recessed to expose opposing end portions of the channel layer to form a first groove, and the first groove is enlarged to form a second groove by directional oxidation and selective etching to partially remove the exposed end portions of the channel layer. In some embodiments, the void is positioned relative to an intermediate portion of one of the internal spacers. In some embodiments, one of the sacrificial layers includes a sacrificial intermediate film disposed between two sacrificial outer films. When the sacrificial layer is partially recessed to form the first groove by a single etching process, the lateral recess of the sacrificial intermediate film is greater than the lateral recess of one of the two sacrificial outer films. In some embodiments, one of the sacrificial layers includes an intermediate portion formed between the outer portions, and the germanium concentration of the intermediate portion is greater than the germanium concentration of the outer portions.

[0131] In yet another exemplary aspect, this disclosure relates to a semiconductor structure. The semiconductor structure includes: a channel member suspended above a substrate; internal spacers interleaved with the channel member; a gate structure enclosing the channel member; source / drain components adjacent to the channel member; a contact etch stop layer located above the source / drain components; and an interlayer dielectric (ILD) layer located above the CESL. The source / drain components are partially embedded in the substrate and located below the ILD layer. The internal spacers extend into the end portions of the channel member adjacent to the internal spacers. One of the internal spacers has a vertical dimension larger than that of the channel member.

[0132] In some embodiments, one of the internal spacers has a vertical thickness greater than the thickness of a portion of the gate structure between two adjacent channel members. In some embodiments, one of the internal spacers includes: a body partially disposed against a lateral side surface of the gate structure; and a protrusion projecting from the body and extending in a direction away from the source / drain members. In some embodiments, the protrusion is vertically spaced from adjacent channel members and makes partial contact with the gate structure between the channel members. In some embodiments, the side surface of the body has a recessed portion, and a gap is formed between the recessed portion of the side surface of the body and the source / drain members. In some embodiments, the protrusion includes a convex surface that contacts the gate structure between the channel members. In some embodiments, one of the top and bottom surfaces of one of the internal spacers includes a first portion adjacent to the gate structure and a second portion adjacent to the source / drain members, and the first portion is more inclined than the second portion relative to the channel members along an extending plane.

[0133] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and alterations can be made to them herein without departing from the spirit and scope of this disclosure.

Claims

1. A method for forming a semiconductor structure, comprising: alternately stacking channel layers and sacrificial layers on a substrate in a vertical direction to form a semiconductor stack; patterning the semiconductor stack to form a fin-shaped structure protruding from the substrate; forming source / drain trenches in the fin-shaped structure; laterally recessing the sacrificial layers in the fin-shaped structure to form first recesses, wherein the first recesses at opposite ends of one of the sacrificial layers are spaced apart from each other along a direction; enlarging the first recesses to form second recesses, wherein one of the second recesses has a vertical dimension greater than a thickness of the sacrificial layers after the first recesses are enlarged; forming inner spacers in the second recesses; forming source / drain components in the source / drain trenches; forming a contact etch stop layer over the source / drain components; and forming an interlayer dielectric (ILD) layer over the contact etch stop layer, wherein a thickness of the contact etch stop layer along the direction is less than a thickness of the interlayer dielectric layer.

2. The method of claim 1, wherein, performing an anisotropic etch to enlarge a vertical dimension of the first recesses.

3. The method of claim 1, wherein, The first recesses expose opposite ends of the channel layers, and forming the second recesses includes partially etching exposed portions of the channel layers to form the second recesses.

4. The method of claim 1, wherein, One of the sacrificial layers includes a sacrificial middle membrane disposed between two sacrificial outer membranes, and when the sacrificial layers are laterally recessed, an amount of lateral recessing of the sacrificial middle membrane is greater than an amount of lateral recessing of one of the sacrificial outer membranes.

5. The method of claim 4, wherein, The sacrificial layers are laterally recessed by etching, and an etch rate of the sacrificial middle membrane is higher than an etch rate of the sacrificial outer membranes.

6. The method of claim 5, wherein, The sacrificial middle membrane and the sacrificial outer membranes of the sacrificial layers are laterally recessed using a single etch process to form the first recesses.

7. The method of claim 4, wherein, A germanium concentration of the sacrificial middle membrane is greater than a germanium concentration of the sacrificial outer membranes.

8. The method of claim 4, wherein, One of the sacrificial outer membranes has a decreasing germanium concentration gradient from the sacrificial middle membrane to the channel layers adjacent to the sacrificial outer membrane.

9. A method for forming a semiconductor structure, comprising: forming a fin-shaped structure, the fin-shaped structure including a stack on top of a base, the stack including channel layers interleaved with sacrificial layers, the base protruding from a substrate, the fin-shaped structure including channel regions and source / drain regions; forming a dummy gate stack over the channel regions of the fin-shaped structure; depositing a gate spacer layer over the dummy gate stack; forming source / drain trenches by recessing the source / drain regions of the fin-shaped structure, wherein the source / drain trenches expose sidewalls of the sacrificial layers and the channel layers; selectively and partially recessing the sacrificial layers to form first recesses; enlarging the first recesses to form second recesses, wherein one of the second recesses has a vertical dimension greater than a thickness of the sacrificial layers; forming inner spacers in the second recesses; and forming source / drain components in the source / drain trenches, wherein voids are formed between the source / drain components and one of the inner spacers; forming a contact etch stop layer over the source / drain features; and forming an interlayer dielectric (ILD) layer over the contact etch stop layer, wherein a dielectric constant of the contact etch stop layer is greater than a dielectric constant of the interlayer dielectric layer.

10. A semiconductor structure, comprising: channel members suspended over a substrate; internal spacers interleaved with the channel members; gate structures wrapping the channel members; source / drain features abutting the channel members, wherein the internal spacers extend into end portions of the channel members adjacent the internal spacers, and one of the internal spacers has a greater vertical dimension than the channel members; a contact etch stop layer over the source / drain features; and an interlayer dielectric (ILD) layer over the contact etch stop layer, wherein the source / drain features are partially embedded in the substrate and are located under the interlayer dielectric layer.

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