Semiconductor device and forming method thereof

Abstract

A metal silicide layer is formed on a source / drain region of a transistor (e.g., a nanostructured transistor and / or another type of transistor) of a semiconductor device prior to formation of a recess in which a source / drain contact is to be formed. This enables the coverage of the metal silicide layer on the surface of the source / drain region to be defined independently of the coverage of the source / drain contact, which is defined by the recess in which the source / drain contact is formed. The embodiment of the invention also relates to a semiconductor device and a forming method thereof.

Description

Technical Field

[0001] Embodiments of this application relate to semiconductor devices and methods of forming the same. Background Technology

[0002] As semiconductor device manufacturing advances and technology processing nodes shrink in size, transistors may become susceptible to short-channel effects (SCE), such as hot carrier degradation, barrier reduction, and quantum confinement, among others. Furthermore, at even smaller technology nodes, as the gate length of the transistor decreases, source / drain (S / D) electron tunneling increases, which increases the cutoff current (the current flowing through the transistor's channel when the transistor is in a cutoff configuration). Silicon (Si) / silicon-germanium (SiGe) nanostructure transistors, such as nanowires, nanosheets, and gate-all-around (GAA) devices, are potential candidate transistors for overcoming short-channel effects at smaller technology nodes. Nanostructure transistors are efficient structures that can experience reduced SCE and enhanced carrier mobility compared to other types of transistors. Summary of the Invention

[0003] Some embodiments of this application provide a method for forming a semiconductor device, comprising: forming a plurality of nanostructured channels, the plurality of nanostructured channels being arranged in a first direction and extending in the semiconductor device in a second direction substantially perpendicular to the first direction; forming source / drain regions adjacent to the plurality of nanostructured channels in the second direction; depositing a first dielectric layer above and beside the source / drain regions; forming a gate structure enclosing at least three sides of the plurality of nanostructured channels; etching the first dielectric layer to form a first groove through the first dielectric layer, such that the top surface of the source / drain regions passes through the... A first groove is exposed; a metal material is deposited on the top surface of the source / drain region in the first groove to form a metal silicide layer on the top surface of the source / drain region; a second dielectric layer is deposited in the first groove such that the second dielectric layer is located above the metal silicide layer and the source / drain region; the second dielectric layer is etched to form a second groove through the second dielectric layer such that the second groove is located above at least a portion of the metal silicide layer; and a source / drain contact is formed in the second groove such that the source / drain contact is formed above at least a portion of the metal silicide layer.

[0004] Other embodiments of this application provide a method for forming a semiconductor device, comprising: forming a plurality of nanostructured channels arranged in a first direction and extending in the semiconductor device in a second direction substantially perpendicular to the first direction; forming source / drain regions adjacent to the plurality of nanostructured channels in the second direction; depositing a first dielectric layer over and beside the source / drain regions; forming a gate structure enclosing at least three sides of the plurality of nanostructured channels; and etching the first dielectric layer to form a first groove through the first dielectric layer, thereby exposing the top surface of the source / drain regions through the first groove. A metal material is deposited on the top surface of the source / drain region in the first groove to form a metal silicide layer on the top surface of the source / drain region; a metal capping layer is deposited on the metal silicide layer; a second dielectric layer is deposited in the groove such that the second dielectric layer is located above the metal capping layer and the source / drain region; the second dielectric layer is etched to form a second groove through the second dielectric layer such that the second groove is located above at least a portion of the metal capping layer; and a source / drain contact is formed in the second groove such that the source / drain contact is formed above at least a portion of the metal capping layer.

[0005] Further embodiments of this application provide a semiconductor device comprising: a plurality of nanostructured channels arranged in the semiconductor device in a first direction; a gate structure enclosing the plurality of nanostructured channels; a source / drain region adjacent to a side of the gate structure and an end of the plurality of nanostructured channels in a second direction substantially perpendicular to the first direction; a dielectric structure adjacent to the opposite side of the source / drain region in a third direction substantially perpendicular to both the first and second directions; a metal silicide layer located on the top surface of the source / drain region; and source / drain contacts located above the metal silicide layer, wherein a first lateral width of the metal silicide layer in the third direction and a second lateral width of the source / drain contacts in the third direction are different lateral widths. Attached Figure Description

[0006] Various aspects of the embodiments of this disclosure will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0007] Figures 1A to 1C This is a diagram of an exemplary embodiment of the fin-defined process described herein.

[0008] Figure 2This is a diagram illustrating an exemplary embodiment of the pseudo-gate formation process described herein.

[0009] Figure 3 This is a diagram of an exemplary implementation of the source / drain trench formation process described herein.

[0010] Figure 4A and Figure 4B This is a diagram of an exemplary embodiment of the internal spacer forming process described herein.

[0011] Figure 5 This is a diagram of an exemplary implementation of the source / drain region formation process described herein.

[0012] Figure 6 This is a diagram of an exemplary embodiment of the interlayer dielectric (ILD) formation process described herein.

[0013] Figure 7 This is a diagram of an exemplary embodiment of the active region isolation structure formation process described herein.

[0014] Figure 8 This is a diagram of an exemplary embodiment of the Replacement Gate (RPG) process described herein.

[0015] Figures 9A to 9D This is a diagram illustrating an exemplary implementation of the source / drain dicing process described herein.

[0016] Figures 10A to 10F This is a diagram illustrating an exemplary embodiment of the metal silicide layer formation process described herein.

[0017] Figures 11A to 11C This is a diagram illustrating an exemplary embodiment of the metal silicide layer formation process described herein.

[0018] Figures 12A to 12C This is a diagram illustrating an exemplary embodiment of the metal silicide layer formation process described herein.

[0019] Figure 13 This is a diagram of an exemplary embodiment of the dicing metal gate process described herein.

[0020] Figures 14A to 14D This is a diagram of an exemplary embodiment of the source / drain contact formation process described herein.

[0021] Figure 15 This is a diagram illustrating an exemplary embodiment of the semiconductor device described herein.

[0022] Figure 16 This is a diagram illustrating an exemplary embodiment of the semiconductor device described herein.

[0023] Figure 17This is a diagram illustrating an exemplary embodiment of the semiconductor device described herein.

[0024] Figure 18 This is a flowchart of an exemplary process related to forming the semiconductor device described herein.

[0025] Figure 19 This is a flowchart of an exemplary process related to forming the semiconductor device described herein. Detailed Implementation

[0026] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify embodiments of this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component on or over a second component may include embodiments where the first and second components are in direct contact, and may also include embodiments where an additional component may be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or characters may be repeated in various instances of embodiments of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0027] Furthermore, for ease of description, this document uses spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” to describe the relationship between one element or component and another (or other elements or components) as shown in the figures. In addition to the orientations depicted in the figures, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0028] Nanostructured transistors (e.g., nanowire transistors, nanosheet transistors, gate-all-around (GAA) transistors, multi-bridge channel transistors, nanoribbon transistors, and / or other types of nanostructured transistors) can overcome one or more of the aforementioned drawbacks of some types of transistors. However, nanostructured transistors face manufacturing challenges that can cause performance problems, manufacturing yield issues, and / or device failures.

[0029] For example, as component size decreases, different parts of a nanostructured transistor may become susceptible to increased resistance. One such part of a nanostructured transistor susceptible to increased resistance is the connection between the source / drain regions and the source / drain contacts formed on those regions. As the size (e.g., lateral width) of the source / drain contacts decreases, they may not completely cover the entire surface of the associated source / drain region, creating a reduced contact surface area between the source / drain region and the associated source / drain contact. A metal silicide layer may be included between the source / drain region and the source / drain contact to achieve lower contact resistance between them. However, if the metal silicide layer is formed in a recess defined for the source / drain contact, it may also not completely cover the entire surface of the source / drain region, thus limiting the reduction in contact resistance provided by the metal silicide layer.

[0030] In some embodiments described herein, a metal silicide layer is formed on the source / drain regions of a transistor (e.g., a nanostructure transistor and / or another type of transistor) of a semiconductor device prior to the formation of the groove in which the source / drain contacts will be formed. This allows the coverage of the metal silicide layer on the surface of the source / drain regions to be defined independently of the coverage of the source / drain contacts (which are defined by the groove in which the source / drain contacts are formed).

[0031] A process of dicing the source / drain regions can be performed to form dielectric walls covered by a metal silicide layer on the surface defining the source / drain regions. The metal silicide layer can be formed such that it substantially covers the entire surface of the source / drain regions between the dielectric walls, achieving near-complete coverage of the surface of the source / drain regions exposed between the dielectric walls. A metal capping layer can be formed on (and can substantially completely cover) the metal silicide layer. A groove for source / drain contacts can then be formed to expose at least a portion of the metal capping layer, such that the source / drain contacts are formed in the groove on at least a portion of the metal capping layer. In this way, if the groove is formed above a surface smaller than the entire source / drain region, the metal capping layer and the metal silicide layer provide an electrical connection between the source / drain contacts and the surface of the source / drain regions, thereby enabling low contact resistance for the connection between the source / drain contacts and the source / drain regions. This also enables improved contact isolation between adjacent source / drain contacts, while promoting contact polysilicon pitch (CPP) scaling and achieving low contact resistance for source / drain contacts.

[0032] Figures 1A to 1CThis is a diagram of an exemplary embodiment 100 of the fin-defined process described herein. Exemplary embodiment 100 includes examples of forming fin structures and associated shallow trench isolation (STI) regions for a semiconductor device 105 described herein. Semiconductor device 105 may be fabricated to include one or more transistors. The one or more transistors may include nanostructured transistors, such as nanowire transistors, nanosheet transistors, gate-all-around (GAA) transistors, multi-bridge channel transistors, nanoribbon transistors, and / or other types of nanostructured transistors. Exemplary embodiment 100 includes examples of forming fin structures and associated STI regions for transistors in semiconductor device 105.

[0033] Figures 1A to 1C Each shows a perspective view of semiconductor device 105 and a cross-sectional view along line AA in the perspective view. For example... Figure 1A As shown, the semiconductor device 105 is processed in conjunction with the semiconductor substrate 110. The semiconductor substrate 110 includes a silicon (Si) substrate, a substrate formed of a material including silicon, a III-V compound semiconductor material substrate such as gallium arsenide (GaAs), a silicon-on-insulator (SOI) substrate, a germanium (Ge) substrate, a silicon-germanium (SiGe) substrate, a silicon carbide (SiC) substrate, or another type of semiconductor substrate.

[0034] A layer stack 115 is formed on a semiconductor substrate 110. The layer stack 115 may be referred to as a superlattice. The layer stack 115 includes a plurality of alternating layers arranged in a direction generally perpendicular to the semiconductor substrate 110 (e.g., the z-direction). For example, the layer stack 115 includes vertically alternating layers of sacrificial nanostructure layer 120 and nanostructure channel layer 125 on the semiconductor substrate 110. Figure 1A The number of sacrificial nanostructure layers 120 and nanostructure channel layers 125 shown are examples, and other numbers of sacrificial nanostructure layers 120 and nanostructure channel layers 125 are within the scope of embodiments of this disclosure.

[0035] The sacrificial nanostructure layer 120 enables the definition of a vertical distance between adjacent nanostructure channels formed by the nanostructure channel layer 125 and serves as a placeholder layer for the subsequently formed gate structure of a transistor for the semiconductor device 105, the subsequently formed gate structure being formed around the nanostructure channels. The sacrificial nanostructure layer 120 comprises a first material composition, and the nanostructure channel layer 125 comprises a second material composition. In some embodiments, the first and second material compositions are the same. In some embodiments, the first and second material compositions are different. As an example, the sacrificial nanostructure layer 120 may comprise silicon germanium (SiGe), and the nanostructure channel layer 125 may comprise silicon (Si). This enables the selective etching of the sacrificial nanostructure layer 120 and / or the nanostructure channel layer 125 (e.g., enabling the etching of the sacrificial nanostructure layer 120 without etching the nanostructure channel layer 125, and vice versa), depending on the type of etchant used.

[0036] One or more types of deposition tools can be used to deposit and / or grow alternating layers of the layer stack 115 to include nanostructures (e.g., nanosheets) on the semiconductor substrate 110. For example, deposition tools can be used to grow the sacrificial nanostructure layer 120 and / or the nanostructure channel layer 125 via epitaxial growth, which can include epitaxial techniques such as molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD) processes, and / or another suitable epitaxial technique. Additionally and / or alternatively, the sacrificial nanostructure layer 120 and / or the nanostructure channel layer 125 can be deposited by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), and / or another suitable deposition technique.

[0037] One or more masking layers may be formed on the layer stack 115 (e.g., using one or more deposition tools). The masking layers may include a hard mask (HM) layer 130, a capping layer 135, an oxide layer 140, and / or a nitride layer 145. The masking layers may be used to perform fin patterning operations to form fin structures in the semiconductor substrate 110.

[0038] like Figure 1BAs shown, the layer stack 115 and semiconductor substrate 110 are etched to remove portions of the layer stack 115 and semiconductor substrate 110. This allows the formation of a fin structure 150 extending over the semiconductor substrate 110. The fin structure 150 may extend in the x-direction within the semiconductor device 105 and may be arranged in the y-direction within the semiconductor device 105. The fin structure 150 includes a portion 155 of the layer stack 115 located above and / or on a fin portion 160 above the semiconductor substrate 110. The fin structure 150 may be formed by patterning one or more masking layers and etching the semiconductor substrate 110 based on the pattern formed in one or more of the masking layers. The one or more masking layers may be patterned using photolithography techniques, including dual patterning or multiple patterning techniques. Etching tools may be used to etch the semiconductor substrate 110 based on the pattern using dry etching techniques (e.g., reactive ion etching), wet etching techniques, and / or combinations thereof.

[0039] like Figure 1B As further shown, for different types of nanostructure transistors, some fin structures 150 can be formed with different widths. As an example, a first subset of fin structures 150a can be formed for p-type nanostructure transistors (e.g., p-type metal-oxide-semiconductor (PMOS) nanostructure transistors), and a second subset of fin structures 150b can be formed for n-type nanostructure transistors (e.g., n-type metal-oxide-semiconductor (NMOS) nanostructure transistors). As another example, a first subset of fin structures 150a can be formed for nanostructure transistors configured to operate at lower voltages, and a second subset of fin structures 150b can be formed for nanostructure transistors configured to operate at higher voltages.

[0040] like Figure 1C As shown, a pad 165 and an STI region 170 are formed between adjacent fin portions 160 of the fin structure 150. Optionally, in some embodiments, the pad 165 may be omitted. In embodiments that include the pad 165, the pad 165 may comprise a dielectric material, such as silicon oxide (SiO2). x ), silicon nitride (Si x N y STI regions 170 may each include a dielectric material such as silicon oxynitride (SiON), fluorine-doped silicate glass (FSG), a low-k dielectric material, and / or another suitable insulating material. x ), silicon nitride (Si x N y ), silicon oxynitride (SiON), fluorine-doped silicate glass (FSG), low-k dielectric material and / or another suitable insulating material.

[0041] A conformal deposition liner can be deposited using a deposition tool (e.g., using ALD or another conformal deposition technique), and a dielectric layer can be deposited on the liner 165 (e.g., using CVD, PVD, ALD, and / or another suitable deposition technique), such that the dielectric layer completely fills the gaps between the fin structures 150 and extends above the top of the fin structures 150. A planarization tool can then be used to perform a planarization or polishing operation (e.g., a chemical mechanical planarization (CMP) operation) to planarize the dielectric layer, such that the top surface of the dielectric layer is substantially coplanar with the top surface of the nitride layer 145. The nitride layer 145 serves as a CMP stop layer in the planarization operation. An etching tool can then be used to etch the dielectric layer to form the STI region 170, such that the top surface of the STI region 170 is substantially coplanar with or below the bottommost sacrificial nanostructure layer 120.

[0042] As pointed out above, Figures 1A to 1C It is provided as an instance. Other instances can be related to... Figures 1A to 1C The descriptions are different.

[0043] Figure 2 This is a diagram of an exemplary embodiment 200 of the dummy gate formation process described herein. Exemplary embodiment 200 includes an example of forming a dummy gate structure 205 for a nanostructured transistor in a semiconductor device 105. In some embodiments, the operations described in conjunction with exemplary embodiment 200 are combined with... Figures 1A to 1C The described process is then implemented.

[0044] Figure 2 A perspective view of a semiconductor device 105 having a dummy gate structure 205 formed thereon is shown. The dummy gate structure 205 (also referred to as a dummy gate stack or temporary gate structure) is formed over a portion of the fin structure 150 and a portion of the STI region 170. The dummy gate structure 205 extends in the y-direction and is arranged in the x-direction such that the dummy gate structure 205 is substantially perpendicular to the fin structure 150. The dummy gate structure 205 is a sacrificial structure that will be replaced by a replacement gate structure or a replacement gate stack in subsequent processing stages for the semiconductor device 105. The dummy gate structure 205 can also be used to define a source / drain (S / D) groove in which the source / drain regions of nanostructured transistors are formed in the fin structure 150.

[0045] The dummy gate structure 205 may include a gate electrode layer 210, a hard mask layer 215 above and / or on the gate electrode layer 210, a spacer layer 220 on the opposite side of the gate electrode layer 210, and a gate dielectric layer 225 below the gate electrode layer 210. The gate electrode layer 210 includes polysilicon (polysilicon or PO) or another material. The hard mask layer 215 includes one or more layers, such as an oxide layer (e.g., a pad oxide layer that may include silicon dioxide (SiO2) or another material) and a nitride layer formed above the oxide layer (e.g., a pad nitride layer that may include silicon nitride such as Si3N4 or another material). The spacer layer 220 includes silicon oxycarbide (SiOC), nitrogen-free SiOC, or another suitable material. The gate dielectric layer 225 may include silicon oxide (e.g., SiO2 such as SiO2). x ), silicon nitride (e.g., Si3N4, etc.) x N y ), high dielectric constant (high k) dielectric materials (e.g., dielectric materials having a dielectric constant greater than approximately 3.9) and / or another suitable material.

[0046] The layer of the dummy gate structure 205 can be formed using various semiconductor processing techniques, such as depositing the layer of the dummy gate structure 205, patterning the layer of the dummy gate structure 205 to define the dummy gate structure 205, and / or other semiconductor processing techniques.

[0047] Figure 2 Reference cross sections used in the following figures described herein are also shown. Cross section AA lies in the xz plane (referred to as the y-cut) across the fin structure 150 in the source / drain region of semiconductor device 105. Cross section BB lies in the yz plane (referred to as the x-cut) perpendicular to cross section AA and across the dummy gate structure 205 and along the underlying fin structure 150. Cross section CC lies in the xz plane parallel to cross section AA and perpendicular to cross section BB, and along the dummy gate structure 205. For clarity, the following figures refer to these reference cross sections. In some figures, reference numerals for components or parts shown may be omitted for ease of depiction to avoid obscuring other components or parts.

[0048] As pointed out above, Figure 2 It is provided as an instance. Other instances can be related to... Figure 2 The descriptions are different.

[0049] Figure 3 This is a diagram of an exemplary embodiment 300 of the source / drain trench formation process described herein. Exemplary embodiment 300 includes an example of a source / drain trench 305 forming a source / drain region for a nanostructure transistor in a semiconductor device 105. Figure 3 From Figure 2 The multiple perspectives shown include Figure 2 The perspective of the cross-sectional plane AA in the middle Figure 2 The viewpoint of the cross-sectional plane BB in the middle and Figure 2 The viewpoint of the cross-sectional plane CC in the diagram. In some embodiments, the operations described in conjunction with exemplary embodiment 300 are combined with... Figures 1A to 2 The described process is then implemented.

[0050] like Figure 3 As shown in cross-sectional planes AA and BB, during the etching operation, the source / drain recess 305 is formed as a portion 155 extending through the fin structure 150. The source / drain recess 305 is formed on the opposite side of the dummy gate structure 205. The etching operation can be performed using an etching tool and can be referred to as a strained source / drain (SSD) etching operation. In some embodiments, the etching operation includes the use of plasma etching techniques, wet chemical etching techniques, and / or another type of etching technique.

[0051] The source / drain recesses 305 also extend into a portion of the fin portion 160 of the fin structure 150. This causes the protrusions 310 to form the fin structure 150. The sidewall of the portion of each source / drain recess 305 located below the stack 115 corresponds to the sidewall of the protrusion 310. The protrusion 310 (also referred to as a base) refers to the region of the fin portion 160 of the fin structure 150 on which a nanostructured channel is defined by a nanostructured channel layer 125. The nanostructured channel 315 extends between adjacent source / drain recesses 305.

[0052] The nanostructured channel 315 includes a silicon-based nanostructure (e.g., nanosheets or nanowires, and other examples) that serves as the semiconductor channel for a nanostructured transistor in the semiconductor device 105. In some embodiments, the nanostructured channel 315 may include silicon germanium (SiGe) or another silicon-based material. The nanostructured channel 315 is arranged in a direction generally perpendicular to the semiconductor substrate 110 (e.g., the z-direction). In other words, the nanostructured channel 315 is arranged perpendicularly or stacked on the semiconductor substrate 110.

[0053] As pointed out above, Figure 3 It is provided as an instance. Other instances can be related to... Figure 3 The descriptions are different.

[0054] Figure 4A and Figure 4B This is a figure of an exemplary embodiment 400 of the internal spacer formation process described herein. Exemplary embodiment 400 includes an example of forming internal spacers between the ends of a nanostructured channel 315 exposed in a source / drain recess 305. Figure 4A and Figure 4B Each is from Figure 2 The multiple perspectives shown include Figure 2 The perspective of the cross-sectional plane AA in the middle Figure 2 The viewpoint of the cross-sectional plane BB in the middle and Figure 2 The viewpoint of the cross-sectional plane CC in the diagram. In some embodiments, the operations described in conjunction with exemplary embodiment 400 are combined with... Figures 1A to 3 The described process is then implemented.

[0055] like Figure 4A As shown in the cross-sectional plane BB, during the etching operation, the ends of the sacrificial nanostructure layer 120 exposed in the source / drain trench 305 are etched laterally (e.g., in the y-direction generally parallel to the length of the sacrificial nanostructure layer 120), thereby forming a cavity 405 between the ends of the sacrificial nanostructure layer 120 exposed in the source / drain trench 305. Specifically, an etching tool can be used to laterally etch the ends of the sacrificial nanostructure layer 120 beneath the dummy gate structure 205 through the source / drain trench 305 to form a cavity 405 between the ends of the nanostructure channel 315. The cavity 405 can be formed in a generally curved shape, a generally concave shape, a generally triangular shape, a generally square shape, or another shape.

[0056] like Figure 4B As shown in cross-sectional planes AA and BB, an internal spacer (InSP) 410 is formed in a cavity 405 between the ends of vertically adjacent nanostructure channels 315 in the source / drain recess 305. The internal spacer 410 is included to reduce parasitic capacitance in the nanostructure transistor and to protect the source / drain regions (which are subsequently formed in the source / drain recess 305) from etching during nanosheet release operations to remove the sacrificial nanostructure layer 120 between the nanostructure channels 315. The internal spacer 410 comprises silicon nitride (Si). x N y ), silicon dioxide (SiO) x ), silicon oxynitride (SiON), silicon oxycarbonate (SiOC), silicon carbonitride (SiCN), silicon carbonitride (SiOCN) and / or another dielectric material.

[0057] To form the internal spacer 410, a dielectric material layer can be deposited in the cavity 405 and along the sidewalls and bottom surface of the source / drain recesses using a deposition tool. CVD, PVD, ALD, and / or another deposition technique can be used to deposit the dielectric material layer. An etching tool is then used to remove excess material from the source / drain recesses, leaving the remaining portion corresponding to the internal spacer 410 in the cavity 405. In some embodiments, the etching operation may cause the surface of the internal spacer 410 facing the source / drain recesses 305 to bend or recess. In some embodiments, the surface of the internal spacer 410 facing the source / drain recesses 305 is generally flat, resulting in a generally flat and flush surface between the surface of the internal spacer 410 and the end surface of the nanostructured channel 315.

[0058] As pointed out above, Figure 4A and Figure 4B It is provided as an instance. Other instances can be related to... Figure 4A and Figure 4B The descriptions are different.

[0059] Figure 5 This is a diagram of an exemplary embodiment 500 of the source / drain region formation process described herein. Exemplary embodiment 500 includes an example of forming the source / drain regions of a nanostructured transistor of semiconductor device 105. Figure 5 From Figure 2 The multiple perspectives shown include Figure 2 The perspective of the cross-sectional plane AA in the middle Figure 2 The viewpoint of the cross-sectional plane BB in the middle and Figure 2 The viewpoint of the cross-sectional plane CC in the diagram. In some embodiments, the operations described in conjunction with exemplary embodiment 500 are combined with... Figures 1A to 4B The described process is then implemented.

[0060] like Figure 5 As shown in cross-sectional planes AA and BB, the source / drain recess 305 is filled with one or more layers to form a source / drain region within the source / drain recess 305. For example, a deposition tool can be used to deposit a buffer region 505 at the bottom of the source / drain recess 305, and the deposition tool can deposit a source / drain region 510 on the buffer region 505 in the source / drain recess 305. In some embodiments, a deposition tool is used to deposit a capping layer 515 on the source / drain region 510 in the source / drain recess 305.

[0061] Buffer region 505 may include silicon (Si), silicon doped with boron (SiB), or another dopant, and / or another material. Buffer region 505 may be located between source / drain region 510 and adjacent protrusion 310 to reduce, minimize, and / or prevent dopant migration and / or current leakage from source / drain region 510 to adjacent protrusion 310, which could otherwise cause short-channel effects in semiconductor device 105. Therefore, buffer region 505 can improve the performance and / or yield of semiconductor device 105.

[0062] The source / drain region 510 may refer to either the source or the drain, individually or collectively, depending on the context. The source / drain regions 510 may be included on opposite sides of the dummy gate structure 205, such that a nanostructured channel 315 beneath the dummy gate structure 205 extends between and is electrically coupled to the source / drain regions 510. Each source / drain region 510 includes silicon (Si) with one or more dopants, such as p-type materials (e.g., boron (B) or germanium (Ge) and other examples), n-type materials (e.g., phosphorus (P) or arsenic (As) and other examples), and / or another type of dopant. Therefore, the semiconductor device 105 may include: a p-type metal-oxide-semiconductor (PMOS) nanostructured transistor including p-type source / drain regions 510, an n-type metal-oxide-semiconductor (NMOS) nanostructured transistor including n-type source / drain regions 510, and / or other types of nanostructured transistors.

[0063] One or more layers of the source / drain region 510 can be epitaxially grown, deposited (e.g., using CVD, PVD, ALD), and / or formed using one or more other deposition techniques. For example, a deposition tool can epitaxially grow a first layer (referred to as L1) of the source / drain region 510 over an associated buffer region 505 (which may be referred to as L0), and a second layer (referred to as L2, L2-1, and / or L2-2) of the source / drain region 510 can be epitaxially grown over the first layer. The first layer may include lightly doped silicon (e.g., doped with boron (B), phosphorus (P), and / or another dopant) and may include a shielding layer to reduce short-channel effects in the semiconductor device 105 and to reduce dopant extrusion or migration into the nanostructure channel 315. The second layer may include heavily doped silicon or heavily doped silicon-germanium. A second layer may be included to provide compressive stress in the source / drain region 510 to reduce boron loss.

[0064] The capping layer 515 may include silicon, silicon-germanium, doped silicon, doped silicon-germanium, and / or another material. The capping layer 515 may be included prior to contact formation to reduce dopant diffusion during semiconductor processing operations for the semiconductor device 105 and to protect the underlying source / drain regions 510. Furthermore, the capping layer 515 may facilitate the formation of a metal-semiconductor (e.g., silicide) alloy.

[0065] As pointed out above, Figure 5 It is provided as an instance. Other instances can be related to... Figure 5 The descriptions are different.

[0066] Figure 6 This is a figure of an exemplary embodiment 600 of the interlayer dielectric (ILD) formation process described herein. Figure 6 From Figure 2 The multiple perspectives shown include Figure 2 The perspective of the cross-sectional plane AA in the middle Figure 2 The viewpoint of the cross-sectional plane BB in the middle and Figure 2 The viewpoint of the cross-sectional plane CC in the diagram. In some embodiments, the operations described in conjunction with exemplary embodiment 600 are combined with... Figures 1A to 5 The described process is then implemented.

[0067] like Figure 6 As shown in cross-sectional planes AA and BB, a dielectric layer 605 is formed above the source / drain region 510. The dielectric layer 605 (which may be referred to as an ILD layer or ILD zero (ILD0 layer)) fills the region between the dummy gate structures 205. The dielectric layer 605 is formed to reduce the likelihood of damage to the source / drain region 510 during a replacement gate process that replaces the dummy gate structure 205 and / or to prevent damage to the source / drain region 510 during a replacement gate process that replaces the dummy gate structure 205.

[0068] In some implementations, a contact etch stop layer (CESL) is conformally deposited (e.g., by a deposition tool) over the source / drain region 510 prior to the formation of the dielectric layer 605. Optionally, the capping layer 515 may be the CESL. The dielectric layer 605 is then formed on the CESL. The CESL provides a mechanism to stop the etch process when forming contacts or vias for the source / drain region 510. The CESL may be formed of a dielectric material with a different etch selectivity relative to adjacent layers or components. The CESL may include or may be a nitrogen-containing material, a silicon-containing material, and / or a carbon-containing material. Furthermore, the CESL may include or may be silicon nitride (Si). x N ySilicon carbonitride (SiCN), carbon nitride (CN), silicon oxynitride (SiON), silicon carbon oxynitride (SiCO), or combinations thereof, and other examples. CESL can be deposited using deposition processes such as ALD, CVD, or another deposition technique.

[0069] like Figure 6 As further shown, in some embodiments, a dielectric layer 610 may be formed over and / or on the dielectric layer 605. Optionally, the dielectric layer 610 may be omitted. The dielectric layer 610 may be a dielectric layer formed on top of the ILD0 layer and may include one or more dielectric materials, such as silicon nitride (Si). x N y Silicon carbonitride (SiCN), carbon nitride (CN), silicon oxynitride (SiON), silicon oxycarbonate (SiOC), or combinations thereof, and other examples. The dielectric layer 610 can be deposited using deposition processes such as ALD, CVD, or another deposition technique.

[0070] In some embodiments, the dielectric layer 610 is deposited such that the dielectric layer 610 contacts the top of the source / drain region 510. In some embodiments, the dielectric layer 610 is merged with a capping layer 515 on the source / drain region 510.

[0071] As pointed out above, Figure 6 It is provided as an instance. Other instances can be related to... Figure 6 The descriptions are different.

[0072] Figure 7 This is a figure of an exemplary embodiment 700 of the active region isolation structure formation process described herein. Figure 7 This is a perspective view of semiconductor device 105. In some embodiments, the operations described in conjunction with exemplary embodiment 700 are combined with... Figures 1A to 6 The described operations will be implemented later.

[0073] Exemplary implementation 700 includes a replacement gate process (which combines) replacing the dummy gate structure 205 with a replacement gate structure (e.g., a metal gate structure) of the semiconductor device 105. Figure 8 Prior to the description, an example of forming an active region isolation structure (e.g., a diced polysilicon (CPODE) structure on an oxide diffusion edge) in semiconductor device 105. Therefore, exemplary embodiment 700 may be referred to as a front-end process (FEOL) CPODE process. The active region isolation structure may be formed along dummy gate structure 205 to create an electrically isolated region extending across one or more stacks of nanostructured channels 315 beneath dummy gate structure 205.

[0074] To form an active region isolation structure, a pattern can be formed in the dielectric layer 610 above the dummy gate structure 205 and the vertical stack of the underlying sacrificial nanostructure layer 120 and nanostructure channel 315. The pattern can be used to etch the dummy gate structure 205 and the vertical stack of the sacrificial nanostructure layer 120 and nanostructure channel 315, and to etch into the underlying fin portion 160 to form an active region isolation recess (e.g., a CPODE recess). In some embodiments, multiple vertical stacks of the sacrificial nanostructure layer 120 and nanostructure channel 315 below the dummy gate structure 205 can be removed to form an active region isolation recess (and therefore an active region isolation structure), such that the active region isolation recess (and therefore the active region isolation structure) is formed to span multiple fin portions 160 in the y-direction.

[0075] In some embodiments, the dielectric layer 610 is etched using a pattern in the photoresist layer to form a pattern. In these embodiments, a deposition tool can be used to form the photoresist layer on the dielectric layer 610 (e.g., using spin coating and / or another suitable deposition technique). An exposure tool can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A developing tool can be used to develop and remove portions of the photoresist layer to expose the pattern. An etching tool can be used to etch the dielectric layer 610 based on the pattern to transfer the pattern to the dielectric layer 610. In some embodiments, the etching operation includes dry etching operations (e.g., plasma-based etching operations, gas-based etching operations), wet chemical etching operations, and / or another type of etching operation. In some embodiments, a photoresist removal tool can be used to remove the remaining portions of the photoresist layer (e.g., using chemical strippers, plasma ashing, and / or another technique).

[0076] In some implementations, the dummy gate structure 205, the sacrificial nanostructure layer 120, and the nanostructure channel 315 can be removed in multiple etch operations to form an active region isolation recess. For example, a first etch operation can be performed to etch and remove the dummy gate structure 205. The first etch operation can stop on top of the vertical stack of the sacrificial nanostructure layer 120 and the nanostructure channel 315. A second etch operation can be performed to etch and remove the vertical stack of the sacrificial nanostructure layer 120 and the nanostructure channel 315. The second etch operation can extend into the underlying fin portion 160. Additionally and / or alternatively, the second etch operation can be non-selective, as the STI region 170 between the fin portions 160 in the y-direction can also be removed.

[0077] like Figure 7As shown, an active region isolation structure 705 can be formed (e.g., in an active region isolation recess) such that the active region isolation structure 705 extends across (and into) a plurality of fin portions 160 in the y-direction. In some embodiments, a dielectric pad 710 can be formed on the sidewalls and bottom surface of the active region isolation recess. The dielectric pad 710 may include a dielectric material, such as silicon oxide (e.g., SiO2). x ), silicon nitride (such as Si3N4) x N y The dielectric substrate 710 can be deposited using deposition tools employing PVD, ALD, CVD, oxidation, and / or another suitable deposition technique.

[0078] An active region isolation structure 705 can be formed on a dielectric pad 710 within an active region isolation recess. The active region isolation structure 705 can be deposited using deposition tools employing PVD, ALD, CVD, oxidation, and / or another suitable deposition technique. The active region isolation structure 705 may include a dielectric material such as silicon oxide (e.g., SiO2). x ), silicon nitride (such as Si3N4) x N y ), silicon oxynitride (SiON), fluorine-doped silicate glass (FSG), high-k dielectric material and / or another suitable dielectric material.

[0079] The active region isolation trench can be overfilled with the material of the active region isolation structure 705 to ensure that the active region isolation trench completely fills the material of the active region isolation structure 705 and to minimize the formation of gaps or voids in the active region isolation structure 705. Therefore, after the active region isolation trench fills the active region isolation structure 705, a planarization operation can be performed to planarize the semiconductor device 105. A planarization tool can be used to perform a CMP operation and / or another type of planarization operation, so that the top of the active region isolation structure 705 and the top of the dielectric layer 610 are substantially coplanar.

[0080] As pointed out above, Figure 7 It is provided as an instance. Other instances can be related to... Figure 7 The descriptions are different.

[0081] Figure 8 This is a figure of an exemplary embodiment 800 of the replacement gate (RPG) process described herein. Figure 8This is a perspective view of semiconductor device 105. Exemplary embodiment 800 includes an example of a replacement gate process for replacing the dummy gate structure 205 with a high-k / metal gate structure (e.g., a replacement gate structure) for a nanostructured transistor of semiconductor device 105. In some embodiments, the operations described in conjunction with exemplary embodiment 800 are combined with... Figures 1A to 7 The described operations will be implemented later.

[0082] The gate replacement process may include a dummy gate removal operation. The dummy gate removal operation includes removing the dummy gate structure 205 from the semiconductor device 105. Removal of the dummy gate structure 205 leaves an opening (or groove) between the dielectric layers 605 and provides access to the underlying sacrificial nanostructure layer 120. The dummy gate structure 205 may be removed in one or more etching operations. Such etching operations may include plasma etching techniques, wet chemical etching techniques, and / or another type of etching technique.

[0083] The gate replacement process may include a nanostructure release operation (e.g., a SiGe release operation). A nanostructure release operation is performed to remove the sacrificial nanostructure layer 120 (e.g., a silicon-germanium layer). This creates openings between the nanostructure channels 315 (e.g., regions around the nanostructure channels 315). The sacrificial nanostructure layer 120 can be removed through the spacers previously occupied by the dummy gate structure 205. The nanostructure release operation may include using an etching tool to perform an etching operation to remove the sacrificial nanostructure layer 120 based on the differences in etch selectivity between the materials of the sacrificial nanostructure layer 120 and the nanostructure channel 315, and between the materials of the sacrificial nanostructure layer 120 and the internal spacer 410. The internal spacer 410 may be used as an etch stop layer in the etching operation to protect the source / drain regions 510 from etching.

[0084] like Figure 8As shown, the gate replacement operation includes forming a gate structure (e.g., a replacement gate structure) 805 in the openings between the source / drain regions 510 and between the internal spacers 410. Specifically, the gate structure 805 fills the regions previously occupied by the sacrificial nanostructure layer 120 between and around the nanostructure channels 315, such that the gate structure 805 completely encloses and surrounds the nanostructure channels 315. This increases the control of the nanostructure channels 315, increases the drive current of the nanostructure transistors of the semiconductor device 105, and / or reduces the short-channel effect (SCE) of the nanostructure transistors for the semiconductor device 105, and other examples. The gate structure 805 may also fill the gaps previously occupied by the dummy gate structure 205. Portions of the gate structure 805 are formed in an alternating vertical arrangement between pairs of nanostructure channels 315. In other words, the semiconductor device 105 includes one or more vertically stacked portions of alternating nanostructure channels 315 and gate structures 805, such as... Figure 8 As shown in the image.

[0085] Each gate structure 805 may include a gate dielectric layer 810 and a metal gate electrode 815. The gate dielectric layer 810 may be a conformal layer, conformally deposited (e.g., by ALD or CVD and other examples) onto the nanostructured channel 315 and the sidewalls of the internal spacer 410 prior to the formation of the gate electrode 815. In some embodiments, the gate structure 805 may be planarized using a planarization tool after the gate structure has been formed.

[0086] The gate dielectric layer 810 may include one or more high-k dielectric materials, such as silicon nitride (Si). x N y ), Hafnium oxide (HfO) x ), Lanthanum oxide (LaO) x The gate electrode 815 may include one or more metallic materials, such as tungsten (W), cobalt (Co), ruthenium (Ru), and / or titanium (Ti), and other examples. Additionally and / or optionally, each gate structure 805 may include one or more work function metal layers for adjusting the work function of the metal gate electrode 815. Each gate structure 805 may include additional layers, such as interface layers, adhesive layers, and / or capping layers, and other examples.

[0087] As pointed out above, Figure 8 It is provided as an instance. Other instances can be related to... Figure 8 The descriptions are different.

[0088] Figures 9A to 9D This is a figure of an exemplary implementation 900 of the source / drain dicing process described herein. Figures 9A to 9DThis is a perspective view of semiconductor device 105. An example of the source / drain dicing process of exemplary embodiment 900 includes an instance of laterally forming a source / drain isolation structure between adjacent source / drain regions 510 in the y-direction. The source / drain isolation structure provides a well-defined opening where a metal silicide layer can be formed on top of the source / drain region 510, such that the metal silicide layer completely covers the top of the source / drain region 510 (which might be difficult to achieve if the metal silicide layer were otherwise formed in a source / drain contact groove defined during a source / drain contact groove process). In some embodiments, the operations described in conjunction with exemplary embodiment 900 are combined with... Figures 1A to 8 The described operations will be implemented later.

[0089] like Figure 9A As shown, a hard mask layer 905 may be formed over and / or on the dielectric layer 610, over and / or on the top of the active region isolation structure 705, and over and / or on the top of the gate structure 805. The hard mask layer 905 may include silicon nitride (Si). x N y ), silicon dioxide (SiO) x The hard mask layer 905 and the dielectric layer 610 may be formed of the same material. In some embodiments, the hard mask layer 905 and the dielectric layer 610 may be formed of different materials. Deposition tools may be used to deposit the material of the hard mask layer 905 using PVD, ALD, CVD, epitaxial, oxidation, and / or another suitable deposition technique. In some embodiments, after depositing the hard mask layer 905, a planarization operation (e.g., CMP) may be performed to planarize the hard mask layer 905.

[0090] like Figure 9A As further shown, a pattern 910 can be formed in the hard mask layer 905. The pattern 910 may include openings through the hard mask layer 905. The openings may extend in the x-direction across the dielectric layer 610, across one or more active region isolation structures 705, and / or across one or more gate structures 805. Therefore, portions of the dielectric layer 610, portions of the one or more active region isolation structures 705, and / or portions of one or more gate structures 805 may be exposed through the openings in the pattern 910 in the hard mask layer 905.

[0091] In some embodiments, a pattern in the photoresist layer is used to etch the hard mask layer 905 to form a pattern 910. In these embodiments, a deposition tool can be used to form the photoresist layer on the hard mask layer 905 (e.g., using spin coating and / or another suitable deposition technique). An exposure tool can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A developing tool can be used to develop and remove portions of the photoresist layer to expose the pattern. An etching tool can be used to etch the hard mask layer 905 based on the pattern to form the pattern 910. In some embodiments, the etching operation includes dry etching (e.g., plasma-based etching, gas-based etching), wet chemical etching, and / or another type of etching operation. In some embodiments, a photoresist removal tool can be used to remove the remaining portions of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or another technique).

[0092] like Figure 9B As shown, a capping layer 915 may be formed on top of the portion of the gate structure 805 exposed through an opening in the pattern 910 in the hard mask layer 905. The capping layer 915 may be included to protect the gate structure 805 during subsequent etching operations (e.g., combined with...). Figure 9C The described source / drain region etching operation is protected from etching and / or damage. Optionally, the capping layer 915 can be omitted. For example, if the pattern 910 is not formed on the gate structure 805, but only on the area to be diced, the capping layer 915 can be omitted. Deposition tools can be used to deposit the material of the capping layer 915 using CVD, ALD, PVD, and / or another suitable deposition technique.

[0093] In some embodiments, the capping layer 915 may include silicon nitride (Si). x N y ), silicon dioxide (SiO) x The capping layer 915 may comprise silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), silicon carbonitride (SiOCN), and / or another suitable dielectric material. In some embodiments, the capping layer 915 may comprise a metallic material such as titanium (Ti), tungsten (W), and / or ruthenium (Ru), and other examples. In some embodiments, the capping layer 915 may comprise another material such as tantalum nitride (TaN) and / or titanium nitride (TiN), and other examples.

[0094] In some embodiments, the capping layer 915 is selectively formed or grown on top of the portion of the gate structure 805 exposed through an opening in the pattern 910 in the hard mask layer 905. In other words, the capping layer 915 is selectively formed or grown on the gate structure 805, while little or no material of the capping layer 915 is grown or deposited on other layers and / or structures (such as dielectric layer 610 and / or active region isolation structure 705) exposed through the opening in the pattern 910 in the hard mask layer 905.

[0095] To achieve selective deposition of the capping layer 915 material on the gate structure 805, the precursors and reactants of the capping layer 915 material can be selected to achieve a reaction on the metal material of the gate structure 805, such that the precursors and reactants react to deposit the capping layer 915 material only on the metal material of the gate structure 805. Additionally and / or optionally, the exposed surfaces of the gate structure 805 can be first treated with a surface modifier (e.g., a self-assembled monolayer) that promotes adhesion of the capping layer 915 material. Additionally and / or optionally, the exposed surfaces of the dielectric layer 610 can be first treated with a surface modifier (e.g., a chemical reagent) that inhibits adhesion of the capping layer 915 material to the surface of the dielectric layer 610.

[0096] In some implementations, the material of the capping layer 915 is non-selectively deposited over the semiconductor device 105, and an etch-back operation is performed to remove portions of the material of the capping layer 915, such that the capping layer 915 remains only on the gate structure 805. For example, a deposition tool can be used to blanket-deposit the material of the capping layer 915, and a pattern in a photoresist layer can be used to etch the material of the capping layer 915 to remove the material of the capping layer 915 that is not located on the gate structure 805.

[0097] In some implementations, a combination of selective deposition and etching is used to define the capping layer 915. For example, the selective deposition technique described above can be performed to deposit the material of the capping layer 915, and a subsequent etch-back operation can be performed to remove the material of the capping layer 915 from the regions of the semiconductor device 105 other than the gate structure 805. Because of the use of selective deposition, a smaller amount of material of the capping layer 915 can be deposited on the regions of the semiconductor device 105 other than the gate structure 805. Therefore, the z-direction thickness of the capping layer 915 on the gate structure 805 can be greater than the z-direction thickness of the capping layer 915 on other regions of the semiconductor device 105. This makes it possible to perform maskless etching to remove the material of the capping layer 915 that can be deposited on the regions of the semiconductor device 105 other than the gate structure 805. In particular, the greater z-direction thickness of the capping layer 915 on the gate structure 805 makes it possible to completely remove the material of the capping layer 915 on other regions of the semiconductor device 105 before completely consuming the capping layer 915 on the gate structure 805.

[0098] like Figure 9C As shown, a cut source / drain groove 920 is formed based on the pattern 910 in the hard mask layer 905. The cut source / drain groove 920 can be called a cut source / drain groove because the cut source / drain groove 920 extends in the x direction between laterally adjacent source / drain regions 510 in the y direction, and in the process of forming the cut source / drain groove 920, portions of the sides of those source / drain regions 510 are removed (or "cut").

[0099] To form the cut source / drain recess 920, an etching tool can be used to perform one or more etching operations to etch through two or more sides laterally adjacent to the source / drain region 510 in the x-direction. The etching operations may include vertical etching (or predominantly vertical etching) from the top of the semiconductor device 105 through the dielectric layer 610, through the capping layer 515 on the sides of the source / drain region 510 in the y-direction, through the sides of the source / drain region 510 in the y-direction, and through the dielectric layer 605 laterally adjacent to the source / drain region 510 in the y-direction. In some embodiments, the etching operations may include vertical etching (or predominantly vertical etching) into the STI region 170 beneath the dielectric layer 605. In this way, the cut source / drain groove 920 can extend from the hard mask layer 905 through the hard mask layer 905, through the cover layer 515 on the side of the source / drain region 510 that is laterally adjacent in the y direction, through the side of the source / drain region 510, through the dielectric layer 605 located between the source / drain regions 510 in the y direction, and into the STI region 170 below the dielectric layer 605.

[0100] In some embodiments, the diced source / drain recess 920 can be formed by plasma-based etching and / or another type of anisotropic etching. This allows for a high aspect ratio (e.g., the ratio of the depth of the diced source / drain recess 920 in the z-direction to the lateral width of the diced source / drain recess 920 in the y-direction) used for the diced source / drain recess 920. Additionally and / or alternatively, another etching technique can be used to form the diced source / drain recess 920. A capping layer 915 on the gate structure 805 protects the gate structure 805 from etching during the formation of the diced source / drain recess 920.

[0101] In some embodiments, the source / drain region 510 may have flat sidewalls (e.g., vertically flat sidewalls) in the y-direction, wherein the source / drain groove 920 is formed in the y-direction on opposite sides of the source / drain region 510. In some embodiments, the source / drain region 510 may have asymmetrical sidewalls in the y-direction, such as flat vertical sidewalls and opposite sidewalls curved in the y-direction, wherein the source / drain groove 920 is formed in the y-direction only on one side of the source / drain region 510.

[0102] A source / drain region 510 having at least one cut sidewall may have a width or diameter in the y-direction smaller than the width or diameter of another source / drain region 510 that does not have at least one cut sidewall. A source / drain region 510 having cut sidewalls in the y-direction may have a width or diameter in the y-direction smaller than the width or diameter of another source / drain region 510 that has only one cut sidewall in the y-direction.

[0103] like Figure 9D As shown, a cut source / drain recess 920 can be filled to form a source / drain isolation structure 925 within the cut source / drain recess 920. The source / drain isolation structure 925 can extend in the semiconductor device 105 in both the z-direction and x-direction. In some embodiments, the source / drain isolation structure 925 extends in the x-direction through one or more active region isolation structures 705. The source / drain isolation structure 925 can be laterally located between laterally adjacent source / drain regions 510 in the y-direction and can provide electrical isolation between the source / drain regions 510. Furthermore, the source / drain isolation structures 925 laterally adjacent to the opposite sides of the source / drain regions 510 in the y-direction provide for bonding... Figures 10A to 10F The described subsequent silicide process forms a defined barrier in which a metal silicide layer is formed on the surface of the source / drain region 510 in the y-direction.

[0104] In some implementations, the source / drain isolation structure 925 extends lower in the z-direction into the semiconductor device than the active region isolation structure 705. In other words, the bottom surface of the source / drain isolation structure 925 may be located at a vertical (z-direction) position in the semiconductor device 105 that is lower than the bottom surface of the active region isolation structure 705.

[0105] In some implementations, the active region isolation structure 705 extends lower in the z-direction into the semiconductor device than the source / drain isolation structure 925. In other words, the bottom surface of the active region isolation structure 705 may be located at a vertical (z-direction) position in the semiconductor device 105 that is lower than the bottom surface of the source / drain isolation structure 925.

[0106] In some implementations, the bottom surfaces of the active region isolation structure 705 and the source / drain isolation structure 925 are substantially coplanar in the xy plane of the semiconductor device 105.

[0107] In some embodiments, the source / drain isolation structure 925 extends into one or more of the underlying STI regions 170. In some embodiments, the source / drain isolation structure 925 has substantially vertical and non-tapered sidewalls. In some embodiments, the source / drain isolation structure 925 has tapered sidewalls, such that the y-direction width of the source / drain isolation structure 925 decreases from the top of the source / drain isolation structure 925 to the bottom of the source / drain isolation structure 925.

[0108] like Figure 9D As shown, the diced source / drain recess 920 may be lined with a conformal pad 930, and the material of the source / drain isolation structure 925 may be deposited on the pad 930 in the source / drain isolation structure 925 to fill the diced source / drain recess 920. The pad 930 may include one or more dielectric materials, such as silicon nitride (Si). x N y ), silicon dioxide (SiO) x Silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), silicon carbonitride (SiOCN), and / or another suitable dielectric material. The source / drain isolation structure 925 may each include one or more dielectric materials, such as silicon nitride (SiON), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), silicon carbonitride (SiOCN), and / or another suitable dielectric material. x N y ), silicon dioxide (SiO) x Silicon oxynitride (SiON), silicon oxycarbonate (SiOC), silicon carbonitride (SiCN), silicon carbonitride (SiOCN), and / or another suitable dielectric material.

[0109] In some embodiments, the pad 930 and the source / drain isolation structure 925 comprise different dielectric materials. For example, the pad 930 may comprise silicon nitride (Si). x N y Furthermore, the source / drain isolation structure 925 may include silicon oxide (SiO2). x In some embodiments, the pad 930 and the source / drain isolation structure 925 comprise the same dielectric material.

[0110] In some embodiments, the active region isolation structure 705 and the source / drain isolation structure 925 comprise different dielectric materials. For example, the active region isolation structure 705 may comprise silicon carbide (SiOC), and the source / drain isolation structure 925 may comprise silicon oxide (SiO2). x In some embodiments, the active region isolation structure 705 and the source / drain isolation structure 925 comprise the same dielectric material.

[0111] Material for the pad 930 can be deposited using conformal deposition techniques such as ALD and / or CVD, and other examples, using deposition tools. Material for the source / drain isolation structure 925 can be deposited using deposition techniques such as ALD, CVD, PVD, and / or oxidation, and other examples, using deposition tools. In some embodiments, planarization tools are used to perform planarization operations such as CMP to remove excess material from the source / drain isolation structure 925. Dielectric layer 610 can also be removed during planarization operations. Planarization operations can make the top of the source / drain isolation structure 925 substantially coplanar with the top of dielectric layer 610.

[0112] As pointed out above, Figures 9A to 9D It is provided as an instance. Other instances can be related to... Figures 9A to 9D The descriptions are different.

[0113] Figures 10A to 10F This is a figure of an exemplary embodiment 1000 of the metal silicide layer formation process described herein. Figures 10A to 10E It is shown from a perspective view of semiconductor device 105, and Figure 10F From along Figure 10EThe cross-section of line BB is illustrated in the figure. Exemplary embodiment 1000 includes an example of defining an opening using a source / drain isolation structure 925 between adjacent source / drain regions 510 in the y-direction, wherein a metal silicide layer can be formed on top of the source / drain regions 510 such that the metal silicide layer completely spans the entire top surface of the source / drain regions 510 in the y-direction and / or along the y-direction (which may be difficult to achieve if the metal silicide layer is otherwise formed in a source / drain contact groove defined during the source / drain contact groove process). In some embodiments, the operations described in conjunction with exemplary embodiment 1000 are combined with... Figures 1A to 9D The described operations will be implemented later.

[0114] like Figure 10A As shown, a hard mask layer 1005 may be formed over and / or on the gate structure 805, such that the hard mask layer 1005 extends along the gate structure 805 in the y-direction. Alternatively, the hard mask layer 1005 may be omitted. The material of the hard mask layer 1005 may be deposited using deposition tools employing CVD, ALD, PVD, and / or another suitable deposition technique.

[0115] In some embodiments, the hard mask layer 1005 may include silicon nitride (Si). x N y ), silicon dioxide (SiO) x The hard mask layer 1005 may comprise silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), silicon carbonitride (SiOCN), and / or another suitable dielectric material. In some embodiments, the hard mask layer 1005 may comprise a metallic material such as titanium (Ti), tungsten (W), and / or ruthenium (Ru), and other examples. In some embodiments, the hard mask layer 1005 may comprise another material such as tantalum nitride (TaN) and / or titanium nitride (TiN), and other examples.

[0116] In some embodiments, the hard mask layer 1005 is selectively formed or grown on top of the gate structure 805. In other words, the hard mask layer 1005 is selectively formed or grown on the gate structure 805, while little or no material of the hard mask layer 1005 is grown or deposited on other layers and / or structures of the semiconductor device 105 (such as dielectric layer 610, active region isolation structure 705, and / or source / drain isolation structure 925).

[0117] To achieve selective deposition of the material of the hard mask layer 1005 on the gate structure 805, the precursors and reactants of the hard mask layer 1005 material can be selected to achieve a reaction on the metal material of the gate structure 805, such that the precursors and reactants react to deposit the material of the hard mask layer 1005 only on the metal material of the gate structure 805. Additionally and / or optionally, the exposed surfaces of the gate structure 805 can first be surface-treated with a surface modifier (e.g., a self-assembled monolayer) that promotes adhesion of the material of the hard mask layer 1005. Additionally and / or optionally, the exposed surfaces of the dielectric layer 610 and the source / drain isolation structure 925 can first be surface-treated with a surface modifier (e.g., a chemical reagent) that inhibits adhesion of the material of the hard mask layer 1005 to the surfaces of the dielectric layer 610 and the source / drain isolation structure 925.

[0118] In some embodiments, the material of the hard mask layer 1005 is non-selectively deposited over the semiconductor device 105, and an etch-back operation is performed to remove portions of the material of the hard mask layer 1005, such that the hard mask layer 1005 remains only on the gate structure 805. For example, a deposition tool can be used to blanket-deposit the material of the hard mask layer 1005, and a pattern in a photoresist layer can be used to etch the material of the hard mask layer 1005 to remove the material of the hard mask layer 1005 that is not located on the gate structure 805.

[0119] In some implementations, a combination of selective deposition and etching is used to define the hard mask layer 1005. For example, the selective deposition technique described above can be performed to deposit material of the hard mask layer 1005, and a subsequent etch-back operation can be performed to remove material of the hard mask layer 1005 from regions of the semiconductor device 105 other than the gate structure 805. Because of the use of selective deposition, a smaller amount of material of the hard mask layer 1005 can be deposited on regions of the semiconductor device 105 other than the gate structure 805. Therefore, the z-direction thickness of the hard mask layer 1005 on the gate structure 805 can be greater than the z-direction thickness of the hard mask layer 1005 on other regions of the semiconductor device 105. This makes it possible to perform maskless etching to remove material of the hard mask layer 1005 that can be deposited on regions of the semiconductor device 105 other than the gate structure 805. In particular, the greater z-direction thickness of the hard mask layer 1005 on the gate structure 805 makes it possible to completely remove material from the hard mask layer 1005 on other regions of the semiconductor device 105 before completely consuming the hard mask layer 1005 on the gate structure 805.

[0120] like Figure 10BAs shown, portions of the dielectric layer 610 and the pad 930 can be removed from the semiconductor device 105 to form a recess 1010 over the source / drain region 510. In an embodiment where the dielectric layer 610 is omitted and a dielectric layer 605 is formed instead over the source / drain region 510, the dielectric layer 605 can be removed from the semiconductor device 105 to form a recess 1010 over the source / drain region 510.

[0121] The source / drain isolation structure 925 may define the sidewalls of the recess 1010 in the y-direction. The spacer layer 220 may define the sidewalls of the recess 1010 in the x-direction. The source / drain isolation structure 925 and the spacer layer 220 may define the recess 1010 such that the top surface of the entire source / drain region 510 is substantially exposed through the recess 1010.

[0122] In some embodiments, an etching tool can be used to perform a wet etching operation with a wet chemical etchant to etch and remove portions of dielectric layer 610 (and / or dielectric layer 605) and pad 930 to form a recess 1010 over the source / drain region 510. A hard mask layer 1005 protects the top of the gate structure 805 from etching during the etching operation that forms the recess 1010. Figure 10B As shown, in some embodiments, wet etching can cause the pad 930 to be partially etched back and recessed in the region laterally located between the spacer layer 220 and the source / drain isolation structure 925.

[0123] In some embodiments, dielectric layer 610 and pad 930 may comprise the same material, and the groove 1010 may be formed using a wet etchant that has a high etch rate to the materials of dielectric layer 610 and pad 930. The wet etchant may selectively remove the materials of dielectric layer 610 and pad 930 while etching little to no spacer layer 220, active region isolation structure 705, source / drain isolation structure 925, and / or hard mask layer 1005, because these structures may be formed from materials different from those of dielectric layer 610 and pad 930. In some embodiments, another type of etching technique (such as gas-based etching) may be used to form the groove 1010.

[0124] like Figure 10CAs shown, spacer layer 1015 can be formed on the sidewalls of spacer layer 220 and on the sidewalls of source / drain isolation structure 925 exposed in recess 1010. The material of spacer layer 1015 can also refill the recessed portion of the pad 930 between source / drain isolation structure 925 and spacer layer 220. Spacer layer 1015 can protect the sidewalls of spacer layer 220 and the sidewalls of source / drain isolation structure 925 exposed in recess 1010 during subsequent siliconization processes to form a metal silicide layer on the top surface of source / drain region 510 exposed in recess 1010.

[0125] Spacer layer 1015 may include one or more dielectric materials, such as silicon nitride (Si). x N y ), silicon dioxide (SiO) x The materials used for the spacer layer 1015 may be silicon oxynitride (SiON), silicon oxycarbonate (SiOC), silicon carbonitride (SiCN), silicon carbonitride (SiOCN), and / or another suitable dielectric material. Deposition tools may be used to deposit the material of the spacer layer 1015 using conformal deposition techniques such as ALD and / or CVD, and other examples.

[0126] like Figure 10D As shown, a metal silicide layer 1020 may be formed over and / or on the top surface of the source / drain region 510. Because the entire (or substantially all) top surface of the source / drain region 510 is exposed through the recess 1010 (e.g., because the recess 1010 is defined by the spacer layer 220 and the source / drain isolation structure 925), the metal silicide layer 1020 substantially covers the entire top surface of the source / drain region 510. Specifically, the metal silicide layer 1020 may span the top surface of the source / drain region 510 in the y-direction (e.g., because the source / drain isolation structure 925 defines the recess 1010 in the y-direction) and may also span the top surface of the source / drain region 510 in the x-direction (e.g., because the spacer layer 220 defines the recess 1010 in the x-direction).

[0127] Each of the metal silicide layers 1020 may include a metal silicide material, such as titanium silicide (TiSi), zirconium silicide (ZrSi), cobalt silicide (CoSi), ruthenium silicide (RuSi), nickel silicide (NiSi) and / or nickel platinum silicide (NiPtSi), and other examples.

[0128] A silicide process can be performed to selectively form a metal silicide layer 1020 on the exposed top surface of the source / drain region 510. For example, a deposition tool can be used to deposit a metal material (e.g., titanium (Ti), zirconium (Zr), cobalt (Co), ruthenium (Ru), nickel (Ni)) onto the exposed top surface of the source / drain region 510. An annealing operation can be performed to react the metal material with the semiconductor material (e.g., silicon (Si), silicon germanium (SiGe)) of the source / drain region 510 to form the metal silicide material of the metal silicide layer 1020. Unreacted metal material deposited on other regions of the semiconductor device 105 can then be removed.

[0129] like Figure 10D As further shown, a metal capping layer 1025 can be formed on the metal silicide layer 1020 above the top of the source / drain region 510 in the groove 1010. The metal capping layer 1025 can substantially cover the entire metal silicide layer 1020.

[0130] A metal capping layer 1025 may be formed on the metal silicide layer 1020 as a protective layer for the metal silicide layer 1020. The metal capping layer 1025 prevents the metal silicide layer 1020 from being exposed to atmospheric conditions and subsequent processing chemicals, which could otherwise degrade the film quality of the metal silicide layer 1020. The metal capping layer 1025 may also be used as a seed layer for subsequent formation of source / drain contacts on the source / drain region 510.

[0131] The metal capping layer 1025 may include one or more low-resistivity metals, such as tungsten (W), cobalt (Co), titanium (Ti), tantalum (Ta), ruthenium (Ru), and / or iridium (Ir), and other examples. In some embodiments, the metal material of the metal capping layer 1025 may differ from the metal composition of the metal silicide layer 1020. For example, the metal silicide layer 1020 may include titanium silicide (TiSi), and the metal capping layer 1025 may include ruthenium (Ru). In some embodiments, the metal material of the metal capping layer 1025 and the metal composition of the metal silicide layer 1020 may be the same metal. For example, the metal silicide layer 1020 may include cobalt silicide (CoSi), and the metal capping layer 1025 may include cobalt (Co).

[0132] In some implementations, a deposition tool is used to non-selectively deposit material for the metal overlay 1025 over the semiconductor device 105, such as... Figure 10DAs illustrated in the examples. In these embodiments, deposition techniques such as PVD, CVD, and / or another suitable deposition technique can be used to deposit the material of the metal capping layer 1025. The material of the metal capping layer 1025 on areas of the semiconductor device 105 other than the metal silicide layer 1020 can then be removed by etching and / or planarization. Optionally, the material of the metal capping layer 1025 can be selectively deposited only (or primarily) on the metal silicide layer 1020, with little or no material deposited on other areas of the semiconductor device 105, such as... Figures 12A to 12C As shown in the example.

[0133] like Figure 10E As shown, the groove 1010 can be refilled with dielectric material over the metal capping layer 1025 to form a dielectric layer 1030 over the source / drain region 510. The dielectric layer 1030 may include silicon nitride (Si). x N y ), silicon dioxide (SiO) x The dielectric material may be silicon oxynitride (SiON), silicon oxycarbonate (SiOC), silicon carbonitride (SiCN), silicon carbonitride (SiOCN), and / or another suitable dielectric material. In some embodiments, dielectric layer 1030 comprises the same dielectric material as pad 930. In some embodiments, dielectric layer 1030 and pad 930 comprise different dielectric materials.

[0134] The dielectric layer 1030 can be deposited using deposition tools employing PVD, ALD, CVD, oxidation, and / or another suitable deposition technique. The dielectric layer 1030 may be deposited in one or more deposition operations. In some embodiments, planarization tools may be used to perform planarization operations (e.g., CMP operations) to planarize the dielectric layer 1030 after deposition.

[0135] like Figure 10F As shown, in the x-direction, since the top surface of the source / drain region 510 is etched during the formation of the groove 1010, the top surface of the source / drain region 510 can be recessed and concave. Therefore, the metal silicide layer 1020 above and / or on the top surface of the source / drain region 510 can be recessed in the top surface of the source / drain region 510 and can have a similar arcuate shape or concave profile in the x-direction. Furthermore, the metal overlay layer 1025 above and / or on the metal silicide layer 1020 can have a similar arcuate shape or concave profile in the x-direction.

[0136] Figure 10F One or more exemplary dimensions of the semiconductor device 105 are also shown. Figure 10FAs shown, the exemplary dimension D1 may correspond to the lateral width of the metal capping layer 1025 in the x-direction. In other words, dimension D1 may correspond to the lateral width of the metal capping layer 1025 between laterally adjacent spacer layers 220 in the x-direction. In some embodiments, dimension D1 includes a range of approximately 6 nanometers to approximately 20 nanometers, such that the metal capping layer 1025 completely covers the underlying metal silicide layer 1020. However, other values ​​and ranges are also within the scope of embodiments of this disclosure.

[0137] Another exemplary dimension D2 may correspond to the z-direction thickness of the metal overlay 1025. In some embodiments, dimension D2 includes a range of approximately 2 nanometers to approximately 8 nanometers to provide sufficient protection for the underlying metal silicide layer 1020. However, other values ​​and ranges are also within the scope of embodiments of this disclosure.

[0138] Another exemplary dimension D3 may correspond to the z-direction thickness of the metal silicide layer 1020. In some embodiments, dimension D3 includes a range of approximately 3 nanometers to approximately 9 nanometers to provide sufficient native oxide formation protection for the underlying source / drain regions 510 while achieving low contact resistance for the source / drain regions 510. However, other values ​​and ranges are also within the scope of embodiments of this disclosure.

[0139] Another exemplary dimension D4 may correspond to the lateral width of the metal silicide layer 1020 in the x-direction. In other words, dimension D4 may correspond to the lateral width of the metal silicide layer 1020 between laterally adjacent spacer layers 220 in the x-direction. Dimension D4 may be larger than the lateral width of the metal capping layer 1025 in the x-direction (e.g., dimension D2) and may be approximately equal to the lateral length of the source / drain region 510 in the x-direction.

[0140] The lateral width of the metal silicide layer 1020 in the x-direction can be greater than that of the metal capping layer 1025 in the x-direction because a spacer layer 1015 is present on the sidewall of the recess 1010 during the formation of the metal capping layer 1025. Even though the spacer layer 1015 is located on the sidewall of the recess 1010 during the formation of the metal silicide layer 1020, the metal silicide layer 1020 is formed by silicide, and therefore the portion of the metal deposited on the surface of the source / drain region 510 for the silicide process may diffuse into the surface of the source / drain region 510 below the spacer layer 1015. Therefore, the metal silicide layer 1020 can extend completely in the x-direction between the ends of the source / drain region 510, while the metal capping layer 1025 can span a length less than the entire length of the source / drain region 510 in the x-direction.

[0141] As pointed out above, Figures 10A to 10FIt is provided as an instance. Other instances can be related to... Figures 10A to 10F The descriptions are different.

[0142] Figures 11A to 11C This is a figure of an exemplary embodiment 1100 of the metal silicide layer formation process described herein. Figures 11A to 11C This is a perspective view of semiconductor device 105. Exemplary embodiment 1100 is combined with... Figures 10A to 10F Alternative embodiments of the metal silicide layer formation process shown and described.

[0143] like Figure 11A As shown, the hard mask layer 1005 can be omitted. Figure 11B As shown, the recess 1010 can be formed without using a hard mask layer 1005. An etchant can be used to selectively etch the dielectric layer 610 and the pad 930, while minimizing or eliminating etching of the metal material of the gate structure 805. For example, a phosphoric acid etchant, a potassium hydroxide (KOH) etchant, and / or a buffered oxide etchant (BOE) can be used to selectively etch the dielectric layer 610 and the pad 930, while minimizing or eliminating etching of the metal material of the gate structure 805.

[0144] like Figure 11C As shown, the metal silicide layer 1020, the metal capping layer 1025, and the dielectric layer 1030 can be bonded to... Figures 10A to 10F It is formed in a similar manner as described.

[0145] As pointed out above, Figures 11A to 11C It is provided as an instance. Other instances can be related to... Figures 11A to 11C The descriptions are different.

[0146] Figures 12A to 12C This is a figure of an exemplary embodiment 1200 of the metal silicide layer formation process described herein. Figures 12A to 12C This is a perspective view of semiconductor device 105. Exemplary embodiment 1200 is combined with... Figures 10A to 10F Alternative embodiments of the metal silicide layer formation process shown and described.

[0147] like Figure 12A As shown, the groove 1010 can be engaged with Figures 10A to 10F Formed in a similar manner as described. Optionally, the groove 1010 can be joined... Figures 11A to 11C It is formed in a similar manner as described.

[0148] like Figure 12BAs shown, a metal silicide layer 1020 can be formed, and a metal capping layer 1025 can be formed on the metal silicide layer 1020 in the recess 1010. In the exemplary embodiment 1200, the metal of the metal capping layer 1025 can be selectively deposited by selecting the precursors and reactants of the metal capping layer 1025 material to achieve a reaction on the metal-containing material of the metal silicide layer 1020, such that the precursors and reactants react to deposit the material of the metal capping layer 1025 only on the metal-containing material of the metal silicide layer 1020. A hard mask layer 1005 on the gate structure 805 prevents reactions from occurring on the metal material of the gate structure 805.

[0149] Additionally and / or alternatively, the exposed surfaces of the spacer layer 220, the active region isolation structure 705, the source / drain isolation structure 925, and / or the spacer layer 1015 may first be surface treated with a surface modifier (e.g., a self-assembled monolayer) that binds the material of the metal overlay 1025 to these surfaces.

[0150] like Figure 12C As shown, dielectric layer 1030 can be bonded Figures 10A to 10F It is formed in a similar manner as described.

[0151] As pointed out above, Figures 12A to 12C It is provided as an instance. Other instances can be related to... Figures 12A to 12C The descriptions are different.

[0152] Figure 13 This is a figure of an exemplary embodiment 1300 of the dicing metal gate process described herein. Figure 13 This is a perspective view of semiconductor device 105. Exemplary embodiment 1300 includes an example of dicing gate structure 805 into two or more gate structure segments and forming a gate isolation structure (e.g., dicing a metal gate (CMG) structure) between the two or more gate structure segments to electrically isolate the gate structure segments. In some embodiments, the operations described in conjunction with exemplary embodiment 1300 are combined with... Figures 1A to 12C One or more operations described are performed afterward.

[0153] like Figure 13As shown, the gate isolation structure 1305 may include dielectric pillars, dielectric columns, dielectric walls, and / or another type of electrically insulating structure similar to the source / drain isolation structure 925, except that the gate isolation structure 1305 extends through one or more gate structures 805, while the source / drain isolation structure 925 does not cut through the gate structure 805. The gate isolation structure 1305 may extend laterally in the x-direction and vertically in the z-direction within the semiconductor device 105. Therefore, the gate isolation structure 1305 and the source / drain isolation structure 925 may extend substantially parallel to each other within the semiconductor device 105.

[0154] In some implementations, in Figures 9A to 9D The gate isolation structure 1305 and the source / drain isolation structure 925 are formed in the same process flow shown. For example, the capping layer 915 can be omitted from the portion of the gate structure 805 exposed by pattern 910, thereby etching through the portion of the gate structure 805.

[0155] In some implementations, the gate isolation structure 1305 and the source / drain isolation structure 925 are formed in different / separate process flows. For example, the source / drain isolation structure 925 can be formed in a first process flow, and the gate isolation structure 1305 can be formed in a second process flow following the first process flow. As another example, the gate isolation structure 1305 can be formed in a first process flow, and the source / drain isolation structure 925 can be formed in a second process flow following the first process flow. Forming the gate isolation structure 1305 and the source / drain isolation structure 925 in separate process flows allows the gate isolation structure 1305 and the source / drain isolation structure 925 to be formed with different properties, such as different depths, different widths, different materials and / or different shapes, and other examples.

[0156] Prior to forming the gate isolation structure 1305, a conformally deposited pad 1310 may be deposited, and the material of the gate isolation structure 1305 may be deposited onto the pad 1310. The pad 1310 may include one or more dielectric materials, such as silicon nitride (Si). x N y ), silicon dioxide (SiO) x The gate isolation structure 1305 may include one or more dielectric materials, such as silicon nitride (SiON), silicon oxynitride (SiOC), silicon carbonitride (SiCN), silicon carbonitride (SiOCN), and / or another suitable dielectric material. x N y ), silicon dioxide (SiO) xSilicon oxynitride (SiON), silicon oxycarbonate (SiOC), silicon carbonitride (SiCN), silicon carbonitride (SiOCN), and / or another suitable dielectric material.

[0157] In some embodiments, the pad 1310 and the gate isolation structure 1305 comprise different dielectric materials. For example, the pad 1310 may comprise silicon nitride (Si). x N y Furthermore, the gate isolation structure 1305 may include silicon oxide (SiO2). x In some embodiments, the pad 1310 and the gate isolation structure 1305 comprise the same dielectric material.

[0158] In some embodiments, the active region isolation structure 705 and the gate isolation structure 1305 comprise different dielectric materials. For example, the active region isolation structure 705 may comprise silicon carbide (SiOC), and the gate isolation structure 1305 may comprise silicon oxide (SiO2). x In some embodiments, the active region isolation structure 705 and the gate isolation structure 1305 comprise the same dielectric material.

[0159] In some embodiments, the source / drain isolation structure 925 and the gate isolation structure 1305 comprise different dielectric materials. For example, the source / drain isolation structure 925 may comprise silicon oxycarbide (SiOC), and the gate isolation structure 1305 may comprise silicon oxide (SiO2). x In some embodiments, the source / drain isolation structure 925 and the gate isolation structure 1305 comprise the same dielectric material.

[0160] Material for the pad 1310 can be deposited using conformal deposition techniques such as ALD and / or CVD, and other examples, using deposition tools. Material for the gate isolation structure 1305 can be deposited using deposition techniques such as ALD, CVD, PVD, and / or oxidation, and other examples, using deposition tools. In some embodiments, planarization tools are used to perform planarization operations such as CMP to remove excess material from the gate isolation structure 1305.

[0161] As pointed out above, Figure 13 It is provided as an instance. Other instances can be related to... Figure 13 The descriptions are different.

[0162] Figures 14A to 14D This is a figure of an exemplary embodiment 1400 of the source / drain contact formation process described herein. Figure 14A and Figure 14B It is derived from a three-dimensional diagram of semiconductor device 105. Figure 14C From along Figure 14B The cross-section of line AA in the diagram is shown, and Figure 14D From along Figure 14B The cross-section of line BB is illustrated. Exemplary embodiment 1400 includes an example of forming source / drain contacts on the source / drain region 510 of semiconductor device 105. In some embodiments, the operations described in connection with exemplary embodiment 1400 are combined with... Figures 1A to 13 One or more operations described are performed afterward.

[0163] like Figure 14A As shown, a hard mask layer 1405 can be formed over the semiconductor device 105. The hard mask layer 1405 may include silicon nitride (Si). x N y ), silicon dioxide (SiO) x The hard mask layer 1405 may be made of silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), silicon carbonitride oxynitride (SiOCN), and / or another suitable dielectric material. Deposition tools may be used to deposit the material of the hard mask layer 1405 using PVD, ALD, CVD, epitaxial, oxidation, and / or another suitable deposition technique. In some embodiments, after depositing the hard mask layer 1405, a planarization operation (e.g., CMP operation) may be performed using planarization tools to planarize the hard mask layer 1405.

[0164] like Figure 14A As further shown, a pattern can be formed in the hard mask layer 1405. The pattern may include openings through the hard mask layer 1405. The openings may extend in the y-direction. In some embodiments, the pattern in the photoresist layer is used to etch the hard mask layer 1405 to form the pattern. In these embodiments, a deposition tool can be used to form the photoresist layer on the hard mask layer 1405 (e.g., using spin coating and / or another suitable deposition technique). An exposure tool can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A development tool can be used to develop and remove portions of the photoresist layer to expose the pattern. An etching tool can be used to etch the hard mask layer 1405 based on the pattern to form the pattern. In some embodiments, the etching operation includes a dry etching operation (e.g., a plasma-based etching operation, a gas-based etching operation), a wet chemical etching operation, and / or another type of etching operation. In some embodiments, a photoresist removal tool can be used to remove the remaining portions of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or another technique).

[0165] like Figure 14AAs further shown, the pattern in the hard mask layer 1405 can be used to etch the dielectric layer 1030 to form source / drain recesses 1410 in the dielectric layer 1030. The source / drain recesses 1410 can be formed over the source / drain regions 510, such that at least a portion of the metal overlay layer 1025 over the top surface of the source / drain regions 510 is exposed through the source / drain recesses 1410. An etching tool can be used to etch the dielectric layer 1030 based on the pattern in the hard mask layer 1405 to form the source / drain recesses 1410. In some embodiments, the etching operation includes dry etching operations (e.g., plasma-based etching operations, gas-based etching operations), wet chemical etching operations, and / or another type of etching operation.

[0166] like Figure 14A As further shown, some of the source / drain recesses 1410 (such as source / drain recess 1410a) can be formed such that a metal capping layer 1025 smaller than the entire y-direction is exposed through the source / drain recess 1410a. A portion of the metal capping layer 1025 can remain covered by the dielectric layer 1030. Some of the source / drain recesses 1410 (such as source / drain recess 1410b) can be formed such that a portion of the source / drain recess 1410b is etched into the portion of the source / drain isolation structure 925 laterally adjacent to the source / drain region 510 at the bottom of the source / drain recess 1410b.

[0167] like Figure 14B As shown, source / drain contacts 1415 can be formed in the source / drain recess 1410, such that the source / drain contacts 1415 are located above and electrically coupled to the source / drain region 510. The source / drain contacts 1415 may include one or more low-resistance metals, such as tungsten (W), cobalt (Co), titanium (Ti), tantalum (Ta), ruthenium (Ru), and / or iridium (Ir), and other examples. In some embodiments, the metal material of the source / drain contacts 1415 may be different from the metal material of the metal capping layer 1025. For example, the source / drain contacts 1415 may include tungsten (W), and the metal capping layer 1025 may include ruthenium (Ru). In some embodiments, the metal material of the source / drain contacts 1415 and the metal material of the metal capping layer 1025 may be the same metal material.

[0168] Material for the source / drain contact 1415 can be deposited using deposition tools employing CVD, PVD, ALD, electroplating, and / or another suitable deposition technique. The material for the source / drain contact 1415 can be deposited in one or more deposition operations. In some embodiments, a seed layer is deposited first, and the material for the source / drain contact 1415 is deposited on the seed layer. In some embodiments, after depositing the source / drain contact 1415, a planarization operation (e.g., CMP operation) is performed using planarization tools to planarize the source / drain contact 1415. In some embodiments, the hard mask layer 1405 can be removed during the planarization operation. In some embodiments, the hard mask layer 1405 can be removed prior to the formation of the source / drain contact 1415.

[0169] In this manner, the metal silicide layer 1020 of the transistor structure of the semiconductor device 105 is formed prior to the formation of the source / drain recess 1410 and prior to the formation of the source / drain contact 1415. The metal silicide layer 1020 is formed in the recess 1010, which is formed prior to the formation of the source / drain recess 1410 and prior to the formation of the source / drain contact 1415. Using the recess 1010 to define the coverage of the metal silicide layer 1020 across the top surface of the source / drain region 510 allows the metal silicide layer 1020 to be formed such that the metal silicide layer 1020 substantially covers the entire top surface of the source / drain region 510, which might not be possible if the metal silicide layer 1020 were formed in the source / drain recess 1410, such as in cases where the source / drain recess 1410a does not completely expose the entire surface of the underlying source / drain region 510.

[0170] The full coverage of the metal silicide layer 1020 on the source / drain region 510 provides a more flexible layout for the source / drain contacts 1415 and the gate structure 805. For example, adjacent source / drain contacts 1415 can be laterally offset in the y-direction and / or the lateral dimensions of the source / drain contacts 1415 in the y-direction can be selected to achieve a high density of source / drain contacts 1415 and / or to achieve a minimum spacing distance for electrical isolation, and the full coverage of the metal silicide layer 1020 on the source / drain region 510 facilitates this flexible layout of the source / drain contacts 1415. As another example, the source / drain contact 1415 can be laterally shifted in the x-direction and / or the lateral dimension of the source / drain contact 1415 in the x-direction can be selected to achieve a minimum spacing distance for electrical isolation between the source / drain contact 1415 and the adjacent gate structure 805, and the full coverage of the metal silicide layer 1020 on the source / drain region 510 facilitates this flexible layout of the source / drain contact 1415.

[0171] like Figure 14C As shown, the source / drain contact 1415a (e.g., formed in the source / drain recess 1410a) can span in the y-direction a width smaller than the entire width of the underlying source / drain region 510 (and smaller than the entire width of the underlying metal silicide layer 1020 and the underlying metal capping layer 1025). This is because a portion of the dielectric layer 1030 remains above the source / drain region 510 (and a portion of the underlying metal silicide layer 1020 and the underlying metal capping layer 1025). Therefore, the lateral width of the top surface of the source / drain region 510 in the y-direction ( Figure 14C The dimension D5 in the middle can be greater than the lateral width of the source / drain contact 1415a in the x direction. Figure 14C The lateral width of the top surface of the source / drain region 510 in the y-direction (e.g., dimension D5) corresponds to the lateral width of the source / drain contact 1415a in the y-direction (e.g., dimension D6) and the lateral width of the portion of the dielectric layer 1030 located above the source / drain region 510 in the y-direction. Figure 14C The combination of dimensions D7 in the middle.

[0172] like Figure 14C As further shown, the source / drain contact 1415b (e.g., formed in the source / drain recess 1410b) may have a lateral width in the y-direction. Figure 14C The dimension D8 in the middle, so that a portion of the source / drain contact 1415b extends laterally outward from the lower source / drain region 510 and above a portion of the adjacent source / drain isolation structure 925 by a distance ( Figure 14C (Dimension D9 in the middle).

[0173] like Figure 14D As shown, the lateral width of the source / drain contact 1415 in the x-direction ( Figure 14DThe dimension D9 of the underlying metal silicide layer 1020 can be smaller than the lateral width (dimension D4) of the underlying metal capping layer 1025 in the x-direction and smaller than the lateral width (dimension D1) of the underlying metal capping layer 1025 in the x-direction. In some embodiments, the difference between the lateral width (dimension D1) of the underlying metal capping layer 1025 in the x-direction and the lateral width (dimension D9) of the source / drain contact 1415 in the x-direction can include a range of approximately 0 nanometers to approximately 6 nanometers. However, other values ​​and ranges are also within the scope of embodiments of this disclosure. In some embodiments, the source / drain contact 1415 can be approximately centered in the x-direction relative to the center of the source / drain region 510. Optionally, some overlap offset may occur during the formation of the source / drain recess 1410 for the source / drain contact 1415, and the source / drain contact 1415 may be laterally offset in the x-direction relative to the center of the source / drain region 510 in the x-direction.

[0174] like Figure 14D As further shown, the source / drain contact 1415 can have a vertical (z-direction) height ranging from approximately 5 nanometers to approximately 25 nanometers. Figure 14D (Dimension D10 in the text). However, other values ​​and ranges are also within the scope of embodiments of this disclosure.

[0175] As pointed out above, Figures 14A to 14D It is provided as an instance. Other instances can be related to... Figures 14A to 14D The descriptions are different.

[0176] Figure 15 This is a figure of an exemplary embodiment 1500 of the semiconductor device 105 described herein. Figure 15 From along Figure 14B The cross-section of line AA in the diagram is shown. Figure 15 It shows relative to Figure 14C The x-direction section shown is an optional x-direction section. For example, in exemplary embodiment 1500, the source / drain contact 1415a (e.g., formed in the source / drain recess 1410a) may span less than the entire width of the underlying source / drain region 510 (and less than the entire width of the underlying metal silicide layer 1020 and the underlying metal capping layer 1025) in the y-direction. However, the source / drain contact 1415b (e.g., formed in the source / drain recess 1410b) laterally adjacent to the source / drain contact 1415a in the y-direction terminates at the sidewall of the adjacent source / drain isolation structure 925. In other words, the source / drain contact 1415b will not be like... Figure 14C As shown in the exemplary embodiment 1400, it extends into the portion of the source / drain isolation structure 925.

[0177] As pointed out above, Figure 15 It is provided as an instance. Other instances can be related to... Figure 15 The descriptions are different.

[0178] Figure 16 This is a figure of an exemplary embodiment 1600 of the semiconductor device 105 described herein. Figure 16 It shows relative to Figure 14C The x-direction section shown is an optional x-direction section. For example, in exemplary embodiment 1600, a source / drain contact 1415b (e.g., formed in a source / drain recess 1410b) that is laterally adjacent to the source / drain contact 1415a in the y-direction extends into a portion of the source / drain isolation structure 925. However, the source / drain contact 1415a (e.g., formed in a source / drain recess 1410a) may substantially span the entire width of the underlying source / drain region 510 in the y-direction.

[0179] As pointed out above, Figure 16 It is provided as an instance. Other instances can be related to... Figure 16 The descriptions are different.

[0180] Figure 17 This is a figure of an exemplary embodiment 1700 of the semiconductor device 105 described herein. Figure 17 From along Figure 14B The cross-section of line AA in the diagram is shown. Figure 17 It shows relative to Figure 14C The x-direction section shown is an optional x-direction section. For example, in exemplary embodiment 1700, source / drain contact 1415a (e.g., formed in source / drain recess 1410a) can substantially span the entire width of the underlying source / drain region 510 in the y-direction, and source / drain contact 1415b (e.g., formed in source / drain recess 1410b) can also substantially span the entire width of the underlying source / drain region 510 in the y-direction.

[0181] As pointed out above, Figure 17 It is provided as an instance. Other instances can be related to... Figure 17 The descriptions are different.

[0182] Figure 18 This is a flowchart of an exemplary process 1800 associated with forming the semiconductor device described herein. In some embodiments, one or more semiconductor processing tools (such as deposition tools, exposure tools, developing tools, etching tools, planarization tools, ion implantation tools, annealing tools, wafer / die transport tools, and / or other types of semiconductor processing tools) are used to implement this. Figure 18 One or more process frames.

[0183] like Figure 18 As shown, process 1800 may include forming a plurality of nanostructured channels arranged in a first direction and extending in a second direction generally perpendicular to the first direction in the semiconductor device 105 (box 1805). For example, one or more semiconductor processing tools may be used to form a plurality of nanostructured channels (e.g., nanostructured channel 315) arranged in a first direction (e.g., z-direction) and extending in a second direction generally perpendicular to the first direction (e.g., x-direction) in the semiconductor device (e.g., semiconductor device 105), as described herein.

[0184] like Figure 18 As further shown, process 1800 may include forming source / drain regions (box 1810) adjacent to the plurality of nanostructure channels in a second direction. For example, one or more semiconductor processing tools may be used to form source / drain regions (e.g., source / drain regions 510) adjacent to the plurality of nanostructure channels in a second direction, as described herein.

[0185] like Figure 18 As further shown, process 1800 may include depositing a first dielectric layer (box 1815) over and beside the source / drain regions. For example, one or more semiconductor processing tools may be used to deposit the first dielectric layer (e.g., dielectric layer 605, dielectric layer 610) over and beside the source / drain regions, as described herein.

[0186] like Figure 18 As further shown, process 1800 may include forming a gate structure (block 1820) that encloses at least three sides of a plurality of nanostructure channels. For example, one or more semiconductor processing tools may be used to form a gate structure (e.g., gate structure 805) that encloses at least three sides of a plurality of nanostructure channels, as described herein.

[0187] like Figure 18 As further shown, process 1800 may include etching the first dielectric layer to form a first groove through the first dielectric layer, thereby exposing the top surface of the source / drain region through the groove (box 1825). For example, one or more semiconductor processing tools may be used to etch the first dielectric layer to form a first groove (e.g., groove 1010) through the first dielectric layer, thereby exposing the top surface of the source / drain region through the groove, as described herein.

[0188] like Figure 18As further shown, process 1800 may include depositing a metal material on the top surface of the source / drain regions in the trench to form a metal silicide layer on the top surface of the source / drain regions (box 1830). For example, one or more semiconductor processing tools may be used to deposit a metal material on the top surface of the source / drain regions in the trench to form a metal silicide layer (e.g., metal silicide layer 1020) on the top surface of the source / drain regions, as described herein.

[0189] like Figure 18 As further shown, process 1800 may include depositing a second dielectric layer in a trench such that the second dielectric layer is situated over the metal silicide layer and the source / drain regions (box 1835). For example, one or more semiconductor processing tools may be used to deposit the second dielectric layer (e.g., dielectric layer 1030) in the trench such that the second dielectric layer is situated over the metal silicide layer and the source / drain regions, as described herein.

[0190] like Figure 18 As further shown, process 1800 may include etching the second dielectric layer to form a second trench through the second dielectric layer, such that the second trench is located above at least a portion of the metal silicide layer (box 1840). For example, one or more semiconductor processing tools may be used to etch the second dielectric layer to form a second trench through the second dielectric layer (e.g., source / drain trench 1410), such that the second trench is located above at least a portion of the metal silicide layer, as described herein.

[0191] like Figure 18 As further shown, process 1800 may include forming source / drain contacts in the second recess such that the source / drain contacts are formed over at least a portion of the metal silicide layer (box 1845). For example, one or more semiconductor processing tools may be used to form source / drain contacts (e.g., source / drain contacts 1415, source / drain contacts 1415a, source / drain contacts 1415b) in the second recess such that the source / drain contacts are formed over at least a portion of the metal silicide layer, as described herein.

[0192] Process 1800 may include additional implementations, such as any single implementation or any combination of implementations of one or more other processes described below and / or described elsewhere herein.

[0193] In the first embodiment, forming the second groove includes forming a second groove such that the second groove is less than the entire metal silicide layer, and forming source / drain contacts in the second groove includes forming source / drain contacts in the second groove such that the source / drain contacts are less than the entire metal silicide layer.

[0194] In the second embodiment, alone or in combination with the first embodiment, process 1800 includes forming a spacer layer (e.g., spacer layer 1015) on the sidewall of the first groove before forming the metal silicide layer.

[0195] In the third embodiment, alone or in combination with one or more of the first and second embodiments, process 1800 includes forming a hard mask layer (e.g., hard mask layer 1005) on the gate structure prior to forming the first recess.

[0196] In the fourth embodiment, forming the first groove, alone or in combination with one or more of the first to third embodiments, includes forming the first groove such that the top surface of the source / drain region is exposed through the entire lateral width (e.g., dimension D4) in the second direction, and forming the metal silicide layer includes forming the metal silicide layer such that the metal silicide layer covers the entire lateral width of the top surface of the source / drain region.

[0197] Although Figure 18 An exemplary block diagram of process 1800 is shown, but in some embodiments, process 1800 includes... Figure 18 The boxes depicted in the text are compared to additional boxes, fewer boxes, different boxes, or boxes with different arrangements. Additionally or optionally, two or more boxes in process 1800 can be implemented in parallel.

[0198] Figure 19 This is a flowchart of an exemplary process 1900 associated with forming the semiconductor device described herein. In some embodiments, one or more semiconductor processing tools (such as deposition tools, exposure tools, development tools, etching tools, planarization tools, ion implantation tools, annealing tools, wafer / die transport tools, and / or other types of semiconductor processing tools) are used to implement this. Figure 19 One or more process frames.

[0199] like Figure 19 As shown, process 1900 may include forming a plurality of nanostructured channels arranged in a first direction and extending in a second direction substantially perpendicular to the first direction in the semiconductor device (box 1905). For example, one or more semiconductor processing tools may be used to form a plurality of nanostructured channels (e.g., nanostructured channel 315) arranged in a first direction (e.g., the z-direction) and extending in a second direction substantially perpendicular to the first direction (e.g., the x-direction) in the semiconductor device (e.g., semiconductor device 105), as described herein.

[0200] like Figure 19 As further shown, process 1900 may include forming source / drain regions (box 1910) adjacent to the plurality of nanostructure channels in a second direction. For example, one or more semiconductor processing tools may be used to form source / drain regions (e.g., source / drain regions 510) adjacent to the plurality of nanostructure channels in a second direction, as described herein.

[0201] like Figure 19 As further shown, process 1900 may include depositing a first dielectric layer (box 1915) over and beside the source / drain regions. For example, one or more semiconductor processing tools may be used to deposit the first dielectric layer (e.g., dielectric layer 605, hard mask layer 610) over and beside the source / drain regions, as described herein.

[0202] like Figure 19 As further shown, process 1900 may include forming a gate structure (block 1920) that encloses at least three sides of a plurality of nanostructure channels. For example, one or more semiconductor processing tools may be used to form a gate structure (e.g., gate structure 805) that encloses at least three sides of a plurality of nanostructure channels, as described herein.

[0203] like Figure 19 As further shown, process 1900 may include etching the first dielectric layer to form a first groove through the first dielectric layer, thereby exposing the top surface of the source / drain region through the groove (box 1925). For example, one or more semiconductor processing tools may be used to etch the first dielectric layer to form a first groove (e.g., groove 1010) through the first dielectric layer, thereby exposing the top surface of the source / drain region through the groove, as described herein.

[0204] like Figure 19 As further shown, process 1900 may include depositing metal material on the top surface of the source / drain regions in the trench to form a metal silicide layer on the top surface of the source / drain regions (box 1930). For example, one or more semiconductor processing tools may be used to deposit metal material on the top surface of the source / drain regions in the trench to form a metal silicide layer (e.g., metal silicide layer 1020) on the top surface of the source / drain regions, as described herein.

[0205] like Figure 19 As further shown, process 1900 may include depositing a metal capping layer on the metal silicide layer (box 1935). For example, one or more semiconductor processing tools may be used to deposit a metal capping layer (e.g., metal capping layer 1025) on the metal silicide layer, as described herein.

[0206] like Figure 19As further shown, process 1900 may include depositing a second dielectric layer in a trench such that the second dielectric layer is situated over the metal capping layer and the source / drain regions (box 1940). For example, one or more semiconductor processing tools may be used to deposit the second dielectric layer (e.g., dielectric layer 1030) in the trench such that the second dielectric layer is situated over the metal capping layer and the source / drain regions, as described herein.

[0207] like Figure 19 As further shown, process 1900 may include etching the second dielectric layer to form a second groove through the second dielectric layer, such that the second groove is located above at least a portion of the metal overlay (box 1945). For example, one or more semiconductor processing tools may be used to etch the second dielectric layer to form a second groove through the second dielectric layer (e.g., source / drain groove 1410), such that the second groove is located above at least a portion of the metal overlay, as described herein.

[0208] like Figure 19 As further shown, process 1900 may include forming source / drain contacts in the second recess such that the source / drain contacts are formed over at least a portion of the metal overlay (box 1950). For example, one or more semiconductor processing tools may be used to form source / drain contacts (e.g., source / drain contacts 1415, source / drain contacts 1415a, source / drain contacts 1415b) in the second recess such that the source / drain contacts are formed over at least a portion of the metal overlay, as described herein.

[0209] Process 1900 may include additional implementations, such as any single implementation or any combination of implementations of one or more other processes described below and / or described elsewhere herein.

[0210] In a first embodiment, the deposited metal capping layer includes a deposited metal capping layer such that the metal capping layer covers the top surface of the source / drain region across the entire lateral width in a third direction that is substantially perpendicular to the first and second directions.

[0211] In the second embodiment, alone or in combination with the first embodiment, the deposited metal capping layer includes a metal capping layer forming a first metal material, wherein forming source / drain contacts includes source / drain contacts forming a second metal material, and the first metal material and the second metal material are different metal materials.

[0212] In the third embodiment, either alone or in combination with one or more of the first and second embodiments, the first lateral width (e.g., dimension D1) of the metal overlay in the second direction is greater than the second lateral width (e.g., dimension D9) of the source / drain contact in the second direction.

[0213] In the fourth embodiment, alone or in combination with one or more of the first to third embodiments, process 1900 includes: selectively forming a hard mask layer (e.g., hard mask layer 1005) on a gate structure before forming the first groove, depositing excess material of the metal capping layer on the hard mask layer; and performing a planarization operation after forming the metal capping layer to remove excess material from the hard mask layer and the metal capping layer.

[0214] In the fifth embodiment, alone or in combination with one or more of the first to fourth embodiments, the deposited metal capping layer includes: depositing a metal material of the metal capping layer on a metal silicide layer and on the sidewalls of the first groove; and performing an etching operation to remove the metal material of the capping layer from the sidewalls of the first groove.

[0215] In the sixth embodiment, alone or in combination with one or more of the first to fifth embodiments, the deposition of the metal capping layer includes selectively depositing a material of the metal capping layer on a metal silicide layer, wherein a first deposition rate of the material of the metal capping layer on the metal silicide layer is greater than a second deposition rate of the material of the metal capping layer on the sidewall of the first groove.

[0216] Although Figure 19 An exemplary block diagram of process 1900 is shown, but in some embodiments, process 1900 includes... Figure 19 The boxes depicted in the text are compared to additional boxes, fewer boxes, different boxes, or boxes with different arrangements. Additionally or optionally, two or more boxes in process 1900 can be implemented in parallel.

[0217] In this way, a metal silicide layer is formed on the source / drain region of a transistor (e.g., a nanostructure transistor and / or another type of transistor) of a semiconductor device before the formation of the groove in which the source / drain contacts will be formed. This allows the coverage of the metal silicide layer on the surface of the source / drain region to be defined independently of the coverage of the source / drain contacts (which is defined by the groove in which the source / drain contacts are formed).

[0218] As described in more detail above, some embodiments described herein provide methods. The methods include forming a plurality of nanostructured channels arranged in a semiconductor device in a first direction and extending in the semiconductor device in a second direction generally perpendicular to the first direction. The methods include forming source / drain regions adjacent to the plurality of nanostructured channels in the second direction. The methods include depositing a first dielectric layer over and beside the source / drain regions. The methods include forming gate structures enclosing at least three sides of the plurality of nanostructured channels. The methods include etching the first dielectric layer to form a first groove through the first dielectric layer, such that the top surface of the source / drain regions is exposed through the groove. The methods include depositing a metal material on the top surface of the source / drain regions in the groove to form a metal silicide layer on the top surface of the source / drain regions. The methods include depositing a second dielectric layer in the groove, such that the second dielectric layer is located above the metal silicide layer and the source / drain regions. The methods include etching the second dielectric layer to form a second groove through the second dielectric layer, such that the second groove is located above at least a portion of the metal silicide layer. The method includes forming source / drain contacts in a second groove, such that the source / drain contacts are formed over at least a portion of the metal silicide layer.

[0219] As described in more detail above, some embodiments described herein provide methods. The methods include forming a plurality of nanostructured channels arranged in a semiconductor device in a first direction and extending in the semiconductor device in a second direction generally perpendicular to the first direction. The methods include forming source / drain regions adjacent to the plurality of nanostructured channels in the second direction. The methods include depositing a first dielectric layer over and beside the source / drain regions. The methods include forming gate structures enclosing at least three sides of the plurality of nanostructured channels. The methods include etching the first dielectric layer to form a first groove through the first dielectric layer, such that the top surface of the source / drain regions is exposed through the groove. The methods include depositing a metal material on the top surface of the source / drain regions in the groove to form a metal silicide layer on the top surface of the source / drain regions. The methods include depositing a metal capping layer on the metal silicide layer. The methods include depositing a second dielectric layer in the groove, such that the second dielectric layer is located above the metal capping layer and the source / drain regions. The methods include etching the second dielectric layer to form a second groove through the second dielectric layer, such that the second groove is located above at least a portion of the metal capping layer. The method includes forming source / drain contacts in a second groove, such that the source / drain contacts are formed over at least a portion of the metal overlay.

[0220] As described in more detail above, some embodiments described herein provide a semiconductor device. The semiconductor device includes a plurality of nanostructured channels disposed in a first direction. The semiconductor device includes a gate structure enclosing the plurality of nanostructured channels. The semiconductor device includes source / drain regions adjacent to the side of the gate structure and adjacent to the ends of the plurality of nanostructured channels in a second direction substantially perpendicular to the first direction. The semiconductor device includes a dielectric structure adjacent to the opposite side of the source / drain regions in a third direction substantially perpendicular to both the first and second directions. The semiconductor device includes a metal silicide layer located on the top surface of the source / drain regions. The semiconductor device includes source / drain contacts located above the metal silicide layer, wherein a first lateral width of the metal silicide layer in the third direction and a second lateral width of the source / drain contacts in the third direction are different lateral widths.

[0221] Some embodiments of this application provide a method for forming a semiconductor device, comprising: forming a plurality of nanostructured channels, the plurality of nanostructured channels being arranged in a first direction and extending in the semiconductor device in a second direction substantially perpendicular to the first direction; forming source / drain regions adjacent to the plurality of nanostructured channels in the second direction; depositing a first dielectric layer above and beside the source / drain regions; forming a gate structure enclosing at least three sides of the plurality of nanostructured channels; etching the first dielectric layer to form a first groove through the first dielectric layer, such that the top surface of the source / drain regions passes through the... A first groove is exposed; a metal material is deposited on the top surface of the source / drain region in the first groove to form a metal silicide layer on the top surface of the source / drain region; a second dielectric layer is deposited in the first groove such that the second dielectric layer is located above the metal silicide layer and the source / drain region; the second dielectric layer is etched to form a second groove through the second dielectric layer such that the second groove is located above at least a portion of the metal silicide layer; and a source / drain contact is formed in the second groove such that the source / drain contact is formed above at least a portion of the metal silicide layer.

[0222] In some embodiments, forming the second recess includes: forming the second recess such that the second recess is less than the entire metal silicide layer; and wherein forming the source / drain contact in the second recess includes: forming the source / drain contact in the second recess such that the source / drain contact is less than the entire metal silicide layer. In some embodiments, the method further includes: forming a spacer layer on the sidewall of the first recess before forming the metal silicide layer. In some embodiments, the method further includes: forming a hard mask layer on the gate structure before forming the first recess. In some embodiments, forming the first recess includes: forming the first recess such that the entire lateral width of the top surface of the source / drain region in the second direction is exposed through the first recess; and wherein forming the metal silicide layer includes: forming the metal silicide layer such that the metal silicide layer covers the entire lateral width of the top surface of the source / drain region.

[0223] Other embodiments of this application provide a method for forming a semiconductor device, comprising: forming a plurality of nanostructured channels arranged in a first direction and extending in the semiconductor device in a second direction substantially perpendicular to the first direction; forming source / drain regions adjacent to the plurality of nanostructured channels in the second direction; depositing a first dielectric layer over and beside the source / drain regions; forming a gate structure enclosing at least three sides of the plurality of nanostructured channels; and etching the first dielectric layer to form a first groove through the first dielectric layer, thereby exposing the top surface of the source / drain regions through the first groove. A metal material is deposited on the top surface of the source / drain region in the first groove to form a metal silicide layer on the top surface of the source / drain region; a metal capping layer is deposited on the metal silicide layer; a second dielectric layer is deposited in the groove such that the second dielectric layer is located above the metal capping layer and the source / drain region; the second dielectric layer is etched to form a second groove through the second dielectric layer such that the second groove is located above at least a portion of the metal capping layer; and a source / drain contact is formed in the second groove such that the source / drain contact is formed above at least a portion of the metal capping layer.

[0224] In some embodiments, depositing the metal capping layer includes depositing the metal capping layer such that the metal capping layer covers the entire lateral width of the top surface of the source / drain region in a third direction substantially perpendicular to the first direction and the second direction. In some embodiments, depositing the metal capping layer includes depositing the metal capping layer of a first metal material; wherein forming the source / drain contacts includes forming the source / drain contacts of a second metal material; and wherein the first metal material and the second metal material are different metal materials.

[0225] In some embodiments, the first lateral width of the metal capping layer in the second direction is greater than the second lateral width of the source / drain contacts in the second direction. In some embodiments, the method further includes: selectively forming a hard mask layer on the gate structure before forming the first recess, wherein excess material of the metal capping layer is deposited on the hard mask layer; and performing a planarization operation after forming the metal capping layer to remove the excess material from the hard mask layer and the metal capping layer. In some embodiments, depositing the metal capping layer includes: depositing a metal material of the metal capping layer on the metal silicide layer and on the sidewalls of the first recess; and performing an etching operation to remove the metal material of the capping layer from the sidewalls of the first recess. In some embodiments, depositing the metal capping layer includes: selectively depositing a material of the metal capping layer on the metal silicide layer, wherein a first deposition rate of the material of the metal capping layer on the metal silicide layer is greater than a second deposition rate of the material of the metal capping layer on the sidewalls of the first recess.

[0226] Further embodiments of this application provide a semiconductor device comprising: a plurality of nanostructured channels arranged in the semiconductor device in a first direction; a gate structure enclosing the plurality of nanostructured channels; a source / drain region adjacent to a side of the gate structure and an end of the plurality of nanostructured channels in a second direction substantially perpendicular to the first direction; a dielectric structure adjacent to the opposite side of the source / drain region in a third direction substantially perpendicular to both the first and second directions; a metal silicide layer located on the top surface of the source / drain region; and source / drain contacts located above the metal silicide layer, wherein a first lateral width of the metal silicide layer in the third direction and a second lateral width of the source / drain contacts in the third direction are different lateral widths.

[0227] In some embodiments, the metal silicide layer has a generally arcuate shape in the third direction. In some embodiments, the first lateral width of the metal silicide layer in the third direction is smaller than the second lateral width of the source / drain contact in the third direction. In some embodiments, the first lateral width of the metal silicide layer in the third direction is greater than the second lateral width of the source / drain contact in the third direction. In some embodiments, the semiconductor device further includes: a metal overlay layer on the metal silicide layer, wherein the source / drain contact is located on the metal overlay layer. In some embodiments, the source / drain contact comprises a first metal material; wherein the metal overlay layer comprises a second metal material; and wherein the first metal material and the second metal material are different metal materials. In some embodiments, the bottom surface of the first dielectric structure of the dielectric structure is located in the semiconductor device at a position lower than the bottom surface of the second dielectric structure of the dielectric structure. In some embodiments, the bottom surfaces of the first dielectric structure and the bottom surfaces of the second dielectric structure are located below the bottom surface of the source / drain region.

[0228] The terms "approximately" and "substantially" can refer to the value of a given quantity that varies within ±5% of the value (e.g., ±1%, ±2%, ±3%, ±4%, ±5% of the value). These values ​​are merely examples and are not intended to be limiting. It should be understood that, given embodiments of this disclosure, the terms "approximately" and "substantially" can refer to a percentage of the value of a given quantity.

[0229] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of the embodiments of this disclosure. Those skilled in the art should understand that they can readily use the embodiments of this disclosure as a basis to design or modify other processes and structures for performing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the embodiments of this disclosure, and that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the embodiments of this disclosure.

Claims

1. A method of forming a semiconductor device, comprising: forming a plurality of nanostructure channels arranged in a first direction in a semiconductor device and extending in a second direction in the semiconductor device that is substantially perpendicular to the first direction; forming a source / drain region adjacent to the plurality of nanostructure channels in the second direction; depositing a first dielectric layer over and alongside the source / drain region; forming a gate structure wrapping at least three sides of the plurality of nanostructure channels; etching the first dielectric layer to form a first recess through the first dielectric layer, such that a top surface of the source / drain region is exposed by the first recess; depositing a metal material on the top surface of the source / drain region in the first recess to form a metal silicide layer on the top surface of the source / drain region; depositing a second dielectric layer in the first recess, such that the second dielectric layer is located over the metal silicide layer and the source / drain region; etching the second dielectric layer to form a second recess through the second dielectric layer, such that the second recess is located over at least a portion of the metal silicide layer; and forming a source / drain contact in the second recess, such that the source / drain contact is formed over at least the portion of the metal silicide layer. Forming the second recess includes:

2. The method of claim 1, wherein, forming the second recess, such that the second recess is over less than the entire metal silicide layer; and wherein forming the source / drain contact in the second recess includes: forming the source / drain contact in the second recess, such that the source / drain contact is over less than the entire metal silicide layer.

3. The method of claim 1, further comprising: forming a spacer layer on sidewalls of the first recess prior to forming the metal silicide layer.

4. The method of claim 1, further comprising: forming a hardmask layer on the gate structure prior to forming the first recess. Forming the first recess includes:

5. The method of claim 1, wherein, forming the first recess, such that an entire lateral width of the top surface of the source / drain region in the second direction is exposed by the first recess; and wherein forming the metal silicide layer includes: forming the metal silicide layer, such that the metal silicide layer covers the entire lateral width of the top surface of the source / drain region.

6. A method of forming a semiconductor device, comprising: forming a plurality of nanostructure channels arranged in a first direction in a semiconductor device and extending in a second direction in the semiconductor device that is substantially perpendicular to the first direction; forming a source / drain region adjacent to the plurality of nanostructure channels in the second direction; depositing a first dielectric layer over and alongside the source / drain region; forming a gate structure wrapping at least three sides of the plurality of nanostructure channels; ​ etching the first dielectric layer to form a first recess through the first dielectric layer, thereby exposing a top surface of the source / drain region through the first recess; depositing a metal material on the top surface of the source / drain region in the first recess to form a metal silicide layer on the top surface of the source / drain region; depositing a metal cap layer on the metal silicide layer; depositing a second dielectric layer in the recess, thereby causing the second dielectric layer to be on the metal cap layer and the source / drain region; etching the second dielectric layer to form a second recess through the second dielectric layer, thereby causing the second recess to be on at least a portion of the metal cap layer; and forming a source / drain contact in the second recess, thereby causing the source / drain contact to be formed on at least the portion of the metal cap layer.

7. The method of claim 6, wherein, depositing the metal cap layer includes: depositing the metal cap layer, thereby causing the metal cap layer to cover an entire lateral width of the top surface of the source / drain region in a third direction that is substantially perpendicular to the first direction and the second direction.

8. The method of claim 6, wherein, depositing the metal cap layer includes: depositing the metal cap layer of a first metal material; wherein forming the source / drain contact includes: forming the source / drain contact of a second metal material; and wherein the first metal material and the second metal material are different metal materials.

9. The method of claim 6, wherein, a first lateral width of the metal cap layer in the second direction is greater than a second lateral width of the source / drain contact in the second direction.

10. A semiconductor device, comprising: a plurality of nanostructure channels arranged in a first direction in the semiconductor device; a gate structure wrapping the plurality of nanostructure channels; a source / drain region adjacent to sides of the gate structure and adjacent to ends of the plurality of nanostructure channels in a second direction that is substantially perpendicular to the first direction; a dielectric structure adjacent to opposite sides of the source / drain region in a third direction that is substantially perpendicular to the first direction and the second direction; a metal silicide layer on a top surface of the source / drain region; and a source / drain contact on the metal silicide layer, wherein a first lateral width of the metal silicide layer in the third direction and a second lateral width of the source / drain contact in the third direction are different lateral widths. ​

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