Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof, and the structure comprises a substrate which comprises an N-type device region and a P-type device region; the working fin part protrudes from the substrate of the P-type device region; the lug boss protrudes on the substrate of the N-type device region, and the surface of the lug boss is provided with an isolation layer; the channel layer is located in the N-type device region and covers the isolation layer; and the gate structure is located on the substrate and stretches across the working fin part and the protruding part, and the gate structure covers the channel layer of the N-type device region and the surface of the working fin part of the P-type device region. The working performance of the semiconductor structure can be improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0002] As the feature size of traditional MOSFETs decreases and integration density increases, the operating voltage and threshold voltage of the devices gradually decrease. The resulting short-channel effect becomes more pronounced, and the reduction in drain-induced barrier and source-drain band tunneling lead to increased leakage current and power consumption. Furthermore, due to the thermionic current mechanism of MOSFETs, their subthreshold slope is limited by thermoelectric potential, with a theoretical limit of 60mV / dec, which cannot be reduced with further reduction in device size. This leads to a further increase in leakage current and exacerbates power consumption issues. Currently, power consumption is a key concern in the design of small-size logic devices, thus attracting widespread attention to research on ultra-steep subthreshold slope devices and related technologies. Summary of the Invention

[0003] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, which is beneficial to improving the working performance of the semiconductor structure.

[0004] To address the aforementioned problems, embodiments of the present invention provide a semiconductor structure comprising: a substrate including an N-type device region and a P-type device region; a working fin protruding from the substrate in the P-type device region; a protrusion protruding from the substrate in the N-type device region, the surface of the protrusion having an isolation layer; a channel layer located in the N-type device region and covering the isolation layer; and a gate structure located on the substrate and spanning the working fin and the protrusion, the gate structure covering the channel layer in the N-type device region and the surface of the working fin in the P-type device region.

[0005] Optionally, all protrusions may be made of insulating layers.

[0006] Optionally, the protrusion includes a working fin that protrudes from the substrate of the N-type device region and an isolation layer covering the surface of the working fin.

[0007] Optionally, in the N-type device region, the isolation layer and the working fin are an integral structure protruding from the substrate, or the working fin is a structure protruding from the substrate, and the isolation layer is a structure located on the substrate and covering the working fin.

[0008] Optionally, the thickness of the isolation layer is greater than or equal to

[0009] Optionally, the material of the working fins includes silicon, germanium, silicon germanide, or group III-V semiconductor materials; the material of the isolation layer includes silicon oxide.

[0010] Optionally, the channel layer can be made of a two-dimensional material.

[0011] Optionally, the two-dimensional material is a two-dimensional transition metal dichalcogenide.

[0012] Accordingly, embodiments of the present invention also provide a method for forming a semiconductor structure, comprising: providing a substrate, wherein a protruding working fin is formed on the substrate, the substrate including an N-type device region and a P-type device region; forming an isolation layer located on the surface of the working fin in the N-type device region; forming a channel layer covering the isolation layer in the N-type device region; and forming a gate structure spanning the working fin on the substrate, the gate structure covering the channel layer in the N-type device region and the surface of the working fin in the P-type device region.

[0013] Optionally, in the step of providing the substrate, an isolation layer covering the working fin is further formed on the substrate; before forming the isolation layer on the surface of the working fin located in the N-type device region, the method further includes: removing the isolation layer covering the working fin of the N-type device region; before forming the gate structure across the working fin on the substrate, the method further includes: removing the isolation layer covering the working fin of the P-type device region.

[0014] Optionally, the step of forming an isolation layer on the surface of the working fin in the N-type device region includes: modifying the working fin in the N-type device region by modifying a portion of the working fin surface thickness into an isolation layer, or modifying the entire working fin into an isolation layer.

[0015] Optionally, an oxidation process can be used to modify the working fins of the N-type device region.

[0016] Optionally, the step of forming an isolation layer on the surface of the working fins in the N-type device region further includes: forming an isolation layer covering the surface of the working fins in the N-type device region.

[0017] Optionally, an isolation layer covering the working fin surface of the N-type device region can be formed using an atomic layer deposition process.

[0018] Optionally, in the step of forming an isolation layer on the surface of the working fins in the N-type device region, the thickness of the isolation layer is greater than or equal to...

[0019] Optionally, in the step of forming a channel layer covering the isolation layer in the N-type device region, the material of the channel layer is a two-dimensional material.

[0020] Optionally, in the step of forming a channel layer covering the isolation layer in the N-type device region, the two-dimensional material is a two-dimensional transition metal dichalcogenide.

[0021] Optionally, the step of forming a channel layer covering the isolation layer in the N-type device region includes: forming an isolation layer covering the N-type device region, the working fin surface of the P-type device region, and a channel material layer on the top surface of the substrate; removing the channel material layer in the P-type device region and retaining the channel material layer in the N-type device region as the channel layer.

[0022] Optionally, before forming a gate structure spanning the working fin on the substrate, the method further includes: forming a channel layer covering the N-type device region and a gate oxide layer on the surface of the working fin covering the P-type device region; in the step of forming a gate structure spanning the working fin on the substrate, the gate structure covers the gate oxide layer.

[0023] Optionally, in the step of providing the substrate, the material of the working fin includes silicon, germanium, silicon germanide, or a group III-V semiconductor material; in the step of forming an isolation layer on the surface of the working fin located in the N-type device region, the material of the isolation layer includes silicon oxide.

[0024] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0025] In the semiconductor structure provided by this invention, the working fin protrudes from the substrate of the P-type device region, and the protrusion protrudes from the substrate of the N-type device region. The surface of the protrusion has an isolation layer. The channel layer is located in the N-type device region and covers the isolation layer. The gate structure is located on the substrate and spans the working fin and the protrusion. The gate structure covers the channel layer of the N-type device region and the surface of the working fin of the P-type device region. In this invention, for the N-type device region, the protrusion serves as a support, the isolation layer is used to isolate the channel layer from the protrusion, and the channel layer serves as the channel of the N-type device region. By forming a channel layer with a shape that covers the protrusion, it is beneficial to form a thinner channel layer, thereby increasing the turn-on current when the device is working, and thus helping to reduce the power consumption of the device at high frequency. For the P-type device region, using the working fin as the channel helps to reduce modifications to the existing structure. Therefore, in this invention, the working performance of the semiconductor structure can be improved while minimizing modifications to the existing structure.

[0026] In the formation method provided by the embodiments of the present invention, an isolation layer is formed on the surface of the working fin of the N-type device region, a channel layer covering the isolation layer is formed in the N-type device region, and a gate structure spanning the working fin is formed on the substrate. The gate structure covers the channel layer of the N-type device region and the surface of the working fin of the P-type device region. In the embodiments of the present invention, for the N-type device region, the working fin serves as a support, the isolation layer is used to isolate the channel layer from the working fin, and the channel layer serves as the channel of the N-type device region. By forming a channel layer with a shape that covers the surface of the working fin, it is beneficial to form a thinner channel layer, thereby increasing the turn-on current of the device during operation and thus helping to reduce the power consumption of the device at high frequency. For the P-type device region, using the working fin as the channel helps to reduce modifications to the existing structure. Therefore, in the embodiments of the present invention, the operating performance of the semiconductor structure can be improved while minimizing modifications to the existing structure. Attached Figure Description

[0027] Figure 1This is a schematic diagram of a corresponding embodiment of the semiconductor structure of the present invention;

[0028] Figure 2 This is a schematic diagram of another embodiment of the semiconductor structure of the present invention;

[0029] Figure 3 This is a schematic diagram of another embodiment of the semiconductor structure of the present invention;

[0030] Figures 4 to 10 This is a schematic diagram of the structure corresponding to each step in one embodiment of the method for forming a semiconductor structure of the present invention;

[0031] Figure 11 This is a schematic diagram of the structure corresponding to each step in another embodiment of the method for forming a semiconductor structure of the present invention;

[0032] Figure 12 This is a schematic diagram of the structure corresponding to each step in another embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0033] As can be seen from the background technology, it is difficult to achieve good working performance in traditional semiconductor structures.

[0034] To address the technical problem, embodiments of the present invention provide a semiconductor structure, comprising: a substrate including an N-type device region and a P-type device region; a working fin protruding from the substrate in the P-type device region; a protrusion protruding from the substrate in the N-type device region, the surface of the protrusion having an isolation layer; a channel layer located in the N-type device region and covering the isolation layer; and a gate structure located on the substrate and spanning the working fin and the protrusion, the gate structure covering the channel layer of the N-type device region and the surface of the working fin of the P-type device region.

[0035] In this embodiment of the invention, for the N-type device region, the protrusion serves as a support, and the isolation layer is used to isolate the channel layer from the protrusion. The channel layer serves as the channel of the N-type device region. By forming a channel layer with a shape that covers the protrusion, it is beneficial to form a thinner channel layer, thereby increasing the turn-on current when the device is working, and thus helping to reduce the power consumption of the device at high frequencies. For the P-type device region, using the working fin as the channel helps to reduce modifications to the existing structure. Thus, in this embodiment of the invention, the working performance of the semiconductor structure can be improved while minimizing modifications to the existing structure.

[0036] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0037] Figure 1 This is a schematic diagram of a semiconductor structure according to one embodiment of the present invention.

[0038] refer to Figure 1 The semiconductor structure includes: a substrate 100, including an N-type device region 100N and a P-type device region 100P; a working fin 220, protruding from the substrate 100 of the P-type device region 100P; a protrusion 700, protruding from the substrate 100 of the N-type device region 100N, the surface of the protrusion 700 having an isolation layer 400; a channel layer 510, located in the N-type device region 100N and covering the isolation layer 400; and a gate structure 600, located on the substrate 100 and spanning the working fin 220 and the protrusion 700, the gate structure 600 covering the channel layer 510 of the N-type device region 100N and the surface of the working fin 220 of the P-type device region 100P.

[0039] The substrate 100 provides the basis for the process operation of forming semiconductor structures, wherein the N-type device region 100N is used to form N-type transistors (NMOS) and the P-type device region 100P is used to form P-type transistors (PMOS).

[0040] In this embodiment, the substrate 100 includes a substrate 110 and a shallow trench isolation (STI) structure 120 located on the substrate 110.

[0041] Substrate 110 is used to provide a basis for process operations for the formation of semiconductor structures.

[0042] In this embodiment, the substrate 110 is made of silicon. In other embodiments, the substrate may also be made of germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium dihydrogen phosphate, or other materials. The substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrates. The substrate material may be suitable for process requirements or easy to integrate.

[0043] Shallow trench isolation structure 120 is used to achieve insulation between different devices. For example, in CMOS manufacturing processes, shallow trench isolation structure 120 is usually formed between NMOS transistors and PMOS transistors.

[0044] In this embodiment, the material of the shallow trench isolation structure 120 includes silicon oxide.

[0045] The working fin 220 is used as a channel for the PMOS transistor in the P-type device region 100P.

[0046] Specifically, in this embodiment, the semiconductor structure includes a fin 200 that protrudes from the substrate 110 and extends beyond the base 100, wherein the fin 200 that protrudes from the substrate 110 and is covered by the shallow trench isolation structure 120 is the bottom fin 210, and the fin 200 that protrudes from the base 100 is the working fin 220.

[0047] In this embodiment, the material of the working fin 220 includes silicon, germanium, silicon germanide, or group III-V semiconductor materials. As an example, the material of the working fin 220 is silicon. In other embodiments, the material of the working fin is determined according to the type and performance of the transistor.

[0048] Accordingly, in this embodiment, the material of the fin 200 includes silicon, germanium, silicon germanide, or group III-V semiconductor materials. As an example, the material of the fin 200 is silicon. In other embodiments, the material of the fin is determined according to the type and performance of the transistor.

[0049] The protrusion 700 is used to provide support for the channel layer 510 of the NMOS transistor in the N-type device region 100N.

[0050] In this embodiment, the surface of the protrusion 700 has an isolation layer 400, which means that an isolation layer 400 located on the surface is formed in the protrusion 700.

[0051] The isolation layer 400 is used to isolate the structure covered by the isolation layer 400 in the channel layer 510 and the protrusion 700 of the NMOS transistor.

[0052] In this embodiment, the protrusion 700 includes a working fin 220 protruding from the N-type device region 100N substrate 100 and an isolation layer 400 covering the surface of the working fin 220.

[0053] The working fin 220 of the N-type device region 100N is used to provide support for the isolation layer 400 and the channel layer 510.

[0054] Correspondingly, the isolation layer 400 is used to isolate the channel layer 510 of the N-type device region 100N from the working fin 220. That is, the working fin 220 of the N-type device region 100N is a pseudo-fin and does not serve to provide a channel for the NMOS transistor.

[0055] In this embodiment, in the N-type device region 100N, the isolation layer 400 and the working fin 220 are an integral structure protruding from the substrate 100.

[0056] The isolation layer 400 and the working fin 220 are an integral structure protruding from the substrate 100. This means that the protrusion 700 formed by the isolation layer 400 and the working fin 220 in the N-type device region 100N is similar in shape and size to the working fin 220 in the P-type device region 100P. In other words, in the semiconductor manufacturing process, the working fin 220 is formed first, and then a portion of the working fin 220 in the N-type device region 100N is modified into the isolation layer 400.

[0057] Specifically, in this embodiment, in the N-type device region 100N, the isolation layer 400 and the fin 200 are an integral structure protruding from the substrate 110.

[0058] In this embodiment, the thickness of the isolation layer 400 is greater than or equal to... The isolation layer 400 can then have sufficient thickness to achieve a better isolation effect.

[0059] In this embodiment, the material of the isolation layer 400 includes silicon oxide.

[0060] Using silicon dioxide to form an isolation layer 400 can achieve a good isolation effect.

[0061] In this embodiment, the working fin 220 is made of silicon, so the working fin 220 can be oxidized to modify a portion of the working fin 220 into silicon oxide as an isolation layer 400.

[0062] The channel layer 510 is used to provide a channel for the NMOS transistors in the N-type device region 100N.

[0063] In this embodiment, for the N-type device region 100N, the protrusion 700 serves as a support, and the isolation layer 400 is used to isolate the channel layer 510 from the protrusion 700. The channel layer 510 serves as the channel for the N-type device region 100N. By forming a channel layer 510 with a shape that covers the protrusion 700, it is beneficial to form a thinner channel layer 510, thereby increasing the turn-on current when the device is working, and thus helping to reduce the power consumption of the device at high frequency. For the P-type device region 100P, the working fin 220 is used as the channel, which helps to reduce the modification of the existing structure. Thus, in this embodiment, the working performance of the semiconductor structure can be improved while minimizing the modification of the existing structure.

[0064] In this embodiment, the channel layer 510 is made of a two-dimensional (2D) material.

[0065] Two-dimensional materials have the characteristic of maintaining high electron mobility even when thin. Therefore, using two-dimensional materials to form the channel layer 510 of an NMOS transistor can result in a thinner channel layer 510. At the same time, the channel layer 510 has high electron mobility, which is beneficial to improving the operating performance of the NMOS transistor. Furthermore, the thinner channel layer 510 can increase the turn-on current of the device during operation, which is beneficial to reducing the power consumption of the device at high frequencies. Meanwhile, the PMOS transistor still uses silicon as the channel, and silicon can enhance the operating performance of the PMOS transistor.

[0066] In this embodiment, the two-dimensional material is a two-dimensional transition metal dichalcogenide (2D TMD).

[0067] Two-dimensional transition metal dichalcogenides (2D TMDs) are two-dimensional layered materials composed of transition metal elements (such as Mo, W, etc.) and chalcogen elements (such as S, Se, Te). Two-dimensional transition metal dichalcogenides have good conductivity and carrier mobility, so using two-dimensional transition metal dichalcogenides to form the channel layer 510 is beneficial to improving the operating performance of NMOS transistors.

[0068] The gate structure 600 is used to control the opening and closing of the transistor channel.

[0069] In this embodiment, the gate structure 600 includes a gate dielectric layer and a gate electrode layer located on the gate dielectric layer.

[0070] The gate dielectric layer is used to isolate the gate electrode layer from the channel layer 510, and the gate electrode layer from the working fin 220.

[0071] The gate dielectric layer material includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, and La2O3. In this embodiment, the gate dielectric layer includes a high-k gate dielectric layer, and the material of the high-k gate dielectric layer includes a high-k dielectric material. A high-k dielectric material refers to a dielectric material with a relative permittivity greater than that of silicon oxide. Specifically, the material of the high-k gate dielectric layer includes HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3, etc.

[0072] In this embodiment, the gate structure 600 is a metal gate structure. Therefore, the material of the gate electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN and TiAlC.

[0073] Specifically, the gate electrode layer includes a work function layer (not shown) and an electrode layer (not shown) located on the work function layer. The work function layer is used to adjust the threshold voltage of the transistor, and the electrode layer is used to bring out the electrical properties of the metal gate structure.

[0074] In other embodiments, the gate electrode layer may also consist of only the work function layer.

[0075] In this embodiment, a gate oxide layer 610 is formed between the gate structure 600 and the channel layer 510 of the N-type device region 100N, between the gate structure 600 and the working fin 220 of the P-type device region 100P, and between the gate structure 600 and the substrate 100. Specifically, the material of the gate oxide layer 610 can be silicon oxide.

[0076] In other embodiments, the gate structure may also be a polysilicon gate structure, depending on process requirements.

[0077] In other embodiments, the gate structure may also be a pseudo-gate structure, occupying space for the formation of the gate structure of subsequent devices.

[0078] Figure 2 This is a schematic diagram of another embodiment of the semiconductor structure of the present invention.

[0079] The similarities between this embodiment and the previous embodiments will not be repeated here. The difference between this embodiment and the previous embodiments is that all the protrusions are isolation layers.

[0080] refer to Figure 2 The raised part 702 is entirely composed of the isolation layer 402.

[0081] The protrusions 702 are all isolation layers 402, which provide support for the formation of the channel layer 512 and isolate the channel layer 512 from the substrate 102.

[0082] Specifically, in this embodiment, in the semiconductor manufacturing process, after the working fin 222 is formed first, the working fin 222 of the N-type device region 102N is completely modified into an isolation layer 402, thereby forming a protrusion 702 that is entirely an isolation layer 402.

[0083] Figure 3 This is a schematic diagram of another embodiment of the semiconductor structure of the present invention.

[0084] The similarities between this embodiment and the previous embodiments will not be repeated here. The difference between this embodiment and the previous embodiments is that in the N-type device region, the working fins and the isolation layer are not an integral structure.

[0085] refer to Figure 3 In the N-type device region 100N, the working fin 221 is a structure that protrudes from the substrate 101, and the isolation layer 401 is a structure that is located on the substrate 101 and covers the working fin 221.

[0086] In this embodiment, in the N-type device region 100N, the working fin 221 and the isolation layer 401 are separately formed structures. That is, the working fin 221 and the bottom fin 211 together form an integral structure fin 201 protruding from the substrate 111, while the isolation layer 401 is a structure covering the fin 201, located outside the fin 201 and in contact with the surface of the substrate 101. Specifically, in the semiconductor process, the working fin 221 is formed first, and then the isolation layer 401 is deposited on the N-type device region 101N to isolate the channel layer 511 and the working fin 221.

[0087] Figures 4 to 10 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.

[0088] refer to Figure 4 A substrate 100 is provided, on which protruding working fins 220 are formed. The substrate 100 includes an N-type device region 100N and a P-type device region 100P.

[0089] The substrate 100 provides the basis for the process operation of forming semiconductor structures, wherein the N-type device region 100N is used to form N-type transistors (NMOS) and the P-type device region 100P is used to form P-type transistors (PMOS).

[0090] In this embodiment, the substrate 100 includes a substrate 110 and a shallow trench isolation (STI) structure 120 located on the substrate 110.

[0091] Substrate 110 is used to provide a basis for process operations for the formation of semiconductor structures.

[0092] In this embodiment, the substrate 110 is made of silicon. In other embodiments, the substrate may also be made of germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium dihydrogen phosphate, or other materials. The substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrates. The substrate material may be suitable for process requirements or easy to integrate.

[0093] Shallow trench isolation structure 120 is used to achieve insulation between different devices. For example, in CMOS manufacturing processes, shallow trench isolation structure 120 is usually formed between NMOS transistors and PMOS transistors.

[0094] In this embodiment, the material of the shallow trench isolation structure 120 includes silicon oxide.

[0095] The working fin 220 of the P-type device region 100P is used as the channel of the PMOS transistor in the P-type device region 100P, and the working fin 220 of the N-type device region 100N is used to provide support for the subsequent formation of the isolation layer and the channel layer.

[0096] Specifically, in this embodiment, the semiconductor structure includes a fin 200 that protrudes from the substrate 110 and extends beyond the base 100, wherein the fin 200 that protrudes from the substrate 110 and is covered by the shallow trench isolation structure 120 is the bottom fin 210, and the fin 200 that protrudes from the base 100 is the working fin 220.

[0097] In this embodiment, the material of the working fin 220 includes silicon, germanium, silicon germanide, or group III-V semiconductor materials. As an example, the material of the working fin 220 is silicon. In other embodiments, the material of the working fin is determined according to the type and performance of the transistor.

[0098] Accordingly, in this embodiment, the material of the fin 200 includes silicon, germanium, silicon germanide, or group III-V semiconductor materials. As an example, the material of the fin 200 is silicon. In other embodiments, the material of the fin is determined according to the type and performance of the transistor.

[0099] In this embodiment, during the step of providing the substrate 100, an insulating layer 300 covering the working fin 220 is also formed on the substrate 100.

[0100] The isolation layer 300 is used to protect the working fins 220 of the P-type device region 100P when the isolation layer and channel layer are subsequently formed in the N-type device region 100N.

[0101] In this embodiment, the material of the insulating layer 300 includes silicon oxide.

[0102] refer to Figure 5 Before the subsequent formation of the isolation layer on the surface of the working fin 220 of the N-type device region 100N, the method further includes: removing the isolation layer 300 covering the working fin 220 of the N-type device region 100N.

[0103] The insulating layer 300 covering the working fin 220 of the N-type device region 100N is removed to expose the working fin 220 of the N-type device region 100N, in preparation for the subsequent formation of an insulating layer on the surface of the working fin 220 of the N-type device region 100N. The insulating layer 300 of the P-type device region 100P is retained to protect the working fin 220 of the P-type device region 100P when the insulating layer is subsequently formed on the surface of the working fin 220 of the N-type device region 100N.

[0104] Specifically, in this embodiment, in the step of removing the isolation layer 300 covering the working fin 220 of the N-type device region 100N, the isolation layer 300 on the top surface of the substrate 100 of the N-type device region 100N is also removed, providing a larger process window for the subsequent formation of the isolation layer and the channel layer in the N-type device region 100N.

[0105] refer to Figure 6 An isolation layer 400 is formed on the surface of the working fin 220 located in the N-type device region 100N.

[0106] The isolation layer 400 is used to isolate the channel layer and the working fin 220 subsequently formed in the NMOS transistor.

[0107] In this embodiment, in the step of forming the isolation layer 400 on the surface of the working fin 220 in the N-type device region 100N, the thickness of the isolation layer 400 is greater than or equal to The isolation layer 400 can then have sufficient thickness to achieve a better isolation effect.

[0108] In this embodiment, in the step of forming the isolation layer 400 on the surface of the working fin 220 in the N-type device region 100N, the material of the isolation layer 400 includes silicon oxide.

[0109] Using silicon dioxide to form an isolation layer 400 can achieve a good isolation effect.

[0110] In this embodiment, the step of forming an isolation layer 400 on the surface of the working fin 220 in the N-type device region 100N includes: modifying the working fin 220 in the N-type device region 100N to modify a portion of the working fin 220 on the surface of the working fin 220 into an isolation layer 400.

[0111] The working fin 220 of the N-type device region 100N is modified by converting a portion of the working fin 220 on the surface into an isolation layer 400.

[0112] In this embodiment, an oxidation process is used to modify the working fin 220 of the N-type device region 100N.

[0113] The oxidation process is relatively simple, and the isolation layer 400 can be formed using the already formed working fin 220.

[0114] Specifically, in this embodiment, the working fin 220 is made of silicon, and an oxidation process can be used to oxidize a portion of the working fin 220 to silicon oxide to form an isolation layer 400.

[0115] Reference Figure 7 and Figure 8 A channel layer 510 is formed in the N-type device region 100N, covering the isolation layer 400.

[0116] The channel layer 510 is used to provide a channel for the NMOS transistor.

[0117] Specifically, in this embodiment, in the step of forming a channel layer 510 covering the isolation layer 400 in the N-type device region 100N, the channel layer 510 further extends to cover the top surface of the substrate 100 of the N-type device region 100N.

[0118] In this embodiment, for the N-type device region 100N, the working fin 220 serves as a support, and the isolation layer 400 is used to isolate the channel layer 510 from the working fin 220. The channel layer 510 serves as the channel for the N-type device region 100N. By forming a channel layer 510 with a shape that covers the surface of the isolation layer 400 of the working fin 220, it is beneficial to form a thinner channel layer 510, thereby increasing the turn-on current when the device is working, and thus helping to reduce the power consumption of the device at high frequency. For the P-type device region 100P, using the working fin 220 as the channel helps to reduce modifications to the existing structure. Thus, in this embodiment, the working performance of the semiconductor structure can be improved while minimizing modifications to the existing structure.

[0119] In this embodiment, in the step of forming a channel layer 510 covering the isolation layer 400 in the N-type device region 100N, the material of the channel layer 510 is a two-dimensional (2D) material.

[0120] Two-dimensional materials have the characteristic of maintaining high electron mobility even when thin. Therefore, using two-dimensional materials to form the channel layer 510 of an NMOS transistor can result in a thinner channel layer 510. At the same time, the channel layer 510 has high electron mobility, which is beneficial to improving the operating performance of the NMOS transistor. Furthermore, the thinner channel layer 510 can increase the turn-on current of the device during operation, which is beneficial to reducing the power consumption of the device at high frequencies. Meanwhile, the PMOS transistor still uses silicon as the channel, and silicon can enhance the operating performance of the PMOS transistor.

[0121] In this embodiment, in the step of forming a channel layer 510 covering the isolation layer 400 in the N-type device region 100N, the two-dimensional material is a two-dimensional transition metal dichalcogenide (2DTMD).

[0122] Two-dimensional transition metal dichalcogenides (2D TMDs) are two-dimensional layered materials composed of transition metal elements (such as Mo, W, etc.) and chalcogen elements (such as S, Se, Te). Two-dimensional transition metal dichalcogenides have good conductivity and carrier mobility, so using two-dimensional transition metal dichalcogenides to form the channel layer 510 is beneficial to improving the operating performance of NMOS transistors.

[0123] Specifically, refer to Figure 7 The step of forming a channel layer 510 covering the isolation layer 400 in the N-type device region 100N includes forming an isolation layer 400 covering the N-type device region 100N, the surface of the working fin 220 of the P-type device region 100P, and a channel material layer 500 covering the top surface of the substrate 100.

[0124] The channel material layer 500 is used to form the channel layer 510.

[0125] Specifically, in this embodiment, the channel material layer 500 in the P-type device region 100P covers the isolation layer 300 covering the working fin 200 in the P-type device region.

[0126] refer to Figure 8 Remove the channel material layer 500 of the P-type device region 100P, and retain the channel material layer 500 of the N-type device region 100N as the channel layer 510.

[0127] In this embodiment, during the step of removing the channel material layer 500 of the P-type device region 100P, the insulating layer 300 protects the working fin portion 220 of the P-type device region 100P.

[0128] refer to Figure 9 Before forming a gate structure across the working fin 220 on the substrate 100, the method further includes removing the isolation layer 300 covering the working fin 220 of the P-type device region 100P.

[0129] Remove the insulating layer 300 covering the working fin 220 of the P-type device region 100P to prepare for the subsequent formation of the gate structure.

[0130] refer to Figure 10 Before forming a gate structure spanning the working fin 220 on the substrate 100, the method further includes forming a channel layer 510 covering the N-type device region 100N and a gate oxide layer 610 on the surface of the working fin 220 covering the P-type device region 100P.

[0131] The gate oxide layer 610 is used to isolate the subsequently formed gate structure from the channel layer 510 of the N-type device region 100N and the working fin 220 of the P-type device region 100P.

[0132] In this embodiment, the gate oxide layer 610 is made of silicon oxide.

[0133] Continue to refer to Figure 10 A gate structure 600 is formed on the substrate 100, spanning the working fin 220. The gate structure 600 covers the channel layer 510 of the N-type device region 100N and the surface of the working fin 220 of the P-type device region 100P.

[0134] The gate structure 600 is used to control the opening and closing of the transistor channel.

[0135] In this embodiment, the gate structure 600 includes a gate dielectric layer and a gate electrode layer located on the gate dielectric layer.

[0136] The gate dielectric layer is used to isolate the gate electrode layer from the channel layer 510, and the gate electrode layer from the working fin 220.

[0137] The gate dielectric layer material includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, and La2O3. In this embodiment, the gate dielectric layer includes a high-k gate dielectric layer, and the material of the high-k gate dielectric layer includes a high-k dielectric material. A high-k dielectric material refers to a dielectric material with a relative permittivity greater than that of silicon oxide. Specifically, the material of the high-k gate dielectric layer includes HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3, etc.

[0138] In this embodiment, the gate structure 600 is a metal gate structure. Therefore, the material of the gate electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN and TiAlC.

[0139] Specifically, the gate electrode layer includes a work function layer (not shown) and an electrode layer (not shown) located on the work function layer. The work function layer is used to adjust the threshold voltage of the transistor, and the electrode layer is used to bring out the electrical properties of the metal gate structure.

[0140] In other embodiments, the gate electrode layer may also consist of only the work function layer.

[0141] In other embodiments, the gate structure may also be a polysilicon gate structure, depending on process requirements.

[0142] In other embodiments, the gate structure may also be a pseudo-gate structure, occupying space for the formation of the gate structure of subsequent devices.

[0143] Figure 11 This is a schematic diagram of the structure corresponding to each step in another embodiment of the method for forming the semiconductor structure of the present invention.

[0144] The similarities between this embodiment and the previous embodiments will not be repeated here. The difference between this embodiment and the previous embodiments is that the entire working fin is modified into an isolation layer.

[0145] refer to Figure 11 The working fin 222 of the N-type device region 102N is modified to completely transform the working fin 222 into an isolation layer 402.

[0146] Specifically, in this embodiment, the working fins 222 of the N-type device region 102N are all subjected to an oxidation process to form an isolation layer 402.

[0147] Figure 12 This is a schematic diagram of the structure corresponding to each step in another embodiment of the semiconductor structure formation method of the present invention.

[0148] The similarities between this embodiment and the previous embodiments will not be repeated here. The difference between this embodiment and the previous embodiments lies in the steps for forming the isolation layer on the surface of the working fins in the N-type device region.

[0149] refer to Figure 12 The step of forming an isolation layer 401 on the surface of the working fin 221 of the N-type device region 101N further includes forming an isolation layer 401 covering the surface of the working fin 221 of the N-type device region 101N.

[0150] An isolation layer 401 is formed to cover the surface of the working fin 221 of the N-type device region 101N, that is, an isolation layer 401 is formed outside the fin 201 where the working fin 221 is located, and the isolation layer 401 is in contact with the top surface of the substrate 101.

[0151] In this embodiment, an isolation layer 401 is formed by atomic layer deposition to cover the surface of the working fin 221 of the N-type device region 100N.

[0152] The isolation layer 401 formed by atomic layer deposition has good thickness uniformity and good step coverage capability, which enables the isolation layer 401 to conformally cover the top surface and sidewall of the working fin 221 of the N-type device region 101N.

[0153] Specifically, in this embodiment, the step of forming an isolation layer 401 covering the surface of the working fin 221 of the N-type device region 101N includes: forming an isolation material layer covering the surface of the working fin 221 of the N-type device region 101N, the surface of the isolation layer 301 of the P-type device region 100P, and the top surface of the substrate 101; removing the isolation material layer covering the surface of the isolation layer 301 of the P-type device region 100P and the top surface of the substrate 101, and retaining the isolation material layer covering the surface of the working fin 221 of the N-type device region 101N as the isolation layer 401.

[0154] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized by, Comprising: a substrate comprising an N-type device region and a P-type device region; an active fin standing up from the substrate of the P-type device region; a protrusion standing up from the substrate of the N-type device region, the protrusion surface having an isolation layer; a channel layer in the N-type device region and covering the isolation layer; a gate structure on the substrate and across the active fin and protrusion, the gate structure covering the channel layer of the N-type device region and the active fin surface of the P-type device region.

2. The semiconductor structure of claim 1, wherein, The protrusion is all the isolation layer.

3. The semiconductor structure of claim 1, wherein, The protrusion comprises an active fin standing up from the substrate of the N-type device region and an isolation layer covering the active fin surface.

4. The semiconductor structure of claim 3, wherein, In the N-type device region, the isolation layer and the active fin are an integral structure protruding from the substrate, or the active fin is a structure protruding from the substrate, and the isolation layer is a structure on the substrate and covering the active fin.

5. The semiconductor structure of claim 1, wherein, The isolation layer thickness is greater than or equal to 6. The semiconductor structure of claim 1, wherein, The material of the active fin comprises silicon, germanium, silicon germanium or group III-V semiconductor material; the material of the isolation layer comprises silicon oxide.

7. The semiconductor structure of claim 1, wherein, The material of the channel layer is a two-dimensional material.

8. The semiconductor structure of claim 7, wherein, The two-dimensional material is a two-dimensional transition metal disulfide.

9. A method of forming a semiconductor structure, comprising: Comprising: providing a substrate having an active fin standing up therefrom, the substrate comprising an N-type device region and a P-type device region; forming an isolation layer on the active fin surface of the N-type device region; forming a channel layer covering the isolation layer in the N-type device region; forming a gate structure on the substrate and across the active fin, the gate structure covering the channel layer of the N-type device region and the active fin surface of the P-type device region.

10. The method of forming a semiconductor structure of claim 9, wherein, In the step of providing the substrate, an insulation layer covering the active fin is also formed on the substrate; before forming the isolation layer on the active fin surface of the N-type device region, further comprising: removing the insulation layer covering the active fin of the N-type device region; before forming the gate structure on the substrate and across the active fin, further comprising: removing the insulation layer covering the active fin of the P-type device region.

11. The method of forming a semiconductor structure of claim 9, wherein, The step of forming the isolation layer on the active fin surface of the N-type device region comprises: modifying the active fin of the N-type device region to modify the active fin of a partial thickness of the active fin surface to the isolation layer, or to modify the active fin to the isolation layer.

12. The method of forming a semiconductor structure of claim 11, wherein, The modification of the active fin of the N-type device region is performed by an oxidation process.

13. The method of forming a semiconductor structure of claim 9, wherein, The step of forming the isolation layer on the active fin surface of the N-type device region further comprises: forming the isolation layer covering the active fin surface of the N-type device region.

14. The method of forming a semiconductor structure of claim 13, wherein, The isolation layer covering the active fin surface of the N-type device region is formed by an atomic layer deposition process.

15. The method of forming a semiconductor structure of claim 9, wherein, In the step of forming an isolation layer on a working fin surface of the N-type device region, the thickness of the isolation layer is greater than or equal to 16. The method of forming a semiconductor structure of claim 9, wherein, In the step of forming the channel layer covering the isolation layer in the N-type device region, the material of the channel layer is a two-dimensional material.

17. The method of forming a semiconductor structure of claim 16, wherein, In the step of forming the channel layer covering the isolation layer in the N-type device region, the two-dimensional material is a two-dimensional transition metal disulfide.

18. The method of forming a semiconductor structure of claim 9, wherein, The step of forming a channel layer overlying the isolation layer in the N-type device region includes forming a channel material layer overlying the isolation layer in the N-type device region, the working fin surface in the P-type device region, and the top surface of the substrate; The channel material layer in the P-type device region is removed, leaving the channel material layer in the N-type device region as the channel layer.

19. The method of forming a semiconductor structure of claim 9, wherein, The step of forming a gate structure overlying the working fin on the substrate further includes forming a gate oxide layer overlying the channel layer in the N-type device region and the working fin surface in the P-type device region; In the step of forming a gate structure overlying the working fin on the substrate, the gate structure overlies the gate oxide layer.

20. The method of forming a semiconductor structure of claim 9, wherein, In the step of providing the substrate, the material of the working fin includes silicon, germanium, silicon germanium, or a group III-V semiconductor material; In the step of forming an isolation layer overlying the working fin surface in the N-type device region, the material of the isolation layer includes silicon oxide.

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