Semiconductor structure and method of manufacturing the same
By forming work function layers with different nitrogen contents and creating a stepped structure in the semiconductor structure, the problem of metal diffusion under metal gate contacts was solved, improving device performance and yield.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- NEXCHIP SEMICON CO LTD
- Filing Date
- 2026-01-20
- Publication Date
- 2026-04-21
Smart Images
Figure CN121548096B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a method for manufacturing the same. Background Technology
[0002] As the geometry of integrated circuits continues to shrink, the method of using metal-gate transistors to enhance performance is widely used in advanced manufacturing processes. In the manufacturing process of Static Random Access Memory (SRAM), the metal gates of NMOS and PMOS transistors are in direct contact with each other, further increasing the functional density of the chip.
[0003] However, when the metal gates of NMOS and PMOS are in contact with each other, uneven deposition of the various film layers at the junction of NMOS and PMOS and low nitrogen content of the boundary barrier layer can easily lead to metal atom diffusion problems (such as aluminum atoms diffusing into the intermediate layer), which can cause the threshold voltage of the transistor to drift, resulting in unstable semiconductor device performance and seriously affecting chip yield. Summary of the Invention
[0004] Therefore, it is necessary to provide a semiconductor structure and its manufacturing method to reduce or avoid the probability of metal elements in the metal layer diffusing into the intermediate layer and forming dipoles.
[0005] This application provides a method for manufacturing a semiconductor structure, including:
[0006] A substrate is provided, the substrate including a first region and a second region, and an intermediate layer covering the first region and the second region is formed on the substrate;
[0007] A first work function layer is formed on the intermediate layer;
[0008] A second work function layer is formed on the first work function layer, wherein the nitrogen content of the second work function layer is less than the nitrogen content of the first work function layer;
[0009] The first work function layer and the second work function layer are graphically processed so that the remaining first work function layer and the second work function layer cover the intermediate layer. The orthographic projection of the second work function layer toward the substrate falls into the orthographic projection of the first work function layer toward the substrate. Above the junction of the first region and the second region, the edge sidewalls of the first work function layer and the edge sidewalls of the second work function layer combine to form a stepped structure.
[0010] In one embodiment, a wet etching process is used to pattern the first work function layer and the second work function layer, and during the wet etching process, the etching rate of the second work function layer is greater than the etching rate of the first work function layer.
[0011] In one embodiment, after graphically processing the first work function layer and the second work function layer, the method for manufacturing the semiconductor structure further includes:
[0012] A third work function layer is formed on the intermediate layer, the first work function layer, and the second work function layer, and the portion of the third work function layer located above the stepped structure is stepped;
[0013] A metal layer is formed on the third work function layer, and the thickness of the metal layer is greater than the height difference of the stepped portion in the third work function layer.
[0014] In one embodiment, after forming the third work function layer and before forming the metal layer, the method for manufacturing the semiconductor structure further includes:
[0015] A diffusion barrier layer is formed on the third work function layer, and the portion of the diffusion barrier layer above the stepped structure is stepped;
[0016] When the diffusion barrier layer is formed on the third work function layer, the thickness of the metal layer is greater than the height difference of the stepped portion in the diffusion barrier layer.
[0017] Accordingly, this application also provides a semiconductor structure manufactured using the semiconductor structure manufacturing method described above.
[0018] In one embodiment, the semiconductor structure includes:
[0019] A substrate, the substrate comprising a first region and a second region;
[0020] An intermediate layer is located on the substrate and covers the first region and the second region;
[0021] The first work function layer is located on the intermediate layer above the second region;
[0022] The second work function layer is located on the first work function layer above the second region, and the orthographic projection of the second work function layer toward the substrate falls into the orthographic projection of the first work function layer toward the substrate. Above the junction of the first region and the second region, the edge sidewalls of the first work function layer and the edge sidewalls of the second work function layer combine to form a stepped structure.
[0023] The nitrogen content of the second work function layer is less than that of the first work function layer.
[0024] In one embodiment, the semiconductor structure further includes:
[0025] The third work function layer is located above the intermediate layer, the first work function layer, and the second work function layer, and the portion of the third work function layer located above the stepped structure is stepped.
[0026] A diffusion barrier layer is located on the third work function layer, and the portion of the diffusion barrier layer above the stepped structure is stepped.
[0027] A metal layer is located on the diffusion barrier layer, and the thickness of the metal layer is greater than the height difference of the stepped portion in the diffusion barrier layer.
[0028] In one embodiment, the materials of the first work function layer and the second work function layer both include P-type work function materials, and the material of the third work function layer includes N-type work function materials.
[0029] In one embodiment, the first work function layer and the second work function layer are both made of titanium nitride, the third work function layer is made of titanium-aluminum alloy, the diffusion barrier layer is made of titanium nitride, and the metal layer is made of aluminum.
[0030] In one embodiment, the first region includes an NMOS device region, and the second region includes a PMOS device region.
[0031] An unexpected effect of this application is that by forming a first work function layer and a second work function layer with different nitrogen contents, the etching rates of the first work function layer and the second work function layer are different during the patterning process. This causes the edge sidewalls of the first work function layer and the second work function layer to form a stepped structure at the junction of the first region and the second region, thereby mitigating the height difference between different film layers at the junction of the first region and the second region. This is beneficial to improving the uniformity of the subsequently formed work function layer, thereby reducing or even avoiding the probability of metal elements in the subsequent metal layer diffusing into the intermediate layer and forming dipoles. This effectively improves the threshold voltage drift problem of semiconductor devices and enhances the performance stability and chip yield of semiconductor devices. Attached Figure Description
[0032] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0033] Figure 1 This is a schematic diagram of the structure corresponding to the step of providing a substrate in a semiconductor device manufacturing method in a related technology.
[0034] Figure 2 This is a schematic diagram of the structure corresponding to the step of patterning a photomask in a semiconductor device manufacturing method in a related technology.
[0035] Figure 3 This is a schematic diagram of the structure corresponding to the step of removing part of the first dielectric layer in a semiconductor device manufacturing method in a related technology.
[0036] Figure 4 This is a schematic diagram of the structure corresponding to the steps of forming the second dielectric layer and the third dielectric layer in a semiconductor device manufacturing method in a related technology.
[0037] Figure 5 This is a schematic diagram of the structure corresponding to the step of forming a metal material layer in a semiconductor device manufacturing method in a related technology.
[0038] Figure 6 A flowchart illustrating a method for manufacturing a semiconductor structure according to one embodiment of this application.
[0039] Figure 7 This is a schematic diagram of the structure corresponding to the step of providing a substrate and forming a first work function layer on the substrate in a method for manufacturing a semiconductor structure according to one embodiment of this application.
[0040] Figure 8 This is a schematic diagram of the structure corresponding to the step of forming the second work function layer in the manufacturing method of a semiconductor structure provided in one embodiment of this application.
[0041] Figure 9 This is a schematic diagram of the structure corresponding to the step of graphically processing the first work function layer and the second work function layer in the manufacturing method of the semiconductor structure provided in one embodiment of this application.
[0042] Figure 10 This is a schematic diagram of the structure corresponding to the step of forming a third work function layer, a diffusion barrier layer and a metal layer on an intermediate layer, a first work function layer and a second work function layer in a method for manufacturing a semiconductor structure according to one embodiment of this application.
[0043] The reference numerals in the figures include: 100-substrate; 101-STI structure; 110-interlayer dielectric layer; 120-first dielectric layer; 121-photomask; 130-second dielectric layer; 140-third dielectric layer; 150-metal material layer; 200-substrate; 201-intermediate layer; 202-shallow trench isolation structure; 210-first work function layer; 220-second work function layer; 221-photoresist layer; 230-third work function layer; 240-diffusion barrier layer; 250-metal layer; Y1-first region; Y2-second region; a-stepped structure. Detailed Implementation
[0044] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be more thorough and complete.
[0045] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
[0046] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this application, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.
[0047] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.
[0048] When used herein, the singular forms of “a,” “an,” and “ / the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.
[0049] Figures 1 to 5 This is a schematic diagram of some steps in a semiconductor device manufacturing method in a related technology. The following section combines... Figures 1 to 5 This section details the manufacturing methods for typical semiconductor devices.
[0050] First, refer to Figure 1 A substrate 100 is provided, on which an interlayer dielectric layer 110, a first dielectric layer 120, and a photomask 121 are formed. The substrate 100 includes mutually isolated pull-down transistor regions (Pull-Down, PD) and pull-up transistor regions (Pull-Up, PU), and an STI structure 101 (Shallow Trench Isolation) is formed within the substrate 100 to isolate the pull-up transistor regions and the pull-down transistor regions. Optionally, the substrate 100 includes a silicon substrate, the interlayer dielectric layer 110 is made of silicon oxide (SiO2), and the first dielectric layer 120 is made of titanium nitride (TiN).
[0051] Next, refer to Figure 2 The photomask 121 is patterned to remove the portion of the photomask 121 located above the pull-down transistor region, thus forming a patterned photomask 121. Optionally, a dry etching process is used to remove part of the photomask 121.
[0052] Then refer to Figure 3 A wet etching process is used to remove the portion of the first dielectric layer 120 not covered by the photomask 121, leaving the remaining first dielectric layer 120 above the pull-up transistor region and exposing the pull-down transistor region. Optionally, after removing part of the first dielectric layer 120, an ashing process and a wet cleaning process are used to remove the photomask 121.
[0053] Next, refer to Figure 4 A second dielectric layer 130 is deposited on the interlayer dielectric layer 110 and the first dielectric layer 120, and a third dielectric layer 140 is formed on the second dielectric layer 130. Optionally, the material of the second dielectric layer 130 includes a titanium-aluminum alloy (TiAl), and the material of the third dielectric layer 140 includes titanium nitride (TiN).
[0054] It should be noted that, since the first dielectric layer 120 only covers part of the interlayer dielectric layer 110, and the sidewalls of the first dielectric layer 120 are stepped, the second dielectric layer 130 and the third dielectric layer 140 inherit the morphology of the previous layer. That is, the portions of the second dielectric layer 130 and the third dielectric layer 140 located above the STI structure 101 exhibit an approximately fault-like morphology (i.e., Figure 4 (The part circled in the middle).
[0055] Then refer to Figure 5 A metal material layer 150 is formed on the third dielectric layer 140. Optionally, the material of the metal material layer 150 includes aluminum (Al). However, see [link to relevant documentation]. Figure 5 It is known that because the portions of the second dielectric layer 130 and the third dielectric layer 140 located above the STI structure 101 exhibit a fault-like morphology, the film thickness of the metal material layer 150 is uneven. Therefore, metal elements (such as aluminum atoms) in the metal material layer 150 can easily escape from the fault points of the third dielectric layer 140 and the second dielectric layer 130 (i.e., Figure 5 The portion circled in the middle diffuses into the interlayer dielectric layer 110 and forms a dipole, which leads to a threshold voltage drift problem in the final semiconductor device.
[0056] Therefore, it is necessary to provide a semiconductor structure and its manufacturing method to reduce or avoid the probability of metal elements in the metal layer diffusing into the intermediate layer and forming dipoles.
[0057] Figure 6 A flowchart illustrating a method for manufacturing a semiconductor structure according to one embodiment of this application. See also... Figure 6 One embodiment of this application provides a method for manufacturing a semiconductor structure, which includes the following steps S01 to S04.
[0058] Step S01: Provide a substrate, the substrate including a first region and a second region, and form an intermediate layer on the substrate covering the first region and the second region.
[0059] Step S02: Form a first work function layer on the intermediate layer.
[0060] Step S03: A second work function layer is formed on the first work function layer, wherein the nitrogen content of the second work function layer is less than the nitrogen content of the first work function layer.
[0061] It should be noted that by forming a first work function layer and a second work function layer with different nitrogen contents, the first work function layer and the second work function layer can have different etching rates in the subsequent etching process, which makes it easier to control the morphology of the first work function layer and the second work function layer after etching.
[0062] Step S04: The first work function layer and the second work function layer are graphically processed so that the remaining first work function layer and the second work function layer cover the intermediate layer. The orthographic projection of the second work function layer toward the substrate falls into the orthographic projection of the first work function layer toward the substrate. Above the junction of the first region and the second region, the edge sidewalls of the first work function layer and the edge sidewalls of the second work function layer combine to form a stepped structure.
[0063] The semiconductor structure manufacturing method described above, by forming a first work function layer and a second work function layer with different nitrogen contents, allows the first and second work function layers to have different etching rates during the patterning process. This results in a stepped structure formed at the boundary between the first and second regions by the sidewalls of the first and second work function layers. This reduces the height difference between different film layers at the boundary between the first and second regions, which is beneficial to improving the uniformity of the subsequently formed work function layers. This reduces or even avoids the probability of metal elements in the subsequent metal layers diffusing into the intermediate layer and forming dipoles, effectively improving the threshold voltage drift problem of semiconductor devices and enhancing the performance stability and chip yield of semiconductor devices.
[0064] See Figure 7 In one embodiment, a substrate 200 is provided, comprising a first region Y1 and a second region Y2, and an intermediate layer 201 covering the first region Y1 and the second region Y2 is formed on the substrate 200. Optionally, a shallow trench isolation structure 202 (STI) is formed between the first region Y1 and the second region Y2. Optionally, the material of the substrate 200 includes silicon (Si), and the material of the intermediate layer 201 includes silicon oxide (SiO2).
[0065] Next, continue reading Figure 7 In one embodiment, a first work function layer 210 is formed on the intermediate layer 201. Optionally, the first work function layer 210 is formed using a magnetron sputtering process. Optionally, the material of the first work function layer 210 includes titanium nitride (TiN).
[0066] Then refer to Figure 8 A second work function layer 220 is formed on the first work function layer 210, and the nitrogen content of the second work function layer 220 is less than that of the first work function layer 210. Optionally, the material of the second work function layer 220 is the same as that of the first work function layer 210, including titanium nitride (TiN). It should be noted that the nitrogen content in the first and second work function layers can be adjusted by controlling the process parameters of the first and second work function layers respectively, so that the nitrogen content of the second work function layer is less than that of the first work function layer. This is common knowledge known to those skilled in the art, and this application does not impose any limitations on it.
[0067] Next, refer to Figure 8 and Figure 9 The first work function layer 210 and the second work function layer 220 are patterned so that the remaining first work function layer 210 and the second work function layer 220 cover the intermediate layer 201. The orthographic projection of the second work function layer 220 toward the substrate 200 falls into the orthographic projection of the first work function layer 210 toward the substrate 200. Above the junction of the first region Y1 and the second region Y2 (i.e. above the shallow trench isolation structure 202), the edge sidewalls of the first work function layer 210 and the edge sidewalls of the second work function layer 220 combine to form a stepped structure a.
[0068] In one embodiment, the specific process of graphically processing the first work function layer and the second work function layer includes: (See attached document) Figure 8 A patterned photoresist layer 221 is formed on the second work function layer 220. The patterned photoresist layer 221 is located above the second region Y2 and exposes the first region Y1. (See also...) Figure 9 Based on the photoresist layer 221, a wet etching process is used to pattern the first work function layer 210 and the second work function layer 220 to form a first work function layer 210 and a second work function layer 220 with a stepped structure a. It should be noted that during the wet etching process, the etching rate of the second work function layer 220 is greater than the etching rate of the first work function layer 210 to form the stepped structure a. Optionally, after forming the stepped structure a, the semiconductor structure manufacturing method further includes: removing the photoresist layer 221 using an ashing process and a wet cleaning process.
[0069] Next, refer to Figure 10 In one embodiment, after patterning the first work function layer 210 and the second work function layer 220, the semiconductor structure manufacturing method further includes: forming a third work function layer 230 on the intermediate layer 201, the first work function layer 210, and the second work function layer 220, wherein the portion of the third work function layer 230 above the stepped structure a is stepped; forming a metal layer 250 on the third work function layer 230, wherein the thickness D of the metal layer 250 is greater than the height difference H1 of the stepped portion in the third work function layer 230. Optionally, the third work function layer 230 comprises a titanium-aluminum alloy (TiAl). Optionally, the material of the metal layer 250 comprises aluminum (Al). In other embodiments of this application, the materials of each film layer in the semiconductor structure can be adjusted according to actual needs, and this application does not impose any limitations on this.
[0070] Continue reading Figure 10 In one embodiment, after forming the third work function layer 230 and before forming the metal layer 250, the semiconductor structure manufacturing method further includes: forming a diffusion barrier layer 240 on the third work function layer 230, wherein the portion of the diffusion barrier layer 240 above the stepped structure a is stepped, to reduce or prevent the diffusion of metal elements in the metal layer 250 into multiple film layers near the substrate 200. Optionally, when the diffusion barrier layer 240 is formed on the third work function layer 230, the thickness of the metal layer 250 is greater than the height difference H2 of the stepped portion in the diffusion barrier layer 240. Optionally, the material of the diffusion barrier layer 240 includes titanium nitride (TiN).
[0071] It should be noted that by forming a stepped structure a, the height difference between the intermediate layer 201, the first work function layer 210 and the second work function layer 220 is reduced, which effectively improves the uniformity of the deposition thickness of the third work function layer 230 and the diffusion barrier layer 240. This improves the blocking effect of the third work function layer 230 and the diffusion barrier layer 240 on the diffusion of metal elements in the metal layer 250, reduces or even avoids the diffusion of metal elements into the intermediate layer 201, and thus helps to improve the stability of the threshold voltage of the finally formed semiconductor device.
[0072] Accordingly, one embodiment of this application also provides a semiconductor structure manufactured using the semiconductor structure manufacturing method described above. See further reading. Figure 10In one embodiment, the semiconductor structure includes a substrate 200, an intermediate layer 201, a first work function layer 210, and a second work function layer 220; wherein the substrate 200 includes a first region Y1 and a second region Y2; the intermediate layer 201 is located on the substrate 200 and covers the first region Y1 and the second region Y2; the first work function layer 210 is located on the intermediate layer 201 above the second region Y2; the second work function layer 220 is located on the first work function layer 210 above the second region Y2, and the orthographic projection of the second work function layer 220 toward the substrate 200 falls within the orthographic projection of the first work function layer 210 toward the substrate 200. Above the boundary between the first region Y1 and the second region Y2, the edge sidewalls of the first work function layer 210 and the edge sidewalls of the second work function layer 220 combine to form a stepped structure a; wherein the nitrogen content of the second work function layer 220 is less than the nitrogen content of the first work function layer 210.
[0073] As described above, the semiconductor structure, based on the different nitrogen content of the first and second work function layers, allows the first and second work function layers to have different etching rates during patterning. This results in a stepped structure at the boundary between the first and second regions, which reduces the height difference between different film layers at the boundary between the first and second regions. This effectively improves the uniformity of the third work function layer, thereby reducing or even avoiding the probability of metal elements in the subsequent metal layers diffusing into the intermediate layer and forming dipoles. Consequently, it effectively improves the threshold voltage drift problem of semiconductor devices, enhancing the performance stability and chip yield of semiconductor devices.
[0074] Continue reading Figure 10 In one embodiment, the semiconductor structure further includes a third work function layer 230, a diffusion barrier layer 240, and a metal layer 250; wherein the third work function layer 230 is located on the intermediate layer 201, the first work function layer 210, and the second work function layer 220, and the portion of the third work function layer 230 above the stepped structure a is stepped; the diffusion barrier layer 240 is located on the third work function layer 230, and the portion of the diffusion barrier layer 240 above the stepped structure a is stepped; the metal layer 250 is located on the diffusion barrier layer 240, and the thickness D of the metal layer 250 is greater than the height difference H2 of the stepped portion in the diffusion barrier layer 240.
[0075] See Figure 10In one embodiment, the first region Y1 is a pull-down transistor region (Pull Down, PD), and the second region Y2 is a pull-up transistor region (Pull Up, PU), with a shallow trench isolation structure 202 provided between the first region Y1 and the second region Y2. Optionally, the first region Y1 includes an NMOS device region (not shown in the figure), and the second region Y2 includes a PMOS device region (not shown in the figure). Optionally, the substrate 200 is made of silicon (Si), and the intermediate layer 201 is made of silicon oxide (SiO2).
[0076] In one embodiment, the first and second work function layers are both made of P-type work function materials, and the third work function layer is made of N-type work function materials. In another embodiment, the first and second work function layers are both made of titanium nitride (TiN), the third work function layer is made of titanium aluminum alloy (TiAl), the diffusion barrier layer is made of titanium nitride (TiN), and the metal layer is made of aluminum (Al). In other embodiments of this application, the materials of each film layer in the semiconductor structure can be adjusted according to actual needs, and this application does not impose any limitations on this.
[0077] An unexpected effect of this application is that by forming a first work function layer and a second work function layer with different nitrogen contents, the etching rates of the first work function layer and the second work function layer are different during the patterning process. This causes the edge sidewalls of the first work function layer and the second work function layer to form a stepped structure at the junction of the first region and the second region, thereby mitigating the height difference between different film layers at the junction of the first region and the second region. This is beneficial to improving the uniformity of the subsequently formed work function layer, thereby reducing or even avoiding the probability of metal elements in the subsequent metal layer diffusing into the intermediate layer and forming dipoles. This effectively improves the threshold voltage drift problem of semiconductor devices and enhances the performance stability and chip yield of semiconductor devices.
[0078] In the description of this specification, the references to terms such as "some embodiments," "other embodiments," "ideal embodiments," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example that are included in at least one embodiment or example of this application. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.
[0079] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0080] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.
Claims
1. A method for manufacturing a semiconductor structure, characterized in that, include: A substrate is provided, the substrate including a first region and a second region, and an intermediate layer covering the first region and the second region is formed on the substrate; A first work function layer is formed on the intermediate layer; A second work function layer is formed on the first work function layer, wherein the nitrogen content of the second work function layer is less than the nitrogen content of the first work function layer; The first work function layer and the second work function layer are graphically processed so that the remaining first work function layer and the second work function layer cover the intermediate layer. The orthographic projection of the second work function layer toward the substrate falls into the orthographic projection of the first work function layer toward the substrate. Above the junction of the first region and the second region, the edge sidewalls of the first work function layer and the edge sidewalls of the second work function layer combine to form a stepped structure.
2. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, The first work function layer and the second work function layer are patterned using a wet etching process, and during the wet etching process, the etching rate of the second work function layer is greater than that of the first work function layer.
3. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, After graphically processing the first work function layer and the second work function layer, the method for manufacturing the semiconductor structure further includes: A third work function layer is formed on the intermediate layer, the first work function layer, and the second work function layer, and the portion of the third work function layer located above the stepped structure is stepped; A metal layer is formed on the third work function layer, and the thickness of the metal layer is greater than the height difference of the stepped portion in the third work function layer.
4. The method for manufacturing a semiconductor structure according to claim 3, characterized in that, After forming the third work function layer and before forming the metal layer, the method for manufacturing the semiconductor structure further includes: A diffusion barrier layer is formed on the third work function layer, and the portion of the diffusion barrier layer above the stepped structure is stepped; When the diffusion barrier layer is formed on the third work function layer, the thickness of the metal layer is greater than the height difference of the stepped portion in the diffusion barrier layer.
5. A semiconductor structure, characterized in that, It is manufactured using the semiconductor structure manufacturing method described in any one of claims 1 to 4.
6. The semiconductor structure according to claim 5, characterized in that, include: Substrate, the substrate comprising a first region and a second region; An intermediate layer is located on the substrate and covers the first region and the second region; The first work function layer is located on the intermediate layer above the second region; The second work function layer is located on the first work function layer above the second region, and the orthographic projection of the second work function layer toward the substrate falls into the orthographic projection of the first work function layer toward the substrate. Above the junction of the first region and the second region, the edge sidewalls of the first work function layer and the edge sidewalls of the second work function layer combine to form a stepped structure. The nitrogen content of the second work function layer is less than that of the first work function layer.
7. The semiconductor structure according to claim 6, characterized in that, The semiconductor structure also includes: The third work function layer is located above the intermediate layer, the first work function layer, and the second work function layer, and the portion of the third work function layer located above the stepped structure is stepped. A diffusion barrier layer is located on the third work function layer, and the portion of the diffusion barrier layer above the stepped structure is stepped. A metal layer is located on the diffusion barrier layer, and the thickness of the metal layer is greater than the height difference of the stepped portion in the diffusion barrier layer.
8. The semiconductor structure according to claim 7, characterized in that, The materials of the first work function layer and the second work function layer both include P-type work function materials, and the materials of the third work function layer include N-type work function materials.
9. The semiconductor structure according to claim 7, characterized in that, The first work function layer and the second work function layer are both made of titanium nitride, the third work function layer is made of titanium-aluminum alloy, the diffusion barrier layer is made of titanium nitride, and the metal layer is made of aluminum.
10. The semiconductor structure according to claim 5, characterized in that, The first region includes an NMOS device region, and the second region includes a PMOS device region.
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