Semiconductor structure and manufacturing method thereof

Abstract

The invention provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure comprises a substrate, a first channel layer and a second channel layer. The semiconductor structure also includes an isolation structure over the substrate and a first gate structure over the first channel layer and the isolation structure. The semiconductor structure also includes a second gate structure over the second channel layer and the isolation structure and an isolation feature laterally sandwiched between the first gate structure and the second gate structure and extending over the isolation structure. Further, the isolation feature has a top width and a bottom width greater than the top width, and an interface between the isolation feature and the first gate structure includes a curved profile.

Description

Technical Field

[0001] Embodiments of this application relate to semiconductor structures and methods of manufacturing the same. Background Technology

[0002] The electronics industry has a growing demand for smaller and faster electronic devices capable of implementing a greater number of increasingly complex and sophisticated functions. Consequently, there is a continuous trend in the semiconductor industry to manufacture low-cost, high-performance, and low-power integrated circuits (ICs). To date, these goals have been largely achieved by shrinking the size of semiconductor ICs (e.g., the smallest component size), thereby improving production efficiency and reducing associated costs. However, such miniaturization introduces greater complexity into semiconductor manufacturing processes. Therefore, continued advancements in semiconductor ICs and devices require similar advancements in semiconductor manufacturing processes and technologies.

[0003] Recently, multi-gate devices have been introduced in an attempt to improve gate control by increasing gate-channel coupling, reducing off-state current, and minimizing short-channel effect (SCE). However, the integration of multi-gate devices in fabrication can be challenging. Summary of the Invention

[0004] Some embodiments of this application provide a semiconductor structure including: a substrate; a first channel layer and a second channel layer extending along a first direction, wherein the first channel layer and the second channel layer are located above the substrate; an isolation structure located above the substrate, wherein the isolation structure is located between the first channel layer and the second channel layer in a top view; a first gate structure extending above the first channel layer and the isolation structure along a second direction, wherein the second direction is different from the first direction; a second gate structure extending above the second channel layer and the isolation structure along the second direction; and an isolation member laterally sandwiched between the first gate structure and the second gate structure and extending above the isolation structure, wherein the isolation member has a top width and a bottom width greater than the top width, and the interface between the isolation member and the first gate structure includes a curved profile.

[0005] Other embodiments of this application provide a semiconductor structure including: a substrate; a first transistor located above the substrate, including: a first substrate structure; a first channel layer extending longitudinally in a first direction above the first substrate structure; and a first gate structure enclosing the first channel layer and extending longitudinally in a second direction, wherein the second direction is different from the first direction; a second transistor located above the substrate, including: a second substrate structure; a second channel layer extending longitudinally in the first direction above the second substrate structure; and a second gate structure enclosing the second channel layer and extending longitudinally in the second direction; an isolation structure located above the substrate and between the first substrate structure and the second substrate structure, wherein the isolation structure is in contact with the sidewalls of the first substrate structure and the sidewalls of the second substrate structure; and a first isolation member sandwiched between the first gate structure and the second gate structure to electrically isolate the first gate structure and the second gate structure, wherein the distance in the second direction between the topmost one of the first channel layer and the first sidewall of the first isolation member is greater than the distance in the second direction between the bottommost one of the first channel layer and the first sidewall of the first isolation member.

[0006] Further embodiments of this application provide a method for manufacturing a semiconductor structure, comprising: alternately stacking a channel layer and a semiconductor sacrificial layer to form a semiconductor stack over a substrate; patterning the semiconductor stack to form a first fin structure and a second fin structure; forming a dummy gate electrode across the first fin structure and the second fin structure; replacing the semiconductor sacrificial layer with a dielectric sacrificial member; forming a first trench having a first width in the dummy gate electrode between the first fin structure and the second fin structure; expanding the top portion of the first trench to a second width greater than the first width; forming an isolation material in the first trench; removing the dummy gate electrode; partially removing the isolation material to form an isolation member, wherein the top surface of the isolation member has a third width less than the first width; removing the dielectric sacrificial member; and forming a first gate structure at a first side of the isolation member and forming a second gate structure at a second side of the isolation member. Attached Figure Description

[0007] Various aspects of the embodiments of this disclosure will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0008] Figure 1A and Figure 1BSchematic perspective views of intermediate stages of manufacturing semiconductor structures in a first region and a second region according to some embodiments are shown respectively.

[0009] Figures 2A-1 to 2T-1 , Figures 2A-3 to 2T-3 and Figures 2A-5 to 2T-5 Intermediate stages for fabricating a semiconductor structure in the first region according to some embodiments are shown respectively. Figure 1A line Y in MG1 -Y MG1 ', X1-X1' and Y SD1 -Y SD1 The cross-sectional view shown.

[0010] Figures 2A-2 to 2T-2 , Figures 2A-4 to 2T-4 and Figures 2A-6 to 2T-6 Intermediate stages for fabricating a semiconductor structure in the second region according to some embodiments are shown respectively. Figure 1B line Y in MG2 -Y MG2 ', X2-X2' and Y SD2 -Y SD2 The cross-sectional view shown.

[0011] Figures 2J-7 to 2T-7 and Figures 2J-8 to 2T-8 A schematic perspective view of an intermediate stage of a semiconductor structure in a first region and a second region according to some embodiments is shown.

[0012] Figure 2T-9 Illustrations are shown according to some embodiments Figure 2T-1 A magnified cross-sectional view of the semiconductor structure in region R.

[0013] Figure 3A and Figure 3B The layout of the semiconductor structure in the first and second regions according to some embodiments is shown respectively.

[0014] Figure 4A and Figure 4B A cross-sectional view of an intermediate stage in the fabrication of a semiconductor structure according to some other embodiments is shown.

[0015] Figure 5A and Figure 5B A cross-sectional view of an intermediate stage in the fabrication of a semiconductor structure according to some other embodiments is shown.

[0016] Figure 6A-1 , Figure 6A-2 , Figure 6B-1 and Figure 6B-2 A cross-sectional view of an intermediate stage in the fabrication of a semiconductor structure according to some embodiments is shown.

[0017] Figure 7A cross-sectional view of a semiconductor structure according to some embodiments is shown.

[0018] Figure 8 A cross-sectional view of a semiconductor structure according to some embodiments is shown.

[0019] Figure 9 A cross-sectional view of a semiconductor structure according to some embodiments is shown.

[0020] Figure 10 A cross-sectional view of a semiconductor structure according to some embodiments is shown. Detailed Implementation

[0021] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify embodiments of this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component on or over a second component may include embodiments where the first and second components are in direct contact, and may also include embodiments where an additional component may be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or characters may be repeated in various instances of embodiments of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0022] Some variations of the embodiments are described. Throughout the various views and illustrative embodiments, the same reference numerals are used to denote the same elements. It should be understood that additional operations may be provided before, during, and after the method, and that some of the described operations may be replaced or eliminated for other embodiments of the method.

[0023] The nanostructure transistors described below (e.g., nanosheet transistors, nanowire transistors, multi-bridge channel transistors, nanoribbon FETs, and gate-all-around (GAA) transistors) can be patterned using any suitable method. For example, the structure can be patterned using one or more photolithography processes, including dual-patterning or multi-patterning processes. Typically, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes, thereby allowing the creation of patterns with spacing, for example, smaller than that achievable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the nanostructure.

[0024] As component sizes continue to shrink in semiconductor devices, gate-all-around (GAA) transistors can be employed. Typically, the channel layer (e.g., a nanostructure) in a GAA transistor is fabricated by forming a semiconductor stack comprising alternating stacked channel layers (e.g., Si layers) and semiconductor sacrificial layers (e.g., SiGe layers). The semiconductor sacrificial layer can be removed so that the subsequently formed gate structure can enclose the channel layer.

[0025] However, during the formation of a semiconductor device, Ge in the semiconductor sacrificial layer may diffuse into the channel layer during manufacturing processes (such as thermal processes). Therefore, Ge diffusion can degrade the performance of the resulting device. Consequently, in some embodiments of this disclosure, the semiconductor sacrificial layer is replaced with a dielectric sacrificial component at a relatively early stage of the manufacturing process (e.g., before implementing high-temperature thermal processes). This reduces or avoids the problem of germanium diffusion. Furthermore, because the channel layer and the dielectric sacrificial component have relatively high etch selectivity, the dielectric sacrificial component can be completely removed without excessive over-etching of the channel layer. Therefore, the size of the channel layer in the resulting device can be better controlled, and the performance of the resulting device can be improved.

[0026] Furthermore, isolation components can be formed to separate the gate structures of different types of transistors. The width and shape of the isolation components can be adjusted by implementing additional trimming processes. For example, the isolation components can have a smaller top width and a larger bottom width, allowing the conductive structure formed above the gate structure to have a larger formation window (i.e., the gate structure can have a larger top width, and therefore the spacing used to form the conductive structure above the gate structure can be relatively large). Moreover, by implementing trimming processes, the size of the isolation components can be adjusted without damaging the channel layer, and therefore the isolation components can be formed at transistors with different sizes and / or spacings.

[0027] Furthermore, when the channel layer has a relatively larger width, an extension portion can be formed on the sidewalls of the isolation component, extending into the channel layer when the channel layer has a relatively larger width during the formation of the isolation component. The resulting structure with the extension portion can have a reduced Cgd (gate-to-drain capacitance) due to the reduced gate end cap. On the other hand, when the channel layer has a relatively smaller width, the isolation component can be formed without forming the extension portion, and the channel layer can be enclosed by the gate structure (e.g., enclosed by four sides). That is, by using channel layers with different widths, different structures can be fabricated without the need for additional complex manufacturing processes.

[0028] Figure 1A and Figure 1BSchematic perspective views are shown of intermediate stages of manufacturing a semiconductor structure 100 in a first region 10 and a second region 20 according to some embodiments. Figures 2A-1 to 2T-1 , Figures 2A-3 to 2T-3 and Figures 2A-5 to 2T-5 Intermediate stages of fabricating a semiconductor structure 100 in a first region 10 according to some embodiments are shown respectively. Figure 1A line Y in MG1 -Y MG1 '(i.e., in the Y direction), X1-X1' (i.e., in the X direction) and Y SD1 -Y SD1 The cross-sectional view shown is shown in the Y direction. Figures 2A-2 to 2T-2 , Figures 2A-4 to 2T-4 and Figures 2A-6 to 2T-6 Intermediate stages of fabricating the semiconductor structure 100 in the second region 20 according to some embodiments are shown respectively. Figure 1B line Y in MG2 -Y MG2 '(i.e., in the Y direction), X2-X2' (i.e., in the X direction) and Y SD2 -Y SD2 The cross-sectional view shown is shown in the Y direction.

[0029] More specifically, Figure 2A-1 , Figure 2A-3 and Figure 2A-5 It shows Figure 1A A cross-sectional view of an intermediate stage of the semiconductor structure 100 in the first region 10 shown, and Figure 2A-2 , Figure 2A-4 and Figure 2A-6 It shows Figure 1B A cross-sectional view of an intermediate stage of the semiconductor structure 100 in the second region 20 shown, and Figures 2B-1 to 2T-1 , Figures 2B-2 to 2T-2 , Figures 2B-3 to 2T-3 , Figures 2B-4 to 2T-4 , Figures 2B-5 to 2T-5 and Figures 2B-6 to 2T-6 A cross-sectional view is shown of an intermediate stage in the subsequent fabrication of the semiconductor structure 100 according to some embodiments.

[0030] Semiconductor structure 100 may be formed over substrate 102. To better understand the semiconductor structure described herein, XYZ coordinate references are provided in the accompanying drawings of embodiments of this disclosure. The X and Y axes are generally oriented in a lateral (or horizontal) direction parallel to the main surface of substrate 102. The Y axis is lateral (e.g., substantially perpendicular) to the X axis. The Z axis is generally oriented in a vertical direction perpendicular to the main surface of substrate 102 (or the XY plane).

[0031] Substrate 102 may be a semiconductor wafer, such as a silicon wafer. Optionally or additionally, substrate 102 may include elemental semiconductor materials, compound semiconductor materials, and / or alloy semiconductor materials. Elemental semiconductor materials may include, but are not limited to, crystalline silicon, polycrystalline silicon, amorphous silicon, germanium, and / or diamond. Compound semiconductor materials may include, but are not limited to, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide. Alloy semiconductor materials may include, but are not limited to, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP.

[0032] According to some embodiments, well regions W1 and W2 are formed in substrate 102 in the first region 10 and the second region 20. Well regions W1 and W2 may be formed close to each other. In some embodiments, well region W1 is a P-type well region, and an N-type transistor is formed above well region W1. In some embodiments, well region W2 is an N-type well region, and a P-type transistor is formed above well region W2. In some other embodiments, well region W1 is an N-type well region, and well region W2 is a P-type well region, and transistors of opposite conductivity types are formed above well regions W1 and W2.

[0033] According to some embodiments, after forming well regions W1 and W2, a semiconductor stack including a first semiconductor material layer 106 and a second semiconductor material layer 108 is formed over the first region 10 and the second region 20 of the substrate 102, such as... Figure 1A , Figure 1B , Figure 2A-1 , Figure 2A-2 , Figure 2A-3 , Figure 2A-4 , Figure 2A-5 and Figure 2A-6 As shown in the image.

[0034] In some embodiments, a first semiconductor material layer 106 and a second semiconductor material layer 108 are alternately stacked over a substrate 102 to form a semiconductor stack. The first semiconductor material layers 106 may also be referred to as sacrificial semiconductor layers because they will be removed subsequently. The second semiconductor material layers 108 may also be referred to as channel layers because they will be used as channel regions in the resulting transistor. In some embodiments, the first semiconductor material layer 106 and the second semiconductor material layer 108 are made of different semiconductor materials. In some embodiments, the first semiconductor material layer 106 is made of SiGe, and the second semiconductor material layer 108 is made of silicon. In some embodiments, the Ge concentration in the first semiconductor material layer 106 is in the range of about 35 atm% to about 50 atm%.

[0035] It should be noted that although three first semiconductor material layers 106 and three second semiconductor material layers 108 are shown in the figure, the semiconductor stack may include fewer or more of the alternately stacked first semiconductor material layers 106 and second semiconductor material layers 108. For example, the semiconductor stack may include two to five of the first semiconductor material layers 106 and two to five of the second semiconductor material layers 108.

[0036] The first semiconductor material layer 106 and the second semiconductor material layer 108 can be formed using low-pressure chemical vapor deposition (LPCVD), epitaxial growth processes, another suitable method, or a combination thereof. In some embodiments, the epitaxial growth process includes molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), or vapor phase epitaxy (VPE).

[0037] According to some embodiments, after the first semiconductor material layer 106 and the second semiconductor material layer 108 are formed as a semiconductor stack above the substrate 102, the semiconductor stack is patterned to form fin structures 104, including fin structures 104-1, 104-2, 104-3, and 104-4, as shown. Figure 1A , Figure 1B , Figure 2A-1 , Figure 2A-2 , Figure 2A-3 , Figure 2A-4 , Figure 2A-5 and Figure 2A-6 As shown in the diagram. Fin structures 104-1 to 104-4 can also be referred to as active regions. (As shown in the diagram...) Figure 1A , Figure 1B , Figure 2A-1 , Figure 2A-2 , Figure 2A-5 and Figure 2A-6 As shown, according to some embodiments, in the Y direction, the width WF1 of fin structures 104-1 and 104-2 is greater than the width WF2 of fin structures 104-3 and 104-4. In some embodiments, the width WF1 is greater than about 32 nm. In some embodiments, the width WF2 is in the range from about 13 nm to about 32 nm.

[0038] According to some embodiments, the fin structure 104 can extend longitudinally in the X direction, such as... Figure 1A and Figure 1BAs shown in the figure. In some embodiments, the fin structure 104 can be formed by performing a patterning process over a semiconductor material stack. The patterning process may include forming a mask structure over the semiconductor material stack and etching the semiconductor material stack and the underlying substrate 102 through the mask structure. In some embodiments, the mask structure is a multilayer structure including a pad oxide layer and a nitride layer formed over the pad oxide layer. The pad oxide layer may be made of silicon oxide, which is formed by thermal oxidation or CVD, and the nitride layer may be made of silicon nitride, which is formed by CVD, such as LPCVD or plasma-enhanced CVD (PECVD). In some embodiments, the fin structure 104 includes a substrate structure 104B and a semiconductor stack formed over the substrate structure 104B, including a first semiconductor material layer 106 and a second semiconductor material layer 108.

[0039] According to some embodiments, after the fin structure 104 is formed, an isolation structure 116 is formed around the fin structure 104, such as... Figure 1A , Figure 1B , Figure 2A-1 , Figure 2A-2 , Figure 2A-5 and Figure 2A-6 As shown in the figure. According to some embodiments, the isolation structure 116 is configured as an active region (e.g., fin structure 104) of the electrically isolated semiconductor structure 100, and is also referred to as a shallow trench isolation (STI) component. The isolation structure 116 may include multiple layers or additional mask structures located above its top portion, but these are not shown in the figure. In some embodiments, the isolation structure 116 is made of a silicon-containing dielectric material, such as silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon carbonitride oxynitride (SiOCN), and / or oxygen-doped silicon carbonitride (Si(O)CN). The isolation structure 116 can be formed by performing a deposition process to form a dielectric layer and performing an etch-back process to remove the top portion of the dielectric layer, such that the fin structure 104 protrudes from the top surface of the isolation structure 116. The deposition process can be such as in-situ vapor generation (ISSG), thermal oxidation, CVD (such as low-pressure CVD (LPCVD), plasma-enhanced CVD (PECVD), high-density plasma CVD (HDP-CVD), high aspect ratio process (HARP), or flowable CVD (FCVD)), atomic layer deposition (ALD), another suitable technology, and / or a combination thereof. The etching process can be a wet etching process or a dry etching process.

[0040] In some embodiments, a portion of the isolation structure 116 is sandwiched between the base structures 104B of fin structures 104-1 and 104-2, and is in contact with the sidewalls of the base structures 104B of fin structure 104-1 and fin structure 104-2. In some embodiments, a portion of the isolation structure 116 is sandwiched between the base structures 104B of fin structures 104-3 and 104-4, and is in contact with the sidewalls of the base structures 104B of fin structure 104-3 and fin structure 104-4. In some embodiments, the isolation structure 116 has an uneven top surface, such as... Figure 2A-1 , Figure 2A-2 , Figure 2A-4 and Figure 2A-5 As shown in the image.

[0041] According to some embodiments, after forming the isolation structure 116, a capping layer 120, a dielectric layer 122, and a dummy gate electrode 124 are formed across the fin structure 104, and the resulting structure is Figure 2B-1 , Figure 2B-2 , Figure 2B-3 , Figure 2B-4 , Figure 2B-5 and Figure 2B-6 As shown in the figure. In some embodiments, the capping layer 120 is made of Si. In some other embodiments, the capping layer 120 is not formed. In some embodiments, the dielectric layer 122 is made of one or more dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride (SiON), HfO2, HfZrO, HfSiO, HfTiO, HfAlO, or combinations thereof. In some embodiments, the dielectric layer 122 is formed using thermal oxidation, CVD, ALD, physical vapor deposition (PVD), another suitable method, or a combination thereof.

[0042] The dummy gate electrode 124 can be used to define the channel region of the resulting semiconductor structure 100. The dummy gate electrode 124 can be longitudinally oriented along the Y direction and can subsequently be replaced with a gate structure. In some embodiments, the dummy gate electrode 124 is made of a conductive material including polysilicon (poly-Si), polysilicon germanium (poly-SiGe), or combinations thereof. In some embodiments, the dummy gate electrode 124 is formed using CVD, PVD, or combinations thereof.

[0043] In some embodiments, a hard mask structure 126 is formed over the dummy gate electrode 124. In some embodiments, each of the hard mask structures 126 includes multiple layers, such as an oxide layer 128 and a nitride layer 130. In some embodiments, the oxide layer 128 is made of silicon oxide, and the nitride layer 130 is made of silicon nitride.

[0044] The formation of the structure described above may include conformally forming a capping layer, a dielectric material serving as a dielectric layer 122, a conductive material above the dielectric material serving as a dummy gate electrode 124, and a hard mask structure 126 above the conductive material. Next, the capping layer, dielectric material, and conductive material can be patterned using the hard mask structure 126 to form the capping layer 120, the dielectric layer 122, and the dummy gate electrode 124.

[0045] According to some embodiments, after the dummy gate electrode 124 is formed, a spacer layer 132 is formed to cover the top surface and sidewalls of the dummy gate electrode 124 and the fin structure 104, such as Figure 2C-1 , Figure 2C-2 , Figure 2C-3 , Figure 2C-4 , Figure 2C-5 and Figure 2C-6 As shown in the diagram. Furthermore, according to some embodiments, the spacer layer 132 also covers the top surface of the isolation structure 116 and the hard mask structure 126. In some embodiments, the spacer layer 132 includes one or more dielectric layers. The dielectric material used to form the spacer layer 132 may include silicon oxide (SiO2), silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon carbonitride (SiOCN), silicon oxycarbonate (SiOC), or combinations thereof. The thickness of the spacer layer 132 is in the range of about 4 nm to about 6 nm.

[0046] According to some embodiments, after forming the spacer layer 132, an etching process is performed to form the gate spacer 134 and the fin spacer 136 with the spacer layer 132, and to form the source / drain recess 138 in the fin structure 104, and the resulting structure is Figure 2D-1 , Figure 2D-2 , Figure 2D-3 , Figure 2D-4 , Figure 2D-5 and Figure 2D-6 As shown in the figure. The gate spacer 134 can be configured to separate the source / drain structure (formed later) from the dummy gate electrode 124, and the fin spacer 136 can be configured to restrict the growth of the source / drain structure formed therein.

[0047] More specifically, according to some embodiments, spacer layer 132 is etched to form gate spacer 134 on the opposing sidewalls of dummy gate electrode 124, dielectric layer 122, and capping layer 120, and to form fin spacer 136 covering the sidewalls of fin structure 104. Furthermore, according to some embodiments, during the etching process, portions of fin structure 104 not covered by dummy gate electrode 124 and gate spacer 134 are etched to form source / drain recesses 138. The etching process can be an anisotropic etching process, such as dry plasma etching, and dummy gate electrode 124 (or mask structure 126) and gate spacer 134 can be used as etching masks during the etching process. In some embodiments, isolation structure 116 is also etched during the etching process, such that isolation structure 116 has a curved and recessed top surface, as... Figure 2D-5 and Figure 2D-6 As shown in the image.

[0048] According to some embodiments, after forming the source / drain trench 138, the first semiconductor material layer 106 is removed through the source / drain trench 138, and the resulting structure is Figure 2E-1 , Figure 2E-2 , Figure 2E-3 , Figure 2E-4 , Figure 2E-5 and Figure 2E-6 As shown in the figure. In some embodiments, an etching process is performed to remove the first semiconductor layer 106, thereby forming gap 140. The etching process can be an isotropic etching process, such as dry chemical etching, remote plasma etching, or wet chemical etching, or a combination thereof. In some embodiments, the isolation structure 116 is also partially etched during the etching process.

[0049] According to some embodiments, after forming the gap 140, a dielectric sacrificial layer 142 is formed, such as... Figure 2F-1 , Figure 2F-2 , Figure 2F-3 , Figure 2F-4 , Figure 2F-5 and Figure 2F-6 As shown in the diagram. More specifically, according to some embodiments, a dielectric sacrificial layer 142 is deposited to fill the gap 140 and to cover the dummy gate electrode 124 and the gate spacer 134, as illustrated. Figure 2F-1 , Figure 2F-2 , Figure 2F-3 and Figure 2F-4 As shown in the diagram. Furthermore, according to some embodiments, the fin spacer 136, the isolation structure 116, and the source / drain groove 138 are also covered by a dielectric sacrificial layer 142, as shown. Figure 2F-5 and Figure 2F-6 As shown in the image.

[0050] The dielectric sacrificial layer 142 may be a single or multiple dielectric material layers. In some embodiments, the dielectric sacrificial layer 142 is made of silicon oxide (SiO2), silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon carbonitride oxynitride (SiOCN), and / or oxygen-doped silicon carbonitride (Si(O)CN). In some embodiments, the dielectric sacrificial layer 142 is formed by performing a deposition process, such as ALD, CVD (such as PECVD, LPCVD, or HARP), another suitable technique, or a combination thereof.

[0051] According to some embodiments, after forming the dielectric sacrificial layer 142, an etching process is performed to form the dielectric sacrificial component 144 using the dielectric sacrificial layer 142, and the resulting structure is Figure 2G-1 , Figure 2G-2 , Figure 2G-3 , Figure 2G-4 , Figure 2G-5 and Figure 2G-6 As shown in the figure. More specifically, an etching process can be performed to etch away the dielectric sacrificial layer 142 outside the gap 140. In some embodiments, according to some examples, the dielectric sacrificial layer 142 in the gap 140 is also partially etched during the etching process, such that the sidewall of the dielectric sacrificial member 144 is recessed from the sidewall of the second semiconductor material layer 108, as shown in the figure. Figure 2G-3 and Figure 2G-4 As shown in the figure. That is, according to some embodiments, a groove 146 is formed between the second semiconductor material layers 108 and between the bottommost one of the second semiconductor material layers 108 and the substrate structure 104B. In some embodiments, the etching process includes anisotropic etching processes such as dry plasma etching, isotropic etching processes such as dry chemical etching, remote plasma etching, or wet chemical etching, or combinations thereof.

[0052] like Figure 2G-1 , Figure 2G-2 , Figure 2G-3 and Figure 2G-4 As shown, the first semiconductor layer 106 is now replaced with a dielectric sacrificial member 144, and thus Ge diffusion caused by the first semiconductor material layer 106 can be prevented in subsequent manufacturing processes (e.g., annealing processes for forming source / drain structures). Furthermore, the dielectric sacrificial member 144 (e.g., SiO2) x The etch selectivity (e.g., greater than 10,000) between the first semiconductor layer 106 (e.g., SiGe) and the second semiconductor layer 108 (e.g., Si) can be much greater than the etch selectivity (e.g., about 170) between the first semiconductor layer 106 (e.g., SiGe) and the second semiconductor layer 108 (e.g., Si). Therefore, the loss of the channel layer (i.e., the second semiconductor layer 108) in the following channel release process can be reduced.

[0053] Subsequently, according to some embodiments, an internal spacer layer 148 is formed, such as... Figure 2H-1 , Figure 2H-2 , Figure 2H-3 , Figure 2H-4 , Figure 2H-5 and Figure 2H-6 As shown in the diagram. More specifically, according to some embodiments, an internal spacer layer 148 is deposited to fill the notch 146 and to cover the dummy gate electrode 124 and the gate spacer 134, as illustrated. Figure 2H-1 , Figure 2H-2 , Figure 2H-3 and Figure 2H-4 As shown in the diagram. Furthermore, according to some embodiments, the fin spacer 136, the isolation structure 116, and the source / drain groove 138 are also covered by the internal spacer layer 148, as shown. Figure 2H-5 and Figure 2H-6 As shown in the image.

[0054] The internal spacer layer 148 may be a single or multiple dielectric material layers. In some embodiments, the internal spacer layer 148 is made of a dielectric material such as silicon oxide (SiO2), silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon carbonitride oxynitride (SiOCN), and / or oxygen-doped silicon carbonitride (Si(O)CN). In some embodiments, the internal spacer layer 148 and the dielectric sacrificial layer 142 are made of different dielectric materials. In some embodiments, the internal spacer layer 148 is formed by performing a deposition process such as ALD, CVD (such as PECVD, LPCVD, or HARP), another suitable technique, or a combination thereof.

[0055] According to some embodiments, after forming the internal spacer layer 148, an etching process is performed to form the internal spacer 150 using the internal spacer layer 148, and the resulting structure is Figure 2I-1 , Figure 2I-2 , Figure 2I-3 , Figure 2I-4 , Figure 2I-5 and Figure 2I-6 As shown in the figure. More specifically, an etching process can be performed to etch away the internal spacer layer 148 outside the slot 146. In some embodiments, the etching process includes anisotropic etching processes such as dry plasma etching, isotropic etching processes such as dry chemical etching, remote plasma etching, or wet chemical etching, or combinations thereof.

[0056] According to some embodiments, the internal spacer 150 is formed as a recessed sidewall surface adjacent to the dielectric sacrificial member 144. In some embodiments, the internal spacer 150 is located directly below the gate spacer 134. The internal spacer 150 can prevent the subsequently formed source / drain structure and gate structure from directly contacting each other, and can be configured to reduce the parasitic capacitances (i.e., Cgs and Cgd) between the gate structure and the source / drain structure. In some embodiments, the internal spacer 150 has a thickness (in the X direction) ranging from about 3 nm to about 6 nm.

[0057] As previously described, according to some embodiments, the inner spacer layer 148 and the dielectric sacrificial layer 142 are made of different materials, and therefore the inner spacer 150 and the dielectric sacrificial member 144 are made of different materials. Therefore, the inner spacer 150 can be retained when the dielectric sacrificial member 144 is removed during a subsequent process.

[0058] According to some embodiments, after forming the internal spacer 150, a semiconductor isolation component 151, a dielectric isolation component 153, and a source / drain structure 152 are formed in the source / drain recess 138, and the resulting structure is Figure 2J-1 , Figure 2J-2 , Figure 2J-3 , Figure 2J-4 , Figure 2J-5 and Figure 2J-6 As shown in the image. Furthermore... Figures 2J-7 to 2T-7 and Figures 2J-8 to 2T-8 A schematic perspective view of an intermediate stage of a semiconductor structure 100 in a first region 10 and a second region 20 according to some embodiments is shown. More specifically, Figure 2J-7 and Figure 2J-8 Illustrations are shown according to some embodiments Figures 2J-1 to 2J-6 A schematic perspective view of the structure shown.

[0059] More specifically, according to some embodiments, an interposer layer, such as a semiconductor isolation component 151, is formed in the bottom portion of the source / drain trench 138. In some embodiments, the semiconductor isolation component 151 is made of an epitaxial semiconductor material such as undoped silicon and is formed by MBE, MOCVD or VPE, another suitable technique or a combination thereof.

[0060] According to some embodiments, after forming the semiconductor isolation component 151, a dielectric isolation component 153 is formed on top of the semiconductor isolation component 151. The dielectric isolation component 153 is configured to reduce the parasitic capacitance of the resulting transistor. In some embodiments, the dielectric isolation component 153 is made of a dielectric material such as silicon oxide (SiO2), silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon carbonitride oxynitride (SiOCN), SiOC, Si, SiO2, and / or oxygen-doped silicon carbonitride (Si(O)CN) or combinations thereof. In some embodiments, the dielectric isolation component 153 is deposited using techniques such as ALD, CVD (such as HDP-CVD, LPCVD, or PECVD), another suitable technique, or combinations thereof, followed by an etch-back process. In some embodiments, the dielectric isolation component 153 has a thickness of about 2 nm to about 6 nm.

[0061] In some embodiments, the source / drain structure 152 is formed by performing an epitaxial growth process, such as MBE, MOCVD, or VPE, another suitable technique, or a combination thereof. In some embodiments, the source / drain structure 152 is doped in situ during the epitaxial process. In some embodiments, the source / drain structure 152 may be a multilayer structure, for example, comprising layers 152a and 152b formed sequentially (e.g., ...). Figure 2J-3 and Figure 2J-4 (as shown in the diagram). In some embodiments, the concentration of dopant in layer 152b is higher than the concentration of dopant in layer 152a.

[0062] In some embodiments, the source / drain structure 152 includes source / drain structures 1521 and 1522. In some embodiments, source / drain structures 1521 and 1522 include different types of dopants. In some embodiments, source / drain structure 1521 includes a P-type dopant (such as B), and source / drain structure 1522 includes an N-type dopant (such as P). In some embodiments, source / drain structures 1521 and 1522 are made of different epitaxial materials. For example, source / drain structure 1521 is a P-type source / drain structure made of SiGe, and source / drain structure 1522 is an N-type source / drain structure made of SiP. Figure 2J-5 and Figure 2J-6 As shown, the source / drain structure 1521 and the source / drain structure 1522 can have different shapes and sizes.

[0063] Source / drain structures 1521 and 1522 can be formed separately. For example, a patterned mask layer (such as a photoresist layer and / or a hard mask layer) can be formed to cover the semiconductor structure above the well region W2, and then the source / drain structure 1521 can be grown. The patterned mask layer can then be removed. Similarly, a patterned mask layer (such as a photoresist layer and / or a hard mask layer) can be formed to cover the semiconductor structure above the well region W1, and then the source / drain structure 1522 can be grown. The patterned mask layer can then be removed. According to some embodiments, once the source / drain structures 1521 and 1522 are formed, an annealing process can be performed to activate the dopants in the source / drain structures 1521 and 1522.

[0064] As previously described, because the first semiconductor material layer 106 has been replaced with dielectric sacrificial component 144 before the source / drain structure 152 is formed, Ge diffusion into the second semiconductor material layer 108 due to the annealing process can be prevented.

[0065] In some embodiments, according to certain examples, the source / drain structure 152 further includes an additional semiconductor isolation component (not shown) in the bottom portion of the source / drain recess 138. In some embodiments, the semiconductor isolation component is made of an epitaxial semiconductor material such as undoped silicon and is formed by MBE, MOCVD or VPE, another suitable technique or a combination thereof.

[0066] According to some embodiments, after forming the source / drain structure 152, a conformally formed contact etch stop layer (CESL) 154 is formed to cover the source / drain structure 152, and an interlayer dielectric (ILD) layer 156 and a mask layer 158 are formed over the contact etch stop layer 154, and the resulting structure is Figure 2K-1 , Figure 2K-2 , Figure 2K-3 , Figure 2K-4 , Figure 2K-5 , Figure 2K-6 , Figure 2K-7 and Figure 2K-8 As shown in the image.

[0067] In some embodiments, the contact etch stop layer 154 is made of a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, another suitable dielectric material, or a combination thereof. The dielectric material for the contact etch stop layer 154 can be conformally deposited over the semiconductor structure by performing CVD, ALD, other suitable methods, or a combination thereof.

[0068] The interlayer dielectric layer 156 may comprise a multilayer made of various dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass (PSG), borosilicate glass (BPSG), or other suitable low-k dielectric materials. The interlayer dielectric layer 156 may be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other suitable processes.

[0069] According to some embodiments, after depositing the contact etch stop layer 154 and the interlayer dielectric layer 156, a planarization process, such as CMP or etch-back, is performed until the dummy gate electrode 124 is exposed. That is, the hard mask structure 126 can be removed during the planarization process. Next, according to some embodiments, the interlayer dielectric layer 156 is recessed to form a groove, and a mask layer 158 is formed in the groove, such as... Figure 2K-3 , Figure 2K-4 , Figure 2K-5 , Figure 2K-6 , Figure 2K-7 and Figure 2K-8 As shown in the diagram, mask layer 158 is made of a dielectric material, such as SiN, SiCN, SiOC, SiOCN, HfO2, ZrO2, or HfAlO. x HfSiO x Al2O3, etc. In some embodiments, the mask layer 158 has a thickness in the range of about 23 nm to about 30 nm.

[0070] Next, according to some embodiments, a mask structure 160 is formed to cover the dummy gate electrode 124, the gate spacer 134, the contact etch stop layer 154, and the mask layer 158, such as Figure 2L-1 , Figure 2L-2 , Figure 2L-3 , Figure 2L-4 , Figure 2L-5 , Figure 2L-6 , Figure 2L-7 and Figure 2L-8 As shown in the figure. Furthermore, according to some embodiments, the mask structure 160 includes an opening 162 that partially exposes the dummy gate electrode 124. In some embodiments, the opening 162 does not vertically overlap with any of the fin structures 104. In some embodiments, the width of the opening 162 is less than the distance between the mutually facing sidewalls of two adjacent fin structures 104 (i.e., the distance between fin structures 104-1 and 104-2 and the distance between fin structures 104-3 and 104-4).

[0071] In some embodiments, the mask structure 160 includes multiple material layers, such as a first mask layer 164, a second mask layer 166 above the first mask layer 164, and a photoresist layer 168 above the second mask layer 166. In some embodiments, the first mask layer 164 is made of titanium nitride (TiN), carbon-doped silicon dioxide (e.g., SiO2:C), titanium oxide (TiO), boron nitride (BN), etc. In some embodiments, the second mask layer 166 is made of silicon nitride (SiN), silicon oxynitride (SiON), etc.

[0072] According to some embodiments, after the mask structure 160 is formed, an etching process 172 is performed to form trenches 170-1 and 170-2 in the dummy gate electrode 124, and then the mask structure 160 is removed, as shown below. Figure 2M-1 , Figure 2M-2 , Figure 2M-3 , Figure 2M-4 , Figure 2M-5 , Figure 2M-6 , Figure 2M-7 and Figure 2M-8 As shown in the diagram. More specifically, according to some embodiments, during etching process 172, the portion of the dummy gate electrode 124 exposed by opening 162 is etched, such that the dielectric layer 122 is partially exposed by trenches 170-1 and 170-2. Furthermore, according to some embodiments, trench 170-1 is located between fin structures 104-1 and 104-2 in the first region 10 and is laterally spaced from fin structures 104-1 and 104-2. Similarly, according to some embodiments, trench 170-2 is located between fin structures 104-3 and 104-4 in the second region 20 and is laterally spaced from fin structures 104-3 and 104-4. Etching process 172 can be a wet etching process or a dry etching process. After performing the etching process, mask structure 160 can be removed.

[0073] As previously described, according to some embodiments, the width of the opening 162 is less than the distance between adjacent fin structures 104, and therefore the width of the groove 170-1 is less than the distance between the sidewall 105-1 of fin structure 104-1 and the sidewall 105-2 of fin structure 104-2. Figure 2M-1 As shown in the figure. Similarly, according to some embodiments, the width of the groove 170-2 is less than the distance between the sidewalls 105-3 and 105-4 of the fin structure 104-3, as shown in the figure. Figure 2M-2 As shown in the diagram. Therefore, trenches 170-1 and 170-2 can be formed between two adjacent fin structures 104 without exposing the fin structure 104. Thus, the risk of damaging the fin structure 104 during the etching process 172 used to form trenches 170-1 and 170-2 can be reduced.

[0074] In some embodiments, the shortest distance D1 between the sidewalls of trenches 170-1 / 170-2 and the nearest sidewalls of fin structures 104 (e.g., sidewalls 105-1, 105-2, 105-3, and 105-4) ranges from about 8 nm to about 14 nm. In some embodiments, portions of the dummy gate electrode 124 are retained at the opposite sidewalls of each of the fin structures 104.

[0075] According to some embodiments, after forming trenches 170-1 and 170-2, a trimming process 174 is performed to widen the trenches 170-1 and 170-2, and the resulting structure is Figure 2N-1 , Figure 2N-2 , Figure 2N-3 , Figure 2N-4 , Figure 2N-5 , Figure 2N-6 , Figure 2N-7 and Figure 2N-8 As shown above, prior to the trimming process 174, the widths of trenches 170-1 and 170-2 are less than the distance between two adjacent fin structures 104, thereby avoiding damage to the fin structures 104 during the etching process 172. Next, according to some embodiments, the dimensions of trenches 170-1 and 170-2 are adjusted (i.e., enlarged) to ensure that the dummy gate electrode 124 laterally sandwiched between the sidewalls of adjacent fin structures 104 is completely removed by performing the trimming process 174, as shown below. Figure 2N-1 , Figure 2N-2 , Figure 2N-7 and Figure 2N-8 As shown in the image.

[0076] More specifically, according to some embodiments, the sidewall portions of the dummy gate electrode 124 exposed by trenches 170-1 and 170-2 are partially removed (e.g., etched), thereby forming enlarged trenches 170-1' and 170-2'. The trimming process 174 can be an etching process, such as a dry etching process, a wet etching process, or a combination thereof. In some embodiments, the etch selectivity between the dielectric layer 122 and the dummy gate electrode 124 in the trimming process 174 is greater than the etch selectivity between the dielectric layer 122 and the dummy gate electrode 124 in the etching process 172, such that the fin structure 104 can be protected by the dielectric layer 122 during the trimming process 174, and the risk of damage to the fin structure 104 can be prevented.

[0077] According to some embodiments, each of the enlarged trenches 170-1' and 170-2' has a top portion 170'T and a bottom portion 170'B located below the top portion 170'T, and the top portion 170'T is wider than the bottom portion 170'B, as shown below. Figure 2N-1 , Figure 2N-2 , Figure 2N-7 and Figure 2N-8 As shown in the image.

[0078] In some embodiments, the top portion 170'T of the enlarged groove 107-1' perpendicularly overlaps with the sidewalls 105-1 and 105-2 of the fin structure 104-1 and fin structure 104-2. In some embodiments, the top portion 170'T of the enlarged groove 107-2' perpendicularly overlaps with the sidewalls 105-3 and 105-4 of the fin structure 104-3 and fin structure 104-4. In some embodiments, the top portion 170'T of the enlarged groove 107-1' also overlaps with the top surfaces of the fin structures 104-1 and 104-2. In some embodiments, the top portion 170'T of the enlarged groove 107-2' also overlaps with the top surfaces of the fin structures 104-3 and 104-4. In some embodiments, the distance D2 between the nearest sidewall of the top portion 170'T above the sidewalls (e.g., sidewalls 105-1, 105-2, 105-3 and 105-4) and the fin structure 104 (e.g., fin structures 104-1, 104-2, 104-3 and 104-4) is less than about 4 nm.

[0079] Furthermore, according to some embodiments, during the finishing process 174, the portion of the dummy gate electrode 124 laterally sandwiched between the sidewall 105-1 of fin structure 104-1 and the sidewall 105-2 of fin structure 104-2, as well as the portion of the dummy gate electrode 124 laterally sandwiched between the sidewall 105-3 of fin structure 104-3 and the sidewall 105-4 of fin structure 104-4, is completely removed.

[0080] Furthermore, according to some embodiments, the top portion of the dummy gate electrode 124 is also partially removed during trimming process 174. Therefore, according to some embodiments, after performing trimming process 174, the height H1 of the dummy gate electrode 124 is lower than the height H2 of the gate spacer 134. Figure 2N-3 , Figure 2N-4 , Figure 2N-7 and Figure 2N-8 As shown

[0081] According to some embodiments, after forming the enlarged trenches 170-1' and 170-2', isolation members 176-1 and 176-2 are formed in the enlarged trenches 170-1' and 170-2', respectively, and the resulting structure is Figure 2O-1 , Figure 2O-2 , Figure 2O-3 , Figure 2O-4 , Figure 2O-5 , Figure 2O-6 , Figure 2O-7 and Figure 2O-8As shown in the figure. According to some embodiments, because the isolation members 176-1 and 176-2 are formed in the enlarged grooves 170-1' and 170-2', the isolation members 176-1 and 176-2 include a top portion 176T and a bottom portion 176B that is narrower than the top portion 176T.

[0082] In some embodiments, according to certain examples, the top portion 176T of the isolation member 176-1 partially overlaps with fin structures 104-1 and 104-2, and the bottom portion 176B of the isolation member 176-1 is laterally sandwiched between fin structures 104-1 and 104-2. In some embodiments, according to certain examples, the top portion 176T of the isolation member 176-2 partially overlaps with fin structures 104-3 and 104-4, and the bottom portion 176B of the isolation member 176-2 is laterally sandwiched between fin structures 104-3 and 104-4. In some embodiments, the width W3 of the top portion 176T of the isolation members 176-1 and 176-2 is greater than the distance between fin structures 104-1 and 104-2 and the distance between fin structures 104-3 and 104-4.

[0083] Isolation components 176-1 and 176-2 may include a variety of isolation materials. In some embodiments, isolation component 176-1 includes a shell layer 178-1 and a core material 180-1 surrounded by the shell layer 178-1. Similarly, according to some embodiments, isolation component 176-2 includes a shell layer 178-2 and a core material 180-2 surrounded by the shell layer 178-2. The formation of isolation components 176-1 and 176-2 may include forming shell layers 178-1 and 178-2 that form liner-enlarged trenches 170-1' and 170-2', a dummy gate electrode 124, a gate spacer 134, a contact etch stop layer 154, and a mask layer 158, and then forming core materials 180-1 and 180-2 over shell layers 178-1 and 178-2. After forming the core materials 180-1 and 180-2, a polishing process can be performed to remove the core materials 180-1 and 180-2 and the shell layers 178-1 and 178-2 located above the dummy gate electrode 124, gate spacer 134, contact etch stop layer 154, and mask layer 158, so that isolation members 176-1 and 176-2 can be formed in the enlarged trenches 170-1' and 170-2'. Furthermore, according to some embodiments, during the polishing process (e.g., CMP process), the top portions of the dummy gate electrode 124, gate spacer 134, contact etch stop layer 154, and mask layer 158 are also partially removed. Therefore, according to some embodiments, the dummy gate electrode 124 is... Figure 2O-1 and Figure 2O-2 The height H3 of the isolation components 176-1 and 176-2 after formation is less than that of the dummy gate electrode 124. Figure 2N-1 and Figure 2N-2 The isolation components 176-1 and 176-2 shown are formed at a height H1. Furthermore, according to some embodiments, the isolation components 176-1 and 176-2 also have a height H3.

[0084] In some embodiments, each of the shells 178-1 and 178-2 has a thickness ranging from about 1 nm to about 2 nm. The thickness of the shells 178-1 and 178-2 can determine the size and shape of the subsequently formed extension (details will be described later). In some embodiments, the shells 178-1 and 178-2 are made of a dielectric material formed at a relatively low temperature (e.g., less than 550°C). In some embodiments, the shells 178-1 and 178-2 are made of SiN formed at a low temperature (e.g., about 500°C). In some embodiments, the core materials 180-1 and 180-2 are made of an oxide formed at a low temperature. In some embodiments, the core materials 180-1 and 180-2 are made of a dielectric material formed at a relatively high temperature (e.g., greater than 550°C). In some embodiments, the core materials 180-1 and 180-2 are made of SiN or SiCN formed at a high temperature. In some embodiments, the shells 178-1 and 178-2 and the core materials 180-1 and 180-2 are made of SiN formed at different temperatures. In subsequent processes, the shells 178-1 and 178-2 can be more easily removed (e.g., etched) than the core materials 180-1 and 180-2.

[0085] According to some embodiments, after forming isolation components 176-1 and 176-2, the dummy gate electrode 124 is removed to form the gate trench 182, and the resulting structure is Figure 2P-1 , Figure 2P-2 , Figure 2P-3 , Figure 2P-4 , Figure 2P-5 , Figure 2P-6 , Figure 2P-7 and Figure 2P-8 As shown in the diagram. The removal process may include one or more etching processes. For example, when the dummy gate electrode 124 is made of polysilicon, a wet etchant such as a tetramethylammonium hydroxide (TMAH) solution can be used to selectively remove the dummy gate electrode 124. Figure 2P-1 , Figure 2P-2 , Figure 2P-7 and Figure 2P-8 As shown, according to some embodiments, portions of dielectric layer 122 not covered by isolation components 176-1 and 176-2 are exposed through gate trench 182.

[0086] According to some embodiments, after removing the dummy gate electrode 124, a trimming process 184 is performed to narrow the top portions of the isolation members 176-1 and 176-2, and the resulting structure is... Figure 2Q-1, Figure 2Q-2 , Figure 2Q-3 , Figure 2Q-4 , Figure 2Q-5 , Figure 2Q-6 , Figure 2Q-7 and Figure 2Q-8 As shown in the figure. More specifically, trimming process 184 is configured to reduce the width of the top portions of the isolation members 176-1 and 176-2, such that the gate structure subsequently formed can have a larger top width, and thus more spacing will be available for the contacts subsequently formed to land on the gate structure. In some embodiments, trimming process 184 is a dry etching process, a wet etching process, or a combination thereof.

[0087] According to some embodiments, during trimming process 184, isolation members 176-1 and 176-2 are etched laterally from the sidewalls exposed by gate trench 182 and vertically from the top surface, thereby forming isolation members 176-1' and 176-2' (including shell layers 178-1' and 178-2' and core materials 180-1' and 180-2') with smaller top widths. According to some embodiments, each of isolation members 176-1' and 176-2' has a top portion 176T' and a bottom portion 176B', and the bottom portion 176B' is wider than the top portion 176T'. In some embodiments, the top portion 176T' of isolation members 176-1' and 176-2' has a width W4, and the width W4 of the top portion 176T' is less than... Figure 2P-1 and Figure 2P-2 The top portion 176T shown has a width W3. Furthermore, the difference between the width W4 and the width W3 ranges from about 15 nm to about 24 nm. The width W4 is relatively small, thus allowing for more spacing in subsequent processes to form the contacts. In some embodiments, the top portion 176T' of the insulating members 176-1' and 176-2' has curved sidewalls, such as... Figure 2Q-1 and Figure 2Q-2 As shown in the image.

[0088] like Figure 2Q-1 , Figure 2Q-2 , Figure 2Q-7 and Figure 2Q-8 As shown, according to some embodiments, the top surface of the fin structure 104 is not covered by the isolation members 176-1' and 176-2'. Figure 2Q-1 , Figure 2Q-2 , Figure 2Q-7 and Figure 2Q-8As shown, according to some embodiments, the upper portions of shells 178-1 and 178-2 are removed, such that the resulting shells 178-1' and 178-2' surround the bottom portions of core materials 180-1' and 180-2', but not the top portions of core materials 180-1' and 180-2'. In some embodiments, the top surfaces of shells 178-1' and 178-2' are lower than the top surface of the topmost second semiconductor material layer 108.

[0089] Furthermore, according to some embodiments, because the isolation components 176-1 and 176-2 are also etched from their top surfaces during the trimming process 184, the top surfaces of the isolation components 176-1' and 176-2' are lower than the top surface of the gate spacer 134, as shown below. Figure 2Q-7 and Figure 2Q-8 As shown in the figure. In some embodiments, the height difference D3 between the isolation members 176-1' and 176-2' and the gate spacer 134 is in the range of about 7 nm to about 12 nm. Figure 2Q-1 and Figure 2Q-2 The height H4 of the isolation components 176-1' and 176-2' shown is less than Figure 2P-1 and Figure 2P-2 The height H3 of the isolation components 176-1 and 176-2 shown. In some embodiments, such as Figure 2Q-1 and Figure 2Q-2 As shown, the height difference D4 between the isolation components 176-1' and 176-2' and the fin structures 104-1, 104-2, 104-3, and 104-4 is in the range of approximately 20 nm to approximately 28 nm. The height difference D4 can be substantially equal to the height of the gate structure formed above the channel region formed in subsequent processes, and therefore the height difference D4 should not be too small, or the gate structure formed later may not have sufficient height.

[0090] According to some embodiments, after performing trimming process 184, and then performing etching process 186 to etch dielectric layer 122, capping layer 120, and dielectric sacrificial member 144, the resulting structure is... Figure 2R-1 , Figure 2R-2 , Figure 2R-3 , Figure 2R-4 , Figure 2R-5 , Figure 2R-6 , Figure 2R-7 and Figure 2R-8As shown in the figure. More specifically, according to some embodiments, the dielectric layer 122 and capping layer 120 exposed by the gate trench 182 are removed, such that the sidewalls of the dielectric sacrificial member 144 are exposed by the gate trench 182 during the etching process 186. The dielectric sacrificial members 144 are then etched from their exposed sidewalls until the dielectric sacrificial members 144 are completely removed to form the gate gap 188. According to some embodiments, the second semiconductor material layer 108 of the fin structures 104-1, 104-2, 104-3, and 104-4 can then be used as channel layers 108-1', 108-2', 108-3', and 108-4', as Figure 2R-1 , Figure 2R-2 , Figure 2R-3 , Figure 2R-4 , Figure 2R-7 and Figure 2R-8 As shown in the figure. In some embodiments, according to some examples, channel layers 108-1', 108-2', 108-3', and 108-4' are vertically suspended above substrate 102 and spaced apart from each other in the Z direction by gate gap 188. Furthermore, according to some examples, channel layers 108-1', 108-2', 108-3', and 108-4' extend laterally in the X direction between and between source / drain structures 152.

[0091] Furthermore, because the fin structures 104-1, 104-2, 104-3 and 104-4 in the first region 10 and the second region 20 have different widths, the dielectric sacrificial component 144 in the first region 10 and the second region 20 also have different widths, resulting in different structures after the etching process 186 is performed.

[0092] More specifically, in the second region 20, the dielectric sacrificial member 144 has a smaller width, and therefore the dielectric sacrificial member 144 in the second region 20 will be removed faster than the dielectric sacrificial member 144 in the first region 10. After the dielectric sacrificial member 144, the etchant can further etch through the shell 178-2' and reach the dielectric layer 122 and the capping layer 120. Therefore, according to some embodiments, in the second region 20, the shell 178-2', dielectric layer 122, and capping layer 120 on the sidewalls of the core material 180-2 are also etched and removed during the etching process 186, as shown below. Figure 2R-2 and Figure 2R-8As shown in the figure. According to some embodiments, after performing etching process 186, an isolation member 176-2” is formed, and the isolation member 176-2” includes a core material 180-2” and a shell layer 178-2” located below the bottom surface of the core material 180-2”. In addition, according to some embodiments, portions of the dielectric layer 122 and the capping layer 120 are retained below the isolation member 176-2” and are vertically sandwiched between the isolation member 176-2” and the isolation structure 116.

[0093] On the other hand, in the first region 10, the dielectric sacrificial member 144 has a larger width, and therefore it will take more time to remove the dielectric sacrificial member 144 in the first region 10. Therefore, according to some embodiments, only the shell layer 178-1', dielectric layer 122, and capping layer 120 on the sidewalls of the core material 180-1' are partially etched during the etching process 186, such as... Figure 2R-1 and Figure 2R-7 As shown in the figure. That is, according to some embodiments, the dielectric layer 122, the capping layer 120, and the shell layer 178-1' laterally sandwiched between the channel layers 108-1' and 108-2' and the core material 180-1' are not completely removed during the etching process 186. According to some embodiments, after the etching process 186 is performed, an isolation member 176-1" is formed, and the isolation member 176-1" includes the core material 180-1" and the shell layer 178-1" located at the sidewalls and bottom surface of the bottom portion of the core material 180-1".

[0094] Furthermore, according to some embodiments, an extension 123 is formed by the dielectric layer 122, and the extension 123 extends laterally to the channel layers 108-1' and 108-2'. In some embodiments, a portion of the cover layer 120 is retained between the extension 123 and the channel layers 108-1' and 108-2'. In some embodiments, according to some embodiments, portions of the dielectric layer 122 and the cover layer 120 are retained below the isolation member 176-1" and vertically sandwiched between the isolation member 176-1" and the isolation structure 116. Furthermore, according to some embodiments, a portion of the shell layer 178-1" is vertically sandwiched between the core material 180-1" and the dielectric layer 122, and some portions of the shell layer 178-1" are laterally sandwiched between the core material 180-1" and the extension 123. Due to the shell layer 178-1", the contours of the extension 123 and the core material 180-1" can be better controlled.

[0095] Furthermore, because the isolation components 176-1” and 176-2” have narrower top portions, during etching process 186, after the dielectric layer 122 and the capping layer 120 are removed, the topmost channel layers 108-1’, 108-2’, 108-3’, and 108-4’ are etched from their opposite sidewalls and their top surfaces. Therefore, according to some embodiments, the topmost channel layers 108-1’, 108-2’, 108-3’, and 108-4’ can be etched more than those channel layers below them.

[0096] In some embodiments, the channel layer 108-1' includes a top channel layer 108-1'_T, an intermediate channel layer 108-1'_M below the top channel layer 108-1'_T, and a bottom channel layer 108-1'_B below the intermediate channel layer 108-1'_M. Furthermore, according to some embodiments, the width of the top channel layer 108-1'_T is smaller than the width of the intermediate channel layer 108-1'_M and the bottom channel layer 108-1'_B. Additionally, an extension 123 is formed between the isolation member 176-1" and the channel layers 108-1'_M and 180-1'_B, but not between the isolation member 176-1" and the channel layer 108-1'_T.

[0097] Similarly, according to some embodiments, the channel layer 108-2' includes a top channel layer 108-22'_T, an intermediate channel layer 108-2'_M below the top channel layer 108-2'_T, and a bottom channel layer 108-2'_B below the intermediate channel layer 108-2'_M. Furthermore, according to some embodiments, the width of the top channel layer 108-2'_T is smaller than the width of the intermediate channel layer 108-2'_M and the bottom channel layer 108-2'_B. Additionally, an extension 123 is formed between the isolation member 176-1" and the channel layers 108-2'_M and 180-2'_B, but not between the isolation member 176-1" and the channel layer 108-2'_T.

[0098] According to some embodiments, channel layer 108-3' includes a top channel layer 108-3'_T, an intermediate channel layer 108-3'_M below the top channel layer 108-3'_T, and a bottom channel layer 108-3'_B below the intermediate channel layer 108-3'_M. Furthermore, according to some embodiments, the width of the top channel layer 108-3'_T is smaller than the width of the intermediate channel layer 108-3'_M and the bottom channel layer 108-3'_B. According to some embodiments, channel layer 108-4' includes a top channel layer 108-4'_T, an intermediate channel layer 108-4'_M below the top channel layer 108-4'_T, and a bottom channel layer 108-4'_B below the intermediate channel layer 108-4'_M. Furthermore, according to some embodiments, the width of the topmost channel layer 108-4'_T is smaller than the width of the middle channel layer 108-4'_M and the width of the bottommost channel layer 108-4'_B. For example... Figure 2R-1 and Figure 2R-2 As shown, the topmost channel layers 108-1'_T, 108-2'_T, 108-3'_T and 108-4'_T have rounded corners.

[0099] Etching process 186 may include one or more etching processes. For example, etching process 186 may include plasma dry etching, dry chemical etching, and / or wet etching. As previously described, because dielectric sacrificial member 144 and second semiconductor material layer 108 have relatively high etch selectivity (e.g., compared to first semiconductor material layer 106 and second semiconductor material layer 108), dielectric sacrificial member 144 can be completely removed without excessive removal of second semiconductor material layer 108.

[0100] Next, according to some embodiments, a gate structure 190 is formed in the gate trench 182 and the gate gap 188, including 190-1, 190-2, 190-3 and 190-4, and the resulting structure is Figure 2S-1 , Figure 2S-2 , Figure 2S-3 , Figure 2S-4 , Figure 2S-5 , Figure 2S-6 , Figure 2S-7 and Figure 2S-8 As shown in the figure. In some embodiments, the gate structure 190 encloses the channel layers 108-1', 108-2', 108-3' and 108-4' and extends longitudinally in the Y direction.

[0101] Furthermore, gate structures 190-1 and 190-2 are separated by isolation member 176-1", and gate structures 190-3 and 190-4 are separated by isolation member 176-2". According to some embodiments, because isolation members 176-1" and 176-2" are configured to isolate adjacent gate structures 190, the top surface of gate structure 190 is substantially flush with the top surfaces of isolation members 176-1" and 176-2". Therefore, although isolation members 176-1" and 176-2" have narrower top portions through the implementation of trimming process 186, the height of isolation members 176-1" and 176-2" should not be too small, or gate structures 190 may also need to have a relatively small height. In some embodiments, the height H5 of the gate structure 190 above the topmost channel layer (i.e., channel layers 108-1'_T, 108-2'_T, 108-3'_T and 108-4'_T) is in the range of about 13 nm to about 15 nm (i.e., the distance between the top surface of the gate structure 190 and the top surface of the channel layers 108-1'_T, 108-2'_T, 108-3'_T and 108-4'_T).

[0102] In some embodiments, the gate structure 190 includes a top portion formed between the gate spacers 134 and an inner portion formed between the inner spacers 150. In some embodiments, the width W of the top portion formed between the gate spacers 134 is... MGT Within the range of approximately 15 nm to approximately 17 nm. In some embodiments, the width W of the inner portion formed between the inner spacers 150 MGB In the range from approximately 15nm to approximately 17nm. For example... Figure 2S-1 As shown, according to some embodiments, the top surface of the substrate structure 104B is higher than the top surface of the isolation structure 116, and therefore the interface between the gate structure 190 and the substrate structure 104B is higher than the interface between the gate structure 190 and the isolation structure 116. In some embodiments, the height difference between the interface between the gate structure 190 and the substrate structure 104B and the interface between the gate structure 190 and the isolation structure 116 is in the range of about 4 nm to about 12 nm.

[0103] In some embodiments, each of the gate structures 190 includes an interface layer 192, a gate dielectric layer 194, and a gate electrode layer 196. The interface layer 192 can be used to improve the interface between the channel layers 108-1', 108-2', 108-3', and 108-4' and the subsequently formed dielectric layer. Furthermore, the interface layer 192 can help suppress charge carrier mobility degradation in the channel layers 108-1', 108-2', 108-3', and 108-4', which serve as the channel regions of the transistor. In some embodiments, the interface layer 192 is an oxide layer formed by performing a thermal process. In some embodiments, a portion of the capping layer 120 is oxidized to form the interface layer 192. In some embodiments, the interface layer 192 has a thickness ranging from about 0.5 nm to about 1.5 nm.

[0104] According to some embodiments, after forming the interface layer 192, a gate dielectric layer 194 is conformally formed to cover the interface layer 192, as well as the bottom surface and sidewalls of the gate trench 182 and the gate gap 188. Furthermore, according to some embodiments, the gate dielectric layer 194 covers the core materials 180-1” and 180-2”, the shell layers 178-1” and 178-2”, and the sidewalls of the extension 123. In some embodiments, the gate dielectric layer 194 also covers (e.g., in contact with) the dielectric layer 122 and the capping layer 120 beneath the isolation members 176-1” and 176-2”.

[0105] In some embodiments, the gate dielectric layer 194 is made of a dielectric material such as HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-alumina (HfO2-Al2O3) alloy, La2O3-Al2O3 or LaO, other suitable high-k dielectric materials, or combinations thereof. In some embodiments, the gate dielectric layer 194 is formed using CVD, ALD, other suitable methods, or combinations thereof. In some embodiments, the gate dielectric layer 194 has a thickness ranging from about 1 nm to about 2 nm.

[0106] According to some embodiments, after forming the gate dielectric layer 194, a gate electrode layer 196 is formed over the gate dielectric layer 194. In some embodiments, the gate electrode layer 196 comprises multiple layers. In some embodiments, the gate electrode layer 196 comprises one or more work function metal layers. In some embodiments, the work function metal layers are made of titanium nitride, tantalum nitride, tungsten nitride, tantalum, etc. In some embodiments, the gate electrode layer 196 includes a gate fill layer formed over the work function layer. In some embodiments, the gate fill layer is made of a conductive material, such as tungsten, titanium, tantalum, cobalt, copper, ruthenium, etc. In some embodiments, the gate fill layer is formed using CVD, ALD, electroplating, another suitable method, or a combination thereof.

[0107] In some embodiments, after depositing the gate dielectric layer 194 and the gate electrode layer 196, a polishing process, such as a CMP process, is performed to remove excess gate dielectric layer 194 and gate electrode layer 196 over the isolation members 176-1” and 176-2”, the gate spacer 134, the contact etch stop layer 154, and the mask layer 158. Furthermore, a polishing process may be performed until the top surfaces of the isolation members 176-1” and 176-2” are exposed, such that during the polishing process, the top portions of the gate spacer 134 and the contact etch stop layer 154 are partially removed, and the mask layer 158 is completely removed.

[0108] Although not clearly shown in the figures, gate structures 190-1 and 190-2 may include different material layers (e.g., different work function metal layers), and gate structures 190-3 and 190-4 may include different material layers (e.g., different work function metal layers). Furthermore, according to some embodiments, gate structures 190-1 and 190-2 are electrically isolated from each other by isolation member 176-1”, and gate structures 190-3 and 190-4 are electrically isolated from each other by isolation member 176-2”. In some embodiments, gate structure 190-2 is spaced apart from gate structure 190-1 by a first distance. Gate structure 190-3 is spaced apart from gate structure 190-4 by a second distance. The first distance may be different from the second distance.

[0109] Next, according to some embodiments, an etch stop layer 200 and a dielectric layer 202 are formed over the gate structure 190, the gate spacer 134, the contact etch stop layer 154, and the interlayer dielectric layer 156, and contacts 204 and 206 are formed to connect to the gate structure 190 and the source / drain structure 152, respectively. According to some embodiments, the resulting semiconductor structure 100... Figure 2T-1 , Figure 2T-2 , Figure 2T-3 , Figure 2T-4 , Figure 2T-5 , Figure 2T-6 , Figure 2T-7 and Figure 2T-8 As shown in the image. Figure 3A and Figure 3B The layouts of semiconductor structures 100 in a first region 10 and a second region 20 according to some embodiments are shown respectively.

[0110] More specifically, according to some embodiments, an etch stop layer 200 is formed over the gate structure 190 and the isolation components 176-1” and 176-2”, such as Figure 2T-1 and Figure 2T-2 As shown in the diagram. Furthermore, according to some embodiments, an etch stop layer 200 is also formed over the gate spacer 134, the contact etch stop layer 154, and the interlayer dielectric layer 156, as illustrated. Figure 2T-3, Figure 2T-4 , Figure 2T-5 , Figure 2T-6 , Figure 2T-7 and Figure 2T-8 As shown in the figure. According to some embodiments, after the etch stop layer 200 is formed, the dielectric layer 202 is formed over the etch stop layer 200.

[0111] In some embodiments, the etch stop layer 200 is made of a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, another suitable dielectric material, or a combination thereof. The dielectric material used for the etch stop layer 200 can be conformally deposited over the semiconductor structure by performing CVD, ALD, other application methods, or combinations thereof. The dielectric layer 202 can comprise a multilayer made of various dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass (PSG), borosilicate glass (BPSG), or other suitable low-k dielectric materials. The dielectric layer 202 can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other suitable processes.

[0112] According to some embodiments, after the etch stop layer 200 and the dielectric layer 202 are formed, a contact 204 is formed over the gate structure 190, and a contact 206 is formed over the source / drain structure 152, such as... Figure 2T-1 , Figure 2T-2 , Figure 2T-3 , Figure 2T-4 , Figure 2T-5 , Figure 2T-6 , Figure 2T-7 , Figure 2T-8 , Figure 3A and Figure 3B As shown in the diagram. More specifically, according to some embodiments, the contact 204 is formed through the etch stop layer 200 and the dielectric layer 202, and rests on the top surface of the gate structures 190-1 and 190-4, as illustrated. Figure 2T-1 , Figure 2T-2 , Figure 2T-7 and Figure 2T-8 As shown in the diagram. As previously described, because the isolation members 176-1” and 176-2” have narrower top portions, the gate structure 190 can have a wider top portion. Therefore, the contact 204 can have a larger forming window above the gate structure 190.

[0113] Forming the contact 204 may include: forming a contact trench through the etch stop layer 200 and the dielectric layer 202 to partially expose the gate structures 190 (i.e., gate structures 190-1 and 190-4); and then forming the contact 204 in the contact trench above the top surface of the gate structures 190. In some embodiments, the contact 204 is made of a conductive material, including aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), titanium nitride (TiN), cobalt, tantalum nitride (TaN), nickel silicide (NiS), cobalt silicide (CoSi), copper silicide, tantalum carbide (TaC), tantalum silicon nitride (TaSiN), tantalum carbonitride (TaCN), titanium aluminum nitride (TiAl), titanium aluminum nitride (TiAlN), other suitable conductive materials, or combinations thereof.

[0114] Contact 204 may also include a gasket and / or a barrier layer. For example, a gasket (not shown) may be formed on the sidewalls and bottom of the contact trench. The gasket may be made of silicon nitride, but any other suitable dielectric material may be used as an option. The gasket may be formed using a plasma-enhanced chemical vapor deposition (PECVD) process, but other suitable processes such as physical vapor deposition or thermal processes may be used as options. A barrier layer (not shown) may be formed over the gasket (if present) and may cover the sidewalls and bottom of the opening. The barrier layer may be formed using chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma-enhanced CVD (PECVD), plasma-enhanced physical vapor deposition (PEPVD), atomic layer deposition (ALD), or any other suitable deposition process. The barrier layer may be made of tantalum nitride, but other materials such as tantalum, titanium, titanium nitride, etc., may also be used.

[0115] In some embodiments, according to certain examples, the contact 206 is formed to pass through the dielectric layer 202, the etch stop layer 200, the interlayer dielectric layer 156, and the contact etch stop layer 154, and is terminated on the source / drain structure 152, such as... Figure 2T-3 , Figure 2T-4 , Figure 2T-5 and Figure 2T-6 As shown in the diagram. Furthermore, according to some embodiments, a silicide layer is formed over the source / drain structure 152 before forming the contact 206. In some embodiments, at least one of the contacts 206 has a width (in the Y direction) greater than the width of the underlying source / drain structure 152, as shown in the diagram. Figure 2T-5 and Figure 2T-6 As shown in the image.

[0116] Contact 206 can be formed by forming a contact trench through dielectric layer 202, etch stop layer 200, interlayer dielectric layer 156, and contact etch stop layer 154 to expose source / drain structure 152. Subsequently, silicide layer 205 can be formed over the exposed portion of source / drain structure 152, and contact 206 can be formed in the contact trench above silicide layer 205. Silicide layer 205 can be formed by forming a metal layer and an annealed metal layer over the top surface of source / drain structure 152, such that the metal layer reacts with source / drain structure 152 to form silicide layer 205. After forming silicide layer 205, unreacted metal layer can be removed.

[0117] In some embodiments, the contact 206 is made of a conductive material, including aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), titanium nitride (TiN), cobalt, tantalum nitride (TaN), nickel silicide (NiS), cobalt silicide (CoSi), copper silicide, tantalum carbide (TaC), tantalum silicon nitride (TaSiN), tantalum carbonitride (TaCN), titanium aluminum nitride (TiAl), titanium aluminum nitride (TiAlN), other suitable conductive materials, or combinations thereof.

[0118] Contact 206 may also include a gasket and / or a barrier layer. For example, a gasket (not shown) may be formed on the sidewalls and bottom of the contact trench. The gasket may be made of silicon nitride, but any other suitable dielectric material may be used as an option. The gasket may be formed using a plasma-enhanced chemical vapor deposition (PECVD) process, but other suitable processes such as physical vapor deposition or thermal processes may be used as options. A barrier layer (not shown) may be formed over the gasket (if present) and may cover the sidewalls and bottom of the opening. The barrier layer may be formed using chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma-enhanced CVD (PECVD), plasma-enhanced physical vapor deposition (PEPVD), atomic layer deposition (ALD), or any other suitable deposition process. The barrier layer may be made of tantalum nitride, but other materials such as tantalum, titanium, titanium nitride, etc., may also be used.

[0119] As described above, according to some embodiments, the semiconductor structure 100 includes a first region 10 and a second region 20, and the fin structures 104-1 and 104-2 in the first region 10 are wider than the fin structures 104-3 and 104-4 in the second region 20. Furthermore, a gate structure 190 is formed around the fin structure 104, and isolation members 176-1” and 176-2” are formed to isolate the gate structure 190. Moreover, because the dimensions and shapes of the isolation members 176-1” and 176-2” are formed and adjusted by performing multiple etching and trimming processes, the resulting isolation members 176-1” and 176-2” can be incorporated into various layouts and applications. Furthermore, the isolation members 176-1” and 176-2” may have a narrower top width and a wider bottom width designed according to some embodiments. In some embodiments, the isolation members 176-1” and 176-2” have curved sidewalls.

[0120] According to some embodiments, in the first region 10, the semiconductor structure 100 includes channel layers 108-1' and 108-2', gate structures 190-1 and 190-2' enclosing the channel layers 108-1' and 108-2', and an isolation component 176-1' separating the gate structures 190-1 and 190-2', such as Figure 2T-1 , Figure 2T-3 , Figure 2T-5 , Figure 2T-7 and Figure 3A As shown in the figure. In some embodiments, the interface between the isolation member 176-1” and the gate structures 190-1 and 190-2 has a curved profile.

[0121] Furthermore, according to some embodiments, the width W4 of the top surface of the core material 180-1” of the isolation member 176-1” is smaller than the width W5 of the bottom surface of the core material 180-1”, such as Figure 2T-1 As shown in the figure. In some embodiments, the difference between the distance D5 between the channel layers 108-1'_T and 108-2'_T and the width W4 of the top surface of the core material 180-1" of the isolation member 176-1" is in the range of about 15 nm to about 25 nm. That is, according to some embodiments, the width W4 of the top surface of the core material 180-1" of the isolation member 176-1" is much smaller than the distance D5 between the channel layers 108-1'_T and 108-2'_T, and therefore there will be more spacing to form the contact 204 above the gate structure 190. In some embodiments, the distance D5 between the channel layers 108-1'_T and 108-2'_T is in the range of about 35 nm to about 45 nm. In some embodiments, the channel layers 108-1'_T and 108-2'_T are separated from the isolation member 176-1" by the gate structures 190-1 and 190-2, respectively.

[0122] Furthermore, according to some embodiments, the width of channel layer 108-1'_T is smaller than the widths of channel layers 108-1'_M and 108-1'_B, and therefore, the distance between channel layer 108-1'_T (i.e., the topmost one of channel layers 108-1') and the sidewall of isolation member 176-1" is greater than the distance between channel layers 108-1'_M and 108-1'B (i.e., the middle and bottommost one of channel layers 108-1') and the sidewall of isolation member 176-1" is greater. In some embodiments, the distance in the Y direction between channel layer 108-1'_T and the sidewall of isolation member 176-1" facing channel layer 108-1'_T is greater than the distance in the Y direction between channel layer 108-1'_B and the sidewall of isolation member 176-1" facing channel layer 108-1'_B.

[0123] The structure of channel layer 108-2' can be the same as or similar to that of channel layer 108-1' described above, and will not be repeated here.

[0124] Figure 2T-9 Illustrations are shown according to some embodiments Figure 2T-1 An enlarged cross-sectional view of the semiconductor structure 100 in region R. As previously described, the extension 123 is laterally sandwiched between the sidewall of the shell 178-1” of the isolation member 176-1” and the channel layers 108-1'_M and 108-1'_B. By forming the extension 123 connecting the isolation member 176-1” and the channel layer 108-1', the resulting device can have improved Cgd.

[0125] In some embodiments, portions 194P of the gate dielectric layer 194 extend into the shell layer 178-1”, but do not reach the core material 180-1”, such as Figure 2T-9 As shown in the diagram. That is, according to some embodiments, the portion of shell 178-1” laterally sandwiched between the gate dielectric layer 194 portion 194P and the core material 180-1” is thinner than the portion of shell 178-1” laterally sandwiched between the extension portion 123 and the core material 180-1”. In some embodiments, the portion of shell 178-1” attached to the extension portion 123 is thicker than the portion of shell 178-1” attached to the gate dielectric layer 194. In some embodiments, the lateral dimension D6 of the sidewalls of the channel layer 108-1'_B (108-1'_M) and the outer sidewalls of the gate dielectric layer 194 portion 194P is in the range of about 3 nm to about 4 nm.

[0126] In some embodiments, each of the extensions 123 has a curved top surface and a curved bottom surface in a cross-sectional view, such as Figure 2T-9As shown in the figure. Furthermore, according to some embodiments, the first edge of the curved top surface of the extension 123 (i.e., the edge of the attachment interface layer 192) is lower than the second edge of the curved top surface of the extension 123 (i.e., the edge of the attachment shell layer 178-1"). That is, according to some embodiments, the thickness of the extension 123 gradually increases from the side attached to the channel layer 108-1' to the side attached to the insulating member 176-1". Furthermore, the first edge of the curved top surface of the extension 123 may be lower than or substantially flush with the top surface of the channel layer 108-1' to which it is attached. In some embodiments, the height difference D7 between the first edge of the curved top surface of the extension 123 and the top surface of the channel layer 108-1' to which it is attached (e.g., ...) Figure 2T-9 (as shown) is not greater than 1 nm. In some embodiments, the thickness D8 of the extension portion 123 (e.g., Figure 2T-9 The thickness shown (e.g., minimum thickness) is in the range of about 3.8 nm to about 4.5 nm. In some embodiments, at least one of the extension portions 123 is smaller in size than the channel layer 108-1' in the Z direction.

[0127] By adjusting the shape and size of the extension 123, the DIBL of the resulting device can be reduced. In some embodiments, the top surface of the topmost one of the extensions 123 is lower than the top surface of the shell 178-1”.

[0128] According to some embodiments, in the second region 20, the semiconductor structure 100 includes channel layers 108-3' and 108-4', gate structures 190-3 and 190-4' enclosing the channel layers 108-3' and 108-4', and an isolation component 176-2' separating the gate structures 190-3' and 190-4', such as Figure 2T-2 , Figure 2T-4 , Figure 2T-6 , Figure 2T-8 and Figure 3B As shown in the image.

[0129] Furthermore, according to some embodiments, the width W4 of the top surface of the core material 180-2” of the isolation member 176-2” is smaller than the width W5 of the bottom surface of the core material 180-2”, such as Figure 2T-2As shown in the diagram. According to some embodiments, the width W4 of the top surface of the core material 180-2” of the isolation member 176-2” is much smaller than the distance D5 between the channel layers 108-3'T and 108-4'T, and therefore there will be more spacing to form the contact 204 above the gate structure 190. Furthermore, according to some embodiments, the width of the channel layer 108-3'_T is smaller than the width of the channel layers 108-3'_M and 108-3'_B, and therefore, the distance between the channel layer 108-3'_T (i.e., the topmost one of the channel layers 108-3') and the sidewall of the isolation member 176-2” is greater than the distance between the channel layers 108-3'_M and 108-3'B (i.e., the middle and bottommost one of the channel layers 108-3') and the sidewall of the isolation member 176-2”.

[0130] As described above, because the channel layers 108-3' and 108-4' have relatively small widths, the shell layer 178-2" and dielectric layer 122 initially sandwiched between the channel layers 108-3' and 108-4' are removed during etching process 186. Therefore, according to some embodiments, no extension is formed in the second region 20, and at least four sides of the channel layers 108-3' and 108-4' are surrounded by gate structures 190-3 and 190-4.

[0131] Figure 4A and Figure 4B A cross-sectional view of an intermediate stage in the fabrication of a semiconductor structure 100 according to some other embodiments is shown. More specifically, according to some embodiments, it is possible to implement... Figure 1A , Figure 1B , Figures 2A-1 to 2M-1 , Figures 2A-2 to 2M-2 , Figures 2A-3 to 2M-3 , Figures 2A-4 to 2M-4 , Figures 2A-5 to 2M-5 , Figures 2A-6 to 2M-6 , Figures 2J-7 to 2M-7 and Figures 2J-8 to 2M-8 The processes shown and described above are used to form trenches 170-1 and 170-2 in the dummy gate electrode 124, and a trimming process 174a is performed to form enlarged trenches 170-1'a and 170-2'a, as... Figure 4A and Figure 4B As shown in the diagram. According to some embodiments, trimming process 174a can be the same as the previously described trimming process 174, except that the sidewalls of the top portions 170'Ta of the enlarged grooves 170-1'a and 170-2'a are substantially aligned with the sidewalls of the fin structures 104-1, 104-2, 104-3, and 104-4, respectively. After forming the enlarged grooves 170-1'a and 170-2'a, the following can be implemented: Figures 2O-1 to 2T-1 , Figures 2O-2 to 2T-2 , Figures 2O-3 to 2T-3 , Figures 2O-4 to 2T-4 , Figures 2O-5 to 2T-5 , Figures 2O-6 to 2T-6 , Figures 2O-7 to 2T-7 and Figures 2O-8 to 2T-8 The processes shown and described above are used to form semiconductor structure 100.

[0132] Figure 5A and Figure 5B A cross-sectional view of an intermediate stage in the fabrication of a semiconductor structure 100 according to some other embodiments is shown. More specifically, it can be implemented... Figure 1A , Figure 1B , Figures 2A-1 to 2P-1 , Figures 2A-2 to 2P-2 , Figures 2A-3 to 2P-3 , Figures 2A-4 to 2P-4 , Figures 2A-5 to 2P-5 , Figures 2A-6 to 2P-6 , Figures 2J-7 to 2P-7 and Figures 2J-8 to 2P-8 The processes shown and described above are used to form isolation components 176-1 and 176-2, and a trimming process 184b is performed to form isolation components 176-1'b and 176-2'b. According to some embodiments, trimming process 184b may be the same as or similar to the previously described trimming process 184, except that the bottom edge of the sidewall of the top portion 176'Tb of isolation components 176-1'b and 176-2'b is substantially flush with the top surfaces of fin structures 104-1, 104-2, 104-3, and 104-4. After performing trimming process 184b, the following can be performed: Figures 2R-1 to 2T-1 , Figures 2R-2 to 2T-2 , Figures 2R-3 to 2T-3 , Figures 2R-4 to 2T-4 , Figures 2R-5 to 2T-5 , Figures 2R-6 to 2T-6 , Figures 2R-7 to 2T-7 and Figures 2R-8 to 2T-8 The processes shown and described above are used to form semiconductor structure 100.

[0133] Figure 6A-1 , Figure 6A-2 , Figure 6B-1 and Figure 6B-2 A cross-sectional view of an intermediate stage in the fabrication of a semiconductor structure 100c according to some embodiments is shown. According to some embodiments, the semiconductor structure 100c may be similar to the previously described semiconductor structure 100, except that its insulating components have a greater thickness. Other processes and materials used to form the semiconductor structure 100c may be similar to or the same as those previously described for forming the semiconductor structure 100, and will not be repeated here.

[0134] More specifically, according to some embodiments, implementation Figure 1A , Figure 1B , Figures 2A-1 to 2L-1 , Figures 2A-2 to 2L-2 , Figures 2A-3 to 2L-3 , Figures 2A-4 to 2L-4 , Figures 2A-5 to 2L-5 , Figures 2A-6 to 2L-6 , Figures 2J-7 to 2L-7 and Figures 2J-8 to 2L-8 The process shown is to form a mask structure 160 with an opening 162, and to perform an etching process 172c to form trenches 170-1c and 170-2c in the dummy gate electrode 124, and then remove the mask structure 160, as... Figure 6A-1 and Figure 6A-2 As shown in the illustration. According to some embodiments, Figure 6A-1 and Figure 6A-2 The trenches 170-1c and 170-2c shown are similar to Figure 2M-1 and Figure 2M-2 The trenches 170-1 and 170-2 shown extend through the dielectric layer 122 and the capping layer 120, except that trenches 170-1c and 170-2c extend further into the isolation structure 116, according to some embodiments. That is, according to some embodiments, the bottom surface of trenches 170-1c and 170-2c is lower than the top surface of the isolation structure 116.

[0135] Subsequently, according to some embodiments, implementation Figures 2N-1 to 2T-1 , Figures 2N-2 to 2T-2 , Figures 2N-3 to 2T-3 , Figures 2N-4 to 2T-4 , Figures 2N-5 to 2T-5 , Figures 2N-6 to 2T-6 , Figures 2N-7 to 2T-7 and Figures 2N-8 to 2T-8 The processes shown and described above are used to form the semiconductor structure 100c, as... Figure 6B-1 and Figure 6B-2 As shown in the image.

[0136] More specifically, according to some embodiments, the semiconductor structure 100c includes isolation members 176-1”c and 176-2”c formed in trenches 170-1c and 170-2c, such that the bottom portions of the isolation members 176-1”c and 176-2”c extend through the dielectric layer 122 and the capping layer 120 and into the isolation structure 116. In some embodiments, the bottom surface of the isolation members 176-1”c and 176-2”c is lower than the top surface of the isolation structure 116. In some embodiments, the bottom surface of the isolation members 176-1”c and 176-2”c is lower than the top surface of the substrate structure 104B. In some embodiments, the bottom surface of the isolation members 176-1”c and 176-2”c is lower than the bottom surface of the gate structure 190.

[0137] Furthermore, according to some embodiments, isolation components 176-1”c and 176-2”c include shells 178-1”c and 178-2”c, and the bottom surface of shells 178-1”c and 178-2”c is lower than the top surface of isolation structure 116. In some embodiments, the interface between isolation structure 116 and the shells 178-1”c and 178-2”c of isolation components 176-1”c and 176-2”c is lower than the bottom surface of gate structure 190.

[0138] Figure 7 A cross-sectional view of a semiconductor structure 100d according to some embodiments is shown. According to some embodiments, the semiconductor structure 100d may be similar to the previously described semiconductor structure 100, except that channel layers 108-1' and 108-4' are formed on opposite sides of the isolation member 176-1"d. The processes and materials used to form the semiconductor structure 100d may be similar to or the same as those previously described for forming the semiconductor structure 100, and will not be repeated here.

[0139] More specifically, according to some embodiments, a channel layer 108-1' with a larger width and a channel layer 108-4' with a smaller width are formed adjacent to each other, and gate structures 190-1 and 190-4 are formed around the channel layers 108-1' and 108-4', respectively. Then, according to some embodiments, an isolation member 176-1"d is formed between the gate structures 190-1 and 190-4 to electrically isolate the gate structures 190-1 and 190-4. In some embodiments, in the Y direction, the width of channel layer 108-1'T is greater than the width of channel layer 108-4'T. In some embodiments, in the Y direction, the width of channel layer 108-1'M is greater than the width of channel layer 108-4'M. In some embodiments, in the Y direction, the width of channel layer 108-1'B is greater than the width of channel layer 108-4'B.

[0140] As previously described, according to some embodiments, when the channel layer 108-1' has a relatively larger width, the extension portion 123 will be formed between the channel layer 108-1' and the sidewall of the isolation structure 176-1”c facing the channel layer 108-1'. In some embodiments, the isolation member 176-1”d includes a core material 180-1”d and a shell layer 178-1”d, and the shell layer 178-1”d is located below the bottom surface of the core material 180-1”d and on the sidewall of the lower portion of the core material 180-1”d facing the channel layer 108-1'.

[0141] On the other hand, according to some embodiments, when the channel layer 108-4' has a relatively smaller width, the extension 123 will not be formed between the channel layer 108-4' and the sidewalls of the isolation structure 176-1”c facing the channel layer 108-4'. Therefore, according to some embodiments, the four sidewalls of each of the channel layers 108-4' are enclosed by the gate structure 190-4. Furthermore, the shell layer 178-1”d does not extend to the sidewalls of the core material 180-1”d facing the channel layer 108-4'.

[0142] Figure 8 A cross-sectional view of a semiconductor structure 100e according to some embodiments is shown. According to some embodiments, the semiconductor structure 100e may be similar to the previously described semiconductor structure 100d, except that its isolation component 176-1”e extends into the isolation structure 116 (similar to the isolation components 176-1”c and 176-2”c of semiconductor structure 100c). The processes and materials used to form the semiconductor structure 100e may be similar to or the same as those previously described for forming semiconductor structures 100c and 100d, and will not be repeated here.

[0143] More specifically, according to some embodiments, the semiconductor structure 100e includes a channel layer 108-1' with a larger width and a channel layer 108-4' with a smaller width, gate structures 190-1 and 190-4, and an isolation component 176-1”e between the gate structures 190-1 and 190-4.

[0144] In some embodiments, the isolation member 176-1”e includes a core material 180-1”e and a shell layer 178-1”e, wherein the shell layer 178-1”e is located below the bottom surface of the core material 180-1”e and on the sidewall of the lower portion of the core material 180-1”e facing the channel layer 108-1’, but not on the sidewall of the core material 180-1”e facing the channel layer 108-4’. Furthermore, according to some embodiments, the bottom surface of the shell layer 178-1”e is lower than the top surface of the isolation structure 116 and the bottom surfaces of the gate structures 190-1 and 190-4.

[0145] Figure 9 A cross-sectional view of a semiconductor structure 100f according to some embodiments is shown. According to some embodiments, the semiconductor structure 100f may be similar to the previously described semiconductor structure 100, except that its isolation member 176-1”f has a sloping sidewall at its bottom portion. The processes and materials used to form the semiconductor structure 100f may be similar to or the same as those previously described for forming the semiconductor structure 100, and will not be repeated here.

[0146] More specifically, according to some embodiments, the insulating member 176-2”f includes a shell 178-2”f and a core material 180-2”f formed above the shell 178-2”f, and the bottom portion of the core material 180-2”f has sloping sidewalls. In some embodiments, the width of the bottom portion of the core material 180-2”f gradually decreases from its top portion to its bottom. Figure 9 As shown, according to some embodiments, the core material 180-2”f has a top width at its top surface, a bottom width at its bottom surface, and an intermediate width between the top and bottom surfaces, wherein the top width is smaller than the bottom width and the bottom width is smaller than the intermediate width. In some embodiments, gate structures 190-3 and 190-4 cover the sloping sidewalls of the isolation member 176-2”f.

[0147] Figure 10 A cross-sectional view of a semiconductor structure 100g according to some embodiments is shown. According to some embodiments, the semiconductor structure 100g may be similar to the previously described semiconductor structure 100f, except that its isolation component 176-2”g extends into the isolation structure 116 (similar to isolation components 176-1”c and 176-2”c of semiconductor structure 100c). The processes and materials used to form the semiconductor structure 100g may be similar to or the same as those previously described for forming semiconductor structures 100c and 100f, and will not be repeated here.

[0148] More specifically, according to some embodiments, the insulating member 176-2”g includes a shell 178-2”g and a core material 180-2”g formed above the shell 178-2”g, and the bottom portion of the core material 180-2”g has sloping sidewalls extending into the insulating structure 116. In some embodiments, the width of the bottom portion of the core material 180-2”g gradually decreases from its top portion to its bottom portion. Figure 10 As shown, according to some embodiments, gate structures 190-3 and 190-4 cover the upper portion of the inclined sidewall of the isolation member 176-2”g, and shell 178-2”g covers the lower portion of the inclined sidewall of the isolation member 176-2”g. Furthermore, according to some embodiments, shell 178-2”g extends into the isolation structure 116.

[0149] Typically, channel layers 108-1' to 108-4' (e.g., nanostructures) are formed by forming a semiconductor stack comprising alternating stacked first semiconductor material layers 106 and second semiconductor material layers 108. The first semiconductor material layer 106 serves as a sacrificial layer during the manufacturing process, and the second semiconductor material layer 108 serves as a channel layer in the resulting transistor. However, during the manufacturing process, such as thermal processes, Ge in the first semiconductor material layer 106 may diffuse into the second semiconductor material layer 108, which can potentially degrade the performance of the resulting device. Therefore, in the embodiment described above, the first semiconductor material layer 106 is replaced with a dielectric sacrificial member 144 before forming the source / drain structure 152, thereby reducing or avoiding the problem of Ge diffusion.

[0150] Furthermore, according to some embodiments, isolation members (e.g., isolation members 176-1”, 176-2”, 176-1”c, 176-2”c, 176-1”d, 176-1”e, 176-2”f, and 176-2”g) are formed to separate the gate structures 190. Because the isolation members have a smaller top width, the gate structures formed adjacent to the isolation members (e.g., gate structure 190) can have a larger top surface. Therefore, more spacing will exist above the gate structures for forming contacts (e.g., contact 204).

[0151] Furthermore, according to some embodiments, extensions (e.g., extension 123) are formed at certain locations in the isolation member. Due to the reduction in the metal gate cap, the extensions connecting the channel layer and the isolation member can contribute to a reduction in Cgd.

[0152] It should be understood that the elements shown in semiconductor structures 100, 100c, 100d, 100e, 100f, and 100g can be combined and / or interchanged. Furthermore, it should be noted that... Figures 1A to 10 The same components can be represented by the same reference numerals, can include the same or similar materials, and can be formed by the same or similar processes; therefore, for the sake of brevity, such redundant details have been omitted. Furthermore, although... Figures 1A to 10 It is described in relation to this method, but it should be understood that... Figures 1A to 10 The structures disclosed are not limited to methods, but can exist independently of methods. Similarly, Figures 1A to 10 The methods shown are not limited to the disclosed structures, but can exist independently of the structures. Furthermore, according to some embodiments, the channel layers (e.g., nanostructures) described above may include nanowires, nanosheets, or other suitable nanostructures.

[0153] Furthermore, while the disclosed methods are shown and described above as a series of steps or events, it should be understood that in some other embodiments, the order in which such steps or events are shown may be changed. For example, some steps may occur in a different order and / or simultaneously with other steps or events besides those shown and / or described above. Moreover, not all steps shown may be necessary to implement one or more aspects or embodiments described above. Furthermore, one or more of the steps depicted above may be performed as one or more separate steps and / or stages.

[0154] Furthermore, the terms “approximately,” “basically,” “essentially,” and “about” used above take into account minor variations and can vary across different technologies, and within the range of deviations understood by those skilled in the art. For example, when used in conjunction with an event or situation, the terms can refer to instances where the event or situation occurred precisely or instances where the event or situation was very close to occurring.

[0155] Embodiments for forming semiconductor structures can be provided. The semiconductor structure may include a first channel layer, a second channel layer, a first gate structure enclosing the first channel layer, a second gate structure enclosing the second channel layer, and an isolation member sandwiched between the first gate structure and the second gate structure. Furthermore, the isolation member has a narrower top surface and a wider bottom surface, such that the first gate structure and the second gate structure formed adjacent to the isolation member can have a larger top surface for forming contacts thereon.

[0156] A semiconductor structure and a method of forming the same are provided. The semiconductor structure includes a substrate and a first channel layer and a second channel layer extending along a first direction. The first and second channel layers are located above the substrate. The semiconductor structure also includes an isolation structure above the substrate, and the isolation structure is located between the first and second channel layers in a top view. The semiconductor structure also includes a first gate structure extending along a second direction above the first channel layer and the isolation structure, and the second direction is different from the first direction. The semiconductor structure also includes a second gate structure extending along the second direction above the second channel layer and the isolation structure, and an isolation member laterally sandwiched between the first and second gate structures and extending above the isolation structure. Furthermore, the isolation member has a top width and a bottom width greater than the top width, and the interface between the isolation member and the first gate structure includes a curved profile.

[0157] A semiconductor structure and a method of forming the same are provided. The semiconductor structure includes a substrate and a first transistor located above the substrate. The first transistor includes a first substrate structure, a first channel layer extending longitudinally in a first direction above the first substrate structure, and a first gate structure enclosing the first channel layer and extending longitudinally in a second direction. Furthermore, the second direction is different from the first direction. The semiconductor structure also includes a second transistor located above the substrate. The second transistor includes a second substrate structure, a second channel layer extending longitudinally in the first direction above the second substrate structure, and a second gate structure enclosing the second channel layer and extending longitudinally in the second direction. The semiconductor structure also includes an isolation structure located above the substrate and between the first substrate structure and the second substrate structure. Furthermore, the isolation structure is in contact with the sidewalls of the first substrate structure and the sidewalls of the second substrate structure. The semiconductor structure also includes a first isolation member sandwiched between the first gate structure and the second gate structure to electrically isolate the first gate structure and the second gate structure. Furthermore, the distance in the second direction between the topmost element in the first channel layer and the first sidewall of the first isolation member is greater than the distance in the second direction between the bottommost element in the first channel layer and the first sidewall of the first isolation member.

[0158] A semiconductor structure and a method for forming the same are provided. The method includes: alternately stacking a channel layer and a semiconductor sacrificial layer to form a semiconductor stack over a substrate; and patterning the semiconductor stack to form a first fin structure and a second fin structure. The method further includes: forming a dummy gate electrode across the first fin structure and the second fin structure; and replacing the semiconductor sacrificial layer with a dielectric sacrificial layer. The method further includes: forming a first trench having a first width in the dummy gate electrode between the first fin structure and the second fin structure; and expanding a top portion of the first trench to a second width greater than the first width. The method further includes: forming an isolation material in the first trench; and removing the dummy gate electrode. The method further includes: partially removing the isolation material to form an isolation member, and the top surface of the isolation member having a third width less than the first width. The method further includes: removing the dielectric sacrificial layer; forming a first gate structure at a first side of the isolation member; and forming a second gate structure at a second side of the isolation member.

[0159] Some embodiments of this application provide a semiconductor structure including: a substrate; a first channel layer and a second channel layer extending along a first direction, wherein the first channel layer and the second channel layer are located above the substrate; an isolation structure located above the substrate, wherein the isolation structure is located between the first channel layer and the second channel layer in a top view; a first gate structure extending above the first channel layer and the isolation structure along a second direction, wherein the second direction is different from the first direction; a second gate structure extending above the second channel layer and the isolation structure along the second direction; and an isolation member laterally sandwiched between the first gate structure and the second gate structure and extending above the isolation structure, wherein the isolation member has a top width and a bottom width greater than the top width, and the interface between the isolation member and the first gate structure includes a curved profile.

[0160] In some embodiments, the semiconductor structure further includes: a first extension that laterally protrudes from the isolation member and is attached to the first channel layer. In some embodiments, the first extension has a curved top surface. In some embodiments, the isolation member further includes: a core material; and a shell layer located around a bottom portion of the core material, wherein the top surface of the shell layer is higher than the top surface of the first extension. In some embodiments, the semiconductor structure further includes: a second extension that laterally protrudes from the isolation member and is attached to the second channel layer. In some embodiments, the semiconductor structure further includes: a third channel layer located above the first channel layer; a fourth channel layer located above the third channel layer; and a third extension that laterally protrudes from the isolation member and is attached to the third channel layer, wherein the fourth channel layer is separated from the isolation member by the first gate structure. In some embodiments, the bottom surface of the isolation member is lower than the bottommost surface of the first gate structure.

[0161] Other embodiments of this application provide a semiconductor structure including: a substrate; a first transistor located above the substrate, including: a first substrate structure; a first channel layer extending longitudinally in a first direction above the first substrate structure; and a first gate structure enclosing the first channel layer and extending longitudinally in a second direction, wherein the second direction is different from the first direction; a second transistor located above the substrate, including: a second substrate structure; a second channel layer extending longitudinally in the first direction above the second substrate structure; and a second gate structure enclosing the second channel layer and extending longitudinally in the second direction; an isolation structure located above the substrate and between the first substrate structure and the second substrate structure, wherein the isolation structure is in contact with the sidewalls of the first substrate structure and the sidewalls of the second substrate structure; and a first isolation member sandwiched between the first gate structure and the second gate structure to electrically isolate the first gate structure and the second gate structure, wherein the distance in the second direction between the topmost one of the first channel layer and the first sidewall of the first isolation member is greater than the distance in the second direction between the bottommost one of the first channel layer and the first sidewall of the first isolation member.

[0162] In some embodiments, the semiconductor structure further includes: a first extension portion laterally connected to the bottommost one of the first channel layers. In some embodiments, the dimension of the first extension portion is smaller than the dimension of the bottommost one of the first channel layers in a third direction substantially perpendicular to the first direction and the second direction. In some embodiments, in the second direction, the dimension of the bottommost one of the first channel layers is larger than the dimension of the topmost one of the first channel layers. In some embodiments, in the second direction, the dimension of the bottommost one of the first channel layers is larger than the dimension of the bottommost one of the second channel layers. In some embodiments, the first isolation member includes: a shell layer covering a bottom portion of the bottom surface and sidewalls of the first isolation member, wherein the first extension portion is attached to a first portion of the shell layer, and the first gate structure is attached to a second portion of the shell layer. In some embodiments, the first portion of the shell layer is thicker than the second portion of the shell layer. In some embodiments, the dimension of the topmost one of the first channel layers is smaller than the dimension of the bottommost one of the first channel layers.

[0163] Further embodiments of this application provide a method for manufacturing a semiconductor structure, comprising: alternately stacking a channel layer and a semiconductor sacrificial layer to form a semiconductor stack over a substrate; patterning the semiconductor stack to form a first fin structure and a second fin structure; forming a dummy gate electrode across the first fin structure and the second fin structure; replacing the semiconductor sacrificial layer with a dielectric sacrificial member; forming a first trench having a first width in the dummy gate electrode between the first fin structure and the second fin structure; expanding the top portion of the first trench to a second width greater than the first width; forming an isolation material in the first trench; removing the dummy gate electrode; partially removing the isolation material to form an isolation member, wherein the top surface of the isolation member has a third width less than the first width; removing the dielectric sacrificial member; and forming a first gate structure at a first side of the isolation member and forming a second gate structure at a second side of the isolation member.

[0164] In some embodiments, the method of manufacturing the semiconductor structure further includes: forming a dielectric layer over the first fin structure and the second fin structure before forming the dummy gate electrode; and partially removing the dielectric layer to form an extension on the sidewall of the isolation member, wherein the extension protrudes laterally toward the sidewall of the channel layer. In some embodiments, the isolation material includes a shell layer and a core material located above the shell layer, and the shell layer is laterally sandwiched between the extension and the core material. In some embodiments, the method of manufacturing the semiconductor structure further includes: forming an isolation structure around the first fin structure and the second fin structure, wherein the first trench extends into the isolation structure. In some embodiments, the interface between the isolation member and the isolation structure is lower than the bottom surface of the first gate structure.

[0165] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of the embodiments of this disclosure. Those skilled in the art should understand that they can readily use the embodiments of this disclosure as a base to design or modify other processes and structures for performing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the embodiments of this disclosure, and that various changes, substitutions, and modifications can be made to them herein without departing from the spirit and scope of the embodiments of this disclosure.

Claims

1. A semiconductor structure, comprising: a substrate; a first channel layer and a second channel layer extending along a first direction, wherein the first channel layer and the second channel layer are located above the substrate; an isolation structure located above the substrate, wherein the isolation structure is located between the first channel layer and the second channel layer in a top view; a first gate structure extending along a second direction above the first channel layer and the isolation structure, wherein the second direction is different from the first direction; a second gate structure extending along the second direction above the second channel layer and the isolation structure; and an isolation component laterally sandwiched between the first gate structure and the second gate structure and extending above the isolation structure, wherein the isolation component has a top width and a bottom width greater than the top width, and an interface between the isolation component and the first gate structure comprises a curved profile.

2. The semiconductor structure of claim 1, further comprising: a first extension portion protruding laterally from the isolation component and attached to the first channel layer.

3. The semiconductor structure of claim 2, wherein, the first extension portion has a curved top surface.

4. The semiconductor structure of claim 2, wherein, the isolation component further comprises: a core material; and a shell layer located around a bottom portion of the core material, wherein a top surface of the shell layer is higher than a top surface of the first extension portion.

5. The semiconductor structure of claim 2, wherein, further comprising: a second extension portion protruding laterally from the isolation component and attached to the second channel layer.

6. The semiconductor structure of claim 2, further comprising: a third channel layer located above the first channel layer; a fourth channel layer located above the third channel layer; and a third extension portion protruding laterally from the isolation component and attached to the third channel layer, wherein the fourth channel layer is separated from the isolation component by the first gate structure. a bottom surface of the isolation component is lower than a bottommost surface of the first gate structure.

7. The semiconductor structure of claim 1, wherein, 8. A semiconductor structure, comprising: a substrate; a first transistor located above the substrate, comprising: a first base structure; a first channel layer extending longitudinally above the first base structure along a first direction; and a first gate structure wrapping around the first channel layer and extending longitudinally along a second direction, wherein the second direction is different from the first direction; a second transistor located above the substrate, comprising: a second base structure; a second channel layer extending longitudinally above the second base structure along the first direction; and a second gate structure wrapping around the second channel layer and extending longitudinally along the second direction; an isolation structure located above the substrate and between the first base structure and the second base structure, wherein the isolation structure interfaces with sidewalls of the first base structure and the second base structure; and a first isolation component sandwiched between the first gate structure and the second gate structure to electrically isolate the first gate structure and the second gate structure, ​ A distance between a topmost one of the first channel layers and a first sidewall of the first isolation component in the second direction is greater than a distance between a bottommost one of the first channel layers and the first sidewall of the first isolation component in the second direction.

9. The semiconductor structure of claim 8, wherein, Also included are: a first extension portion laterally connected to the bottommost one of the first channel layers.

10. A method for fabricating a semiconductor structure, comprising: alternately stacking channel layers and semiconductor sacrificial layers to form a semiconductor stack over a substrate; patterning the semiconductor stack to form first and second fin structures; forming a dummy gate electrode across the first and second fin structures; replacing the semiconductor sacrificial layers with dielectric sacrificial components; forming a first trench in the dummy gate electrode between the first and second fin structures having a first width; enlarging a top portion of the first trench to a second width greater than the first width; forming an isolation material in the first trench; removing the dummy gate electrode; partially removing the isolation material to form an isolation component, wherein a top surface of the isolation component has a third width less than the first width; removing the dielectric sacrificial components; and forming a first gate structure at a first side of the isolation component and a second gate structure at a second side of the isolation component.

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