Silicon SPAD detector of integrated waveguide and manufacturing method thereof
By integrating waveguides onto silicon SPAD detectors and employing guard and cutoff rings, the problems of coupling loss and increased noise between silicon SPADs and photonic integrated chips are solved, achieving efficient optical coupling and low-noise photonic detection.
Patent Information
- Application Number
- CN202511729947.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-24
- Publication Date
- 2026-02-17
AI Technical Summary
The coupling between existing silicon SPADs and photonic integrated chips suffers from significant losses, and directly fabricating waveguide-type silicon SPADs on photonic integrated chips leads to increased noise.
Waveguides are integrated on silicon SPAD detectors, coupling loss is reduced by optical fiber connection, and noise is suppressed by guard rings and cutoff rings. High-efficiency optical coupling is achieved by monolithic integration.
It reduces coupling loss, improves photon detection efficiency, reduces noise, enhances detector response and signal-to-noise ratio, and improves device mechanical stability and long-term operating life.
Smart Images
Figure CN121548121A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of photodetector chips and relates to a silicon SPAD detector with integrated waveguide and its manufacturing method. Background Technology
[0002] Silicon SPAD (single-photon avalanche diode) is a special type of photodiode that operates in Geiger mode and has approximately 10 6 With an internal gain on the order of magnitude, single-photon detection can be achieved. Most existing silicon SPADs are discrete devices, while photonic integrated chips represent the future direction of optical computing, optical sensing, and other fields. The interconnection or integration of silicon SPADs and photonic integrated chips is crucial.
[0003] Currently, ordinary silicon SPADs can be coupled to the exit waveguide end face of photonic integrated chips via optical fibers. However, there is significant coupling loss between the optical fiber and the waveguide, which reduces the photon detection efficiency of the SPAD. On the other hand, fabricating waveguide-type silicon SPADs directly on photonic integrated chips presents the problem that etching the silicon waveguide will generate more dangling bond defects on the surface of the waveguide SPAD, leading to increased noise such as dark counting. Summary of the Invention
[0004] In view of this, the purpose of the present invention is to provide a silicon SPAD detector with integrated waveguide and a method for manufacturing the same. By integrating the silicon SPAD detector with the waveguide, the coupling loss caused by connecting the photonic integrated chip and the silicon SPAD through optical fiber is reduced, thereby improving the detection efficiency.
[0005] To achieve the above objectives, the present invention provides a silicon SPAD detector with an integrated waveguide, which, from bottom to top, includes a second dielectric layer, a lower electrode, a first dielectric layer, an n+ contact region, an avalanche region, a p- absorption region, a p+ contact region, a third dielectric layer, and a fourth dielectric layer, as well as an upper electrode and a waveguide located above the fourth dielectric layer.
[0006] The lower electrode is connected to the n+ contact area through the contact hole of the first dielectric layer; A step is provided at one end of the p+ contact region, and the third dielectric layer is located on the step and sandwiched between the p+ contact region and the fourth dielectric layer. The waveguide is positioned above the fourth dielectric layer and extends to the region corresponding to the third dielectric layer. The refractive index of the waveguide is greater than that of the third and fourth dielectric layers. The upper electrode is connected to the p+ contact area through the contact hole of the fourth dielectric layer.
[0007] Furthermore, the device also includes a guard ring located above the first dielectric layer and surrounding the n+ contact region and the avalanche region.
[0008] Furthermore, the device also includes a stop ring located above the first dielectric layer and distributed outside the guard ring.
[0009] Furthermore, the device is provided with a through hole that passes through the fourth dielectric layer, the p+ contact region, the p- absorption region and the first dielectric layer, exposing the surface of the lower electrode.
[0010] Furthermore, the device also includes a support carrier sheet disposed below the second dielectric layer.
[0011] Furthermore, the thickness of the fourth dielectric layer is 10 nm to 50 nm.
[0012] On the other hand, the present invention provides a method for manufacturing a silicon SPAD detector with integrated waveguide, comprising: Prepare a clean p-type epitaxial silicon wafer, and grow a silicon oxide dielectric layer on the surface of the epitaxial layer of the epitaxial silicon wafer; A cutoff ring pattern is formed by photolithography and etching of the silicon oxide dielectric layer, and then the cutoff ring is formed by ion implantation; a guard ring pattern is formed by photolithography and etching of the silicon oxide dielectric layer, and then the guard ring is formed by ion implantation; wherein, the cutoff ring is located on the outside of the guard ring; Avalanche region patterns are formed by photolithography and etching of the silicon oxide dielectric layer, boron is injected, and the boron diffuses into the epitaxial layer through a high-temperature process; then phosphorus is injected, and the phosphorus diffuses into the epitaxial layer through a high-temperature process, thus complementing the boron to form avalanche regions. The n+ contact region pattern is formed by photolithography and etching of the silicon oxide dielectric layer, and the n+ contact region is formed by ion implantation. A first dielectric layer is deposited on the front side, and contact holes are etched in the first dielectric layer; aluminum is deposited, and a lower electrode is formed by photolithography and etching, and the lower electrode contacts the n+ contact area through the contact holes; A second dielectric layer is deposited on the front side; The epitaxial silicon wafer is flipped over, and the substrate on the back side of the epitaxial silicon wafer is removed by mechanical grinding and self-stopping etching. Then, the transition region between the substrate and the epitaxial layer is removed by wet etching. A groove is formed by etching the epitaxial layer; a p+ contact region is formed on the back side of the epitaxial layer by ion implantation. A third dielectric layer is deposited in the groove, and the height of the third dielectric layer is flush with the surface of the p+ contact region. A fourth dielectric layer is deposited to cover the p+ contact region and the third dielectric layer, and contact holes are etched out; a waveguide is formed on the surface of the fourth dielectric layer, and the waveguide extends on the surface of the fourth dielectric layer to the corresponding region of the third dielectric layer; wherein, the refractive index of the waveguide should be greater than the refractive index of the third dielectric layer and the fourth dielectric layer; Metallic aluminum is deposited on the surface of the fourth dielectric layer to form the upper electrode. The upper electrode does not contact the waveguide, but it contacts the p+ contact region through the contact hole of the fourth dielectric layer.
[0013] Furthermore, the method also includes etching through holes in the device that extend to the surface of the lower electrode, exposing the lower electrode.
[0014] Furthermore, the thickness of the fourth dielectric layer is 10 nm to 50 nm.
[0015] The beneficial effects of this invention are as follows: (1) This invention achieves efficient optical coupling with photonic integrated chips by directly integrating the waveguide onto the silicon SPAD detector. This invention adopts a monolithic integration method, which eliminates the need for optical fiber connection. Through the direct optical path formed by the waveguide and the detector, the transmission loss can be greatly reduced and the utilization efficiency of optical signals can be improved, providing a more reliable photonic interface for applications such as optical computing and optical sensing.
[0016] (2) In this invention, the refractive index of the waveguide is set to be greater than that of the third and fourth dielectric layers. This allows the incident light to be confined within the waveguide in the region covering the third dielectric layer during transmission, while it leaks into the absorption region of the silicon SPAD in the region covering only the fourth dielectric layer. This photon guidance and leakage method ensures that photons are fully captured and absorbed, reducing scattering and loss of photons during transmission, thereby enhancing the overall response capability and photon detection efficiency of the detector.
[0017] (3) By introducing a guard ring and a stop ring, this invention suppresses edge breakdown and leakage current, and reduces noise sources such as dark count rate. At the same time, the surface passivation layer and doping process reduce dangling bond defects generated during etching, which greatly reduces defect-induced noise. In addition, the mechanical stability of the device is enhanced by supporting the carrier sheet, thereby improving the detection signal-to-noise ratio and long-term operating life of the device.
[0018] Other advantages, objectives, and features of the invention will be set forth in part in the description which follows, and in part will be apparent to those skilled in the art from the following examination, or may be learned from practice of the invention. The objectives and other advantages of the invention can be realized and obtained through the following description. Attached Figure Description
[0019] To make the objectives, technical solutions, and advantages of the present invention clearer, the preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings, wherein: Figure 1 This is a schematic diagram of a silicon SPAD detector structure with integrated waveguide provided in an embodiment of the present invention; Figure 2 for Figure 1 Top view of the device shown; Figure 3 A flowchart illustrating a method for manufacturing a silicon SPAD detector with integrated waveguides according to an embodiment of the present invention; Figure 4 This is a simulated cross-sectional view of the propagation and absorption of incident light in a silicon SPAD detector with integrated waveguide. Figure 5 This is an enlarged schematic diagram of the waveguide segment corresponding to the third dielectric layer. Detailed Implementation
[0020] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Unless otherwise specified, the following embodiments and features can be combined with each other.
[0021] The accompanying drawings are for illustrative purposes only and are schematic diagrams, not actual pictures. They should not be construed as limiting the invention. To better illustrate the embodiments of the invention, some parts in the drawings may be omitted, enlarged, or reduced, and do not represent the actual product dimensions. It is understandable to those skilled in the art that some well-known structures and their descriptions may be omitted in the drawings.
[0022] In the accompanying drawings of the embodiments of the present invention, the same or similar reference numerals correspond to the same or similar components. In the description of the present invention, it should be understood that if terms such as "upper," "lower," "left," "right," "front," and "rear" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, they are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, the terms used to describe positional relationships in the drawings are only for illustrative purposes and should not be construed as limiting the present invention. For those skilled in the art, the specific meaning of the above terms can be understood according to the specific circumstances.
[0023] To address the issues of coupling loss in silicon SPADs coupled to the exit waveguide end face of photonic integrated chips via optical fibers, which reduces the photonic detection efficiency of SPADs, and the increased noise associated with directly fabricating waveguide-type silicon SPADs on photonic integrated chips, this invention provides a silicon SPAD detector with integrated waveguides. By integrating waveguides onto the silicon SPAD detector, the coupling loss generated by connecting the photonic integrated chip and the silicon SPAD via optical fibers can be reduced, and the detection efficiency can be improved.
[0024] like Figure 1 As shown, this is a silicon SPAD detector with integrated waveguide provided in an embodiment of the present invention. The detector includes a waveguide, a p+ contact region, a p- absorption region, an avalanche region, an n+ contact region, a guard ring, a cutoff ring, an upper electrode, a lower electrode, a first dielectric layer, a second dielectric layer, a third dielectric layer, a fourth dielectric layer, and a support carrier sheet.
[0025] The second dielectric layer is disposed above the support carrier sheet, the first dielectric layer is located above the second dielectric layer, and the n+ contact area is disposed above the first dielectric layer. A lower electrode is disposed between the first dielectric layer and the second dielectric layer, and the lower electrode has two protrusions that pass through the first dielectric layer and connect to the n+ contact area.
[0026] The avalanche zone is positioned above the n+ contact zone.
[0027] The protective ring is positioned above the first dielectric layer and surrounds the n+ contact area and the avalanche zone.
[0028] The stop ring is positioned above the first dielectric layer and outside the guard ring, and the guard ring is spaced a certain distance apart from the stop ring.
[0029] The p-absorbing region is located above the first dielectric layer and covers the cutoff ring, guard ring, n+ contact region, and avalanche region.
[0030] The p+ contact area is located above the p- absorption area, and a step is provided on the right side of the p+ contactor, on which the third dielectric layer is located.
[0031] The fourth dielectric layer is disposed above the p+ contact area and covers the third dielectric layer.
[0032] The upper electrode is disposed above the fourth dielectric layer, and the upper electrode has a protrusion structure that passes through the fourth dielectric layer and is connected to the p+ contact area.
[0033] The waveguide is positioned above the fourth dielectric layer and extends above the fourth dielectric layer to the region corresponding to the third dielectric layer.
[0034] The refractive index of the waveguide should be greater than that of the third and fourth dielectric layers.
[0035] like Figure 2 As shown, when incident light propagates in the waveguide segments located on the third and fourth dielectric layers, it is confined within the waveguide. However, when incident light propagates in the waveguide segment located only on the fourth dielectric layer, due to the thinness of the fourth dielectric layer, the incident light leaks into the silicon material beneath the fourth dielectric layer and is thus detected by the SPAD.
[0036] like Figure 3As shown, another embodiment of the present invention provides a method for manufacturing a silicon SPAD detector with integrated waveguides, the method comprising: (1) Prepare a clean p-type epitaxial silicon wafer, including a p-epitaxial layer and a p+ substrate. The substrate resistivity is 0.01~0.05 Ω·cm, and the epitaxial layer resistivity is 250~300 Ω·cm. The epitaxial layer serves as the p-absorption region.
[0037] (2) A silicon oxide dielectric layer is grown on the surface of the epitaxial layer.
[0038] (3) A stop ring pattern is formed by photolithography and etching of the dielectric layer, and a stop ring is formed by implantation of a large dose of boron.
[0039] The volume concentration range of the cutoff ring is 1E18 cm⁻¹. -3 ~1E20 cm -3 .
[0040] (4) A protective ring pattern is formed by photolithography and etching of the dielectric layer, and a protective ring is formed by injecting an appropriate amount of phosphorus.
[0041] The volume concentration range of the protective ring is 5E15 cm⁻¹. -3 ~5E17 cm -3 .
[0042] The stop ring is located outside the protection ring.
[0043] (5) Avalanche pattern is formed by photolithography and etching of the dielectric layer, an appropriate amount of boron is injected, and then the boron is diffused into the epitaxial layer through a high-temperature process.
[0044] The injection dose range for P-type impurities in the avalanche zone is 4E12~1E13 cm⁻¹. -2 .
[0045] The diffusion temperature range for P-type impurities in the avalanche zone is 1100~1200℃, and the diffusion time is 2~10 hours.
[0046] (6) Inject an appropriate amount of phosphorus element, and then use a high temperature process to diffuse the phosphorus element into the epitaxial layer, thereby forming an avalanche region by complementary doping with boron element.
[0047] The injection dose of N-type impurities in the avalanche zone ranges from 2E12 to 8E12 cm⁻¹ -2 .
[0048] The diffusion temperature range for N-type impurities in the avalanche zone is 1100~1200℃, and the diffusion time is 1~20 hours.
[0049] (7) The n+ contact area pattern is formed by photolithography and etching of the dielectric layer, and the n+ contact area is formed by large dose of phosphorus element implantation.
[0050] The volume concentration range of the n+ contact region is 1E18 cm⁻¹. -3 ~1E20 cm -3 .
[0051] (8) A first dielectric layer is deposited on the front side to passivate the surface.
[0052] The dielectric layer material is preferably silicon oxide.
[0053] (9) Etch contact holes in the first dielectric layer.
[0054] (10) Metallic aluminum is deposited on the front side and the lower electrode is formed by photolithography and etching.
[0055] In this process, the deposited metallic aluminum comes into contact with the n+ contact area through contact holes.
[0056] (11) A second dielectric layer is deposited on the front side to protect and support the lower electrode.
[0057] The second dielectric layer material is preferably silicon oxide.
[0058] (12) Use bonding adhesive to bond the carrier sheet to the surface of the second dielectric layer, i.e. the front side of the silicon epitaxial wafer, so as to provide mechanical support in subsequent thinning processes.
[0059] (13) Flip the epitaxial silicon wafer, and then use mechanical grinding and self-stopping etching to remove the p+ substrate on the back of the epitaxial silicon wafer, leaving the epitaxial layer.
[0060] The remaining substrate thickness after mechanical polishing is 50 μm to 80 μm.
[0061] The self-stopping etching solution consists of nitric acid, hydrofluoric acid, and glacial acetic acid. It automatically stops etching after the substrate is completely etched by utilizing the difference in etching rate of silicon materials with different doping concentrations.
[0062] (14) Wet etching is used to remove the transition region between the p+ substrate and the epitaxial layer.
[0063] The corrosion thickness should be greater than 3 μm.
[0064] (15) An epitaxial layer is etched to form a groove in the corresponding region of the third dielectric layer.
[0065] The groove depth is 500 nm to 1000 nm.
[0066] (16) A p+ contact region is formed on the back side of the epitaxial layer by implanting a large dose of boron, and the boron is activated by laser annealing.
[0067] The volume concentration range of the p+ contact region is 1E18 cm⁻¹. -3 ~1E20 cm -3 .
[0068] (17) A third dielectric layer is deposited on the back side, and the thickness of the deposited layer should be greater than the depth of the groove.
[0069] The preferred material for the third dielectric layer is silicon oxide.
[0070] (18) Remove excess dielectric layer by chemical mechanical polishing so that the height of the third dielectric layer is flush with the surface of the silicon wafer.
[0071] (19) Deposit the fourth dielectric layer.
[0072] The fourth dielectric layer material is preferably silicon oxide with a thickness of 10 nm to 50 nm.
[0073] (20) Deposit waveguide layer and then etch to form waveguide.
[0074] The waveguide material is preferably silicon nitride, silicon oxynitride, or germanium-doped silicon oxide.
[0075] In addition, the refractive index of the waveguide should be greater than that of the third and fourth dielectric layers.
[0076] (21) Etch contact holes in the fourth dielectric layer.
[0077] (22) Metallic aluminum is deposited on the back side to form the upper electrode.
[0078] (23) Etch through holes extending to the surface of the lower electrode in the device to expose the lower electrode and fabricate a silicon SPAD detector with integrated waveguide.
[0079] like Figure 4 and Figure 5 As shown, when incident light propagates in the waveguide, 99.7% of the incident light enters the silicon SPAD via the waveguide. This demonstrates that by setting the refractive index of the waveguide to be greater than that of the third and fourth dielectric layers, the loss of incident light is greatly reduced when it propagates in the waveguide section corresponding to the third dielectric layer. Consequently, the light leaks into the silicon SPAD in the waveguide section corresponding to the fourth dielectric layer and is fully absorbed, thus improving the detection efficiency.
[0080] In summary, this invention provides a silicon SPAD detector with integrated waveguide. By integrating a waveguide into the silicon SPAD detector, the coupling loss caused by connecting the photonic integrated chip and the silicon SPAD through optical fiber is reduced, thereby improving the detection efficiency of the device.
[0081] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.
Claims
1. A silicon SPAD detector with integrated waveguide, characterized in that, From bottom to top, it includes a second dielectric layer, a lower electrode, a first dielectric layer, an n+ contact region, an avalanche region, a p- absorption region, a p+ contact region, a third dielectric layer, and a fourth dielectric layer, as well as an upper electrode and a waveguide located above the fourth dielectric layer; The lower electrode is connected to the n+ contact area through the contact hole of the first dielectric layer; A step is provided at one end of the p+ contact region, and the third dielectric layer is located on the step and sandwiched between the p+ contact region and the fourth dielectric layer. The waveguide is positioned above the fourth dielectric layer and extends to the region corresponding to the third dielectric layer. The refractive index of the waveguide is greater than that of the third and fourth dielectric layers. The upper electrode is connected to the p+ contact area through the contact hole of the fourth dielectric layer.
2. The silicon SPAD detector according to claim 1, characterized in that, It also includes a protective ring, which is located above the first dielectric layer and surrounds the n+ contact area and the avalanche zone.
3. The silicon SPAD detector according to claim 2, characterized in that, It also includes a stop ring, which is located above the first dielectric layer and distributed outside the guard ring.
4. The silicon SPAD detector according to claim 1, characterized in that, The device has a through hole that passes through the fourth dielectric layer, the p+ contact region, the p- absorption region and the first dielectric layer, exposing the surface of the lower electrode.
5. The silicon SPAD detector according to claim 1, characterized in that, The device also includes a support carrier sheet disposed below the second dielectric layer.
6. The silicon SPAD detector according to claim 1, characterized in that, The thickness of the fourth dielectric layer is 10 nm to 50 nm.
7. A method for manufacturing a silicon SPAD detector with integrated waveguide, characterized in that, The method includes: Prepare a clean p-type epitaxial silicon wafer, and grow a silicon oxide dielectric layer on the surface of the epitaxial layer of the epitaxial silicon wafer; A cutoff ring pattern is formed by photolithography and etching of the silicon oxide dielectric layer, and then the cutoff ring is formed by ion implantation; a guard ring pattern is formed by photolithography and etching of the silicon oxide dielectric layer, and then the guard ring is formed by ion implantation; wherein, the cutoff ring is located on the outside of the guard ring; Avalanche region patterns are formed by photolithography and etching of the silicon oxide dielectric layer, boron is injected, and the boron diffuses into the epitaxial layer through a high-temperature process; then phosphorus is injected, and the phosphorus diffuses into the epitaxial layer through a high-temperature process, thus complementing the boron to form avalanche regions. The n+ contact region pattern is formed by photolithography and etching of the silicon oxide dielectric layer, and the n+ contact region is formed by ion implantation. A first dielectric layer is deposited on the front side, and contact holes are etched in the first dielectric layer; aluminum is deposited, and a lower electrode is formed by photolithography and etching, and the lower electrode contacts the n+ contact area through the contact holes; A second dielectric layer is deposited on the front side; The epitaxial silicon wafer is flipped over, and the substrate on the back side of the epitaxial silicon wafer is removed by mechanical grinding and self-stopping etching. Then, the transition region between the substrate and the epitaxial layer is removed by wet etching. A groove is formed by etching the epitaxial layer; a p+ contact region is formed on the back side of the epitaxial layer by ion implantation. A third dielectric layer is deposited in the groove, and the height of the third dielectric layer is flush with the surface of the p+ contact region. A fourth dielectric layer is deposited to cover the p+ contact region and the third dielectric layer, and contact holes are etched out; a waveguide is formed on the surface of the fourth dielectric layer, and the waveguide extends on the surface of the fourth dielectric layer to the corresponding region of the third dielectric layer; wherein, the refractive index of the waveguide should be greater than the refractive index of the third dielectric layer and the fourth dielectric layer; Metallic aluminum is deposited on the surface of the fourth dielectric layer to form the upper electrode. The upper electrode does not contact the waveguide, but it contacts the p+ contact region through the contact hole of the fourth dielectric layer.
8. The method according to claim 7, characterized in that, The method also includes etching through holes in the device that extend to the surface of the lower electrode, exposing the lower electrode.
9. The method according to claim 7, characterized in that, The thickness of the fourth dielectric layer is 10 nm to 50 nm.