Method for manufacturing back contact cells, back contact cells and photovoltaic modules

Abstract

The application relates to a preparation method of a back contact cell, the back contact cell and a photovoltaic module. The preparation method of the back contact cell comprises the following steps: providing a silicon substrate, the silicon substrate comprising a first surface and a second surface oppositely arranged along the thickness direction of the silicon substrate, forming a first texture structure on the first surface, performing a first diffusion treatment on the silicon substrate, forming a first diffusion region with a first conductive type on the first surface of the silicon substrate and a first silicon glass layer covering the first diffusion region, removing part of the first silicon glass layer of a first region of the first surface, so that the thickness of the first silicon glass layer of the first region is smaller than the thickness of the first silicon glass layer of a second region of the first surface; removing the first silicon glass layer and the first diffusion region of the first region, exposing the silicon substrate of the first region, and reducing the thickness of the first silicon glass layer of the second region; and forming a semiconductor doping layer in the first region, so that the process flow is simplified and the cost is saved.

Description

Technical Field

[0001] This application relates to the field of photovoltaic technology, and in particular to a method for preparing a back contact cell, the back contact cell, and a photovoltaic module. Background Technology

[0002] In recent years, as the photovoltaic industry has continued to pursue higher cell conversion efficiency, back contact (BC) cells have become a key development direction for next-generation high-efficiency battery technology. This type of cell places the PN junction and all metal electrodes on the back of the cell, completely eliminating optical shading losses from the front-side grid lines.

[0003] The key technology of back-contact solar cells lies in how to fabricate alternating P-type and N-type doped regions on the back of a silicon wafer and achieve high-quality surface passivation. Existing back-contact solar cells typically utilize masks to fabricate alternating P-type and N-type doped regions, such as polycrystalline silicon (POLY) masks or silicon oxide (SiO2) masks. The P-type doped regions are blocked by the mask, and wet etching is used to open the process window for the N-type doped regions, thus forming the N-type doped regions. However, these methods suffer from drawbacks such as complex processes and high costs. Summary of the Invention

[0004] Therefore, it is necessary to provide a method for manufacturing back contact batteries, a back contact battery, and a photovoltaic module that can reduce the manufacturing process and production cost of back contact batteries, in order to address the above-mentioned technical problems.

[0005] In a first aspect, this application provides a method for preparing a back contact battery, the method comprising:

[0006] A silicon substrate is provided, the silicon substrate including a first surface and a second surface disposed opposite to each other along its thickness direction, and a first texture structure is formed on the first surface;

[0007] The silicon substrate is subjected to a first diffusion process to form a first diffusion region having a first conductivity type and a first silicon glass layer covering the first diffusion region on a first surface of the silicon substrate.

[0008] Remove a portion of the first silicon glass layer in the first region of the first surface, so that the thickness of the first silicon glass layer in the first region is less than the thickness of the first silicon glass layer in the second region of the first surface;

[0009] Remove the first silicon glass layer and the first diffusion region in the first region to expose the silicon substrate in the first region, and thin the thickness of the first silicon glass layer in the second region;

[0010] A semiconductor doped layer is formed in the first region.

[0011] In one embodiment, removing a portion of the first silicon glass layer in the first region of the first surface includes: laser etching to remove a portion of the first silicon glass layer in the first region;

[0012] The laser frequency is 600kHz-1400kHz, the scanning speed is 20000mm / s-60000mm / s, and the laser power is 5W-30W.

[0013] In one embodiment, an etching solution is used to clean and remove the first silicon glass layer and the first diffusion region in the first region, and the thickness of the first silicon glass layer in the second region is reduced.

[0014] In one embodiment, the step of forming a semiconductor doped layer in the first region includes:

[0015] The first region is treated with alkaline polishing to remove the damaged layer of the silicon substrate. After alkaline polishing, the thickness of the silicon substrate in the first region is less than the thickness of the silicon substrate in the second region.

[0016] In one embodiment, forming a semiconductor doped layer in the first region includes:

[0017] A tunneling oxide layer, a semiconductor material layer, and a second silicon glass layer are sequentially formed on the first surface, covering the silicon substrate in the first region and the first silicon glass layer in the second region;

[0018] The silicon substrate is heat-treated, and dopant elements are precipitated from the second silicon glass layer and diffused into the semiconductor material layer to form the semiconductor doped layer.

[0019] In one embodiment, after forming the semiconductor doped layer in the first region, the method further includes:

[0020] The tunneling oxide layer, the semiconductor doped layer, and the second silicon glass layer in the second region are removed by etching.

[0021] In one embodiment, the method for preparing the back contact battery further includes:

[0022] The first surface of the silicon substrate is laser-etched to form a spacer region at the junction of the first region and the second region, the spacer region exposing the silicon substrate;

[0023] The silicon substrate in the spacer region is texturized to form a second textured structure.

[0024] In one embodiment, after removing a portion of the first silicon glass layer in the first region, the thickness of the first silicon glass layer in the first region is 5nm-20nm.

[0025] After thinning the thickness of the first silicon glass layer in the second region, the thickness of the first silicon glass layer in the second region is 65nm-110nm.

[0026] Secondly, this application also provides a back contact battery, which is prepared by the method for preparing a back contact battery as described in any one of the first aspects; the back contact battery includes:

[0027] A silicon substrate includes a first surface and a second surface disposed opposite to each other along its thickness direction, the first surface including a first region and a second region;

[0028] A first diffusion region is located in the second region of the first surface, and the side of the first diffusion region facing away from the silicon substrate has a first texture structure;

[0029] A semiconductor doped layer is located in the first region of the first surface.

[0030] Thirdly, this application also provides a photovoltaic module, which includes a back contact battery as described in the second aspect.

[0031] The aforementioned method for fabricating a back-contact battery, the back-contact battery, and the photovoltaic module provides a silicon substrate. The silicon substrate includes a first surface and a second surface disposed opposite to each other along its thickness direction. A first textured structure is formed on the first surface. The silicon substrate undergoes a first diffusion treatment, forming a first diffusion region with a first conductivity type and a first silicon glass layer covering the first diffusion region on the first surface. A portion of the first silicon glass layer in the first region of the first surface is removed, so that the thickness of the first silicon glass layer in the first region is less than the thickness of the first silicon glass layer in the second region of the first surface. The first silicon glass layer and the first diffusion region in the first region are removed, exposing the silicon substrate in the first region, and the thickness of the first silicon glass layer in the second region is thinned. A semiconductor doped layer is formed in the first region. In this embodiment, by removing a portion of the first silicon glass layer in the first region of the first surface to form a film thickness difference based on the first textured structure, and then removing the first silicon glass layer and the first diffusion region in the first region, and thinning the thickness of the first silicon glass layer in the second region, a textured film-forming process with low damage is achieved. In the case of large-area film-forming, the damage of laser to the silicon substrate can be significantly reduced. Compared with printing ink and mask fabrication processes, this simplifies the process flow and saves costs. Attached Figure Description

[0032] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0033] Figure 1 A schematic diagram of the process flow for a method of preparing a back contact battery provided in an exemplary embodiment of this application;

[0034] Figure 2 A schematic diagram of the preparation process of a back contact battery preparation method provided for an exemplary embodiment of this application;

[0035] Figure 3 A schematic diagram of the process flow for a method of preparing a back contact battery provided as another exemplary embodiment of this application;

[0036] Figure 4 A schematic diagram of the preparation process of a method for preparing a back contact battery provided as another exemplary embodiment of this application;

[0037] Figure 5 This is a schematic diagram of a back contact battery provided for an exemplary embodiment of this application.

[0038] Figure label:

[0039] 10. Silicon substrate; 11. First textured structure; 12. First diffusion region; 13. First silicon glass layer; 14. Tunneling oxide layer; 15. Semiconductor material layer; 16. Second silicon glass layer; 17. Semiconductor doped layer; 18. Second textured structure; 101. First surface; 102. Second surface; 1011. First region; 1012. Second region; 19. Spacer region. Detailed Implementation

[0040] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0041] It should be noted that the terms "first," "second," etc., used in this application can be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish the first element from the second element. The terms "comprising" and "having," and any variations thereof, used in this application, are intended to cover non-exclusive inclusion. The term "multiple" used in this application refers to two or more. The term "and / or" used in this application refers to one of the embodiments, or any combination of multiple embodiments.

[0042] Existing BC cell designs with a dual-POLY structure require two POLY depositions, resulting in a long process and high cost. Single-POLY structure designs using textured borosilicate glass (BSG) films typically involve additional masking processes, such as POLY masks and SiO2 masks, which are complex and costly. Alternatively, single-POLY structures are generally designed with texturing, boron diffusion, and ink printing as a protective process, followed by etching of the non-printed BSG film using hydrofluoric acid (HF) solution. This design involves high ink costs, difficult cleaning, and uneven edges of the ink-printed area, increasing the difficulty of alignment for secondary laser processing and subsequent metal printing.

[0043] In one exemplary embodiment, such as Figure 1 As shown, a method for preparing a back contact battery is provided, including the following steps S101 to S105. Wherein:

[0044] Step S101: Provide a silicon substrate 10, the silicon substrate 10 including a first surface 101 and a second surface 102 disposed opposite to each other along its thickness direction, and a first texture structure 11 is formed on the first surface 101.

[0045] Among them, such as Figure 2 As shown, the silicon substrate 10 includes a first surface 101 and a second surface 102 disposed opposite to each other along its thickness direction. In this embodiment, the first surface 101 is the back surface of the silicon substrate 10, and the second surface 102 is the front surface of the silicon substrate 10.

[0046] In this embodiment, the silicon substrate 10 may have an N-type conductivity, may be doped with phosphorus, or may be doped with antimony, or may be a phosphorus-antimony co-doped substrate.

[0047] In this embodiment, an alkaline solution (such as KOH or NaOH) can be used to anisotropically etch the back side of the silicon substrate 10 to form a randomly distributed first texture structure 11, thereby removing dirt from the silicon substrate 10 and improving light-harvesting capability.

[0048] For example, by controlling the concentration, temperature and corrosion time of the alkaline solution, the base width of the first texture structure 11 can be controlled within the range of 2μm-5μm, and the base height of the first texture structure 11 can be controlled within the range of 1.5μm-4μm. The uniform and moderate first texture structure 11 is conducive to ensuring the consistency of subsequent laser absorption and the anti-reflection effect.

[0049] Step S102: Perform a first diffusion process on the silicon substrate 10 to form a first diffusion region 12 having a first conductivity type and a first silicon glass layer 13 covering the first diffusion region 12 on the first surface of the silicon substrate 10.

[0050] In this embodiment, a boron-containing gas (such as B2H6) and oxygen are introduced, and at a high temperature of 800℃-1200℃, boron atoms diffuse into the silicon substrate 10 to form P. + The region (emitter) is where the surface of the silicon substrate 10 reacts with oxygen to generate SiO2, and boron atoms are incorporated into the SiO2 lattice to form the first silicon glass layer 13 (BSG).

[0051] For example, the thickness of the first silicon glass layer 13 is 70nm-130nm. Further, the thickness of the first silicon glass layer 13 can be 80nm-120nm; further still, the thickness of the first silicon glass layer 13 can be 90nm-110nm. For instance, the thickness of the first silicon glass layer 13 can be 80nm, 90nm, 100nm, or 120nm.

[0052] Step S103: Remove a portion of the first silicon glass layer 13 in the first region 1011 of the first surface 101, so that the thickness of the first silicon glass layer 13 in the first region 1011 is less than the thickness of the first silicon glass layer 13 in the second region 1012 of the first surface 101.

[0053] After removing a portion of the thickness of the first silicon glass layer 13 in the first region 1011, the thickness of the first silicon glass layer 13 in the first region 1011 is 5nm-20nm, for example, 5nm, 10nm, 15nm, or 20nm. The remaining thickness of the first silicon glass layer 13 in the first region 1011 is within the range of 5nm-20nm. This ensures that the remaining first silicon glass layer 13 in the first region 1011 can be quickly removed in subsequent fabrication processes, and also reduces the laser energy acting on the silicon substrate 10 in the first region 1011, thereby protecting the silicon substrate 10 in the first region 1011.

[0054] In this embodiment, by controlling the power, speed, frequency and other parameters of the laser device, it is possible to remove only a portion of the thickness of the first silicon glass layer 13 in the first region 1011, retain another portion of the thickness of the first silicon glass layer 13 in the first region 1011, while the first silicon glass layer 13 in the second region 1012, which is not irradiated by the laser device, retains its original thickness.

[0055] In one alternative implementation, a precision-controlled spray gun can be used to spray extremely fine abrasive (such as alumina powder) or a high-pressure water jet only onto the first region 1011, thereby grinding away a portion of the thickness of the first silicon glass layer 13 through physical friction.

[0056] In another alternative implementation, a highly focused gallium ion beam can be used to bombard the first silicon glass layer 13 of the first region 1011 point by point, thereby stripping off a portion of the thickness of the first silicon glass layer 13 of the first region 1011 through a sputtering effect.

[0057] It is understood that after step S103 removes part of the first silicon glass layer 13 of the first region 1011 of the first surface 101, the thickness of the remaining first silicon glass layer 13 of the first region 1011 is less than the thickness of the first silicon glass layer 13 of the second region 1012. That is, there is a thickness difference between the remaining first silicon glass layer 13 of the first region 1011 and the first silicon glass layer 13 of the second region 1012.

[0058] In this embodiment of the application, after step S103 removes a portion of the first silicon glass layer 13 in the first region 1011 of the first surface 101, the thickness difference between the remaining first silicon glass layer 13 in the first region 1011 and the first silicon glass layer 13 in the second region 1012 ranges from 65nm to 125nm. Further, after step S103 removes a portion of the first silicon glass layer 13 in the first region 1011 of the first surface 101, the thickness difference between the remaining first silicon glass layer 13 in the first region 1011 and the first silicon glass layer 13 in the second region 1012 ranges from 80nm to 100nm. For example, the thickness difference between the remaining first silicon glass layer 13 in the first region 1011 and the first silicon glass layer 13 in the second region 1012 can be 65nm, 90nm, 95nm, 110nm, or 125nm.

[0059] Step S104: Remove the first silicon glass layer 13 and the first diffusion region 12 of the first region 1011 to expose the silicon substrate 10 of the first region 1011, and thin the thickness of the first silicon glass layer 13 of the second region 1012.

[0060] Specifically, after thinning the thickness of the first silicon glass layer 13 in the second region 1012, the thickness of the first silicon glass layer 13 in the second region 1012 is 65nm-110nm. Further, after thinning the thickness of the first silicon glass layer 13 in the second region 1012, the thickness of the first silicon glass layer 13 in the second region 1012 is 75nm-95nm. For example, after thinning the thickness of the first silicon glass layer 13 in the second region 1012, the remaining thickness of the first silicon glass layer 13 in the second region 1012 can be 65nm, 68nm, 82nm, 90nm, or 110nm.

[0061] In this embodiment, an etching solution is used to clean and remove the first silicon glass layer 13 and the first diffusion region 12 of the first region 1011, and to thin the thickness of the first silicon glass layer 13 of the second region 1012.

[0062] In this embodiment, the first silicon glass layer 13 of the first region 1011 and the first silicon glass layer 13 of the second region 1012 are etched in the same process. Because there is a thickness difference between the remaining first silicon glass layer 13 in the first region 1011 and the first silicon glass layer 13 in the second region 1012, after completely removing the first silicon glass layer 13 and the first diffusion region 12 in the first region 1011, the second region 1012 still contains the unremoved first silicon glass layer 13. That is, in this step, the first silicon glass layer 13 in the second region is only thinned, not completely removed.

[0063] In other alternative implementation methods, high-energy lasers (energy density > 1 J / cm²) can be used. 2 Irradiation causes the first silicon glass layer 13 and the first diffusion region 12 of the first region 1011 to heat up and vaporize instantly, directly removing the first silicon glass layer 13 and the first diffusion region 12 of the first region 1011; reducing the laser energy density (0.1 J / cm²). 2 -0.5J / cm 2 The thickness of the first silicon glass layer 13 in the second region 1012 is reduced by gentle thermal ablation or photochemical etching. In this embodiment, the amount of thinning can be precisely controlled by adjusting the number and speed of laser scans.

[0064] Step S105: Form a semiconductor doped layer 17 in the first region 1011.

[0065] In this embodiment, a tunneling oxide layer 14, a semiconductor material layer 15, and a second silicon glass layer 16 are sequentially formed on the first surface 101, covering the silicon substrate 10 of the first region 1011 and the first silicon glass layer 13 of the second region 1012; the silicon substrate 10 is heat-treated, and doping elements are precipitated from the second silicon glass layer 16 and diffused into the semiconductor material layer 15 to form a semiconductor doped layer 17.

[0066] In an alternative implementation, a liquid containing a phosphorus source (such as a phosphoric acid solution or an organophosphorus compound) can be spin-coated or sprayed onto the first surface 101, and the first region 1011 can be scanned using a continuous or pulsed laser (such as an 808nm infrared laser). The laser energy is absorbed by the silicon substrate 10, generating localized high temperatures, which melt part of the silicon material in the silicon substrate 10 and cause phosphorus atoms from the phosphorus source to diffuse into the molten silicon substrate 10, forming a semiconductor doped layer 17 in the first region 1011. The surface residual dopant source is then cleaned away with deionized water or the like.

[0067] In the above-described method for fabricating a back-contact battery, a silicon substrate 10 is provided. The silicon substrate 10 includes a first surface 101 and a second surface 102 disposed opposite to each other along its thickness direction. A first texture structure 11 is formed on the first surface 101. A first diffusion treatment is performed on the silicon substrate 10. A first diffusion region 12 having a first conductivity type and a first silicon glass layer 13 covering the first diffusion region 12 are formed on the first surface 101 of the silicon substrate 10. A portion of the first silicon glass layer 13 in the first region 1011 of the first surface 101 is removed so that the thickness of the first silicon glass layer 13 in the first region 1011 is less than the thickness of the first silicon glass layer 13 in the second region 1012 of the first surface 101. The first silicon glass layer 13 and the first diffusion region 12 in the first region 1011 are removed to expose the silicon substrate 10 in the first region 1011, and the thickness of the first silicon glass layer 13 in the second region 1012 is thinned. A semiconductor doped layer 17 is formed in the first region 1011. This embodiment of the application achieves textured film opening with low damage by removing part of the first silicon glass layer 13 in the first region 1011 of the first surface 101 to form a film thickness difference, then removing the first silicon glass layer 13 and the first diffusion region 12 in the first region 1011, and thinning the thickness of the first silicon glass layer 13 in the second region 1012. In the case of large-area film opening, the damage of laser to silicon substrate 10 can be greatly reduced. Compared with printing ink and mask making process, the process is simplified and the cost is saved.

[0068] In one embodiment, step S103, which removes a portion of the first silicon glass layer 13 in the first region 1011 of the first surface 101, includes: laser etching to remove a portion of the first silicon glass layer 13 in the first region 1011; wherein the laser frequency is 600kHz-1400kHz, the scanning speed is 20000mm / s-60000mm / s, and the laser power is 5W-30W.

[0069] In this embodiment of the application, a picosecond laser is used to partially ablate the first silicon glass layer 13 of the first region 1011 from its initial thickness (e.g., 70nm-130nm), leaving only a uniform residual layer with a thickness of 5nm-20nm. In this way, the damage of the laser to the silicon substrate 10 of the first region 1011 can be reduced.

[0070] For example, since both the first silicon glass layer 13 and the silicon substrate 10 have good absorption rates for short-wavelength light, and the spot size of short-wavelength light is smaller, the processing precision is higher. For example, green light (532nm) or ultraviolet light (355nm) can be used for laser etching.

[0071] The laser frequency of the laser device is 600kHz-1400kHz; further, the laser frequency is 800kHz-1100kHz. For example, the laser frequency can be 600kHz, 800kHz, 1000kHz, 1200kHz, or 1400kHz. Higher laser frequencies result in higher overlap between adjacent spots at the same scanning speed, leading to more uniform processing. For precision processing involving the removal of partial film layers, the laser used needs to have a high frequency (e.g., above 1000kHz) and a high overlap rate to ensure that each point on the undulating surface of the first texture structure 11 is effectively acted upon by at least one pulse of suitable energy, improving the pulse gap and preventing uneven removal of defects.

[0072] The scanning speed of the laser equipment is 20,000 mm / s to 60,000 mm / s; further, the scanning speed is 35,000 mm / s to 50,000 mm / s; for example, the scanning speed can be 20,000 mm / s, 40,000 mm / s, 55,000 mm / s, or 60,000 mm / s. The laser scanning speed is positively correlated with the removal thickness of the first silicon glass layer 13 in the first region 1011 (at a fixed power, the slower the speed, the more pulses are superimposed, and the more is removed). In order to achieve uniform removal of the first silicon glass layer 13, the laser needs extremely high speed stability. In this embodiment, selecting a higher scanning speed (such as 40,000 mm / s) is beneficial to reduce heat accumulation, and by adjusting the laser power, the ablation amount of a single pulse or a few pulses can be precisely controlled.

[0073] The laser power of the laser device ranges from 5W to 30W; further, it ranges from 15W to 325W. For example, the laser power of the laser device can be 5W, 8W, 12W, 16W, 23W, or 30W. With a fixed scanning speed and frequency, the scanning power directly determines the single-pulse energy and energy density of the laser. To achieve partial removal of the first silicon glass layer 13 in the first region 1011, the laser scanning power must be set within a range below the complete ablation threshold but above the ablation initiation threshold. For example, if the initial thickness of the first silicon glass layer 13 is 100nm, and the goal is to ablate the first silicon glass layer to a remaining thickness of 15nm, the laser scanning power can be set to 18W.

[0074] In this application, the term "ablation initiation threshold" refers to the minimum laser energy density (unit: joules per square centimeter, J / cm²) required for permanent removal of the material when the laser interacts with it. 2 ).

[0075] In one embodiment, step S104 removes the first silicon glass layer 13 and the first diffusion region 12 of the first region 1011, exposing the silicon substrate 10 of the first region 1011, and thins the thickness of the first silicon glass layer 13 of the second region 1012, including: cleaning with an etching solution to remove the first silicon glass layer 13 and the first diffusion region 12 of the first region 1011, and thinning the thickness of the first silicon glass layer 13 of the second region 1012.

[0076] In this embodiment, the first silicon glass layer 13 and the first diffusion region 12 in the first region 1011 can be removed by cleaning in an HF solution, and the thickness of the first silicon glass layer 13 in the second region 1012 can be reduced. For example, the cleaning time is 20s-100s, the concentration of the HF solution is 5%-15%, and the temperature is 15℃-30℃.

[0077] In the above-mentioned embodiments, the first silicon glass layer 13 and the first diffusion region 12 of the first region 1011 are removed by etching solution cleaning, and the thickness of the first silicon glass layer 13 of the second region 1012 is reduced. Compared with dry etching (plasma bombardment) or laser complete burn-through, the pure wet chemical process does not have high-energy particles or photons bombarding it, and will not generate lattice defects, dangling bonds or implanted impurities on the surface of the silicon substrate 10, which is beneficial to improving the life of the back contact battery.

[0078] In one embodiment, such as Figure 3 As shown, the method for preparing a back contact battery also includes steps S301-S306 performed after step S105.

[0079] Step S301: Alkali polishing is performed on the first region 1011 to remove the damaged layer of the silicon substrate 10. After alkaline polishing, the thickness of the silicon substrate 10 in the first region 1011 is less than the thickness of the silicon substrate 10 in the second region 1012.

[0080] After step S103 of this embodiment removes part of the first silicon glass layer 13 of the first region 1011 of the first surface 101, part of the first silicon glass layer 13 is retained in the first region 1011 to protect the silicon substrate 10. However, the laser processing may still damage the silicon substrate 10 of the first region 1011, forming a damaged layer in the first region 1011 (not shown in the figure).

[0081] In this application embodiment, in conjunction with the above Figure 2As shown, laser damage is removed by alkaline polishing with an etching depth of 3µm-10µm. This removes the damaged layer of the silicon substrate 10 in the first region 1011, resulting in a thickness of the silicon substrate 10 in the first region 1011 that is less than the thickness of the silicon substrate 10 in the second region 1012 after alkaline polishing. The exposed surface of the silicon substrate 10 in the first region 1011 exhibits a regular and ordered lattice arrangement. For example, the alkaline polishing temperature is 65℃-80℃, and the polishing time is 200s-500s.

[0082] Step S302: A tunneling oxide layer 14, a semiconductor material layer 15, and a second silicon glass layer 16 are sequentially formed on the first surface 101, covering the silicon substrate 10 of the first region 1011 and the first silicon glass layer 13 of the second region 1012.

[0083] In the embodiments of this application, such as Figure 4 As shown, an ultrathin silicon oxide (SiO2) layer is grown on the first surface 101 as a tunneling oxide layer 14, which allows carrier tunneling while suppressing interface recombination.

[0084] Then, a layer of phosphorus-doped amorphous silicon with a thickness of about 150nm-300nm is formed on the tunneling oxide layer 14 by low pressure chemical vapor deposition (LPCVD). The silicon crystallizes into polycrystalline silicon (POLY) at a high temperature in the subsequent process as a semiconductor material layer 15, while a second silicon glass layer 16 is generated.

[0085] Step S303: Heat-treat the silicon substrate 10, and the dopant elements are precipitated from the second silicon glass layer 16 and diffused into the semiconductor material layer 15 to form a semiconductor doped layer 17.

[0086] In this embodiment, the silicon substrate 10 can be heat-treated in a nitrogen-oxygen atmosphere at 700℃-1000℃. Phosphorus atoms precipitate from the second silicon glass layer 16, pass through the tunneling oxide layer 14, and enter the underlying silicon substrate 10 to form a semiconductor doped layer 17 (N). + (Emitter).

[0087] Step S304: Etch to remove the tunneling oxide layer 14, semiconductor doped layer 17 and second silicon glass layer 16 of the second region 1012.

[0088] In this embodiment, wet etching can be used to remove the tunneling oxide layer 14, the semiconductor doped layer 17, and the second silicon glass layer 16 of the second region 1012. For example, the silicon substrate 10 is immersed in a dilute HF solution, and the second silicon glass layer 16 is rapidly and uniformly etched laterally and vertically until it is completely removed, exposing the underlying semiconductor doped layer 17. The silicon substrate 10 after removing the second silicon glass layer 16 is then transferred to a hot potassium hydroxide (KOH) solution. The silicon substrate 10 after removing the semiconductor doped layer 17 is then immersed in a dilute HF solution again. Since the tunneling oxide layer 14 is extremely thin, it can be completely removed by immersing it in the dilute HF solution for only a very short time (a few seconds to a dozen seconds).

[0089] In an alternative implementation, a laser can be used to ablate and remove the tunneling oxide layer 14, the semiconductor doped layer 17, and the second silicon glass layer 16 above the second region 1012 in a single operation.

[0090] Step S305: Laser etching of the first surface 101 of the silicon substrate 10 to form a spacer region 19 at the junction of the first region 1011 and the second region 1012, the spacer region 19 exposing the silicon substrate 10.

[0091] In this embodiment, a green or ultraviolet picosecond laser is used to scan along the boundary between the first region 1011 and the second region 1012, removing all film layers within a narrow band at the boundary and forming a spacer region 19 at the boundary between the first region 1011 and the second region 1012, exposing the silicon substrate 10. For example, the laser frequency is 600kHz-1400kHz, the scanning speed is 20000mm / s-60000mm / s, and the laser power is 5W-40W.

[0092] Step S306: Texturing the silicon substrate 10 of the spacer region 19 to form a second textured structure 18.

[0093] In this embodiment, the silicon substrate 10 is immersed in an alkaline texturing solution (such as KOH + IPA solution) to selectively form a second texture structure 18 on the bottom and sidewalls of the spacer region 19. The IPA solution is an isopropanol solution. The IPA solution selectively inhibits the corrosion rate of certain crystal planes by adsorbing onto the surface of the silicon substrate 10, making the corrosion controllable and helping to form a uniform and densely distributed second texture structure 18.

[0094] For example, before texturing the silicon substrate 10 of the spacer region 19 to form the second textured structure 18, impurities in the silicon substrate 10 can be quickly removed using HNO3 silicon oxide or HF solution, efficiently removing the first silicon glass layer 13 grown on the front side of the silicon substrate 10 during the first diffusion process, as well as the second silicon glass layer 16 or polycrystalline silicon layer generated during the formation of the semiconductor doped layer 17.

[0095] The silicon substrate 10 is immersed in an alkaline solution (temperature 65℃-80℃, time 400s-700s) to anisotropically etch the spacer region 19. This process removes laser damage and simultaneously grows a new, uniform textured structure on the freshly cleaned front side of the silicon substrate 10, while a second textured structure 18 is formed within the spacer region 19. The alkaline solution slowly but continuously etches the first silicon glass layer 13. After prolonged processing, the first silicon glass layer 13, which serves as a mask, and the polycrystalline silicon (POLY) layer above the second region 1012 can be removed. Similarly, the alkaline solution can etch away any remaining second silicon glass layer 16 in the first region 1011. The resulting battery in this embodiment has a textured structure on the front side and a second textured structure 18 in the spacer region 19, improving the bifaciality compared to a dual-POLY battery.

[0096] Furthermore, after texturing, cleaning and drying, an ultrathin layer of aluminum oxide (Al2O3) can be deposited on both sides of the silicon substrate 10.

[0097] Because the spacing region 19 is relatively narrow, the size of the first texture structure 11 is larger than that of the second texture structure 18 due to the size limitation of the spacing region 19. For example, the base width of the first texture structure 11 can be 2um-5um, and the height of the tower body of the first texture structure 11 can be 1.5um-4um; the base width of the second texture structure 18 can be 0.5um-2um, and the height of the tower body of the second texture structure 18 can be 0.3um-1.5um.

[0098] In the above-mentioned embodiments, based on laser-controlled film thickness difference, low-damage patterning without additional masks was achieved on the silicon substrate 10 by wet selective etching, which greatly simplified the process and reduced costs. Finally, a high-efficiency back contact battery with a textured emitter structure was successfully fabricated, which improved the bifaciality of the back contact battery.

[0099] According to an exemplary embodiment, such as Figure 5 As shown, this embodiment provides a back contact battery, which is fabricated using the back contact battery fabrication method described in the above embodiment. The back contact battery includes a silicon substrate 10, a first diffusion region 12, and a semiconductor doped layer 17. The silicon substrate 10 includes a first surface 101 and a second surface 102 disposed opposite to each other along its thickness direction. The first surface 101 includes a first region 1011 and a second region 1012. The first diffusion region 12 is located in the second region 1012 of the first surface 101, and the side of the first diffusion region 12 facing away from the silicon substrate 10 has a first texture structure 11. The semiconductor doped layer 17 is located in the first region 1011 of the first surface 101.

[0100] According to an exemplary embodiment, this embodiment provides a photovoltaic module, which includes a back contact battery as described in the above embodiment.

[0101] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages in other steps. It is understood that the steps in different embodiments can be freely combined as needed, and all non-contradictory solutions formed by such combinations are within the scope of protection of this application.

[0102] Based on the same inventive concept, this application also provides an apparatus for fabricating a back contact battery to implement the aforementioned method for fabricating a back contact battery. The solution provided by this apparatus is similar to the solution described in the above method; therefore, the specific limitations of one or more embodiments of the back contact battery fabrication apparatus provided below can be found in the limitations of the back contact battery fabrication method described above, and will not be repeated here.

[0103] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0104] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A method of fabricating a back contact cell, characterized by, The method for preparing the back contact battery includes: A silicon substrate is provided, the silicon substrate including a first surface and a second surface disposed opposite to each other along its thickness direction, and a first texture structure is formed on the first surface; The silicon substrate is subjected to a first diffusion process to form a first diffusion region having a first conductivity type and a first silicon glass layer covering the first diffusion region on a first surface of the silicon substrate. Remove a portion of the first silicon glass layer in the first region of the first surface, so that the thickness of the first silicon glass layer in the first region is less than the thickness of the first silicon glass layer in the second region of the first surface; Remove the first silicon glass layer and the first diffusion region in the first region to expose the silicon substrate in the first region, and thin the thickness of the first silicon glass layer in the second region; A semiconductor doped layer is formed in the first region.

2. The method of claim 1, wherein, The removal of a portion of the first silicon glass layer in the first region of the first surface includes: laser etching to remove a portion of the first silicon glass layer in the first region; The laser frequency is 600kHz-1400kHz, the scanning speed is 20000mm / s-60000mm / s, and the laser power is 5W-30W.

3. The method of claim 2, wherein the back contact cell is prepared by a method comprising: The first silicon glass layer and the first diffusion region in the first region are removed by cleaning with an etching solution, and the thickness of the first silicon glass layer in the second region is reduced.

4. The method of claim 1, wherein, Before forming the semiconductor doped layer in the first region, the process includes: The first region is treated with alkaline polishing to remove the damaged layer of the silicon substrate. After alkaline polishing, the thickness of the silicon substrate in the first region is less than the thickness of the silicon substrate in the second region.

5. The method of claim 1, wherein, The formation of a semiconductor doped layer in the first region includes: A tunneling oxide layer, a semiconductor material layer, and a second silicon glass layer are sequentially formed on the first surface, covering the silicon substrate in the first region and the first silicon glass layer in the second region; The silicon substrate is heat-treated, and dopant elements are precipitated from the second silicon glass layer and diffused into the semiconductor material layer to form the semiconductor doped layer.

6. The method of claim 5, wherein the back contact cell is prepared by, After forming the semiconductor doped layer in the first region, the method further includes: The tunneling oxide layer, the semiconductor doped layer, and the second silicon glass layer in the second region are removed by etching.

7. The method of claim 1, wherein the back contact cell is prepared by a method comprising: The method for preparing the back contact battery further includes: The first surface of the silicon substrate is laser-etched to form a spacer region at the junction of the first region and the second region, the spacer region exposing the silicon substrate; The silicon substrate in the spacer region is texturized to form a second textured structure.

8. The method of claim 1, wherein, After removing part of the first silicon glass layer in the first region, the thickness of the first silicon glass layer in the first region is 5nm-20nm; After thinning the thickness of the first silicon glass layer in the second region, the thickness of the first silicon glass layer in the second region is 65nm-110nm.

9. A back contact cell characterized in that, The back contact battery is prepared using the method for preparing a back contact battery as described in any one of claims 1-8; the back contact battery comprises: A silicon substrate includes a first surface and a second surface disposed opposite to each other along its thickness direction, the first surface including a first region and a second region; A first diffusion region is located in the second region of the first surface, and the side of the first diffusion region facing away from the silicon substrate has a first texture structure; A semiconductor doped layer is located in the first region of the first surface.

10. A photovoltaic module, characterized by, The photovoltaic module includes the back contact battery as described in claim 9.

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