Formation method of semiconductor structure and semiconductor structure

Abstract

The invention provides a semiconductor structure forming method and a semiconductor structure. The forming method comprises the following steps: forming a substrate, and forming a first ion implantation region on the surface of the substrate; and forming a first epitaxial layer on the substrate, and forming a second ion implantation region on the surface of the first epitaxial layer. A second epitaxial layer is formed on the first epitaxial layer. Forming a second contact hole, enabling the second contact hole to penetrate through the second epitaxial layer along the stacking direction of the second epitaxial layer so as to expose the second ion implantation region, and forming a first contact hole, enabling the first contact hole to penetrate through the second epitaxial layer and the first epitaxial layer along the stacking direction of the second epitaxial layer so as to expose the first ion implantation region. A conductive interconnection layer is formed, and the conductive interconnection layer is located in the first contact hole and the second contact hole and connected with the first ion implantation region and the second ion implantation region, so that the substrate and the first epitaxial layer are electrically conducted through the conductive interconnection layer. The problem that the contact resistance is high when the deep groove contact hole is optimized can be solved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a method for forming a semiconductor structure and a semiconductor structure. Background Technology

[0002] Silicon carbide (SiC), as a third-generation wide-bandgap semiconductor material, has become an ideal substrate material for manufacturing high-voltage, high-frequency, high-temperature, and high-power semiconductor devices due to its excellent properties such as high critical breakdown electric field, high saturated electron drift velocity, and high thermal conductivity.

[0003] In devices such as silicon carbide metal-oxide-semiconductor field-effect transistors (SiC MOSFETs), silicon carbide junction field-effect transistors (JFETs), silicon carbide Schottky barrier diodes (SBDs), and silicon carbide PIN diodes, deep substrate vias (DSVs) are typically etched on the SiC substrate to achieve vertical interconnection and connection to the substrate in order to realize the vertical conductive structure of the device and reduce the on-resistance.

[0004] However, the high hardness, high chemical stability, and low self-diffusion coefficient of SiC material itself pose significant challenges to the fabrication of ohmic contacts in DSV structures. Unlike silicon, forming excellent ohmic contacts on SiC typically requires high concentrations of doping. When deep trench contact holes penetrate different layers, the sidewalls and bottom of the deep trench contact holes have different requirements for doping elements and concentrations. Traditional single-point implantation cannot simultaneously optimize the contact interfaces of both the sidewalls and bottom of the deep trench contact holes, resulting in inconsistent ohmic contact performance. The overall conductivity of the deep trench contact hole will be limited to the part with the worst contact. Summary of the Invention

[0005] This application provides a method for forming a semiconductor structure and a semiconductor structure to solve the problem in the prior art that it is difficult to simultaneously optimize the contact interface of the sidewall and bottom of the deep trench contact hole, resulting in high contact resistance.

[0006] To achieve the above objectives, this application adopts the following technical solution:

[0007] A first aspect of this application provides a method for forming a semiconductor structure, comprising: forming a substrate and forming a first ion implantation region on the surface of the substrate; forming a first epitaxial layer on the substrate with a conductivity type opposite to that of the substrate, and forming a second ion implantation region on the surface of the first epitaxial layer; forming a second epitaxial layer on the first epitaxial layer with the same conductivity type as the first epitaxial layer; forming a second contact hole and extending the second contact hole through the second epitaxial layer along the stacking direction of the second epitaxial layer to expose the second ion implantation region; and forming a first contact hole and extending the first contact hole through the second epitaxial layer and the first epitaxial layer along the stacking direction of the second epitaxial layer to expose the first ion implantation region; and forming a conductive interconnect layer located at the first contact hole and the second contact hole, and both connected to the first ion implantation region and the second ion implantation region, so that the substrate and the first epitaxial layer are electrically connected through the conductive interconnect layer.

[0008] As an optional implementation, before forming the second contact hole, the formation method further includes: activating the internal doping impurities of the first epitaxial layer by a high-temperature annealing process.

[0009] As an optional implementation, after activating the internal doping impurities of the first epitaxial layer and before forming the second contact hole, the formation method further includes: forming a gallium nitride epitaxial layer on top of the second epitaxial layer.

[0010] As an optional implementation, forming a second contact hole and extending the second contact hole through the second epitaxial layer along the stacking direction of the second epitaxial layer to expose the second ion implantation region includes: depositing silicon dioxide on the second epitaxial layer and forming a mask layer on the silicon dioxide by photolithography to define the positions of the first contact hole and the second contact hole; etching the second epitaxial layer to form the second contact hole, the second contact hole extending through the second epitaxial layer and exposing the second ion implantation region.

[0011] As an optional implementation, a first contact hole is formed, which penetrates the second epitaxial layer and the first epitaxial layer along the stacking direction of the second epitaxial layer to expose the first ion implantation region. This includes: defining the region corresponding to the first contact hole through a photoresist layer, and continuing to etch the region corresponding to the first contact hole to form the first contact hole; the first contact hole exposes the first ion implantation region on the substrate.

[0012] As an optional implementation, forming a second contact hole and extending the second contact hole through the second epitaxial layer along the stacking direction of the second epitaxial layer to expose the second ion implantation region includes: depositing silicon dioxide on the gallium nitride epitaxial layer and forming a mask layer on the silicon dioxide by photolithography to define the positions of the first contact hole and the second contact hole; etching the gallium nitride epitaxial layer and the second epitaxial layer to form the second contact hole, the second contact hole extending through the gallium nitride epitaxial layer and the second epitaxial layer and exposing the second ion implantation region.

[0013] As an optional implementation, a first contact hole is formed, which penetrates the second epitaxial layer and the first epitaxial layer along the stacking direction of the second epitaxial layer to expose the first ion implantation region. This includes: defining the region corresponding to the first contact hole through a photoresist layer, continuing to etch the region corresponding to the first contact hole to form the first contact hole, and exposing the first ion implantation region on the substrate.

[0014] As an optional implementation, forming a conductive interconnect layer includes: activating doped ions in a first ion implantation region and a second ion implantation region in two annealing processes using a nickel silicide process; wherein the first annealing process precedes the second annealing process, and the first annealing temperature in the first annealing process is lower than the second annealing temperature in the second annealing process; depositing an adhesion layer on the activated first ion implantation region and second ion implantation region, and filling the first contact hole and the second contact hole with the conductive interconnect layer.

[0015] A second aspect of this application provides a semiconductor structure comprising: a substrate, wherein a first ion implantation region is formed on the surface of the substrate; a first epitaxial layer is formed on top of the substrate, and the conductivity type of the first epitaxial layer is opposite to that of the substrate; and a second ion implantation region is formed on the surface of the first epitaxial layer; a second epitaxial layer is formed on top of the first epitaxial layer, and the conductivity type of the second epitaxial layer is the same as that of the first epitaxial layer; a first contact hole that sequentially penetrates the second epitaxial layer and the first epitaxial layer along the stacking direction of the second epitaxial layer to expose the first ion implantation region; a second contact hole that penetrates the second epitaxial layer along the stacking direction of the second epitaxial layer to expose the second ion implantation region; and a conductive interconnect layer located at the first contact hole and the second contact hole, and connected to both the first ion implantation region and the second ion implantation region, so that the substrate and the first epitaxial layer are electrically connected through the conductive interconnect layer.

[0016] As an optional implementation, it further includes: a gallium nitride epitaxial layer formed on top of the second epitaxial layer; and a first contact hole passing through the gallium nitride epitaxial layer, the second epitaxial layer and the first epitaxial layer sequentially along the stacking direction of the gallium nitride epitaxial layer; and a second contact hole passing through the gallium nitride epitaxial layer and the second epitaxial layer sequentially along the stacking direction of the gallium nitride epitaxial layer.

[0017] As an alternative implementation, the first epitaxial layer is activated by a high-temperature annealing process to remove internal doping impurities; the second epitaxial layer is formed on top of the first epitaxial layer after the internal doping impurities are activated by a vapor deposition process; and the gallium nitride epitaxial layer is formed on top of the second epitaxial layer by a vapor deposition process.

[0018] As an optional implementation, the first ion implantation region is formed on the surface of the substrate through multiple ion implantation processes, and / or the second ion implantation region is formed on the surface of the first epitaxial layer through multiple ion implantation processes.

[0019] As an optional implementation, multiple first contact holes are provided, and the multiple first contact holes are spaced apart along the thickness direction perpendicular to the substrate; or, multiple second contact holes are provided, and the multiple second contact holes are spaced apart along the thickness direction perpendicular to the substrate; or, multiple first contact holes and multiple second contact holes are provided, and the multiple first contact holes and multiple second contact holes are spaced apart along the thickness direction perpendicular to the substrate.

[0020] As an optional implementation, an adhesion layer is deposited between the first ion implantation region and the conductive interconnect layer and / or between the second ion implantation region and the conductive interconnect layer.

[0021] As an alternative implementation, the adhesion layer includes at least one of a titanium layer and a titanium nitride layer.

[0022] This application provides a method for forming a semiconductor structure and a semiconductor structure. The method includes: forming a substrate and forming a first ion implantation region on the surface of the substrate; forming a first epitaxial layer on the substrate and forming a second ion implantation region on the surface of the first epitaxial layer; the second ion implantation region having an opposite conductivity type to the first ion implantation region; forming a second epitaxial layer on the first epitaxial layer; forming a second contact hole that penetrates the second epitaxial layer along the stacking direction of the second epitaxial layer to expose the second ion implantation region; and forming a first contact hole that penetrates both the second epitaxial layer and the first epitaxial layer along the stacking direction of the second epitaxial layer to expose the first ion implantation region; and forming a conductive interconnect layer located at the first contact hole and the second contact hole, and connected to both the first and second ion implantation regions, so that the substrate and the first epitaxial layer are electrically connected through the conductive interconnect layer.

[0023] With the above configuration, the first contact hole exposes the substrate located below, thereby exposing the first ion implantation region disposed on the substrate surface. The first ion implantation region is formed before the first epitaxial layer and is used to achieve precise and optimized doping of the substrate.

[0024] The second contact hole only penetrates the second epitaxial layer, exposing the top of the first epitaxial layer located between the substrate and the second epitaxial layer. At this point, the second ion implantation region disposed on the surface of the first epitaxial layer is exposed, and the second ion implantation region can achieve precise and optimized doping of the first epitaxial layer. Furthermore, by connecting the first ion implantation region and the second ion implantation region through a conductive interconnect layer, electrical conductivity between the substrate and the first epitaxial layer can be achieved.

[0025] In this way, by separating the sidewall and bottom regions of the DSV cell into two independent ohmic contact systems, it is possible to achieve partitioned processing of the bottom doping and sidewall doping of a single DSV cell. This allows for precise optimization based on the doping requirements of different regions, i.e., selecting the most suitable ion implantation conditions for the first and second ion implantation regions respectively to achieve optimal overall performance. This solves the problem of high contact resistance caused by the difficulty in simultaneously optimizing the contact interface of the sidewall and bottom of deep trench contact holes in existing technologies. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1 A schematic flowchart illustrating a method for forming a semiconductor structure according to an embodiment of this application;

[0028] Figure 2 This is a schematic cross-sectional view of a semiconductor structure obtained by the semiconductor structure formation method provided in the embodiments of this application.

[0029] Figure 3 This is a schematic cross-sectional view of another semiconductor structure obtained by the semiconductor structure formation method provided in the embodiments of this application.

[0030] Figure 4 for Figure 2 A schematic diagram of the cross-sectional structure of the substrate formed during the semiconductor structure formation process is provided.

[0031] Figure 5 for Figure 2 A schematic cross-sectional view of the first ion implantation region formed during the semiconductor structure formation process is provided.

[0032] Figure 6 for Figure 2 A schematic cross-sectional view of the first epitaxial layer formed during the semiconductor structure formation process is provided.

[0033] Figure 7 for Figure 2 A schematic cross-sectional view of the second ion implantation region formed during the semiconductor structure formation process is provided.

[0034] Figure 8 for Figure 2 A schematic cross-sectional view of the formation of the second epitaxial layer during the semiconductor structure formation process is provided.

[0035] Figure 9 for Figure 2 A schematic diagram of the cross-sectional structure of the mask layer formed during the semiconductor structure formation process is provided.

[0036] Figure 10 for Figure 2 A schematic cross-sectional view of the second contact hole formed during the semiconductor structure formation process is provided.

[0037] Figure 11 for Figure 2 A schematic cross-sectional view of the first contact hole formed during the semiconductor structure formation process is provided.

[0038] Figure 12 for Figure 2 A schematic diagram of the cross-sectional structure of the semiconductor structure being formed by removing the mask layer;

[0039] Figure 13 for Figure 3 A schematic cross-sectional view of the gallium nitride epitaxial layer formed during the semiconductor structure formation process is provided.

[0040] Figure 14 for Figure 3 A schematic diagram of the cross-sectional structure of the mask layer formed during the semiconductor structure formation process is provided.

[0041] Figure 15 for Figure 3 A schematic cross-sectional view of the second contact hole formed during the semiconductor structure formation process is provided.

[0042] Figure 16 for Figure 3 A schematic cross-sectional view of the first contact hole formed during the semiconductor structure formation process is provided.

[0043] Figure 17 for Figure 3 A schematic diagram of the cross-sectional structure of the semiconductor structure being formed by removing the mask layer;

[0044] Figure 18 This is a schematic cross-sectional view of a deep trench contact hole in a semiconductor structure.

[0045] Explanation of reference numerals in the attached figures:

[0046] 10-Semiconductor structure;

[0047] 100 - Substrate; 110 - First ion implantation region;

[0048] 200 - First epitaxial layer; 210 - Second ion implantation region;

[0049] 300 - Second epitaxial layer;

[0050] 410 - First contact hole;

[0051] 420 - Second contact hole;

[0052] 500-Conductive interconnect layer;

[0053] 600-Gallium nitride epitaxial layer;

[0054] 700 - Mask layer;

[0055] 800 - Photoresist layer. Detailed Implementation

[0056] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0057] Silicon carbide (SiC), as a third-generation wide-bandgap semiconductor material, has become an ideal substrate material for manufacturing high-voltage, high-frequency, high-temperature, and high-power semiconductor devices due to its excellent properties such as high critical breakdown electric field, high saturated electron drift velocity, and high thermal conductivity.

[0058] In power devices such as SiC MOSFETs, JFETs, SBDs, and PIN diodes, deep substrate vias (DSVs) are typically etched on the SiC substrate to achieve vertical interconnects and connections to the substrate in order to realize the vertical conductivity structure of the device and reduce the on-resistance.

[0059] However, the high hardness, high chemical stability, and low self-diffusion coefficient of SiC material itself pose significant challenges to the fabrication of ohmic contacts in DSV structures. Unlike silicon, forming excellent ohmic contacts on SiC typically requires high concentrations of doping.

[0060] Related technologies have also explored the realization of ohmic contacts in SiC materials. However, existing ion implantation and metallization techniques are mainly designed for planar regions. When applied to deep trench structures, variations in sidewall tilt angle and depth lead to uneven ion distribution and discontinuous metal coverage, resulting in a significant increase in contact resistance.

[0061] When deep trench contact holes need to penetrate different layers, the sidewalls and bottom of the hole have different requirements for doping elements and concentrations. Traditional single-point implantation cannot simultaneously optimize the contact interfaces of both the sidewalls and bottom of the deep trench contact hole. This results in inconsistent ohmic contact performance between the two, and the overall conductivity of the deep trench contact hole will be limited by the part with the worst contact, thus leading to increased contact resistance.

[0062] For example, when a deep trench contact hole passes through a P-type epitaxial layer and extends to the surface of an N-type substrate, in order to form an ohmic contact, the bottom of the deep trench contact hole needs to be doped with the N-type substrate, while the sidewalls of the deep trench contact hole need to be doped with the P-type epitaxial layer.

[0063] It is understandable that the types and concentrations of doping elements used in N-type and P-type doping are different. In other words, when using existing methods to dope the bottom of deep trench contact holes with N-type dopant, the doping conditions effective for N-type substrates are ineffective for P-type epitaxial layers, and may even have a counterproductive effect. This results in either the sidewall or the bottom failing to achieve optimal contact performance, leading to excessively high contact resistance on either side of the deep trench contact hole. Consequently, the overall conductivity of the deep trench contact hole is limited to the area with the worst contact.

[0064] In view of the above, this application provides a method for forming a semiconductor structure and a semiconductor structure. The method includes: forming a substrate and forming a first ion implantation region on the surface of the substrate; forming a first epitaxial layer on the substrate and forming a second ion implantation region on the surface of the first epitaxial layer; the second ion implantation region having an opposite conductivity type to the first ion implantation region; forming a second epitaxial layer on the first epitaxial layer; forming a second contact hole that penetrates the second epitaxial layer along the stacking direction of the second epitaxial layer to expose the second ion implantation region; and forming a first contact hole that penetrates the second epitaxial layer and the first epitaxial layer along the stacking direction of the second epitaxial layer to expose the first ion implantation region; and forming a conductive interconnect layer located at the first contact hole and the second contact hole, and connected to both the first ion implantation region and the second ion implantation region, so that the substrate and the first epitaxial layer are electrically connected through the conductive interconnect layer.

[0065] With the above configuration, the first contact hole exposes the substrate located below, thereby exposing the first ion implantation region disposed on the substrate surface. The first ion implantation region is formed before the first epitaxial layer and is used to achieve precise and optimized doping of the substrate.

[0066] The second contact hole only penetrates the second epitaxial layer, exposing the top of the first epitaxial layer located between the substrate and the second epitaxial layer. At this point, the second ion implantation region disposed on the surface of the first epitaxial layer is exposed, and the second ion implantation region can achieve precise and optimized doping of the first epitaxial layer. Furthermore, by connecting the first ion implantation region and the second ion implantation region through a conductive interconnect layer, electrical conductivity between the substrate and the first epitaxial layer can be achieved.

[0067] In this way, by separating the sidewall and bottom regions of the DSV cell into two independent ohmic contact systems, it is possible to achieve partitioned processing of the bottom doping and sidewall doping of a single DSV cell. This allows for precise optimization based on the doping requirements of different regions, i.e., selecting the most suitable ion implantation conditions for the first and second ion implantation regions respectively to achieve optimal overall performance. This solves the problem of high contact resistance caused by the difficulty in simultaneously optimizing the contact interface of the sidewall and bottom of deep trench contact holes in existing technologies.

[0068] The contents of this application will now be described in detail with reference to the accompanying drawings, so that those skilled in the art can have a clearer and more detailed understanding of the contents of this application.

[0069] Figure 1 This is a schematic flowchart illustrating a method for forming a semiconductor structure according to an embodiment of this application. Figure 2 This is a cross-sectional schematic diagram of a semiconductor structure obtained by the semiconductor structure formation method provided in the embodiments of this application. Figure 3 This is a cross-sectional schematic diagram of another semiconductor structure obtained by the semiconductor structure formation method provided in the embodiments of this application. Figures 4-12 for Figure 2 The provided semiconductor structure is illustrated in schematic diagrams at different stages of its formation process. Figures 13-17 for Figure 3 The provided semiconductor structure is illustrated in schematic diagrams at different stages of its formation process.

[0070] Reference Figure 1 As shown in the figure, this application provides a method for forming a semiconductor structure 10, the method comprising:

[0071] S100, Provide a substrate and form a first ion implantation region on the surface of the substrate.

[0072] Reference Figure 4 and Figure 5 As shown, the first ion implantation region 110 can be formed on the surface of the substrate 100 by ion implantation. Furthermore, the first ion implantation region 110 can precisely dope the substrate 100. The provided substrate 100 can be a SiC substrate.

[0073] For example, the substrate 100 can be an N-type substrate, and nitrogen ions, phosphorus ions, or arsenic ions can be implanted into the surface of the N-type substrate to form a first ion implantation region 110 (N-type). Alternatively, aluminum ions (or boron ions or gallium ions) can be implanted into the surface of the N-type substrate to form a first ion implantation region 110 (N-type).

[0074] The substrate 100 can also be a P-type substrate, and aluminum ions (or boron ions or gallium ions) can be implanted into the surface of the P-type substrate to form a first ion implantation region 110 (P-type). Alternatively, nitrogen ions, phosphorus ions or arsenic ions can be implanted into the surface of the P-type substrate to form a first ion implantation region 110 (N-type).

[0075] S200: A first epitaxial layer is formed on a substrate, and a second ion implantation region is formed on the surface of the first epitaxial layer. The conductivity type of the second ion implantation region is opposite to that of the first ion implantation region.

[0076] It should be noted that the conductivity types of the substrate 100 and the first epitaxial layer 200 can be the same or opposite, and can be designed according to requirements.

[0077] Reference Figure 6 As shown, at this time, the semiconductor structure 10 includes a substrate 100 and a first epitaxial layer 200 formed on top of the substrate 100. The first epitaxial layer 200 can be grown on the surface of the substrate 100 by chemical vapor deposition (CVD) process.

[0078] Furthermore, one of the substrate 100 and the first epitaxial layer 200 is hole-conducting and the other is electron-conducting. For example, the substrate 100 can be an N-type substrate (conductivity type is electron-conducting) and the first epitaxial layer 200 can be a P-type epitaxial layer (conductivity type is hole-conducting).

[0079] Alternatively, the substrate 100 can be a P-type substrate (with hole conductivity), and the first epitaxial layer 200 can be an N-type epitaxial layer.

[0080] Alternatively, both the substrate 100 and the first epitaxial layer 200 can be N-type substrates (conductivity type is electron conductivity) or both can be P-type substrates (conductivity type is hole conductivity), without making specific limitations here.

[0081] Based on this, refer to Figure 7 As shown, a second ion implantation region 210 with the opposite conductivity type to the first ion implantation region 110 can be formed on the surface of the first epitaxial layer 200 by ion implantation. The second ion implantation region 210 can precisely dope the first epitaxial layer 200.

[0082] For example, when the substrate 100 can be an N-type substrate, the first epitaxial layer 200 can be a P-type epitaxial layer, and aluminum ions (or boron ions or gallium ions) can be implanted into the surface of the first epitaxial layer 200 to form a second ion implantation region 210 (P-type).

[0083] The substrate 100 can also be a P-type substrate, and the first epitaxial layer 200 is an N-type epitaxial layer. Nitrogen ions (or phosphorus ions or arsenic ions) can be implanted into the surface of the first epitaxial layer 200 to form a second ion implantation region 210 (N-type).

[0084] S300, A second epitaxial layer is formed on the first epitaxial layer.

[0085] It is understandable that the conductivity types of the first epitaxial layer 200 and the second epitaxial layer 300 can be the same or opposite.

[0086] Reference Figure 8 As shown, the second epitaxial layer 300 can also be formed on the surface of the first epitaxial layer 200 by chemical vapor deposition (CVD). In this case, the first epitaxial layer 200 and the second epitaxial layer 300 have the same conductivity type.

[0087] It should be noted that, regardless of... Figure 2 During the formation of the provided semiconductor structure 10, it is still in Figure 3 The above steps are common process steps in the formation of the provided semiconductor structure 10.

[0088] S400, Form a second contact hole and make the second contact hole penetrate the second epitaxial layer along the stacking direction of the second epitaxial layer to expose the second ion implantation region.

[0089] Understandably, the second contact hole 420 allows the second ion implantation region 210 to be exposed outward, which is beneficial for achieving subsequent ohmic contact.

[0090] And, in step S500, a first contact hole is formed, which penetrates the second epitaxial layer and the first epitaxial layer along the stacking direction of the second epitaxial layer to expose the first ion implantation region.

[0091] The first contact hole 410 allows the first ion implantation region 110 to be exposed outward. At this time, both the first ion implantation region 110 on the substrate 100 and the second ion implantation region 210 on the first epitaxial layer 200 are partially exposed outward, which is beneficial to achieve communication between the first ion implantation region 110 and the second ion implantation region 210.

[0092] S600. A conductive interconnect layer is formed. The conductive interconnect layer is located at the first contact hole and the second contact hole, and is connected to the first ion implantation region and the second ion implantation region, so that the substrate and the first epitaxial layer are electrically connected through the conductive interconnect layer.

[0093] The conductive interconnect layer 500 can be filled in the first contact hole 410 and the second contact hole 420, and is connected to the first ion implantation region 110 and the second ion implantation region 210.

[0094] The conductive interconnect layer 500 can be a metal layer, or other semiconductor layer that can achieve electrical conduction, or an ion-implanted semiconductor layer, and there is no limitation on it here.

[0095] By setting the conductive interconnect layer 500, electrical conduction between the substrate 100 and the first epitaxial layer 200 can be achieved, and support can also be provided for complex three-dimensional DSV holes.

[0096] It is understandable that by introducing the first ion implantation region 110 on the substrate 100 and the second ion implantation region 210 on the first epitaxial layer 200 using the method described above, high-concentration doping can be achieved on the SiC material. Furthermore, the first ion implantation region 110 and the second ion implantation region 210 can be used to achieve precise optimized doping of the corresponding regions, so that the contact resistance of both regions is optimized to the lowest level.

[0097] In this way, the sidewall (P+ region) and bottom (N+ region) of the originally separate DSV tank can be physically separated, and the first ion implantation region 110 is exposed through the first contact hole 410 and the second ion implantation region 210 is exposed through the second contact hole 420, forming two independent ohmic contact systems.

[0098] Furthermore, since the most suitable ion implantation conditions can be selected for the first ion implantation region 110 and the second ion implantation region 210 respectively during their formation, optimal overall performance can be achieved. This solves the problem of high contact resistance caused by the difficulty in simultaneously optimizing the contact interface of the sidewalls and bottom of deep trench contact holes in the prior art.

[0099] In one implementation, step S400, forming a second contact hole and extending the second contact hole through the second epitaxial layer along the stacking direction of the second epitaxial layer to expose the second ion implantation region, may include:

[0100] S411. Deposit silicon dioxide on the second epitaxial layer and form a mask layer on the silicon dioxide by photolithography to define the positions of the first contact hole and the second contact hole.

[0101] Reference Figure 9As shown, the semiconductor structure 10 at this time includes a substrate 100, a first epitaxial layer 200, a second epitaxial layer 300, and a plurality of mask layers 700 connected to the top of the second epitaxial layer 300.

[0102] In this way, the positions of the first contact hole 410 and the second contact hole 420 can be defined by setting the mask layer 700, thereby enabling selective area processing to locally etch the first epitaxial layer 200 and the second epitaxial layer 300, preparing for the subsequent fabrication of the first contact hole 410 and the second contact hole 420.

[0103] S412. Etch the second epitaxial layer and form a second contact hole. The second contact hole penetrates the second epitaxial layer and exposes the second ion implantation region.

[0104] Reference Figure 10 As shown, at this time, at least two slots are provided on the second epitaxial layer 300. The size of the at least two slots can be the same as the size of the second contact hole 420. In this case, the second ion implantation region 210 on the first epitaxial layer 200 corresponding to the at least two slots can be exposed.

[0105] Thus, at least one slot can be used as a second contact hole 420 for subsequent use. It should be noted that the etching process can be dry etching, for example, inductively coupled plasma (ICP) etching and ion beam etching (IBE), and there is no limitation on it here.

[0106] Based on this, as one implementation method, a first contact hole is formed, which penetrates the second epitaxial layer and the first epitaxial layer along the stacking direction of the second epitaxial layer to expose the first ion implantation region, including:

[0107] S511. Define the region corresponding to the first contact hole through the photoresist layer, and continue to etch the region corresponding to the first contact hole to form the first contact hole; the first contact hole exposes the first ion implantation region on the substrate.

[0108] Reference Figure 11 As shown, the photoresist layer 800 covers a portion of the surface of the mask layer 700. The uncovered portion corresponds to the area of ​​the first contact hole 410, facilitating processing of this area. At this point, the first epitaxial layer 200 is etched downwards until the first ion implantation region 110 is exposed, resulting in the first contact hole 410. The first contact hole 410 penetrates the first epitaxial layer 200 and the second epitaxial layer 300, and exposes the first ion implantation region 110.

[0109] In this way, through the gradual formation of the second contact hole 420 and the first contact hole 410, the first ion implantation region 110 and the second ion implantation region 210 can be exposed to the outside, thereby facilitating the subsequent conductive connection layer 500 to connect the substrate 100 and the first epitaxial layer 200.

[0110] As one implementation method, in order to make the semiconductor structure formation method applicable to the manufacturing process of gallium nitride devices, i.e., corresponding to... Figure 3 The method for forming the semiconductor structure 10 shown may further include, prior to forming the second contact hole:

[0111] The internal doped impurities of the first epitaxial layer are activated by a high-temperature annealing process.

[0112] In this way, high-temperature annealing can generate controllable charge carriers within the first epitaxial layer 200, allowing it to behave as a P-type or N-type semiconductor. Furthermore, it can reduce the resistivity of the first epitaxial layer 200, meeting conductivity requirements. This avoids the thermal decomposition of gallium nitride material that occurs when high-temperature annealing activates doping within the first epitaxial layer 200 during the formation of a thick gallium nitride epitaxial layer, thus preventing impacts on semiconductor device performance.

[0113] Based on this, after activating the internal doping impurities of the first epitaxial layer and before forming the second contact hole, the formation method may further include:

[0114] A gallium nitride epitaxial layer is formed on top of the second epitaxial layer.

[0115] For example, a gallium nitride epitaxial layer 600 can be grown on the second epitaxial layer 300 using a chemical vapor deposition (CVD) process.

[0116] At this time, as Figure 13 As shown, the semiconductor structure 10 includes a substrate 100, a first epitaxial layer 200, a second epitaxial layer 300, and a gallium nitride epitaxial layer 600 stacked together. It is understood that this allows for the epitaxial layer of GaN required for GaN devices to be grown on a SiC substrate after implantation and high-temperature activation, without affecting the performance of the GaN material.

[0117] Based on this, in step S400, a second contact hole is formed, and the second contact hole extends through the second epitaxial layer along the stacking direction of the second epitaxial layer to expose the second ion implantation region. This may include:

[0118] S421. Deposit silicon dioxide on the gallium nitride epitaxial layer and form a mask layer on the silicon dioxide by photolithography etching to define the positions of the first contact hole and the second contact hole.

[0119] Reference Figure 14As shown, the semiconductor structure 10 at this time includes a substrate 100, a first epitaxial layer 200, a second epitaxial layer 300, a gallium nitride epitaxial layer 600, and a plurality of mask layers 700 connected to the top of the gallium nitride epitaxial layer 600. Similar to S411, the mask layers 700 can be used to achieve selective region processing, which will not be described in detail here.

[0120] S422, Etch gallium nitride epitaxial layer and second epitaxial layer to form second contact hole, the second contact hole penetrates gallium nitride epitaxial layer and second epitaxial layer and exposes second ion implantation region.

[0121] Reference Figure 15 As shown, at least two vias can penetrate the gallium nitride epitaxial layer 600 and the second epitaxial layer 300 to expose the second ion implantation region 210. The dimensions of these at least two vias can be the same as the dimensions of the second contact hole 420. Thus, at least one via can be used as the second contact hole 420 for subsequent applications.

[0122] As an optional implementation, forming a first contact hole that penetrates the second epitaxial layer and the first epitaxial layer along the stacking direction of the second epitaxial layer to expose the first ion implantation region may include:

[0123] S521. Define the region corresponding to the first contact hole through the photoresist layer, continue etching the region corresponding to the first contact hole to form the first contact hole, and expose the first ion implantation region on the substrate.

[0124] Reference Figure 16 As shown, the photoresist layer 800 covers a portion of the surface of the mask layer 700. The uncovered portion corresponds to the area of ​​the first contact hole 410, facilitating processing of that area.

[0125] At this point, the first epitaxial layer 200 is etched downwards until the first ion implantation region 110 is exposed, forming the first contact hole 410. The first contact hole 410 can penetrate the gallium nitride epitaxial layer 600, the second epitaxial layer 300, and the first epitaxial layer 200.

[0126] As one implementation, the method for forming the semiconductor structure 10 before forming the conductive interconnect layer may further include:

[0127] S610, remove the photoresist layer 800 and the mask layer 700 to obtain a first contact hole 410 and a second contact hole 420 exposed with different ion implantation regions.

[0128] Reference Figure 12 and Figure 17 As shown, the mask layer 700 has been removed at this point, providing space for the subsequent deposition of the conductive interconnect layer 500.

[0129] In some embodiments, forming the conductive interconnect layer 500 in S600 may include:

[0130] S620: Through nickel silicide process, the doped ions in the first ion implantation region and the second ion implantation region are activated by stepwise annealing in two annealing processes.

[0131] The first annealing process precedes the second annealing process, and the first annealing temperature in the first annealing process is lower than the second annealing temperature in the second annealing process.

[0132] For example, the first annealing temperature can be 650 degrees Celsius, and the second annealing temperature can be 1000 degrees Celsius. The first annealing time of the first annealing process can be set to 300 seconds, and the second annealing time of the second annealing process can be set to 180 seconds.

[0133] This configuration allows for optimized interface reactions through processes such as step-by-step annealing and rapid annealing, and creates low-resistance ohmic contacts in both the first ion implantation region 110 and the second ion implantation region 210. Simultaneously, it minimizes potential thermal damage.

[0134] S630, deposit an adhesion layer on the activated first ion implantation region and second ion implantation region, and fill the first contact hole and the second contact hole with a conductive interconnect layer 500.

[0135] For example, the adhesion layer can be either a titanium (Ti) layer or a titanium nitride (TiN) layer. This can enhance the interfacial adhesion between the conductive interconnect layer 500 and the first ion implantation region 110 and the second ion implantation region 210.

[0136] The conductive interconnect layer 500 can be a metal layer, such as a tungsten metal layer. Through the provision of the conductive interconnect layer 500, the substrate 100 and the first epitaxial layer 200 (P+EPI) thereon can be connected. The semiconductor structure 10 finally obtained by the above method can be referred to... Figure 2 or Figure 3 As shown.

[0137] It should be noted that the semiconductor structure 10 formation method provided in this application embodiment can be used as a general design method for deep trench contact structures. Furthermore, it can be extended to DSV trenches of different sizes and various silicon carbide polymorphs (such as 4H-SiC and 6H-SiC).

[0138] This application also provides a semiconductor structure. (Refer to...) Figure 2As shown, this application provides a semiconductor structure 10, which includes a substrate 100, a first epitaxial layer 200, and a second epitaxial layer 300. A first ion implantation region 110 is formed on the surface of the substrate 100. The first ion implantation region 110 can precisely dope the substrate 100. The substrate 100 may be a silicon carbide substrate.

[0139] A first epitaxial layer 200 is formed on top of the substrate 100, and a second ion implantation region 210 is formed on the surface of the first epitaxial layer 200. The second ion implantation region 210 has the opposite conductivity type to the first ion implantation region 110. The second ion implantation region 210 can precisely dope the first epitaxial layer 200.

[0140] The second epitaxial layer 300 is formed on top of the first epitaxial layer 200, and the substrate 100, the first epitaxial layer 200 and the second epitaxial layer 300 are stacked.

[0141] It should be noted that the conductivity type of the substrate 100, the first epitaxial layer 200, and the second epitaxial layer 300 can be selected according to design requirements, as long as the conductivity type of the second ion implantation region 210 is opposite to that of the first ion implantation region 110. No specific limitation is made here.

[0142] In some embodiments, the conductivity type of the first epitaxial layer 200 is the same as that of the second epitaxial layer 300, and the conductivity types of the first epitaxial layer 200 and the second epitaxial layer 300 are opposite to the conductivity type of the substrate 100.

[0143] For example, the substrate 100 can be an electron-conducting substrate, i.e., the substrate 100 is an N-type substrate. In this case, the first epitaxial layer 200 and the second epitaxial layer 300 are hole-conducting substrates, and both the first epitaxial layer 200 and the second epitaxial layer 300 are P-type epitaxial layers (P+EPI).

[0144] The substrate 100 can also be hole-conducting, meaning it is a P-type substrate. In this case, the first epitaxial layer 200 and the second epitaxial layer 300 are electron-conducting, and both the first epitaxial layer 200 and the second epitaxial layer 300 are N-type epitaxial layers (N+EPI).

[0145] It is understandable that the growth of the first epitaxial layer 200 on the surface of the substrate 100 and the second epitaxial layer 300 on the surface of the first epitaxial layer 200 can be achieved by chemical vapor deposition (CVD) process.

[0146] Based on this, the semiconductor structure 10 also includes a first contact hole 410, a second contact hole 420, and a conductive interconnect layer 500.

[0147] The first contact hole 410 penetrates both the second epitaxial layer 300 and the first epitaxial layer 200 sequentially along the stacking direction of the second epitaxial layer 300 to expose the first ion implantation region 110. The second contact hole 420 penetrates the second epitaxial layer 300 along the stacking direction of the second epitaxial layer 300 to expose the second ion implantation region 210. A conductive interconnect layer 500 is located at the first contact hole 410 and the second contact hole 420, and the conductive interconnect layer 500 is connected to both the first ion implantation region 110 and the second ion implantation region 210.

[0148] At this time, the first ion implantation region 110, which is doped with a corresponding high concentration in the substrate 100, and the second ion implantation region 210, which is doped with a corresponding high concentration in the first epitaxial layer 200, can be electrically connected through the conductive interconnect layer 500, thereby forming an ohmic contact and realizing electrical conduction between the substrate 100 and the first epitaxial layer 200.

[0149] It is understood that the conductive interconnect layer 500 can be a metal layer, or other semiconductor layer capable of electrical conduction, or an ion-implanted semiconductor layer; no limitation is made here. Furthermore, the conductive interconnect layer 500 fills the first contact hole 410 and the second contact hole 420, providing a supporting foundation for the subsequent formation of the semiconductor structure 10.

[0150] With the above configuration, the first contact hole 410 exposes the substrate 100 located in the lower layer to the outside, thereby exposing the first ion implantation region 110 disposed on the surface of the substrate 100. The first ion implantation region 110 can be formed before the first epitaxial layer 200 and is used to achieve precise optimized doping of the substrate 100.

[0151] The second contact hole 420 only penetrates the second epitaxial layer 300, allowing the top of the first epitaxial layer 200 located between the substrate 100 and the second epitaxial layer 300 to be exposed outwards. At this time, the second ion implantation region 210 disposed on the surface of the first epitaxial layer 200 is exposed, and the second ion implantation region 210 can achieve precise and optimized doping of the first epitaxial layer 200. Furthermore, by connecting the first ion implantation region 110 and the second ion implantation region 210 through the conductive interconnect layer 500, electrical conductivity between the substrate 100 and the first epitaxial layer 200 can be achieved.

[0152] This allows for partitioning the bottom and sidewall doping of the DSV, thus separating the sidewall and bottom regions of the DSV cell into two independent ohmic contact systems. This enables precise optimization for the doping requirements of different regions, allowing for the selection of the most suitable ion implantation conditions for the first ion implantation region 110 and the second ion implantation region 210 to achieve optimal overall performance. This solves the problem of high contact resistance caused by the difficulty in simultaneously optimizing the contact interfaces of the sidewalls and bottom of deep trench contact holes in existing technologies.

[0153] It should be noted that the implantation parameters of the first ion implantation region 110 and the second ion implantation region 210 can be further selected according to specific design needs, and are not limited here. The implantation parameters include, but are not limited to, the type of implanted element (such as P-type implanted element or N-type implanted element), implantation energy, implantation dose, and implantation method.

[0154] Reference Figure 3 As shown, the semiconductor structure 10 may further include a gallium nitride epitaxial layer 600, which is formed on top of the second epitaxial layer 300. The gallium nitride epitaxial layer 600, the second epitaxial layer 300, the first epitaxial layer 200, and the substrate 100 are stacked.

[0155] Furthermore, the first contact hole 410 sequentially passes through the gallium nitride epitaxial layer 600, the second epitaxial layer 300, and the first epitaxial layer 200 along the stacking direction of the gallium nitride epitaxial layer 600, thereby exposing the first ion implantation region 110. Similarly, the second contact hole 420 sequentially passes through the gallium nitride epitaxial layer 600 and the second epitaxial layer 300 along the stacking direction of the gallium nitride epitaxial layer 600, thereby exposing the second ion implantation region 210. The two can be connected via a conductive interconnect layer 500.

[0156] This setup enables synergistic performance of SiC and GaN materials. By using SiC as a support for the growth of gallium nitride (GaN) epitaxial layers, the disadvantage of the difficulty in fabricating GaN substrates can be overcome. At the same time, the wide bandgap and high electron mobility of GaN can be maximized, providing a foundation for the fabrication of high-performance GaN semiconductor devices.

[0157] It should be noted that different GaN devices require different GaN epitaxial structures, which are not discussed here. Figure 3 The GaN epitaxial layer in the diagram is only used to illustrate the positional relationship between the GaN epitaxial structure required for GaN devices and the first contact hole 410, the second contact hole 420, and the second epitaxial layer 300, and does not reflect the actual arrangement structure and shape of the gallium nitride epitaxial layer 600.

[0158] In some embodiments, the first epitaxial layer 200 can be activated by a high-temperature annealing process to dopant impurities, thereby obtaining controllable charge carriers and making the first epitaxial layer 200 behave as a P-type semiconductor or an N-type semiconductor. Furthermore, the resistivity of the first epitaxial layer 200 is reduced to meet conductivity requirements.

[0159] For example, the annealing temperature in the high-temperature annealing process can be set to 1820 degrees and the annealing time can be set to 15 minutes to effectively activate the internal doped impurities in the first epitaxial layer 200.

[0160] Based on this, the second epitaxial layer 300 can be formed on top of the first epitaxial layer 200 after activating internal doping impurities using a vapor deposition process. Furthermore, the gallium nitride epitaxial layer 600 can be formed on top of the second epitaxial layer 300 using a vapor deposition process. This results in a stacked structure of substrate 100, first epitaxial layer 200, second epitaxial layer 300, and gallium nitride epitaxial layer 600.

[0161] Understandably, when fabricating gallium nitride (GaN) devices, GaN material exhibits a tendency to decompose at high temperatures. Neither silicon-based GaN nor SiC-based GaN can utilize high-temperature annealing processes exceeding 1600 degrees Celsius to activate the doped ions in SiC material during GaN device fabrication.

[0162] With the above settings, since the activation of the doped impurities inside the first epitaxial layer 200 precedes the formation of the GaN epitaxial layer, the stability of the GaN epitaxial layer can be avoided when activating the doped impurities in the first epitaxial layer 200. This is beneficial for achieving ohmic contact between different Epi layers and DSV in the manufacturing process environment of GaN devices.

[0163] In one embodiment, in the first ion implantation region 110 and the second ion implantation region 210, the implanted ion in one is a nitrogen ion ( The other implanted ion is aluminum ion ( ).

[0164] For example, when the substrate 100 is an N-type substrate, and the first epitaxial layer 200 and the second epitaxial layer 300 are P-type epitaxial layers (P+EPI), that is, the conductivity type of the substrate 100 is electronic conductivity, and the conductivity type of the first epitaxial layer 200 and the second epitaxial layer 300 is hole conductivity, the ions implanted in the first ion implantation region 110 are nitrogen ions, and the ions implanted in the second ion implantation region 210 are aluminum ions.

[0165] Alternatively, when the substrate 100 is a P-type substrate, and the first epitaxial layer 200 and the second epitaxial layer 300 are both N-type epitaxial layers (N+EPI), that is, when the conductivity type of the substrate 100 is hole conductivity and the conductivity type of the first epitaxial layer 200 and the second epitaxial layer 300 is electron conductivity, the ions implanted in the first ion implantation region 110 are aluminum ions, and the ions implanted in the second ion implantation region 210 are nitrogen ions.

[0166] In this way, the corresponding doped ions can be precisely selected according to the conductivity type of the first ion implantation region 110 and the second ion implantation region 210, so as to reduce the resistivity of ohmic contact.

[0167] It should be noted that in other embodiments, phosphorus ions (P-ions) can also be used. ) or arsenic ions ( ) Replace nitrogen ions ( Alternatively, use boron ions (). ) or gallium ions ( ) to replace aluminum ions ( ).

[0168] The following explanation will be based on the example of substrate 100 being an N-type substrate, the first epitaxial layer 200 and the second epitaxial layer 300 being P-type epitaxial layers (P+EPI), the first ion implantation region 110 implanting nitrogen ions, and the second ion implantation region 210 implanting aluminum ions.

[0169] In some embodiments, the first ion implantation region 110 may be formed on the surface of the substrate 100 by multiple ion implantation processes.

[0170] Alternatively, the second ion implantation region 210 can be formed on the surface of the first epitaxial layer 200 through multiple ion implantation processes.

[0171] Alternatively, while the first ion implantation region 110 is formed on the surface of the substrate 100 through multiple ion implantation processes, the second ion implantation region 210 can be formed on the surface of the first epitaxial layer 200 through multiple ion implantation processes.

[0172] Multiple ion implantations can achieve ion implantation at various energy doses. This means that the same or different types of donor / acceptor impurities are implanted multiple times in the first ion implantation region 110, the second ion implantation region 210, or both. Furthermore, different implantation energies and doses are used for each implantation. Additionally, multi-angle ion implantation can also be employed. In this embodiment, vertical implantation can be used to implant the entire surface of the substrate 100.

[0173] In this way, multiple ion implantation processes can be used to achieve step-by-step stacking and on-demand plasticity, thereby achieving precise doping of ion distribution.

[0174] The following explanation uses the example of a first ion implantation region 110 being formed on the surface of a substrate 100 through multiple ion implantation processes, while a second ion implantation region 210 is formed on the surface of a first epitaxial layer 200 through multiple ion implantation processes.

[0175] For example, both the first ion implantation region 110 and the second ion implantation region 210 can be formed by a three-stage ion implantation process.

[0176] The initial nitrogen ion implantation dose into the first ion implantation region 110 can be 5E14cm. -2 The injected energy is 130keV.

[0177] The implantation dose of nitrogen ions for the second implantation into the first ion implantation region 110 can be 6E14cm. -2 The injected energy is 80keV.

[0178] The third nitrogen ion implantation dose into the first ion implantation region 110 can be 4E14cm. -2 The injected energy is 50keV.

[0179] Furthermore, the implantation dose of aluminum ions first implanted into the second ion implantation region 210 is 1.5E15cm. -2 The injected energy is 150keV.

[0180] The implantation dose of aluminum ions for the second implantation into the second ion implantation region 210 can be 1E15cm. -2 The injected energy is 60keV.

[0181] The implantation dose of aluminum ions for the third implantation into the second ion implantation region 210 can be 1E15cm. -2 The injected energy is 40keV.

[0182] In this way, high-energy injection can be used for deep layers, low-energy injection for shallow layers, and different doses can be used to control the concentration at each depth, thus achieving precise doping of ion distribution.

[0183] In one implementation, ions in the first ion implantation region 110 and the second ion implantation region 210 can be activated by stepwise annealing in two annealing processes using a nickel silicide process.

[0184] The first annealing process precedes the second annealing process, and the first annealing temperature in the first annealing process is lower than the second annealing temperature in the second annealing process.

[0185] For example, the first annealing temperature can be 650 degrees and the second annealing temperature can be 1000 degrees.

[0186] Based on this, the first annealing time of the first annealing process can be set to 300 seconds, and the second annealing time of the second annealing process can be set to 180 seconds.

[0187] In this way, interface reaction optimization can be achieved through processes such as stepwise annealing and rapid annealing, and low-resistance ohmic contacts can be formed in both the first ion implantation region 110 and the second ion implantation region 210. At the same time, potential thermal damage can be minimized.

[0188] In one embodiment, multiple first contact holes 410 may be provided, and the multiple first contact holes 410 may be spaced apart along the thickness direction perpendicular to the substrate 100.

[0189] Alternatively, multiple second contact holes 420 may be provided, with the multiple second contact holes 420 spaced apart along the thickness direction perpendicular to the substrate 100.

[0190] Alternatively, multiple first contact holes 410 and multiple second contact holes 420 may be provided, with the multiple first contact holes 410 and multiple second contact holes 420 being spaced apart along the thickness direction perpendicular to the substrate 100.

[0191] It is understandable that when there are multiple first contact holes 410 and multiple second contact holes 420, multiple parallel contact resistors can be formed, thereby making the overall contact resistance of the semiconductor structure 10 smaller and its performance better.

[0192] For example, the conductive interconnect layer 500 can be a metal layer. Specifically, the conductive interconnect layer 500 can be a tungsten metal layer. A high-purity, low-resistivity tungsten metal layer can be formed by chemical vapor deposition (CVD) or atomic layer deposition (ALD).

[0193] Because metals have high carrier concentration and good mobility, their resistivity is much lower than that of alternative materials such as semiconductors or conductive polymers, which can significantly reduce the Joule heat loss of the conductive interconnect layer 500.

[0194] In some embodiments, an adhesion layer may be deposited between the first ion implantation region 110 and the conductive interconnect layer 500. Figure 1 (Not shown in the image). Alternatively, an adhesion layer may be deposited between the second ion implantation region 210 and the conductive interconnect layer 500.

[0195] In other embodiments, the adhesion layer may be deposited between the first ion implantation region 110 and the conductive interconnect layer 500, and between the second ion implantation region 210 and the conductive interconnect layer 500.

[0196] Understandably, the adhesion layer enhances the interfacial bonding between the conductive interconnect layer 500 and the first ion implantation region 110 and the second ion implantation region 210, thereby strengthening the structural stability of the connection.

[0197] For example, the adhesion layer includes at least one of a titanium layer and a titanium nitride layer.

[0198] For example, the adhesion layer may include a titanium layer, in which case the titanium layer can serve as a metal silicide forming layer, reducing ohmic contact resistance, repairing surface damage in the ion implantation region, and improving doping activation rate.

[0199] Alternatively, the adhesion layer may include a titanium nitride layer, which can act as a diffusion barrier layer to suppress interdiffusion between metal atoms and dopant atoms. Furthermore, it can enhance the corrosion resistance and electromigration resistance of the conductive interconnect layer 500.

[0200] Alternatively, the adhesion layer can comprise both a titanium layer and a titanium nitride layer. In this case, the adhesion layer can achieve functional synergy between the titanium and titanium nitride layers, improving issues such as atomic diffusion, interface delamination, and process incompatibility, while also reducing contact resistance. This, in turn, enhances the electrical performance and reliability of the device.

[0201] Understandably, the use of the above-mentioned composite metal system is beneficial for simultaneously optimizing the interfacial reaction of P-type SiC and N-type SiC, thereby forming low-resistance ohmic contacts on both sides.

[0202] This application also provides a semiconductor device including the semiconductor structure 10 described above. This semiconductor device has the same technical solution and effects as the semiconductor structure 10 described above, and will not be elaborated upon here.

[0203] For example, semiconductor devices may include power devices such as silicon carbide metal-oxide-semiconductor field-effect transistors (SiCMOSFETs), silicon carbide junction field-effect transistors (JFETs), silicon carbide Schottky barrier diodes (SBDs), and silicon carbide PIN diodes. Semiconductor devices may also include gallium nitride (GaN) devices, without limiting their specific types.

[0204] The semiconductor structure formation method and semiconductor structure provided in this application have the following technical effects:

[0205] (1) Significantly reduce and equalize contact resistance. By forming a first ion implantation region and a second ion implantation region and customizing the ion implantation doping scheme, the contact resistance of both regions can be optimized to the lowest level, avoiding performance shortcomings and significantly reducing the overall on-resistance.

[0206] (2) The process is robust and widely applicable. Since this scheme adopts independent optimization of the partition, it can maintain good process effect for DSV tanks with different aspect ratios and different sizes. Therefore, it is not necessary to redevelop a complex injection process for each new tank type, which greatly enhances the feasibility of mass production.

[0207] (3) It can be adapted to complex three-dimensional structures. By multi-energy and multi-angle injection and conformal doping, the problem of sidewall doping uniformity can be solved, providing a general solution for high aspect ratio SiC devices.

[0208] Figure 18 This is a schematic cross-sectional view of a deep trench contact hole in a semiconductor structure.

[0209] Reference Figure 18 As shown, the applicant has... Figure 18 After DSV N+ was injected under the injection conditions, experimental data showed that the resistance of a single N-Sub circular hole DSV was about 50 ohms.

[0210] Since the P+ implantation of P+ Epi has only achieved overall vertical implantation (the actual effective implantation concentration on the side is lower due to the implantation angle), the DSV resistance of a single circular hole of P+ Epi on the side is about E4~E5 level. This result indicates that a certain degree of ohmic contact has been achieved on the surface.

[0211] Therefore, it can be inferred that if the DSV is etched to the P+ Epi layer and P+ is injected into the entire bottom region of the DSV, the bottom P+ injection concentration will be much greater than the concentration on the side in the current experiment, and the connection between the P+ Epi layer and the DSV will achieve a better ohmic contact.

[0212] It should be noted that the embodiments referred to in the specification, such as "one embodiment," "embodiment," "exemplary embodiment," and "some embodiments," may include specific features, structures, or characteristics, but not every embodiment necessarily includes that specific feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Moreover, when a specific feature, structure, or characteristic is described in connection with an embodiment, implementing such a feature, structure, or characteristic in conjunction with other embodiments, whether explicitly described or not, is within the knowledge scope of those skilled in the art.

[0213] Generally speaking, terms should be understood at least in part by their use in context. For example, at least in part by context, the term "one or more" as used in the text can be used to describe any feature, structure, or characteristic of the singular meaning, or a combination of features, structures, or characteristics of the plural meaning. Similarly, at least in part by context, terms such as "one" can be understood to convey either singular or plural usage.

[0214] It should be readily understood that the terms “on,” “above,” and “on top of” in this application should be interpreted in the broadest possible sense, such that “on” means not only “directly on something” but also “on something” with an intermediate feature or layer therebetween, and that “above” or “on top of” means not only “on something” but also “on something” without an intermediate feature or layer therebetween (i.e., directly on something).

[0215] Furthermore, for ease of explanation, spatially relative terms such as "below," "below," "under," "above," and "above" may be used to describe the relationship of one element or feature relative to other elements or features as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation other than those shown in the figures. The device may have other orientations (rotated 90° or in other orientations), and the spatially relative descriptive terms used herein may be interpreted accordingly.

[0216] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A method of forming a semiconductor structure, characterized by, The method comprises: forming a substrate, and forming a first ion implantation region on a surface of the substrate; forming a first epitaxial layer on the substrate, and forming a second ion implantation region on a surface of the first epitaxial layer, the second ion implantation region being opposite in conductivity type to the first ion implantation region; forming a second epitaxial layer on the first epitaxial layer; forming a second contact hole, and making the second contact hole penetrate the second epitaxial layer in a stacking direction of the second epitaxial layer to expose the second ion implantation region, and forming a first contact hole, and making the first contact hole penetrate the second epitaxial layer and the first epitaxial layer in the stacking direction of the second epitaxial layer to expose the first ion implantation region; forming a conductive interconnection layer, the conductive interconnection layer being located in the first contact hole and the second contact hole, and being connected with the first ion implantation region and the second ion implantation region, so that the substrate and the first epitaxial layer are electrically connected through the conductive interconnection layer.

2. The method of forming a semiconductor structure of claim 1, wherein, Before forming the second contact hole, the forming method further comprises: activating internal doped impurities of the first epitaxial layer through a high-temperature annealing process.

3. The method of forming a semiconductor structure of claim 2, wherein, After activating the internal doped impurities of the first epitaxial layer, and before forming the second contact hole, the forming method further comprises: forming a gallium nitride epitaxial layer on top of the second epitaxial layer.

4. The method of forming a semiconductor structure of claim 1, wherein, The forming of the second contact hole, and making the second contact hole penetrate the second epitaxial layer in a stacking direction of the second epitaxial layer to expose the second ion implantation region, comprises: depositing silicon dioxide on the second epitaxial layer, and forming a mask layer on the silicon dioxide through photolithography etching to define positions of the first contact hole and the second contact hole; etching the second epitaxial layer, and forming the second contact hole penetrating the second epitaxial layer and exposing the second ion implantation region.

5. The method of forming a semiconductor structure of claim 4, wherein, The forming of the first contact hole, and making the first contact hole penetrate the second epitaxial layer and the first epitaxial layer in a stacking direction of the second epitaxial layer to expose the first ion implantation region, comprises: defining a corresponding region of the first contact hole through a photoresist layer, and continuing etching on the corresponding region of the first contact hole to form the first contact hole, the first contact hole exposing the first ion implantation region on the substrate.

6. The method of forming a semiconductor structure of claim 3, wherein, The forming of the second contact hole, and making the second contact hole penetrate the second epitaxial layer in a stacking direction of the second epitaxial layer to expose the second ion implantation region, comprises: depositing silicon dioxide on the gallium nitride epitaxial layer, and forming a mask layer on the silicon dioxide through photolithography etching to define positions of the first contact hole and the second contact hole; etching the gallium nitride epitaxial layer and the second epitaxial layer, and forming the second contact hole penetrating the gallium nitride epitaxial layer and the second epitaxial layer and exposing the second ion implantation region.

7. The method of forming a semiconductor structure of claim 6, wherein, The forming of the first contact hole, and making the first contact hole penetrate the second epitaxial layer and the first epitaxial layer in a stacking direction of the second epitaxial layer to expose the first ion implantation region, comprises: The first contact hole corresponding region is defined by a photoresist layer, and the first contact hole corresponding region is etched to form the first contact hole and expose the first ion implantation region on the substrate.

8. The method of forming a semiconductor structure of claim 1, wherein, The forming of the conductive interconnection layer comprises: The dopant ions in the first ion implantation region and the second ion implantation region are activated by a nickel silicide process in two annealing processes; the first annealing process is prior to the second annealing process, and a first annealing temperature in the first annealing process is less than a second annealing temperature in the second annealing process; An adhesion layer is deposited on the activated first ion implantation region and the second ion implantation region, and a conductive interconnection layer is filled in the first contact hole and the second contact hole.

9. A semiconductor structure, characterized by Comprise: a substrate, a surface of the substrate is formed with a first ion implantation region; a first epitaxial layer, the first epitaxial layer is formed on top of the substrate; and a surface of the first epitaxial layer is formed with a second ion implantation region; a conductive type of the second ion implantation region is opposite to a conductive type of the first ion implantation region; a second epitaxial layer, the second epitaxial layer is formed on top of the first epitaxial layer; a first contact hole, the first contact hole penetrates the second epitaxial layer and the first epitaxial layer in sequence along a stacking direction of the second epitaxial layer to expose the first ion implantation region; a second contact hole, the second contact hole penetrates the second epitaxial layer to expose the second ion implantation region; a conductive interconnection layer, the conductive interconnection layer is located in the first contact hole and the second contact hole, and is connected with the first ion implantation region and the second ion implantation region, so that the substrate and the first epitaxial layer are electrically connected through the conductive interconnection layer.

10. The semiconductor structure of claim 9, wherein, Further comprise: a gallium nitride epitaxial layer, the gallium nitride epitaxial layer is formed on top of the second epitaxial layer; and the first contact hole penetrates the gallium nitride epitaxial layer, the second epitaxial layer and the first epitaxial layer in sequence along a stacking direction of the gallium nitride epitaxial layer; and the second contact hole penetrates the gallium nitride epitaxial layer and the second epitaxial layer in sequence along the stacking direction of the gallium nitride epitaxial layer.

11. The semiconductor structure of claim 10, wherein, The first epitaxial layer activates internal doping impurities through a high-temperature annealing process; The second epitaxial layer is formed on top of the first epitaxial layer after activating internal doping impurities through a vapor deposition process; The gallium nitride epitaxial layer is formed on top of the second epitaxial layer through a vapor deposition process.

12. The semiconductor structure of any of claims 9-11, wherein, The first ion implantation region is formed on the surface of the substrate through a multiple ion implantation process, and / or The second ion implantation region is formed on the surface of the first epitaxial layer through a multiple ion implantation process.

13. The semiconductor structure of any of claims 9-11, wherein the semiconductor structure is a semiconductor-on-insulator structure. The first contact hole is provided with a plurality of first contact holes, and the plurality of first contact holes are arranged along a direction perpendicular to the thickness of the substrate; or The second contact hole is provided with a plurality of second contact holes, and the plurality of second contact holes are arranged along a direction perpendicular to the thickness of the substrate; or The first contact hole and the second contact hole are each provided with a plurality of first contact holes and a plurality of second contact holes, and the plurality of first contact holes and the plurality of second contact holes are arranged along a direction perpendicular to the thickness of the substrate.

14. The semiconductor structure of any of claims 9-11, wherein the semiconductor structure is a semiconductor-on-insulator structure. An adhesion layer is deposited between the first ion implantation region and the conductive interconnect layer and / or between the second ion implantation region and the conductive interconnect layer.

15. The semiconductor structure of claim 14, wherein, The adhesion layer includes at least one of a titanium layer and a titanium nitride layer.

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