Board-level chip packaging method and structure based on large-size glass-based carrier plate

Abstract

The invention discloses a board-level chip packaging method based on a large-size glass-based carrier plate. The method comprises the following steps: preparing a glass-based carrier plate with upper and lower alignment target spot patterns; coating photolysis bonding glue to form a temporary bonding layer, and bonding the chip with the bonding pad facing upwards to form a temporary bonding body; forming a plastic package layer through plastic package, and preparing plated-through holes penetrating through the plastic package layer based on target spot pattern positioning; the carrier plate and the temporary bonding layer are removed through ultraviolet de-bonding, packaging is completed through solder ball planting and radiator back pasting, and the problems that in the existing packaging technology, thermal expansion coefficients are not matched, alignment is difficult, and the process is tedious are solved.

Description

Technical Field

[0001] This invention relates to the field of chip packaging, and more particularly to a chip packaging structure and packaging method using a glass substrate. Background Technology

[0002] In existing technologies, the fabrication process of chip packaging structures typically involves determining the bonding method based on the orientation of the chip pads, then bonding the chip to be packaged to the surface of a carrier board using pyrolysis bonding adhesive; encapsulating the bonded chip to form a molding layer; positioning the chip pads and creating metallized holes; and preparing a redistribution layer after the chip pads are precisely aligned; removing the carrier board using a high-temperature pyrolysis bonding process; and finally, performing subsequent processing such as solder ball placement and back heat sink attachment on the separated chip to complete the entire packaging process.

[0003] However, this packaging process suffers from problems such as poor matching of the coefficient of thermal expansion (CTE) between the carrier and the chip, difficulty in aligning internal and external patterns and metallized holes, and a cumbersome processing flow. This is because commonly used carriers include silicon-based, metal-based, and organic substrate carriers. Metal-based and organic substrate carriers have significantly different CTEs from the silicon substrate of the chip, resulting in significant stress during subsequent processing, which can easily lead to product structural deformation and warping. While silicon-based carriers have the best CTE compatibility with the silicon substrate, limitations in processing technology and cost prevent them from meeting the industry's demand for large-size carriers (typically >400mm × 500mm, or even larger).

[0004] In traditional packaging processes, the orientation of the chip pads determines the two packaging processes: Face up and Face down. Both processes involve cumbersome alignment procedures. In the Face up packaging process, the chip pads are located on the side away from the carrier board. To achieve accurate alignment of the chip pads after packaging, it is necessary to first locate the pre-made alignment pattern on the carrier board, and then remove the molding compound at the alignment target position using techniques such as laser drilling and mechanical removal. Figure 15b-5 Taking conventional substrate processing as an example, this step alone requires multiple processes such as X-ray target drilling, laser drilling, and cleaning to remove drilling debris. The process is complex and the positioning accuracy is easily affected. In the face-down packaging process, the chip pads face the carrier board. To achieve pad alignment, the carrier board must first be removed through a high-temperature pyrolysis bonding process. Figure 16c-5 High-temperature cycling can easily cause thermal warping. Figure 6 , Figure 7 This further exacerbates the product warpage problem caused by CTE mismatch. In the face-down packaging process, after the carrier board is removed, the chip pads are exposed, requiring an additional secondary molding and layering protection process. Figure 16c-6This not only wastes expensive molding compound materials, but also requires multiple auxiliary processes such as chip pad cleaning, interface adhesive removal, injection molding or lamination molding; to match the product's heat dissipation performance, face-down packaging also requires thinning of the exposed molding compound on the back of the chip. Figure 16ac-1 This process not only further wastes molding materials, but also easily leads to quality risks such as delamination and cracking of various materials in the product, and micro-cracks caused by chip vibration, thus reducing the packaging yield.

[0005] It is evident that existing large-size board-level chip packaging technologies suffer from problems such as mismatch between the carrier board and the chip CTE, difficulty in alignment, and cumbersome processing procedures. These issues severely restrict the stability, reliability, and production efficiency of the packaging structure, and fail to meet the application requirements of advanced packaging fields for high precision, low cost, and high yield. Summary of the Invention

[0006] To address the shortcomings of existing technologies, the present invention provides a method and structure for temporary bonding and separation of chips at the board level on a large-size glass substrate. This method solves the problems of mismatch between the substrate and the chip CTE, difficulty in aligning internal and external patterns and metallized holes, and cumbersome processing procedures in the fabrication of existing board-level packaging structures.

[0007] In a first aspect, the present invention provides a board-level chip packaging method based on a large-size glass substrate, the method comprising the following steps: 1. Prepare a glass substrate; process the upper and lower surfaces of the glass substrate to form an upper alignment target pattern and a lower alignment target pattern; 2. A photolytic bonding adhesive is coated on the surface of the glass substrate to form a photolytic bonding adhesive layer. The photolytic bonding adhesive layer is then hot-pressed to form a temporary bonding layer. 3. Position the chip according to the above alignment target pattern, and attach the chip to be packaged with the pads facing up to the temporary bonding layer to form a temporary bond; 4. The temporary bond is encapsulated to obtain an encapsulation layer; 5. Drill holes on the upper surface of the molding compound to form interconnect holes and fill them with metal to form metallized holes. The metallized holes penetrate the molding compound and connect to the pads of the chip. 6. Based on the lower alignment target pattern, debond the temporary bonding layer from the reverse side of the glass substrate, remove the glass substrate and the temporary bonding layer, and obtain a semi-formed encapsulation structure; 7. Perform solder ball placement and back heat sink application on the semi-formed package structure to complete the packaging.

[0008] Optionally, the formation of the alignment target pattern includes the following sub-steps: S1. Sputter a seed layer onto the surface of the glass substrate; S2. Coat the surface of the seed layer with a layer of photoresist, and etch out multiple alignment target point pattern windows by exposure and development; S3. On the seed layer exposed in the alignment target pattern window, a copper layer is thickened by electroplating to form multiple metal alignment targets; S4. After removing the photoresist outside the metal alignment target points, the seed layer is etched, and multiple metal alignment target points form an upper alignment target pattern and a lower alignment target pattern.

[0009] Optionally, attaching the chip to be packaged to the glass substrate includes: providing a photodegradable bonding adhesive layer; attaching one side of the photodegradable bonding adhesive layer to the glass substrate; and attaching the chip to be packaged with its pads facing upwards to the other side of the photodegradable bonding adhesive layer. After spin-coating the photodegradable bonding adhesive onto the glass substrate, thermocompression bonding is performed by applying specific temperature, pressure, and time to form a temporary bonding layer.

[0010] Optionally, based on the alignment target pattern and the deviation calculated by the least squares method, the chip pad position is located, and a hole is made in the corresponding area of ​​the molding compound to create a metallized hole.

[0011] Optionally, the temporary bonding layer is rendered ineffective by ultraviolet light irradiation, and the glass substrate is separated from the chip to obtain a semi-formed package structure with the glass substrate removed. This includes: providing ultraviolet light of a specific wavelength and energy, scanning the entire panel area according to a preset scanning speed and grid scanning path, the ultraviolet light penetrating the transparent glass substrate to irradiate the temporary bonding layer, rendering the photodegradable bonding adhesive ineffective, removing the glass substrate, and obtaining the semi-formed package structure.

[0012] Secondly, the present invention provides a board-level chip semi-finished packaging structure based on a large-size glass substrate, the structure comprising: a glass substrate, a chip to be packaged, a molding compound, metallized vias, an upper alignment target pattern, and a lower alignment target pattern; the upper and lower alignment target patterns are respectively disposed on the upper and lower surfaces of the glass substrate, and the vertical center lines of the corresponding upper and lower alignment target patterns on the upper and lower surfaces coincide; a photodegradable bonding adhesive layer is located between the glass substrate and the chip to be packaged, and the chip to be packaged forms a temporary bond with the glass substrate through the photodegradable bonding adhesive layer; the molding compound is disposed in a manner that encapsulates the chip; the metallized via is embedded in the molding compound, and the metallized via penetrates the molding compound and is connected to the chip.

[0013] Optionally, the packaging structure further includes: the alignment target pattern is typically designed as any one or more combinations of a symmetrical cross, square, or circle; the upper and lower surfaces of the glass substrate are provided with alignment target patterns, and multiple target points are evenly distributed at the panel edge and inside.

[0014] Optionally, the glass substrate can be made of materials with high light transmittance, high chemical stability, and a coefficient of thermal expansion that is compatible with the chip, including borosilicate glass, fused silica glass, etc.

[0015] Optionally, the photolytic bonding adhesive can be a system with excellent thermal stability and chemical resistance, capable of withstanding subsequent high-temperature processes such as electroplating, and maintaining a high modulus at that temperature; it can resist the erosion of various process chemicals such as electroplating solutions, developing solutions, and etching solutions, without swelling or delamination; its glass transition temperature Tg > 200℃ and decomposition temperature > 250℃ can adapt to the thermal process requirements of the entire encapsulation process.

[0016] Compared with the prior art, the present invention has the following beneficial effects: In the packaging structure fabrication method of this embodiment, a glass substrate is used to provide mechanical support for the chip to be packaged. During the packaging process, the alignment target points pre-made on the glass substrate are identified by the back side. In the face-up packaging process, it is not necessary to remove the molding material at the alignment target position. In the face-down packaging process, compared with the packaging process in the prior art, there is no need for additional secondary chip molding layer protection and subsequent molding thinning process. This invention reduces the process steps and reduces the process difficulty. Moreover, the difference in thermal expansion coefficient between the glass substrate and the chip is small, which can reduce the problem of wafer warpage in subsequent processes. The photodebonding adhesive is debonded by ultraviolet light irradiation at room temperature or low temperature, avoiding the problem of thermal warpage caused by high temperature thermal cycling. In addition, the glass substrate has high flatness, excellent chemical and thermal stability, and is suitable for panel-level packaging, which can significantly improve the production efficiency per unit area and significantly reduce the packaging cost of a single chip. Attached Figure Description

[0017] Figure 1 The image shown is a side view of the chip to be packaged provided in this embodiment; Figure 2 The image shown is a top view of the chip to be packaged provided in this embodiment; Figure 3 The image shown is a rear view of the chip to be packaged provided in this embodiment; Figure 4 The diagram shown is a schematic of the finished board-level chip packaging structure provided in this embodiment; Figure 5 The diagram shown is a schematic diagram illustrating the matching state of the thermal expansion coefficients of the silicon-based substrate and the chip provided in this embodiment. Figure 6 The diagram shown is a schematic diagram of the structural deformation of the metal substrate and the chip provided in this embodiment due to the mismatch of their coefficients of thermal expansion. Figure 7 The diagram shown is a schematic of the structural deformation caused by the mismatch in the coefficients of thermal expansion between the organic substrate carrier and the chip provided in this embodiment. Figure 8 The diagram shown illustrates the structure of the large-size glass substrate and the alignment target points provided in this embodiment. Figure 9 The diagram shown is a structural schematic of the chip face-up packaging method provided in this embodiment; Figure 10 The diagram shown is a structural schematic of the chip face-down packaging method provided in this embodiment; Figure 11 The diagram shown is a schematic of the chip semi-package structure provided in this embodiment; Figure 12 The diagram shown is a schematic of the exposed and recessed chip back packaging structure provided in this embodiment; Figure 13 The diagram shown is a schematic of the chip semi-package structure provided in this embodiment. This structure is the state after removing the glass substrate and the temporary bonding layer. Figure 14 The diagram shown is a schematic of the recessed packaging structure with the back of the chip exposed in this embodiment. This structure is the state after the glass substrate and temporary bonding layer have been removed. Figure 15a-1 This is a schematic diagram of the glass substrate in the Face up packaging process of the chip of the present invention; Figure 15a-2 This is a schematic diagram of the glass substrate structure after coating with photodegradable bonding adhesive in the Face up packaging process of the chip of the present invention; Figure 15a-3 This is a schematic diagram of the structure in the Face up packaging process of the chip of the present invention, in which the chip is fixed to the glass substrate by a temporary bonding layer. Figure 15a-4 This is a schematic diagram of the structure of the temporary bond after plastic encapsulation in the Face up packaging process of the chip of the present invention; Figure 15a-5 This is a schematic diagram of the interconnect hole formation on the molding layer in the face-up packaging process of the chip of the present invention; Figures 15a-6 are schematic diagrams of the structure of forming metallized holes by filling metal into interconnect holes in the face up packaging process of the chip of the present invention. Figure 15ab-1 This is a schematic diagram of the semi-finished package structure obtained after removing the glass substrate and temporary bonding layer in the chip Face up packaging process of the present invention. Figure 15ab-2 This is a schematic diagram of the structure after solder balls are added to the semi-finished package structure in the Face up packaging process of the chip of the present invention. Figure 15ab-3 This is a schematic diagram of the structure of the chip Face up packaging process of the present invention, which is completed after the heat sink is attached to the back of the half-molded packaging structure. Figure 15b-1 This is a schematic diagram of the structure of a traditional carrier board in the traditional carrier board chip face-up packaging process. Figure 15b-2 A schematic diagram of a traditional carrier board structure after being coated with pyrolytic bonding adhesive in the traditional carrier board chip face-up packaging process. Figure 15b-3 This is a schematic diagram of the structure in the traditional carrier-based chip face-up packaging process, in which the chip is mounted onto the traditional carrier using pyrolysis of bonding adhesive. Figure 15b-4 This is a schematic diagram of the encapsulation structure after the bonding between the chip and the traditional carrier board is plastic-encapsulated in the traditional carrier board chip face-up packaging process. Figure 15b-5 This is a schematic diagram of the structure for removing the molding compound at the alignment target point in the traditional carrier chip face-up packaging process. Figure 15b-6 This is a schematic diagram of the structure for removing the molding compound at the chip pads in the traditional carrier-based chip face-up packaging process. Figure 15b-7 A schematic diagram of the traditional packaging structure after metallization holes are made in the traditional carrier chip face-up packaging process.

[0018] Figure 16c-1 This is a schematic diagram of the structure of a traditional carrier board in the traditional carrier board chip face-down packaging process. Figure 16c-2 A schematic diagram of the traditional carrier board structure after applying pyrolytic bonding adhesive in the traditional carrier board chip face-down packaging process. Figure 16c-3 This is a schematic diagram of the structure for bonding chips using a flip-chip method with the chip pads facing the carrier board in the traditional carrier board face-down packaging process. Figure 16c-4 This is a schematic diagram of the structure after the bonded chip and the traditional carrier board are encapsulated in the traditional carrier board face-down packaging process. Figure 16c-5 This is a schematic diagram of the structure of the traditional carrier board separated by a high-temperature pyrolysis process in the traditional carrier board chip face-down packaging process. Figure 16c-6 This is a schematic diagram of a structure in the traditional carrier-based chip face-down packaging process where a plastic encapsulation layer is applied to the chip so that the chip pads face upwards. Figure 16c-7 This is a schematic diagram of the structure in which the molding compound is made into the corresponding area of ​​the chip pad in the traditional carrier chip face-down packaging process. Figure 16c-8A schematic diagram of the traditional packaging structure after metallization hole structure is fabricated in the traditional carrier chip face-down packaging process. Figure 16ac-1 This is a schematic diagram of the semi-finished package structure obtained by traditional carrier board packaging in the traditional carrier board chip face-down packaging process. Figure 16ac-2 This is a schematic diagram of the structure after solder balls are added to the semi-finished package structure in the traditional carrier chip face-down packaging process. Figure 16ac-3 This is a schematic diagram of the structure of a semi-finished package structure after a heat sink is attached to the back of the traditional carrier chip face-down packaging process. Figure 17a-1 This is a schematic diagram of the glass substrate in the process of fabricating the alignment target pattern of the present invention. Figure 17a-2 This is a schematic diagram of the structure after sputtering a seed layer on the surface of a glass substrate during the target pattern fabrication process of this invention. Figure 17a-3 This is a schematic diagram of the structure after photoresist is coated on the surface of the seed layer in the process of fabricating the alignment target pattern of the present invention. Figure 17a-4 This is a schematic diagram of the structure after the alignment target pattern window is etched by exposure and development in the alignment target pattern fabrication process of the present invention. Figure 17a-5 This is a schematic diagram of the structure after the metal alignment target is formed in the target pattern window during the alignment target pattern fabrication process of the present invention. Figure 17a-6 This is a schematic diagram of the structure after removing photoresist other than the metal alignment target during the alignment target pattern fabrication process of the present invention. Figure 17a-7 This is a schematic diagram of the glass substrate structure used to form the upper and lower alignment target patterns in the alignment target pattern fabrication process of this invention. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. All other embodiments obtained by those skilled in the art based on the embodiments in this application without creative effort are within the scope of protection of the present invention.

[0020] In a first aspect, the present invention provides a board-level chip packaging method and structure based on a large-size glass substrate, specifically including the following embodiments: Example

[0021] Figures 1 to 3The images shown are a side view, a top view, and a back view of a single chip 3 to be packaged. The side where the chip pad 31 is located is the front side, and the side away from the chip pad 31 is the back side.

[0022] Figure 4 This is a longitudinal cross-sectional view of the packaging structure in a specific embodiment of the present invention. The packaging structure includes solder balls 8, a molding compound 4, and a chip 3 covered by the molding compound 4, which are stacked sequentially from bottom to top. The molding compound 4 has embedded metallized holes 6, which vertically penetrate the molding compound 4 and connect to the chip 3. A heat sink 9 is attached to the back of the chip.

[0023] Figure 5 The figure shows that the coefficient of thermal expansion (CTE) of the silicon substrate is comparable to that of the chip, and the two have excellent matching thermal expansion characteristics, which can effectively reduce thermal stress during the packaging process.

[0024] Figure 6 The image shows thermal warping caused by a mismatch in the coefficient of thermal expansion (CTE) between the metal substrate and the chip.

[0025] Figure 7 The image shows thermal warping caused by a mismatch in the coefficient of thermal expansion (CTE) between the organic substrate and the chip.

[0026] Figure 8 The upper alignment target pattern 10 is an alignment target pattern on a large-size glass substrate in a specific embodiment of the present invention.

[0027] In a preferred embodiment, a plurality of upper alignment target patterns 10 are evenly distributed on the edge of the glass substrate 1. The alignment target patterns 10 are typically designed as any one or more combinations of symmetrical crosses, squares, or circles.

[0028] Figure 9 The image shows a face-up package structure with the chip pads facing upwards.

[0029] The photodegradable bonding adhesive layer 2 is located between the glass substrate 1 and the chip to be packaged 3. The chip to be packaged 3 forms a temporary bond with the glass substrate 1 through the photodegradable bonding adhesive layer 2. The chip pads 31 face upward and are located on the side away from the temporary bonding layer 222.

[0030] Figure 10 The diagram shows a face-down packaging structure with the chip pads facing the carrier board (this invention uses a face-down mounting method to achieve chip pads facing upwards for bonding, which is different from the traditional flip-chip process).

[0031] The pyrolytic bonding layer 22 is located between the carrier 21 and the chip 3 to be packaged. The chip 3 to be packaged forms a temporary bond with the carrier 21 through the pyrolytic bonding layer 22. The chip pads 31 face downward and are attached to one side of the temporary bonding layer 223.

[0032] like Figures 11 to 14 The diagram shows the chip semi-package structure and the recessed package structure, including: 1. Glass substrate, 3. Chip to be packaged, 4. Molding layer, and 6. Metallized vias; One side surface of the glass substrate 1 is closely attached to the side of the chip 3 to be packaged that is away from its pad 31; a portion of the chip 3 to be packaged is covered by a molding compound 4; the metallized hole 6 is disposed in the molding compound 4; the metallized hole 6 is used for electrical connection with the chip 3.

[0033] In this embodiment, Figure 11 and Figure 12 The encapsulation structure further includes a photodegradable bonding adhesive layer 2, which is disposed between the glass substrate 1 and the chip to be encapsulated 3. A temporary bonding layer 222 is formed by a hot-press bonding process to achieve a detachable fixed connection between the chip to be encapsulated 3 and the glass substrate 1.

[0034] Figure 11 The image shows the chip's semi-encapsulated structure without the glass substrate 1 removed. Figure 13 This is the semi-packaged chip structure after the glass substrate 1 and the photodebonding adhesive layer 2 have been removed by ultraviolet photodebonding. Figure 12 The image shows a chip recessed packaging structure with the glass substrate 1 still in place and the back of the chip 3 to be packaged embedded in a pre-set recessed structure of the glass substrate 1. Figure 14 The image shows the chip recessed packaging structure with the back of the chip to be packaged exposed after the glass substrate 1 and the photodebonding adhesive layer 2 are removed by ultraviolet light debonding. This exposed design can meet the heat dissipation requirements of high-power devices.

[0035] It should be noted that glass substrates can be processed to create uneven structures through various methods, exposing the back of the chip and improving heat dissipation. Processing methods include laser processing and wet etching. Laser processing uses ultrashort pulse lasers (such as picosecond and femtosecond lasers) to first scan the glass interior according to the desired structural shape, modifying the scanned area to make it more susceptible to acid corrosion. The entire glass is then immersed in an etching solution such as hydrofluoric acid, where the modified areas are rapidly etched away, forming the uneven structure. Wet etching uses an acid-resistant mask (such as metal or photoresist) to cover the glass surface. The pattern to be grooved is transferred onto the mask using photolithography. The glass is then immersed in a hydrofluoric acid or buffer oxide etching solution, where the unmasked portions are etched away, forming the uneven structure.

[0036] Figure 15 is a flowchart illustrating a board-level chip packaging method based on a large-size glass substrate according to an embodiment of the present invention; as shown in Figure 15, the board-level chip packaging method based on a large-size glass substrate specifically includes the following steps: Step S1, provide a glass substrate 1, such as Figure 15a-1 As shown, the materials for large-size glass substrates can be borosilicate glass or fused silica, etc. Step S2 involves processing the glass substrate 1 to form an upper alignment target pattern 10 and a lower alignment target pattern 11, as shown in Figure 17. The specific fabrication steps include: S01, providing a glass substrate 1, such as Figure 17a-1 As shown, the upper and lower surfaces of the glass substrate 1 are processed to sputter a seed layer 12, as follows. Figure 17a-2 As shown.

[0037] S02, a layer of photoresist 13 is coated on the surface of the seed layer 12, such as Figure 17a-3 As shown, multiple alignment target point graphic windows 14 are etched through exposure and development, as follows. Figure 17a-4 As shown; S03, on the seed layer 12 exposed in the alignment target pattern window 14, a copper layer is thickened by electroplating to form multiple metal alignment target points 15, such as... Figure 17a-5 As shown; S04, remove the photoresist 13 outside the metal alignment target 15, such as Figure 17a-6 As shown; then, the seed layer 12 is etched, and multiple metal alignment target points 15 form an upper alignment target pattern 10 and a lower alignment target pattern 11, as shown. Figure 17a-7 As shown.

[0038] In a preferred embodiment, the upper and lower surfaces of the glass substrate 1 are provided with alignment target patterns, which can be evenly distributed on the edge and inside of the panel. The number of upper alignment target patterns 10 and lower alignment target patterns 11 on the upper and lower surfaces is more than 8. The vertical center lines of the upper alignment target patterns 10 and lower alignment target patterns 11 on the upper and lower surfaces coincide. The positional deviation of each upper alignment target pattern 10 and lower alignment target pattern 11 on the upper and lower surfaces is measured in real time, and the positional deviation of the front and back target points is calculated and calibrated by the least squares method. The three upper alignment target patterns 10 on the front and the three lower alignment target patterns 11 on the back with the smallest error are selected to form a set of alignment target patterns.

[0039] Preferably, when the glass is thick or the alignment accuracy requirement is extremely high, a double-sided alignment vision system can be used to simultaneously identify the alignment target pattern on both the front and back sides, and can measure and compensate for visual position deviations caused by glass thickness and refractive index in real time; the alignment target pattern is usually designed as any one or more combinations of symmetrical cross, square or circle, which facilitates the software to calculate the center point and is suitable for the camera resolution. It should be noted that in the fabrication of the target pattern, an opaque metal film needs to be deposited and patterned. By selecting a metal system with strong adhesion, such as chromium, a chromium-copper composite seed layer is formed to solve the problem of weak direct adhesion between copper and glass and easy detachment. In the design of the target pattern, sharp corners are avoided to reduce stress concentration, optimize the adhesion between metal and glass, and prevent the target from falling off.

[0040] Step S3: A photolytic bonding adhesive is coated on the surface of the glass substrate 1 to form a photolytic bonding adhesive layer 2, such as... Figure 15a-2 As shown. The chip 3 to be packaged is pasted with its pads facing upwards onto the upper surface of the photopolymer bonding adhesive 2. The other side of the photopolymer bonding adhesive 2 is already pasted onto the glass substrate 1. The photopolymer bonding adhesive layer 2 is then thermo-pressed to form a temporary bonding layer 222, as shown. Figure 15a-3 As shown; Preferably, in this embodiment, the glass transition temperature (Tg) of the photolytic bonding adhesive 2 is 220°C, the decomposition temperature is 300°C, the bonding temperature is set to 250°C, and the maximum temperature of subsequent processes does not exceed 280°C.

[0041] Preferably, the formation of the temporary bonding layer (222) in this embodiment includes: spin coating of photolytic bonding adhesive, pre-curing of photolytic bonding adhesive, and hot-press bonding. First, a four-stage spin coating process is used to spin coat the photolytic bonding adhesive, with spin coating parameters of 800 rpm / 15s, 2000 rpm / 40s, 3000 rpm / 60s, and 1000 rpm / 20s. The viscosity of the photolytic bonding adhesive at 25°C is 2000-4000 mPa·s, and the uniformity of the adhesive layer thickness is ≤±3μm. Second, the pre-curing is divided into two stages. In the first stage, the colloidal solvent is evaporated at 80°C for 60-90s. In the second stage, the adhesive is cured at 120°C for 90-120s to remove residual solvent and initiate the cross-linking reaction of the adhesive, raising the viscosity to above 100,000 mPa·s before placing the chip. Finally, the carrier board is aligned with the chip and a contact pressure of 0.05-0.1 MPa is applied. When the temperature is rapidly increased to the bonding temperature of 250°C, the bonding pressure is simultaneously applied to 0.5 MPa for thermo-press bonding.

[0042] Preferably, in this embodiment, after coating the photodegradable bonding adhesive, the adhesive layer of the three selected upper alignment target point patterns (10) areas is removed by laser ablation according to a preset path. A 355nm ultraviolet laser is selected, with a pulse width of 10-30ns, a repetition frequency of 20-100kHz, a single pulse energy of 10-50μJ, and a scanning speed of 100-500mm / s. Scanning and ablation are performed according to the preset path, using a multi-circle scanning or filling scanning mode, with a scan line overlap rate of 20-50% and a pulse point overlap rate of 50-80%. The preset path is set to be a square or circle slightly larger than the target point pattern.

[0043] Step S4: Position the chip 3 to be packaged with the pads 31 facing upwards according to the upper alignment target pattern 10, and attach it to the temporary bonding layer 222 through the temporary bonding layer 222 to form a temporary bond; Figure 15a-3 As shown; Step S5: The temporary bond is encapsulated to prepare encapsulation layer 4, as shown below. Figure 15a-4 As shown; Step S6: Based on the alignment target patterns 10 and 11, locate the chip pad 31, perform opening processing on the molding compound 4 to form interconnect holes 5 and fill them with metal, creating metallized holes 6, so that the chip pad 31 is not covered by the molding compound 4. Figure 15a-5 As shown in Figures 15a-6; In a preferred embodiment, the formation of the metallized hole 6 includes the following steps: based on the light transmittance of the glass substrate 1, the pre-made upper alignment target pattern 10 and lower alignment target pattern 11 on the glass substrate can be directly identified through the back side. Combined with the translation amount (Tx, Ty) and rotation amount (θ) calculated by the least squares method, the positioning deviation caused by glass refraction is calibrated to locate the position of the chip pad 31 and determine the target area on the molding compound 4 to be formed of the interconnect hole 5; laser drilling is performed on the area on the molding compound 4 to be formed of the interconnect hole 5 to form an interconnect hole 5 that penetrates the molding compound 4 to the surface of the chip pad 31; a seed layer is deposited and a copper filler is electroplated on the hole wall of the interconnect hole 5 to form a metallized hole 6 that can be connected to the chip pad 31.

[0044] Step S7: Based on the lower alignment target pattern 11, debond the temporary bonding layer 222 from the reverse side of the glass substrate 1, remove the glass substrate 1 and the temporary bonding layer 222, and obtain the following... Figure 15ab-1 The semi-molded packaging structure 7 shown; In a preferred embodiment, when debonding the temporary bonding layer 222, an ultraviolet laser with a wavelength of 355nm is used, with an energy density of 200mJ / cm², a scanning speed of 100mm / s, and a pulse frequency of 40kHz. After irradiating the entire panel area according to a preset grid path, the polymer chains break, the molecular weight drops sharply, and the Tg and modulus decrease significantly. At this time, the material changes from a glassy or elastic state to a viscous flow state, and its viscosity drops rapidly to below 100mPa·s, thereby achieving debonding.

[0045] Step S8 involves applying solder balls 8 and attaching a heat sink 9 to the semi-formed package structure 7 to complete the packaging process. Figure 15ab-2 He Ru Figure 15ab-3 As shown.

[0046] Preferably, in the embodiment, a heat sink 9 is provided on the chip surface away from the chip pad 31, and solder balls 8 are processed on one side of the chip pad 31 so that the solder balls 8 form an electrical connection with the chip pad 31.

[0047] It should be noted that, Figures 15b-1 to 15b-7 The diagram shows a conventional face-up encapsulation process using a carrier substrate. Compared to the glass-based carrier substrate encapsulation solution of this invention, conventional carrier substrate encapsulation requires an additional step of removing the encapsulating material at the alignment target 110 position (e.g., Figure 15b-5 As shown in the figure, it is specifically achieved through multiple processes such as X-ray drilling, laser drilling, and cleaning to remove drilling debris. In addition, in the carrier separation process, traditional carriers require high-temperature thermal decomposition bonding process, while this invention utilizes the light transmittance of the glass-based carrier and the characteristics of the photodecomposition bonding adhesive to achieve low-temperature non-destructive decomposition bonding through ultraviolet light irradiation, without the need for high-temperature thermal cycling.

[0048] It should be noted that, Figures 16c-1 to 16c-8 The diagram shows a conventional face-down packaging method using a carrier substrate. Compared to the glass-based carrier substrate packaging solution of this invention, conventional carrier substrate packaging requires flip-chip bonding with the chip pads facing the carrier substrate (e.g., Figure 16c-3 (As shown); after molding, the carrier plate needs to be separated through a high-temperature pyrolysis process (e.g. Figure 16c-5 As shown), the chip is then encapsulated and layered to make the pads face upwards (as shown). Figure 16c-6 As shown), only after this can the molding compound be opened in the corresponding area of ​​the chip pad (e.g. Figure 16c-7 (as shown in the figure). This invention, through the upright mounting method with the chip pads facing upwards, combined with the back alignment technology of the glass substrate, can directly and precisely open holes on the molding layer without the need for additional molding layer addition and substrate pyrolysis separation process, which significantly simplifies the process flow.

[0049] like Figures 16ac-1 to 16ac-3As shown, the subsequent processing of the semi-molded package structure 7 is carried out in sequence: the solder balls 8 are placed on the upper surface of the semi-molded package structure 7, and the solder balls 8 form a reliable electrical connection with the metallized holes 6; the heat sink 9 is attached to the lower surface of the semi-molded package structure 7 (i.e. the chip surface away from the pads), thus completing the entire board-level chip packaging process.

[0050] Compared with the prior art, this embodiment has the following beneficial effects: 1. In the packaging structure fabrication method of this embodiment, a glass substrate is used to provide mechanical support for the chip to be packaged. During the packaging process, there is no need to remove the substrate through a high-temperature pyrolysis bonding process; the photodegradable bonding adhesive can be deactivated simply by ultraviolet light irradiation at room temperature or low temperature, achieving non-destructive separation of the substrate and the chip, effectively avoiding thermal stress caused by high-temperature thermal cycling. Furthermore, the difference in the coefficient of thermal expansion (CTE) between the glass substrate and the chip substrate material is significantly smaller than that of metal-based or organic substrates, which can significantly reduce the risk of wafer warpage due to CTE mismatch in subsequent processes. In addition, the glass substrate possesses… Outstanding performance advantages: Strong large-size machinability, easily achieving sizes >400mm×500mm, adapting to panel-level packaging requirements; Excellent mechanical strength, its high Young's modulus can provide stable mechanical support for ultra-thin wafers with a thickness <100µm, effectively preventing wafer deformation or breakage during the process; Excellent chemical and thermal stability, the chemical inertness of glass can resist the corrosion of various acids, alkalis and solvents in the packaging process, and its glass transition temperature (Tg) is usually >500℃, far higher than the packaging process temperature (usually <400℃), and will not soften or deform under high temperature environment, ensuring process reliability.

[0051] 2. The packaging structure fabrication method of this embodiment significantly optimizes the packaging process: In the face-up packaging scenario, the high light transmittance of the glass substrate allows for direct identification of the pre-made alignment target on the glass substrate through back-side alignment, eliminating the need for multiple processes such as laser drilling and mechanical removal to remove the molding compound at the alignment target position, as required by existing technologies, thus significantly simplifying the positioning process; In the face-down packaging scenario, the upright mounting method with the chip pads facing upwards eliminates the need for secondary molding layering and molding thinning processes after substrate removal compared to traditional flip-chip mounting, effectively reducing process steps and molding compound waste, while avoiding quality risks such as delamination and chip micro-cracks that may occur during the thinning process, ultimately achieving a simplified process and an effective reduction in packaging costs.

Claims

1. A board-level chip packaging method based on a large-size glass substrate, characterized in that, include: S1, Prepare the glass substrate (1). S2, the upper and lower surfaces of the glass substrate (1) are processed to form an upper alignment target pattern (10) and a lower alignment target pattern (11). S3, a photodegradable bonding adhesive is coated on the surface of the glass substrate (1) to form a photodegradable bonding adhesive layer (2), and the photodegradable bonding adhesive layer (2) is hot-pressed to form a temporary bonding layer (222). S4, according to the upper alignment target pattern (10), the chip (3) to be packaged with the pad (31) facing up is attached to the temporary bonding layer (222) through the temporary bonding layer (222) to form a temporary bonding body; S5, the temporary bond is encapsulated to prepare the encapsulation layer (4). S6, make holes on the upper surface of the molding compound (4) to form interconnect holes (5) and fill them with metal to form metallized holes (6). The metallized holes (6) penetrate the molding compound (4) and connect to the pads (31) of the chip (3). S7. Based on the lower alignment target pattern (11), the temporary bonding layer (222) is debonded from the opposite side of the glass substrate (1) to remove the glass substrate (1) and the temporary bonding layer (222) to obtain a semi-formed encapsulation structure (7). S8, the semi-formed packaging structure (7) is subjected to solder ball (8) and back heat sink (9) treatment to complete the packaging.

2. The board-level chip packaging method based on a large-size glass substrate according to claim 1, characterized in that, In step S2, the formation of the upper alignment target pattern (10) and the lower alignment target pattern (11) specifically includes the following steps: S01, a seed layer (12) is sputtered onto the surface of the glass substrate (1). S02, a layer of photoresist (13) is coated on the surface of the seed layer (12), and multiple alignment target point pattern windows (14) are etched by exposure and development. S03, on the seed layer (12) exposed in the alignment target pattern window (14), the copper layer is thickened by electroplating process to form multiple metal alignment targets (15). S04, after removing the photoresist (13) other than the metal alignment target (15), the seed layer (12) is etched, and multiple metal alignment target (15) form an upper alignment target pattern (10) and a lower alignment target pattern (11).

3. The board-level chip packaging method based on a large-size glass substrate according to claim 2, characterized in that, Upper alignment target pattern (10) and lower alignment target pattern (11) are simultaneously fabricated on the upper and lower surfaces of the glass substrate (1). The number of upper alignment target pattern (10) and lower alignment target pattern (11) on the upper and lower surfaces is more than 8. The vertical center lines of the upper alignment target pattern (10) and lower alignment target pattern (11) on the upper and lower surfaces coincide. The position deviation of the front and back target points is calculated and calibrated by the least squares method. The three upper alignment target patterns (10) on the front and the three lower alignment target patterns (11) on the back with the smallest error are selected to form a set of alignment target patterns.

4. The board-level chip packaging method based on a large-size glass substrate according to claim 3, characterized in that, The formation of the metallized hole (6) includes the following steps: determining the target area of ​​the interconnect hole (5) to be formed on the molding compound (4) according to the upper alignment target point pattern (10); performing laser drilling on the area of ​​the interconnect hole (5) to be formed on the molding compound (4) to form an interconnect hole (5) that penetrates the molding compound (4) to the surface of the chip pad (31); and sequentially depositing a seed layer and electroplating copper metal on the hole wall of the interconnect hole (5) to form a metallized hole (6) that can be connected to the chip pad (31).

5. The board-level chip packaging method based on a large-size glass substrate according to claim 1, characterized in that, In step S3, the glass transition temperature Tg of the photolytic bonding adhesive layer (2) is >200℃ and the decomposition temperature is >250℃, which can withstand a heat process of 200-250℃ for more than 1 hour; after contact in electroplating solution, developer, etching solution and adhesive remover, the bonding strength decreases by <10% and there is no swelling or delamination; the room temperature modulus is 1-3GPa and the modulus at 200℃ is >50MPa.

6. The board-level chip packaging method based on a large-size glass substrate according to claim 5, characterized in that, The formation of the temporary bonding layer (222) includes: spin-coating photodegradable bonding adhesive onto a glass substrate (1) with spin-coating parameters of 800 rpm / 15 s, 2000 rpm / 40 s, 3000 rpm / 60 s, and 1000 rpm / 20 s, respectively. The viscosity of the photodegradable bonding adhesive at 25°C is 2000-4000 mPa·s, and the uniformity of the adhesive layer thickness is ≤±3 μm. After evaporation and solvent removal at 80°C / 60-90 s and pre-curing at 120°C / 90-120 s, the chip to be packaged (3) is aligned with the glass substrate and a contact pressure of 0.05-0.1 MPa is applied. Then, a bonding temperature of Tg+20°C to Tg+40°C is applied and a bonding pressure of 0.2-0.6 MPa is applied simultaneously. Hot-press bonding is performed for 1 min to 60 min to form a temporary bonding layer (222).

7. The board-level chip packaging method based on a large-size glass substrate according to claim 3, characterized in that, After coating the photodegradable bonding adhesive, the adhesive layer of the three selected upper alignment target point patterns (10) areas is removed by laser ablation according to the preset path. A 355nm ultraviolet laser or a 515nm or 1030nm femtosecond laser is selected, with a pulse width of 10-30ns, a repetition frequency of 20-100kHz, a single pulse energy of 10-50μJ, and a scanning speed of 100-500mm / s. Scanning and ablation are performed according to the preset path, with a scan line overlap rate of 20-50% and a pulse point overlap rate of 50-80%. The preset path is set to a square or circle that is slightly larger than the target image.

8. The board-level chip packaging method based on a large-size glass substrate according to claim 6, characterized in that, The encapsulation body is subjected to the removal of the glass substrate (1) and the temporary bonding layer (222) to obtain a semi-formed encapsulation structure (7), including the following steps: selecting an ultraviolet laser with a wavelength of 300-365nm, setting the energy density to 100-500mJ / cm², the scanning speed to 100mm / s, and the pulse frequency to 40kHz, scanning the entire panel area according to the preset grid path, removing the glass substrate (1), and obtaining the semi-formed encapsulation structure (7) after removing the residual adhesive.

9. The board-level chip packaging method based on a large-size glass substrate according to claim 8, characterized in that, The semi-formed packaging structure (7) is processed by setting a heat sink (9) on the chip surface away from the chip pad (31) and performing solder ball (8) processing on one side of the chip pad (31).

10. A board-level chip semi-finished product packaging structure based on a large-size glass substrate, characterized in that, include: A glass substrate (1), a chip to be packaged (3), a molding compound (4), a metallized hole (6), an upper alignment target pattern (10), and a lower alignment target pattern (11) are provided on the upper and lower surfaces of the glass substrate (1), respectively, and the vertical center lines of the corresponding upper alignment target patterns (10) and lower alignment target patterns (11) on the upper and lower surfaces coincide. The photodegradable bonding adhesive layer (2) is located between the glass substrate (1) and the chip to be packaged (3), and the chip to be packaged (3) forms a temporary bond with the glass substrate (1) through the photodegradable bonding adhesive layer (2). The molding compound (4) is provided in a way that covers the chip (3). The metallized hole (6) is embedded in the molding compound (4), and the metallized hole (6) penetrates the molding compound (4) and is connected to the chip (3).

Images