Test circuit and test method for transmitting circuit of physical layer interface

Abstract

The invention relates to the technical field of integrated circuits and provides a test circuit and a test method for a sending circuit of a physical layer interface. The test circuit comprises a deserializer which is deployed in a sending simulation part of each of a plurality of data sending channels and is used for deserializing serial data output by the sending simulation part so as to obtain sending loopback data; and the comparators are deployed in the sending digital parts of the data sending channels and used for comparing the data to be transmitted with the sending loopback data so as to judge whether error codes exist or not, and then sending circuit testing is achieved. Therefore, not only can the module in the link loopback with the problem be quickly positioned, but also the test cost and the test time are saved.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a test circuit and test method for a transmitting circuit for a physical layer interface. Background Technology

[0002] Chip probing (CP) testing and final testing (FT) require external equipment to test the chip. For example, external loopback testing verifies the timing characteristics and functionality of the receiving chip used for communication. CP testing occurs before chip packaging, where probes are used to connect exposed pins on the die to test equipment, focusing on verifying voltage, current, timing, and functionality. After chip packaging, FT testing is performed to verify the packaging process quality, focusing on timing and functional verification. Current CP and FT testing technologies require connecting unpackaged pins or packaged ports on the chip to external test equipment via probes or wires to establish an external loopback test circuit. This external test equipment simulates communication between the receiving and transmitting chips, increasing testing costs. Furthermore, building a separate external loopback test circuit for each data transmission channel within the chip further increases testing costs and time. Furthermore, loopback testing requires the chip at the transmitting end under test to send test data in a random mode, such as pseudo-random binary sequence (PRBS) test data. Moreover, external test equipment must simulate the receiving end to test each data channel and clock channel together, checking each data channel one by one. This is not conducive to quickly locating the problem.

[0003] Therefore, this application provides a test circuit and test method for the transmission circuit of the physical layer interface, which can not only quickly locate the module in the link loopback where the problem occurs, but also save test costs and test time. Summary of the Invention

[0004] In a first aspect, this application provides a test circuit for a transmission circuit of a physical layer interface. The transmission circuit of the physical layer interface includes multiple data transmission channels and a clock transmission channel shared among the multiple data transmission channels. Each of the multiple data transmission channels includes a digital transmission section and a digital transmission section. The digital transmission section transmits data to be transmitted in parallel to the analog transmission section, and the analog transmission section performs a serial operation on the parallel data received from the digital transmission section to obtain serial data. The test circuit includes: a deserializer deployed in the analog transmission section of each of the multiple data transmission channels, used to deserialize the serial data output by the analog transmission section to obtain loopback data; and a comparator deployed in the digital transmission section of each of the multiple data transmission channels, used to compare the data to be transmitted and the loopback data to determine whether there are any bit errors, thereby enabling testing of the transmission circuits of each of the multiple data transmission channels.

[0005] Through the first aspect of this application, by deploying a comparator in the digital transmission section and a deserializer in the analog transmission section of each data transmission channel, each data transmission channel can internally complete a series of operations to extract serial data, deserialize the serial data to obtain the transmitted loopback data, and compare the data to be transmitted with the transmitted loopback data, thereby completing the transmitted loopback test. The transmitted loopback tests performed by each data transmission channel are independent of each other, so the execution order can be serial, parallel, or in any order, increasing the degree of testing flexibility. Because the original serial data is directly extracted from the serializer in the analog transmission section of each data transmission channel, it means that the constituent modules, working modes, and data transmission-related functions of each data transmission channel can be adapted. By combining any subsequent modules, the corresponding analog transmission section of the data transmission channel can be constructed, which helps to meet the transmission circuit testing requirements of various physical layer protocols and related physical layer interface standards. The deserializer of each data transmission channel can be set to be in a power-off state during normal data transmission, thus avoiding increased power consumption and the losses caused by introducing external test equipment, simplifying the testing complexity and improving the testing efficiency.

[0006] In one possible implementation of the first aspect of this application, the physical layer interface conforms to the physical layer interface standard defined by the processor interface protocol of the mobile communications industry.

[0007] In one possible implementation of the first aspect of this application, the physical layer interface belongs to a source-synchronous physical layer, which includes a high-speed module and a low-power module.

[0008] In one possible implementation of the first aspect of this application, the physical layer interface is used for a high-speed interface chip, and the high-speed interface chip is used for a mobile display screen.

[0009] In one possible implementation of the first aspect of this application, the serial operation performed by the transmission simulation portion of each of the plurality of data transmission channels is based on the clock signal output by the clock transmission channel, and the deserialization operation performed by the deserializer of the transmission simulation portion of each of the plurality of data transmission channels is based on the clock signal on which the serial operation performed by the corresponding transmission simulation portion depends.

[0010] In one possible implementation of the first aspect of this application, the transmission circuit tests of the plurality of data transmission channels are performed independently of each other, and the execution order of the transmission circuit tests of the plurality of data transmission channels is serial or parallel.

[0011] In one possible implementation of the first aspect of this application, the test circuit is used to construct the internal loopback circuit required for wafer testing and finished product testing of the chip where the physical layer interface is located.

[0012] In one possible implementation of the first aspect of this application, the deserializer of the analog transmission section and the comparator of the digital transmission section of each of the plurality of data transmission channels are configured to operate independently of each other among the plurality of data transmission channels, and when the first data transmission channel among the plurality of data transmission channels is operating normally, the deserializer of the analog transmission section and the comparator of the digital transmission section of the first data transmission channel are in a power-off state.

[0013] In one possible implementation of the first aspect of this application, the test circuit supports wafer testing and finished product testing of a single data transmission channel among the plurality of data transmission channels.

[0014] Secondly, this application provides a testing method for a transmission circuit of a physical layer interface. The transmission circuit of the physical layer interface includes multiple data transmission channels and a clock transmission channel shared among the multiple data transmission channels. Each of the multiple data transmission channels includes a digital transmission section and a digital transmission section. The digital transmission section is used to transmit data to be transmitted in parallel to the analog transmission section. The analog transmission section is used to perform a serial operation on the parallel data received from the digital transmission section to obtain serial data. The testing method includes: using a deserializer deployed in the analog transmission section of each of the multiple data transmission channels to deserialize the serial data output by the analog transmission section to obtain loopback data; and using a comparator deployed in the digital transmission section of each of the multiple data transmission channels to compare the data to be transmitted and the loopback data to determine whether there are any bit errors, thereby achieving testing of the transmission circuits of each of the multiple data transmission channels.

[0015] Through the second aspect of this application, by deploying a comparator in the digital transmission section and a deserializer in the analog transmission section of each data transmission channel, each data transmission channel can internally complete a series of operations to extract serial data, deserialize the serial data to obtain the transmitted loopback data, and compare the data to be transmitted with the transmitted loopback data, thereby completing the transmitted loopback test. The transmitted loopback tests performed by each data transmission channel are independent of each other, so the execution order can be serial, parallel, or in any order, increasing the degree of testing flexibility. Because the original serial data is directly extracted from the serializer in the analog transmission section of each data transmission channel, it means that the constituent modules, working modes, and data transmission-related functions of each data transmission channel can be adapted. By combining any subsequent modules, the corresponding analog transmission section of the data transmission channel can be constructed, which helps to meet the transmission circuit testing requirements of various physical layer protocols and related physical layer interface standards. The deserializer of each data transmission channel can be set to be in a power-off state during normal data transmission, thus avoiding increased power consumption and the losses caused by introducing external test equipment, simplifying the testing complexity and improving the testing efficiency. Attached Figure Description

[0016] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1A schematic diagram of a test circuit for a transmission circuit of a physical layer interface provided in an embodiment of this application; Figure 2 A flowchart illustrating a testing method for a transmission circuit of a physical layer interface provided in an embodiment of this application; Figure 3 This is a schematic diagram illustrating the execution order of testing the transmission circuits of multiple data transmission channels according to an embodiment of this application. Detailed Implementation

[0018] The embodiments of this application will now be described in further detail with reference to the accompanying drawings.

[0019] It should be understood that in the description of this application, "at least one" means one or more, and "multiple" means two or more. In addition, the words "first," "second," etc., unless otherwise stated, are used only for the purpose of distinguishing descriptions and should not be construed as indicating or implying relative importance or order.

[0020] Figure 1 This is a schematic diagram of a test circuit for a physical layer interface transmission circuit provided in an embodiment of this application. The physical layer interface transmission circuit includes multiple data transmission channels ( Figure 1 The example illustrates data transmission channels A110 and B120, as well as a clock transmission channel shared among the plurality of data transmission channels (data transmission channel A110 and data transmission channel B120). It should be understood that... Figure 1 The diagram only illustrates data transmission channels A110 and B120 as examples. The physical layer interface can include any number of data transmission channels. These multiple data transmission channels (data transmission channel A110 and data transmission channel B120) each include a digital transmission section and an analog transmission section (e.g., ...). Figure 1 As shown, data transmission channel A110 has a digital transmission section and a digital transmission section, as well as data transmission channel B120 has a digital transmission section and a digital transmission section. The digital transmission section transmits the data to be transmitted in parallel to the analog transmission section, and the analog transmission section performs serial operations on the parallel data received from the digital transmission section to obtain serial data. Thus, for each data transmission channel, which includes a digital transmission section and a digital transmission section, the conversion of digital signals into analog signals to be transmitted is realized. Figure 1For example, the digital transmission section of data transmission channel A110 transmits the data to be transmitted in parallel to the analog transmission section of data transmission channel A110. The analog transmission section of data transmission channel A110 performs serial operations on the parallel data received from the digital transmission section of data transmission channel A110 to obtain serial data. Similarly, the digital transmission section of data transmission channel B120 transmits the data to be transmitted in parallel to the analog transmission section of data transmission channel B120. The analog transmission section of data transmission channel B120 performs serial operations on the parallel data received from the digital transmission section of data transmission channel B120 to obtain serial data. Each data transmission channel independently and separately completes the parallel transmission of data and the serial operation on the parallel data.

[0021] Continue reading Figure 1 The test circuit includes: a deserializer deployed in the transmission analog section of each of the plurality of data transmission channels (data transmission channel A110 and data transmission channel B120), used to deserialize the serial data output by the transmission analog section to obtain transmission loopback data; and a comparator deployed in the transmission digital section of each of the plurality of data transmission channels (data transmission channel A110 and data transmission channel B120), used to compare the data to be transmitted and the transmission loopback data to determine whether there are bit errors, thereby realizing the transmission circuit test of each of the plurality of data transmission channels (data transmission channel A110 and data transmission channel B120). Here, the test circuit includes a deserializer A116 deployed in the transmission analog section of data transmission channel A110, used to deserialize the serial data output by the transmission analog section of data transmission channel A110 to obtain transmission loopback data. The test circuit also includes a comparator A118 deployed in the digital transmission section of data transmission channel A110, used to compare the data to be transmitted with the transmitted loopback data to determine whether there are bit errors, thereby realizing the transmission circuit test of data transmission channel A110. The test circuit also includes a deserializer B126 deployed in the analog transmission section of data transmission channel B120, used to deserialize the serial data output from the analog transmission section of data transmission channel B120 to obtain transmitted loopback data. The test circuit also includes a comparator B128 deployed in the digital transmission section of data transmission channel B120, used to compare the data to be transmitted with the transmitted loopback data to determine whether there are bit errors, thereby realizing the transmission circuit test of data transmission channel B120.

[0022] Continue reading Figure 1The digital transmission section of data transmission channel A110 includes a generation module A111, which provides data for normal transmission and test data required for testing. The test data can be generated using a pattern generator to have a certain random pattern, such as a pseudo-random binary sequence (PRBS). Transmission module A112 transmits the data to be transmitted in parallel to the analog transmission section of data transmission channel A110. The analog transmission section of data transmission channel A110 includes a serializer A113, which performs serialization on the parallel data to obtain serial data. The input of deserializer A116 in the analog transmission section of data transmission channel A110 is connected to the output of serializer A113, allowing deserialization of the serial data output by serializer A113 to obtain the transmitted loopback data. The digital transmission section of data transmission channel A110 includes a comparator A118. One input of comparator A118 is connected to generation module A111 to obtain the data to be transmitted, and the other input is connected to deserializer A116 to obtain the transmitted loopback data. Comparator A118 compares the data to be transmitted with the transmitted loopback data to determine whether there are any bit errors.

[0023] Continue reading Figure 1 The digital transmission section of data transmission channel B120 includes a generation module B121, which provides data for normal transmission and test data required for testing. The test data can be generated using a pattern generator to have a certain random pattern, such as a pseudo-random binary sequence. The transmission module B122 transmits the data to be transmitted in parallel to the analog transmission section of data transmission channel B120. The analog transmission section of data transmission channel B120 includes a serializer B123, which performs a serial operation on the parallel data to obtain serial data. The input of the deserializer B126 in the analog transmission section of data transmission channel B120 is connected to the output of the serializer B123, allowing the serial data output by the serializer B123 to be deserialized to obtain the transmitted loopback data. The digital transmission section of data transmission channel B120 includes a comparator B128. One input of comparator B128 is connected to the generation module B121 to obtain the data to be transmitted, and the other input is connected to the deserializer B126 to obtain the transmitted loopback data. Comparator B128 compares the data to be transmitted with the transmitted loopback data to determine whether there are any bit errors.

[0024] Continue reading Figure 1As can be seen, by deploying a comparator in the digital transmission section and a deserializer in the analog transmission section of each data transmission channel, each data transmission channel can internally perform a series of operations to complete the transmission loopback test, including extracting serial data, deserializing the serial data to obtain the transmission loopback data, and comparing the data to be transmitted with the transmission loopback data. Furthermore, the transmission loopback tests performed by each data transmission channel are independent of each other, so the execution order can be serial, parallel, or any other order. Because the original serial data is directly extracted from the serializer in the analog transmission section of each data transmission channel, the influence of subsequent modules does not need to be considered. Figure 1 The example illustrates that in the transmission simulation section of data transmission channel A110, a subsequent module A114 follows the serializer A113; similarly, in the transmission simulation section of data transmission channel B120, a subsequent module A124 follows the serializer B123. Here, depending on the differences in the constituent modules, operating modes, and data transmission-related functions of each data transmission channel, the subsequent module A114 of the transmission simulation section of data transmission channel A110 may differ from the subsequent module A124 of the transmission simulation section of data transmission channel B120, for example, there may be different data transmission rate requirements. Figure 1 The test circuit shown can be adapted to the constituent modules, operating modes, and data transmission-related functions of each data transmission channel. By combining it with any subsequent module, the transmission simulation part of the corresponding data transmission channel can be constructed, increasing the flexibility of testing. It can be seen that by embedding a data loopback module in each data transmission channel, the Built-in Self-Test (BIST) scheme can be completed relying solely on the data transmission channel itself, without requiring an external test environment or the participation of the receiving end. Furthermore, while completing the functional check of the transmission circuit, it can support CP testing and FT testing of a single data transmission channel, saving testing time and hardware costs.

[0025] Continue reading Figure 1 , Figure 1The test circuit shown for the physical layer interface's transmitting circuit can be extended to conform to the physical layer definition of the Mobile Industry Processor Interface (MIPI) protocol and the physical layer interface standard D-PHY. According to MIPI's definition, D-PHY includes a High-Speed ​​(HS) operating mode and a Low-Power (LP) operating mode, used in various embedded imaging devices, such as the connection between the image sensor and processor in smartphones, and the connection between a vehicle camera and a display module. The D-PHY defined by the MIPI protocol transmits high-resolution image quality through the HS operating mode and saves power through the LP mode, thus simultaneously including both high-speed and low-power modules, contributing to improved efficiency. It should be understood that besides the MIPI protocol, other physical layer protocols and related physical layer interface standards exist, specifying the components, operating modes, and data reception-related functions of the physical layer interface. Figure 1 The test circuit shown for the physical layer interface transmission circuit can be supplemented with HS and LP modules to provide HS and LP signals, thereby supporting the testing requirements of the MIPI protocol-related transmission circuits. Furthermore, in scenarios with multiple data transmission channels, each channel can have its own constituent modules, operating modes, and data transmission-related functions. Through their respective embedded data loopback modules, they can independently complete BIST testing, thus adapting to their respective testing needs. Additionally, each data transmission channel's deserializer can be configured to be powered down during normal data transmission, avoiding increased power consumption. This simplifies testing complexity and improves testing efficiency with almost no increase in power consumption or area. It also supports FT and CP testing for a single data channel without the need for an additional receiver, and each data channel can be independently and in parallel, greatly increasing testing flexibility. Furthermore, since the transmission circuit tests of each data transmission channel can be performed independently in any order, the problem of checking each data channel one by one due to the introduction of external test environments and receivers is avoided. This allows for quick location of the problem, such as identifying the module causing the problem in the link loopback, which helps save test costs and test time.

[0026] In short, Figure 1The test circuit shown for the physical layer interface transmit circuit deploys a comparator in the digital transmit section and a deserializer in the analog transmit section of each data transmit channel. This allows each data transmit channel to internally perform a series of operations: extracting serial data, deserializing the serial data to obtain the transmit loopback data, and comparing the data to be transmitted with the transmit loopback data, thus completing the transmit loopback test. The transmit loopback tests performed by each data transmit channel are independent of each other, therefore the execution order can be sequential, parallel, or arbitrary, increasing the testing flexibility. The raw serial data is extracted directly from the serializer of the transmission simulation section of each data transmission channel. This means that it can adapt to the constituent modules, operating modes, and data transmission-related functions of each data transmission channel. By combining any subsequent module, the transmission simulation section of the corresponding data transmission channel can be constructed, which helps to meet the transmission circuit testing requirements of various physical layer protocols and related physical layer interface standards. The deserializer of each data transmission channel can be set to be powered off during normal data transmission, which avoids increased power consumption and the loss caused by introducing external test equipment, simplifies the testing complexity, and improves the testing efficiency.

[0027] Figure 2 This is a flowchart illustrating a testing method for a transmission circuit of a physical layer interface, provided in an embodiment of this application. The transmission circuit of the physical layer interface includes multiple data transmission channels and a clock transmission channel shared among the multiple data transmission channels. Each of the multiple data transmission channels includes a digital transmission section and a digital transmission section. The digital transmission section is used to transmit data to be transmitted in parallel to the analog transmission section, and the analog transmission section is used to perform serial operations on the parallel data received from the digital transmission section to obtain serial data. The testing method includes the following steps.

[0028] Step S201: The serial data output by the transmission simulation part is deserialized by the deserializer deployed in the transmission simulation part of each of the plurality of data transmission channels to obtain the transmission loopback data.

[0029] Step S203: By comparing the data to be transmitted with the transmitted loopback data through the comparator of the transmit digital part of each of the plurality of data transmission channels, it is determined whether there are bit errors, thereby realizing the transmission circuit test of each of the plurality of data transmission channels.

[0030] Figure 2The test method for the transmitting circuit of the physical layer interface shown employs a comparator in the digital transmitting section and a deserializer in the analog transmitting section of each data transmitting channel. This allows each data transmitting channel to internally perform a series of operations: extracting serial data, deserializing the serial data to obtain the transmitted loopback data, and comparing the data to be transmitted with the transmitted loopback data, thus completing the transmitted loopback test. The transmitted loopback tests performed by each data transmitting channel are independent of each other, therefore the execution order can be sequential, parallel, or arbitrary, increasing the testing flexibility. The raw serial data is extracted directly from the serializer of the transmission simulation section of each data transmission channel. This means that it can adapt to the constituent modules, operating modes, and data transmission-related functions of each data transmission channel. By combining any subsequent module, the transmission simulation section of the corresponding data transmission channel can be constructed, which helps to meet the transmission circuit testing requirements of various physical layer protocols and related physical layer interface standards. The deserializer of each data transmission channel can be set to be powered off during normal data transmission, which avoids increased power consumption and the loss caused by introducing external test equipment, simplifies the testing complexity, and improves the testing efficiency.

[0031] Figure 3 This is a schematic diagram illustrating the execution order of tests on the transmission circuits of multiple data transmission channels provided in an embodiment of this application. For example... Figure 3As shown, following the arrow indicating test time 300, the transmission circuit tests of data transmission channel C310, D312, and E314 were performed sequentially. Therefore, the execution order of these three data transmission channels is serial. Additionally, the transmission circuit test of data transmission channel F316 was also performed. It can be seen that the completion of the transmission circuit test of data transmission channel F316 precedes the start of the transmission circuit test of data transmission channel E314, and the start of the transmission circuit test of data transmission channel F316 follows the start of the transmission circuit test of data transmission channel D312. The transmission circuit tests of data transmission channel F316 and data transmission channel D312 are partially executed in parallel. Thus, by deploying comparators in the digital transmission section and deserializers in the analog transmission section of each data transmission channel, each channel can internally perform a series of operations to complete the transmission loopback test, including extracting serial data, deserializing the serial data to obtain the transmission loopback data, and comparing the data to be transmitted with the transmission loopback data. Furthermore, the transmission loopback tests performed by each data transmission channel are independent of each other, allowing for sequential, parallel, or arbitrary execution orders. This flexibility in execution order allows the transmitter to design a comprehensive test scheme for multiple data transmission channels based on actual needs. For example, there might be a logical dependency between several data transmission channels; data transmitted by one channel, after processing and feedback, might become the data to be transmitted by another channel. Therefore, a sequential execution order can be designed to better simulate the sequential data transmission operations that may exist in real-world applications. For example, to maximize bandwidth utilization, multiple data transmission channels should be used in parallel as much as possible to test system limits and the upper limits of subsequent nodes. To achieve this, the execution order of parallel relationships (including partial parallel relationships between the transmission circuit tests of data transmission channel F316 and data transmission circuit tests of data transmission channel D312) can be designed. This supports a highly flexible testing scheme. In scenarios with multiple data transmission channels, each channel can have its own constituent modules, operating modes, and data transmission-related functions. Through their respective embedded data loopback modules, they can independently complete BIST tests, thus adapting to their respective testing requirements.

[0032] See Figure 1 , Figure 2 and Figure 3In one possible implementation, the physical layer interface conforms to the physical layer interface standard defined by the Mobile Industry Processor Interface (MIPI) protocol. The MIPI protocol defines a high-speed, low-power source-synchronous physical layer interface standard, D-PHY. According to MIPI definitions, D-PHY includes a high-speed (HS) operating mode and a low-power (LP) operating mode, applied in various embedded imaging devices, such as the connection between the image sensor and processor in a smartphone, and the connection between a vehicle camera and a display module. The D-PHY defined by the MIPI protocol transmits high-resolution image quality through the HS operating mode and saves power through the LP mode, thus simultaneously including high-speed and low-power modules, contributing to improved efficiency. It should be understood that besides the MIPI protocol, other physical layer protocols and related physical layer interface standards exist, specifying the components, operating modes, and data reception-related functions of the physical layer interface. Thus, the test circuit has good scalability and can be adapted to various physical layer protocols and physical layer interface standards regarding the components, operating modes, and data reception-related functions of the physical layer interface.

[0033] In some embodiments, the physical layer interface belongs to a source-synchronous physical layer, which includes a high-speed module and a low-power module. This supports the physical layer definitions related to the MIPI protocol and can meet the testing requirements of the D-PHY transmit circuits specified by the MIPI protocol, such as for testing the transmit circuits of the physical layer interface of chips in embedded imaging devices.

[0034] In some embodiments, the physical layer interface is used for a high-speed interface chip, which is used for a mobile display screen. This supports the testing requirements of the transmission circuitry of the high-speed interface chip.

[0035] In one possible implementation, the serial operation performed by the transmit analog section of each of the plurality of data transmit channels is based on the clock signal output by the clock transmit channel, and the deserialization operation performed by the deserializer of the transmit analog section of each of the plurality of data transmit channels is based on the clock signal upon which the serial operation performed by the corresponding transmit analog section depends. Thus, by deploying a comparator in the transmit digital section and a deserializer in the transmit analog section of each data transmit channel, each data transmit channel can internally complete a series of operations including extracting serial data, deserializing the serial data to obtain transmit loopback data, and comparing the data to be transmitted with the transmit loopback data to complete a transmit loopback test. Furthermore, the transmit loopback tests performed by each data transmit channel are independent of each other, and therefore can be performed serially, in parallel, or in any order. Because the original serial data is directly extracted from the serializer of the transmit analog section of each data transmit channel, the influence of subsequent modules does not need to be considered. By embedding a data loopback module in each data transmission channel, a built-in self-test scheme can be completed solely using that data transmission channel, without requiring an external testing environment or the involvement of the receiving end. Furthermore, while performing functional checks on the transmission circuit, it can support CP and FT tests on a single data transmission channel, saving testing time and hardware costs.

[0036] In some embodiments, the transmission circuit tests of the multiple data transmission channels are performed independently, and the execution order of the transmission circuit tests of the multiple data transmission channels can be serial or parallel. This degree of freedom in the execution order allows the transmitter to design an overall test scheme for multiple data transmission channels according to actual needs. This highly flexible test scheme allows each data transmission channel in a multi-channel scenario to have its own constituent modules, operating modes, and data transmission-related functions. Through their respective embedded data loopback modules, they can independently complete BIST tests, thereby adapting to their respective test requirements. For example, there may be a logical relationship of sequential dependency between several data transmission channels. For instance, data sent by one data transmission channel, after processing and feedback, becomes data to be sent by another data transmission channel. Therefore, a serial execution order can be designed to better simulate the sequential data transmission operations that may exist in actual applications. For example, in order to maximize the use of bandwidth resources, multiple data transmission channels should be used in parallel as much as possible to send data, thereby testing the system limits and the upper limit of subsequent nodes. For this purpose, the execution order of parallel relationships (including partial parallel relationships) can be designed.

[0037] In one possible implementation, the test circuit is used to construct the internal loopback circuit required for wafer testing and final product testing of the chip containing the physical layer interface. Thus, while implementing the internal loopback testing function, it can also support FT testing and CP testing of the transmitting circuit.

[0038] In one possible implementation, the deserializer of the analog transmission section and the comparator of the digital transmission section of each of the plurality of data transmission channels are configured to operate independently of each other among the plurality of data transmission channels. Furthermore, when the first data transmission channel is operating normally, the deserializer of the analog transmission section and the comparator of the digital transmission section of the first data transmission channel are powered down. In this way, the deserializer of each data transmission channel can be set to be powered down during normal data transmission, thus avoiding increased power consumption. This simplifies testing complexity and improves testing efficiency with almost no increase in power consumption and area. It also supports FT and CP testing of a single data channel without the need for an additional receiver, and each data channel can be independently and in parallel, greatly increasing the flexibility of testing.

[0039] In some embodiments, the test circuit supports wafer testing and final product testing of individual data transmission channels among the plurality of data transmission channels. This satisfies the MIPI protocol's definition of the physical layer and supports testing of the transmission circuits of both high-speed and low-power modules. No additional receiver is required, and each data channel can be performed independently and in parallel, greatly improving the flexibility of testing.

[0040] The methods and devices provided in this application are based on the same inventive concept. Since the principles by which the methods and devices solve problems are similar, the embodiments, implementation methods, examples, or methods of implementation of the methods and devices can be referred to each other, and repeated details will not be repeated. This application also provides a system comprising multiple computing devices, the structure of each computing device of which can refer to the structure of the computing devices described above. The functions or operations achievable by this system can refer to the specific implementation steps in the above method embodiments and / or the specific functions described in the above device embodiments, and will not be repeated here.

[0041] This application also provides a computer-readable storage medium storing computer instructions. When these computer instructions are executed on a computer device (such as one or more processors), they can implement the method steps described in the above method embodiments. The specific implementation of the above method steps by the processor of the computer-readable storage medium can refer to the specific operations described in the above method embodiments and / or the specific functions described in the above device embodiments, and will not be repeated here.

[0042] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. This application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Embodiments of this application can be implemented wholly or partially by software, hardware, firmware, or any other combination. When implemented in software, the above embodiments can be implemented wholly or partially as a computer program product. This application can take the form of a computer program product embodied on one or more computer-usable storage media containing computer-usable program code. The computer program product includes one or more computer instructions. When the computer program instructions are loaded or executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line) or wireless (e.g., infrared, wireless network communication, microwave, etc.) means. Computer-readable storage media can be any available medium that a computer can access, or a data storage device such as a server or data center that contains one or more sets of available media. Available media can be magnetic media (such as floppy disks, hard disks, and magnetic tapes), optical media, or semiconductor media. Semiconductor media can be solid-state drives, random access memory, flash memory, read-only memory, erasable programmable read-only memory, electrically erasable programmable read-only memory, registers, or any other suitable form of storage medium.

[0043] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. Each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The functions specified in one or more boxes. These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable apparatus for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0044] In the above embodiments, the descriptions of each embodiment have their own emphasis. Parts not described in detail in a certain embodiment can be referred to in the relevant descriptions of other embodiments. Obviously, those skilled in the art can make various modifications and variations to the embodiments of this application without departing from the spirit and scope of the embodiments of this application. The steps in the methods of the embodiments of this application can be adjusted in order, combined, or deleted according to actual needs; the modules in the systems of the embodiments of this application can be divided, combined, or deleted according to actual needs. If these modifications and variations of the embodiments of this application fall within the scope of the claims of this application and their equivalents, then this application also intends to include these modifications and variations.

Claims

1. A test circuit for a transmitting circuit of a physical layer interface, characterized in that, The physical layer interface's transmitting circuit includes multiple data transmitting channels and a clock transmitting channel shared among the multiple data transmitting channels. Each of the multiple data transmitting channels includes a digital transmitting section and a digital transmitting section. The digital transmitting section is used to transmit data to be transmitted in parallel to the analog transmitting section. The analog transmitting section is used to perform serial operations on the parallel data received from the digital transmitting section to obtain serial data. The test circuit includes: A deserializer in the transmission simulation section of each of the plurality of data transmission channels is used to perform a deserialization operation on the serial data output by the transmission simulation section to obtain transmission loopback data; A comparator in the digital transmission section of each of the multiple data transmission channels is deployed to compare the data to be transmitted with the transmitted loopback data to determine whether there are any bit errors, thereby enabling the testing of the transmission circuits of each of the multiple data transmission channels.

2. The test circuit according to claim 1, characterized in that, The physical layer interface conforms to the physical layer interface standard defined by the processor interface protocol in the mobile communications industry.

3. The test circuit according to claim 2, characterized in that, The physical layer interface belongs to the source-synchronous physical layer, which includes a high-speed module and a low-power module.

4. The test circuit according to claim 3, characterized in that, The physical layer interface is used for a high-speed interface chip, and the high-speed interface chip is used for a mobile terminal display screen.

5. The test circuit according to claim 1, characterized in that, The serial operation performed by the transmission simulation section of each of the plurality of data transmission channels is based on the clock signal output by the clock transmission channel, and the deserialization operation performed by the deserializer of the transmission simulation section of each of the plurality of data transmission channels is based on the clock signal on which the serial operation performed by the corresponding transmission simulation section depends.

6. The test circuit according to claim 5, characterized in that, The transmission circuit tests of the multiple data transmission channels are performed independently of each other, and the execution order of the transmission circuit tests of the multiple data transmission channels is either serial or parallel.

7. The test circuit according to claim 1, characterized in that, The test circuit is used to construct the internal loopback circuit required for wafer testing and finished product testing of the chip where the physical layer interface is located.

8. The test circuit according to claim 1, characterized in that, The deserializers of the analog transmission section and the comparators of the digital transmission section of each of the plurality of data transmission channels are configured to operate independently of each other among the plurality of data transmission channels, and when the first data transmission channel among the plurality of data transmission channels is operating normally, the deserializers of the analog transmission section and the comparators of the digital transmission section of the first data transmission channel are in a power-off state.

9. The test circuit according to claim 8, characterized in that, The test circuit supports wafer testing and finished product testing for a single data transmission channel among the multiple data transmission channels.

10. A test method for a transmitting circuit of a physical layer interface, characterized in that, The physical layer interface's transmitting circuit includes multiple data transmitting channels and a clock transmitting channel shared among the multiple data transmitting channels. Each of the multiple data transmitting channels includes a digital transmitting section and a digital transmitting section. The digital transmitting section is used to transmit data to be transmitted in parallel to the analog transmitting section. The analog transmitting section is used to perform serial operations on the parallel data received from the digital transmitting section to obtain serial data. The testing method includes: By using the deserializer in the transmission simulation section of each of the multiple data transmission channels, the serial data output by the transmission simulation section is deserialized to obtain the transmission loopback data. By comparing the data to be transmitted with the transmitted loopback data through a comparator deployed in the digital transmission section of each of the multiple data transmission channels, it is determined whether there are any bit errors, thereby enabling the testing of the transmission circuits of each of the multiple data transmission channels.

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