Testing device, testing method and testing equipment for output performance of digital chip and storage medium

Abstract

The invention relates to a testing device, a testing method and testing equipment for the output performance of a digital chip and a readable storage medium. The circuit comprises a control module, at least one ADC chip, at least one DAC chip and at least two soft switches. The control module is respectively connected with the ADC chip and the DAC chip; each soft switch is arranged in a channel between the analog ground and the digital ground, and at least two soft switches are arranged in parallel; the DAC is connected with the ADC chip; the control module is used for testing the output performance of the DAC chip under the on-off states of different soft switches to obtain a test result; according to the device, the output performance of the DAC chip is compared under the on-off states of different soft switches, the optimal switching mode is determined, the noise of analog signals of the device is reduced, and the transmission precision of the analog signals is improved.

Description

Technical Field

[0001] This application relates to the field of intelligent testing technology, and in particular to a testing device, testing method, testing equipment, and readable storage medium for testing the output performance of a digital chip. Background Technology

[0002] As the requirements for stable operation of the power grid gradually increase, traditional sensors cannot meet the needs of high-precision data acquisition. Quantum sensors are gradually replacing traditional sensors. In quantum sensors, digital-to-analog converter (DAC) chips are required to output analog signals whose frequency changes rapidly over time. However, because analog signals have small amplitudes, they are often susceptible to interference from factors such as crosstalk and noise in digital circuits, which in turn affects the measurement accuracy of quantum sensors.

[0003] Therefore, improving the measurement accuracy of quantum sensors has become a pressing technical problem to be solved in the field of power grid measurement. Summary of the Invention

[0004] Therefore, it is necessary to provide a testing device, testing method, testing equipment, and readable storage medium for testing the output performance of digital chips to address the aforementioned technical problems.

[0005] In a first aspect, this application provides a testing device for the output performance of a digital chip, comprising: a control module, at least one ADC chip, at least one DAC chip, and at least two soft switches; the control module is connected to the ADC chip and the DAC chip respectively; each soft switch is disposed in a channel between analog ground and digital ground, and at least two soft switches are arranged in parallel; the DAC is connected to the ADC chip;

[0006] The control module is used to test the output performance of the DAC chip under different soft-switching states and obtain the test results.

[0007] In one embodiment, at least one ADC chip includes: a first ADC chip; at least one DAC chip includes: a first DAC chip; and at least two soft switches include a first soft switch and a second soft switch.

[0008] The control module is used to control the first soft switch and the second soft switch to be in the first state, the second state and the third state respectively, to test the output performance of the DAC chip and obtain the test results.

[0009] The first state includes both the first soft switch and the second soft switch being in the on state; the second state includes both the first soft switch and the second soft switch being in the off state; and the third state includes the first soft switch being in the on state and the second soft switch being in the off state.

[0010] In one embodiment, at least one ADC chip includes: a first ADC chip; at least one DAC chip includes: a first DAC chip; and at least two soft switches include a third soft switch, a fourth soft switch, and a fifth soft switch.

[0011] The control module is used to control the third, fourth, and fifth soft switches to be in the fourth, fifth, sixth, and seventh states respectively, to test the output performance of the DAC chip and obtain the test results.

[0012] The fourth state includes the third, fourth, and fifth soft switches all being in the off state; the fifth state includes the third soft switch being in the on state, and the fourth and fifth soft switches being in the off state; the sixth state includes the third and fourth soft switches being in the on state, and the fifth soft switch being in the off state; the seventh state includes the third, fourth, and fifth soft switches all being in the on state.

[0013] In one embodiment, at least one ADC chip includes: a first ADC chip; at least one DAC chip includes: a first DAC chip; and at least two soft switches include a sixth soft switch, a seventh soft switch, an eighth soft switch, and a ninth soft switch.

[0014] The control module is used to control the sixth, seventh, eighth, and ninth soft switches to be in the eighth, ninth, tenth, eleventh, and twelfth states, respectively, to test the output performance of the DAC chip and obtain the test results.

[0015] The eighth state includes the sixth, seventh, eighth, and ninth soft switches all being in the off state; the ninth state includes the sixth soft switch being in the on state, and the seventh, eighth, and ninth soft switches all being in the off state; the tenth state includes the sixth and seventh soft switches being in the on state, and the eighth and ninth soft switches all being in the off state; the eleventh state includes the sixth, seventh, and eighth soft switches being in the on state, and the ninth soft switch being in the off state; the twelfth state includes the sixth, seventh, eighth, and ninth soft switches all being in the on state.

[0016] In one embodiment, a method for testing the output performance of a digital chip, applied to a testing apparatus for the output performance of a digital chip, includes:

[0017] Each soft switch in the control test device is in a different on / off state;

[0018] The output performance of the DAC chip was tested under different on / off states of each soft switch, and the test results were obtained.

[0019] In one embodiment, the output performance of the DAC chip is tested with each soft switch in a different on / off state, and the test results are obtained, including:

[0020] Generate test signals corresponding to the different on / off states of each soft switch, and send each test signal to the DAC chip in the test device;

[0021] The ADC chip in the receiving test device processes each test signal and sends the processed signal.

[0022] Determine the amplitude error between each test signal and the corresponding processed signal, and test the output performance of the DAC chip based on each amplitude error to obtain the test results.

[0023] In one embodiment, the output performance of the DAC chip is tested based on each amplitude error to obtain test results, including:

[0024] The optimal switching state is determined by taking the switching state with the smallest amplitude error, and the test results are obtained.

[0025] In one embodiment, a method for testing the output performance of a digital chip further includes, after a preset interval, returning to the execution control test device to ensure that each soft switch is in a different on / off state.

[0026] Secondly, this application also provides a testing device for a digital chip output performance testing apparatus, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to perform the following steps:

[0027] Each soft switch in the control test device is in a different on / off state;

[0028] The output performance of the DAC chip was tested under different on / off states of each soft switch, and the test results were obtained.

[0029] Thirdly, this application also provides a storage medium for a testing device for the output performance of a digital chip, on which a computer program is stored, and when the computer program is executed by a processor, it performs the following steps:

[0030] Each soft switch in the control test device is in a different on / off state;

[0031] The output performance of the DAC chip was tested under different on / off states of each soft switch, and the test results were obtained.

[0032] The aforementioned testing apparatus, method, equipment, and readable storage medium for testing the output performance of digital chips include a control module, at least one ADC chip, at least one DAC chip, and at least two soft switches. The control module is connected to both the ADC chip and the DAC chip. Each soft switch is located in a channel between analog ground and digital ground, and at least two soft switches are arranged in parallel. The DAC chip is connected to the ADC chip. The control module is used to test the output performance of the DAC chip under different soft switch on / off states and obtain test results. By comparing the output performance of the DAC chip under different soft switch on / off states, the above apparatus establishes the optimal switching mode, thereby reducing analog signal noise and improving the transmission accuracy of analog signals. Attached Figure Description

[0033] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0034] Figure 1 This is a diagram illustrating the application environment of the testing device for the output performance of a digital chip in the embodiments of this application.

[0035] Figure 2 This is one of the structural block diagrams of a digital chip output performance testing device in the embodiments of this application;

[0036] Figure 3 This is a second structural block diagram of a testing device for the output performance of a digital chip in an embodiment of this application;

[0037] Figure 4 This is the third structural block diagram of the digital chip output performance testing device in the embodiments of this application;

[0038] Figure 5 This is one of the flowcharts illustrating a method for testing the output performance of a digital chip in an embodiment of this application.

[0039] Figure 6 This is a second schematic flowchart of a method for testing the output performance of a digital chip in an embodiment of this application.

[0040] Figure 7 This is the third flowchart illustrating the testing method for the output performance of a digital chip in this application.

[0041] Figure 8 This is the fourth flowchart illustrating the testing method for the output performance of a digital chip in this application.

[0042] Figure 9 This is a flowchart of the re-triggering test method for the output performance of a digital chip in an embodiment of this application;

[0043] Figure 10 This is a diagram of a 4-channel GND switch array test device for the output performance of a digital chip in an embodiment of this application.

[0044] Figure 11 This is a block diagram of a test device for the output performance of a digital chip in one embodiment;

[0045] Figure 12 This is an internal structural diagram of a testing device for the output performance of a digital chip in one embodiment. Detailed Implementation

[0046] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0047] It should be noted that the terms "first," "second," etc., used in this application can be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish the first element from the second element. The terms "comprising" and "having," and any variations thereof, used in this application, are intended to cover non-exclusive inclusion. The term "multiple" used in this application refers to two or more. The term "and / or" used in this application refers to one of the embodiments, or any combination of multiple embodiments.

[0048] As the requirements for stable operation of the power grid gradually increase, traditional sensors cannot meet the needs of high-precision data acquisition. Quantum sensors are gradually replacing traditional sensors. In quantum sensors, digital-to-analog converter (DAC) chips are required to output analog signals whose frequency changes rapidly over time. However, because analog signals have small amplitudes, they are often susceptible to interference from factors such as crosstalk and noise in digital circuits, which in turn affects the measurement accuracy of quantum sensors.

[0049] Therefore, improving the measurement accuracy of quantum sensors has become a pressing technical problem to be solved in the field of power grid measurement.

[0050] In view of the above-mentioned technical problems, this application provides a testing device and method for testing the output performance of a digital chip. The following embodiments will specifically describe the testing device and method for testing the output performance of the digital chip.

[0051] In one exemplary embodiment, such as Figure 1As shown, a testing device for the output performance of a digital chip is provided. The testing device includes a control module, at least one ADC chip, at least one DAC chip, and at least two soft switches. The control module is connected to the ADC chip and the DAC chip respectively. Each soft switch is disposed in a channel between analog ground and digital ground, and at least two soft switches are arranged in parallel. The DAC is connected to the ADC chip.

[0052] The control module is used to test the output performance of the DAC chip under different soft-switching states and obtain test results. Optionally, the control module can be implemented based on a field-programmable gate array (FPGA) or other types of logic controllers; the test results include the optimal switching state corresponding to the analog-to-digital converter (ADC) chip.

[0053] Soft switching refers to a switching technology applied to power supply circuits. The testing device can reduce losses and noise by optimizing the switching process.

[0054] The working principle of the digital chip output performance testing device described in this application embodiment includes: When the test is started, the control module in the testing device can first determine multiple test states of different soft switches (i.e., determined by the on / off states of different soft switches), and in each test state, generate a standard digital signal and send the standard digital signal to the DAC chip. The DAC chip performs digital-to-analog conversion on the standard digital signal and outputs the corresponding analog signal. Then, the analog signal is passed to the ADC chip for analog-to-digital conversion, and outputs the test digital signal to the control module. Then, the control module can calculate the signal error based on the test digital signal and the standard digital signal. The control module can calculate the signal error in all test states based on the above method, and determine the test state corresponding to the minimum signal error as the optimal switching state of the DAC chip in the testing device, thus obtaining the test result.

[0055] The digital chip output performance testing device described in the above embodiments provides a testing method to improve the data conversion accuracy of DAC chips. This is achieved by optimizing the soft switching layout around the DAC chip, reducing DAC output interference, and thus improving the DAC output performance, making it applicable to quantum sensors with high-precision acquisition requirements.

[0056] In one exemplary embodiment, such as Figure 2 As shown, Figure 1The at least one ADC chip shown includes: a first ADC chip; at least one DAC chip includes: a first DAC chip; at least two soft switches include a first soft switch and a second soft switch;

[0057] The control module is used to control the first soft switch and the second soft switch to be in the first state, the second state and the third state respectively, to test the output performance of the DAC chip and obtain the test results.

[0058] The first state includes both the first soft switch and the second soft switch being in the on state; the second state includes both the first soft switch and the second soft switch being in the off state; and the third state includes the first soft switch being in the on state and the second soft switch being in the off state.

[0059] The working principle of the digital chip output performance testing device described in this application embodiment includes: When the test is started, the control module in the testing device can first determine multiple test states of the first soft switch and the second soft switch, that is, in the first state, both the first soft switch and the second soft switch are in the on state; in the second state, both the first soft switch and the second soft switch are in the off state; in the third state, the first soft switch is in the on state and the second soft switch is in the off state. In each test state, a standard digital signal is generated and sent to the DAC chip. That is, in the first state, the control module generates a first standard digital signal and sends it to the DAC chip. Similarly, the second standard digital signal and the third standard digital signal can be obtained. Then, the DAC chip performs digital-to-analog conversion on each standard digital signal and outputs the corresponding analog signal (first analog signal, second analog signal, and third analog signal). Then, the first analog signal, the second analog signal, and the third analog signal are transmitted to the ADC chip for analog-to-digital conversion, and the first test digital signal, the second test digital signal, and the third test digital signal are output to the control module respectively. Then, the control module can calculate the first signal error, the second signal error, and the third signal error sequentially based on the three test digital signals and the three standard digital signals. The control module can compare the first signal error, the second signal error, and the third signal error, and determine the test state corresponding to the minimum signal error as the optimal switching state of the DAC chip in the test device, thereby obtaining the test result.

[0060] In one exemplary embodiment, such as Figure 3 As shown, Figure 1 The at least one ADC chip shown includes: a first ADC chip; at least one DAC chip includes: a first DAC chip; at least two soft switches include a third soft switch, a fourth soft switch and a fifth soft switch;

[0061] The control module is used to control the third, fourth, and fifth soft switches to be in the fourth, fifth, sixth, and seventh states respectively, to test the output performance of the DAC chip and obtain the test results.

[0062] The fourth state includes the third, fourth, and fifth soft switches all being in the off state; the fifth state includes the third soft switch being in the on state, and the fourth and fifth soft switches being in the off state; the sixth state includes the third and fourth soft switches being in the on state, and the fifth soft switch being in the off state; the seventh state includes the third, fourth, and fifth soft switches all being in the on state.

[0063] The working principle of the digital chip output performance testing device described in this application embodiment includes: when the test is started, the control module in the testing device can first determine multiple test states of the third soft switch, the fourth soft switch, and the fifth soft switch, that is, in the fourth state, the third soft switch, the fourth soft switch, and the fifth soft switch are all in the off state; in the fifth state, the third soft switch is in the on state, and the fourth soft switch and the fifth soft switch are all in the off state; in the sixth state, the third soft switch and the fourth soft switch are both in the on state, and the fifth soft switch is in the off state; in the seventh state, the third soft switch, the fourth soft switch, and the fifth soft switch are all in the on state, and in each test state, a standard digital signal is generated and sent to the DAC chip, that is, in the fourth state, the control module generates a fourth standard digital signal and sends a fourth standard digital signal to the DAC chip, and similarly, the fifth standard digital signal, the sixth standard digital signal, and the seventh standard digital signal can be obtained. The DAC chip then performs digital-to-analog conversion on each standard digital signal and outputs corresponding analog signals (fourth analog signal, fifth analog signal, sixth analog signal, and seventh analog signal). These analog signals are then passed to the ADC chip for analog-to-digital conversion, outputting the fourth, fifth, sixth, and seventh test digital signals, respectively, to the control module. The control module then calculates the errors for the fourth, fifth, sixth, and seventh signals sequentially based on the four test digital signals and the four standard digital signals. The control module compares these errors and determines the test state corresponding to the minimum error as the optimal switching state for the DAC chip in the test device, thus obtaining the test result.

[0064] In one exemplary embodiment, such as Figure 4 As shown, Figure 1The at least one ADC chip shown includes: a first ADC chip; at least one DAC chip includes: a first DAC chip; at least two soft switches include a sixth soft switch, a seventh soft switch, an eighth soft switch and a ninth soft switch;

[0065] The control module is used to control the sixth, seventh, eighth, and ninth soft switches to be in the eighth, ninth, tenth, eleventh, and twelfth states, respectively, to test the output performance of the DAC chip and obtain the test results.

[0066] The eighth state includes the sixth, seventh, eighth, and ninth soft switches all being in the off state; the ninth state includes the sixth soft switch being in the on state, and the seventh, eighth, and ninth soft switches all being in the off state; the tenth state includes the sixth and seventh soft switches being in the on state, and the eighth and ninth soft switches all being in the off state; the eleventh state includes the sixth, seventh, and eighth soft switches being in the on state, and the ninth soft switch being in the off state; the twelfth state includes the sixth, seventh, eighth, and ninth soft switches all being in the on state.

[0067] The working principle of the digital chip output performance testing device described in this application embodiment includes: when the test is started, the control module in the testing device can first determine multiple test states of the sixth soft switch, the seventh soft switch, the eighth soft switch, and the ninth soft switch. That is, in the eighth state, the sixth soft switch, the seventh soft switch, the eighth soft switch, and the ninth soft switch are all in the off state; in the ninth state, the sixth soft switch is in the on state, and the seventh soft switch, the eighth soft switch, and the ninth soft switch are all in the off state; in the tenth state, the sixth soft switch and the seventh soft switch are both in the on state, and the eighth soft switch and the ninth soft switch are both in the off state. In the eleventh state, the sixth, seventh, and eighth soft switches are all in the conducting state, while the ninth soft switch is in the off state. In the twelfth state, the sixth, seventh, eighth, and ninth soft switches are all in the conducting state. In each test state, a standard digital signal is generated and sent to the DAC chip. Specifically, in the eighth state, the control module generates the eighth standard digital signal and sends it to the DAC chip; similarly, the ninth, tenth, eleventh, and twelfth standard digital signals can be obtained. The DAC chip then performs digital-to-analog conversion on each standard digital signal and outputs the corresponding analog signal (eighth analog signal, ninth analog signal, tenth analog signal, eleventh analog signal, and twelfth analog signal). These analog signals are then passed to the ADC chip for analog-to-digital conversion, outputting the eighth, ninth, tenth, eleventh, and twelfth test digital signals to the control module. Then, the control module can sequentially calculate the eighth, ninth, tenth, eleventh, and twelfth signal errors based on five test digital signals and five standard digital signals. The control module can compare these errors and determine the test state corresponding to the minimum signal error as the optimal switching state for the DAC chip in the test device, thus obtaining the test result.

[0068] In one exemplary embodiment, the testing apparatus for the output performance of a digital chip based on any of the foregoing embodiments also provides a method for testing the output performance of a digital chip. Figure 5 As shown, it includes:

[0069] S101, each soft switch in the control test device is in a different on / off state;

[0070] In this embodiment of the application, the on / off state of each soft switch in the test device is controlled by the control module in the test device. For example, if the control module is implemented based on FPGA, the FPGA sends corresponding on / off commands (complete disconnection, single-point connection, or multi-point connection) to each soft switch for different test states, thereby realizing the control of each soft switch in different on / off states.

[0071] S102, with each soft switch in a different on / off state, tests the output performance of the DAC chip and obtains the test results.

[0072] This application embodiment relates to a specific method for testing a DAC chip when each soft switch is in a different on / off state. This method is similar to the aforementioned... Figures 1-4 The testing methods described in any implementation under different testing conditions are basically the same. For details, please refer to the foregoing description, which will not be repeated here.

[0073] In an exemplary embodiment, the above-mentioned S102, "testing the output performance of the DAC chip under different on / off states of each soft switch, and obtaining test results," is as follows: Figure 6 As shown, it includes:

[0074] S201, generate test signals corresponding to the different on / off states of each soft switch, and send each test signal to the DAC chip in the test device;

[0075] In this embodiment of the application, the "test signal" corresponds to the aforementioned "first standard digital signal, second standard digital signal, third standard digital signal, fourth standard digital signal, fifth standard digital signal, sixth standard digital signal, seventh standard digital signal, eighth standard digital signal, ninth standard digital signal, tenth standard digital signal, eleventh standard digital signal, and twelfth standard digital signal", and the test method is the same as described above. Figures 1-4 The testing methods described in any implementation under different testing conditions are basically the same. For details, please refer to the foregoing description, which will not be repeated here.

[0076] S202, receive the processing signal sent by the ADC chip in the test device after processing each test signal;

[0077] In this embodiment, the "processing signal" corresponds to the aforementioned "first test digital signal, second test digital signal, third test digital signal, fourth test digital signal, fifth test digital signal, sixth test digital signal, seventh test digital signal, eighth test digital signal, ninth test digital signal, tenth test digital signal, eleventh test digital signal, and twelfth test digital signal", and the test method is the same as described above. Figures 1-4The testing methods described in any implementation under different testing conditions are basically the same. For details, please refer to the foregoing description, which will not be repeated here.

[0078] S203, determine the amplitude error between each test signal and the corresponding processed signal, and test the output performance of the DAC chip based on each amplitude error to obtain the test results.

[0079] In this application embodiment, a specific method is involved for calculating the amplitude error between each test signal and the corresponding processed signal when each soft switch is in different on / off states. This method is similar to the aforementioned Figures 1-4 The amplitude error calculation methods described in any implementation under different test states are basically the same; for details, please refer to the foregoing explanation, which will not be repeated here. Taking the control module using an FPGA to control the test device and four test states of a four-channel switch array as an example, the analog signal to be tested is generated by the DAC chip as the reference standard signal, and this node is set as... The FPGA initializes the switch state, meaning the 4-way GND connection switch is disconnected, and this node is set to... The analog ground and digital ground are completely separated. The ADC chip acquires the signal amplitude of the DAC output at this moment and calculates the amplitude error between the acquired signal amplitude and the reference standard signal generated by the DAC chip. That is, amplitude error = DAC chip output amplitude - ADC chip output amplitude. Then, the FPGA sequentially switches different combinations of GND array states: single-channel connection, two-channel connection, and three-channel connection. The ADC acquires the corresponding DAC output signal amplitude in different states, and the FPGA calculates the amplitude error. The single-channel connection state is set to... The two-way connection status is The three-way connection status is As shown in Table 1:

[0080] Table 1

[0081]

[0082] In an exemplary embodiment, the above-mentioned S203, "testing the output performance of the ADC chip based on each amplitude error and obtaining the test results," is as follows: Figure 7 As shown, this includes: taking the opening state with the smallest amplitude error as the optimal switching state, and obtaining the test results.

[0083] In this application embodiment, a specific method is described for testing the output performance of a DAC chip and obtaining test results based on various amplitude errors when each soft switch is in a different on / off state. This method is similar to the aforementioned... Figures 1-4The amplitude error calculation methods described in any implementation under different test states are basically the same; for details, please refer to the foregoing explanation, which will not be repeated here. Taking the control module using an FPGA to control the test device and four test states of a four-channel switch array as an example, the amplitude of the DAC chip output signal is calculated when the four GND connection switches are open. Amplitude error of the ADC sampled signal The calculation formula is: Represent this state as With the GND connection switch on (channel 1) open, calculate the amplitude of the DAC chip's output signal. The amplitude error of the ADC sampled signal at this time The calculation formula is: Represent this state as With both GND connection switches on, calculate the amplitude of the DAC chip's output signal. The amplitude error of the ADC sampled signal at this time The calculation formula is: Represent this state as With the 3-way GND connection switch on, calculate the amplitude of the DAC chip's output signal. The amplitude error of the ADC sampled signal at this time The calculation formula is: Represent this state as As shown in Table 2:

[0084] Table 2

[0085]

[0086] In one exemplary embodiment, a method for testing the output performance of a digital chip further includes, as follows: Figure 8 As shown:

[0087] S103, after a preset interval, return to the step of executing each soft switch in the control test device being in a different open / closed state.

[0088] In this embodiment, the testing device can use an FPGA to set an interval time to perform timed cyclic calculations on the amplitude error between the DAC chip and the ADC chip, periodically re-triggering the testing method flow, such as... Figure 9 As shown, taking a test setup containing a 4-channel GND switch array as an example, the test setup is as follows: Figure 10 As shown, by comparing all errors, the GND connection method corresponding to the smallest amplitude error value is selected, and the GND switch connection state is locked in the optimal mode.

[0089] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages in other steps. It is understood that the steps in different embodiments can be freely combined as needed, and all non-contradictory solutions formed by such combinations are within the scope of protection of this application.

[0090] Based on the same inventive concept, this application also provides a testing apparatus for the output performance of a digital chip to implement the aforementioned testing method for the output performance of a digital chip. The solution provided by this apparatus is similar to the implementation described in the above-described method. Therefore, the specific limitations in the embodiments of one or more testing apparatuses for the output performance of a digital chip provided below can be found in the limitations of the testing method for the output performance of a digital chip described above, and will not be repeated here.

[0091] In one exemplary embodiment, such as Figure 11 As shown, a testing device for the output performance of a digital chip is provided, comprising:

[0092] The control module 301 is used to control each soft switch in the test device to be in a different on / off state.

[0093] Test module 302 is used to test the output performance of the DAC chip under different on / off states of each soft switch and obtain test results.

[0094] In one embodiment, the measurement module includes:

[0095] The generation unit is used to generate test signals corresponding to the different on / off states of each soft switch, and send each test signal to the DAC chip in the test device.

[0096] The processing unit receives the processed signals sent by the ADC chip in the testing device after processing each test signal;

[0097] The test unit determines the amplitude error between each test signal and the corresponding processed signal, and tests the output performance of the DAC chip based on each amplitude error to obtain the test results.

[0098] In a test subunit of a measurement module, the optimal switching state is determined by taking the opening state with the smallest amplitude error, and the test results are obtained.

[0099] The modules in the aforementioned digital chip output performance testing device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in or independent of the processor in a computer device, or stored in the memory of a computer device as software, so that the processor can call and execute the operations corresponding to each module.

[0100] In one exemplary embodiment, a test device for a method of testing the output performance of a digital chip is provided. This test device can be a terminal, and its internal structure diagram can be as follows: Figure 12 As shown, the test equipment includes a processor, memory, input / output interfaces, a communication interface, and input devices. The processor, memory, and input / output interfaces are connected via a system bus, and the communication interface and input devices are also connected to the system bus via the input / output interfaces. The processor provides computational and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system and computer programs. The internal memory provides the environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The input / output interfaces are used for exchanging information between the processor and external devices. The communication interface is used for wired or wireless communication with external terminals; wireless communication can be achieved through Wi-Fi, mobile cellular networks, Near Field Communication (NFC), or other technologies. When the computer program is executed by the processor, it implements a method for testing the output performance of a digital chip.

[0101] Those skilled in the art will understand that Figure 12 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the control device to which the present application is applied. The specific control device may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0102] In some exemplary embodiments, a testing device is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to perform the following steps:

[0103] The soft switches in the test device are controlled to be in different on / off states;

[0104] The output performance of the DAC chip is tested under different on / off states of each soft switch, and the test results are obtained.

[0105] In one embodiment, when the computer program is executed by a processor, it also performs the following steps:

[0106] Generate test signals corresponding to the different on / off states of each soft switch, and send each test signal to the DAC chip in the test device;

[0107] Receive the processing signal sent by the ADC chip in the test device after processing each of the test signals;

[0108] The amplitude error between each test signal and the corresponding processing signal is determined, and the output performance of the DAC chip is tested based on each amplitude error to obtain the test results.

[0109] In one embodiment, when the computer program is executed by a processor, it also performs the following steps:

[0110] The test result is obtained by taking the switching state with the smallest amplitude error as the optimal switching state.

[0111] In one embodiment, when the computer program is executed by the processor, it further performs the following steps: after a preset interval, returning to the step of controlling each soft switch in the test device to be in a different on / off state.

[0112] In some exemplary embodiments, a storage medium is provided that, when the processor executes a computer program, performs the following steps:

[0113] The soft switches in the test device are controlled to be in different on / off states;

[0114] The output performance of the DAC chip is tested under different on / off states of each soft switch, and the test results are obtained.

[0115] In one embodiment, when the computer program is executed by a processor, it also performs the following steps:

[0116] Generate test signals corresponding to the different on / off states of each soft switch, and send each test signal to the DAC chip in the test device;

[0117] Receive the processing signal sent by the ADC chip in the test device after processing each of the test signals;

[0118] The amplitude error between each test signal and the corresponding processing signal is determined, and the output performance of the DAC chip is tested based on each amplitude error to obtain the test results.

[0119] In one embodiment, when the computer program is executed by a processor, it also performs the following steps:

[0120] The test result is obtained by taking the switching state with the smallest amplitude error as the optimal switching state.

[0121] In one embodiment, when the computer program is executed by the processor, it further performs the following steps: after a preset interval, returning to the step of controlling each soft switch in the test device to be in a different on / off state.

[0122] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, artificial intelligence (AI) processors, etc., and are not limited to these.

[0123] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0124] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A testing device for the output performance of a digital chip, characterized in that, The testing device includes: a control module, at least one ADC chip, at least one DAC chip, and at least two soft switches; the control module is connected to the ADC chip and the DAC chip respectively; each soft switch is disposed in a channel between analog ground and digital ground, and the at least two soft switches are arranged in parallel; the DAC is connected to the ADC chip. The control module is used to test the output performance of the DAC chip under different on / off states of the soft switch and obtain test results.

2. The apparatus according to claim 1, characterized in that, The at least one ADC chip includes: a first ADC chip; the at least one DAC chip includes: a first DAC chip; the at least two soft switches include a first soft switch and a second soft switch; The control module is used to control the first soft switch and the second soft switch to be in the first state, the second state and the third state respectively, to test the output performance of the DAC chip and obtain the test results. The first state includes both the first soft switch and the second soft switch being in the ON state; the second state includes both the first soft switch and the second soft switch being in the OFF state; and the third state includes the first soft switch being in the ON state and the second soft switch being in the OFF state.

3. The apparatus according to claim 1, characterized in that, The at least one ADC chip includes: a first ADC chip; the at least one DAC chip includes: a first DAC chip; the at least two soft switches include a third soft switch, a fourth soft switch and a fifth soft switch; The control module is used to control the third soft switch, the fourth soft switch and the fifth soft switch to be in the fourth state, the fifth state, the sixth state and the seventh state respectively, to test the output performance of the DAC chip and obtain the test results; The fourth state includes the third soft switch, the fourth soft switch, and the fifth soft switch all being in the off state; the fifth state includes the third soft switch being in the on state, and the fourth soft switch and the fifth soft switch all being in the off state; the sixth state includes the third soft switch and the fourth soft switch all being in the on state, and the fifth soft switch being in the off state; the seventh state includes the third soft switch, the fourth soft switch, and the fifth soft switch all being in the on state.

4. The apparatus according to claim 1, characterized in that, The at least one ADC chip includes: a first ADC chip; the at least one DAC chip includes: a first DAC chip; the at least two soft switches include a sixth soft switch, a seventh soft switch, an eighth soft switch, and a ninth soft switch; The control module is used to control the sixth soft switch, the seventh soft switch, the eighth soft switch and the ninth soft switch to be in the eighth state, the ninth state, the tenth state, the eleventh state and the twelfth state respectively, to test the output performance of the ADC chip and obtain the test results; The eighth state includes the sixth, seventh, eighth, and ninth soft switches all being in the off state; the ninth state includes the sixth soft switch being in the on state, and the seventh, eighth, and ninth soft switches all being in the off state; the tenth state includes the sixth and seventh soft switches being in the on state, and the eighth and ninth soft switches all being in the off state; the eleventh state includes the sixth, seventh, and eighth soft switches being in the on state, and the ninth soft switch being in the off state; the twelfth state includes the sixth, seventh, eighth, and ninth soft switches all being in the on state.

5. A method for testing the output performance of a digital chip, characterized in that, Applied to the testing apparatus as described in any one of claims 1-4, the method comprises: The soft switches in the test device are controlled to be in different on / off states; The output performance of the DAC chip is tested under different on / off states of each soft switch, and the test results are obtained.

6. The method according to claim 5, characterized in that, The output performance of the DAC chip is tested under different on / off states of each of the soft switches, and the test results are obtained, including: Generate test signals corresponding to the different on / off states of each soft switch, and send each test signal to the DAC chip in the test device; Receive the processing signal sent by the ADC chip in the test device after processing each of the test signals; The amplitude error between each test signal and the corresponding processing signal is determined, and the output performance of the DAC chip is tested based on each amplitude error to obtain the test results.

7. The method according to claim 6, characterized in that, The step of testing the output performance of the DAC chip based on each amplitude error to obtain test results includes: The test result is obtained by taking the switching state with the smallest amplitude error as the optimal switching state.

8. The method according to claims 5-7, characterized in that, The method further includes: After a preset interval, the process returns to the step of controlling each soft switch in the test device to be in a different on / off state.

9. A testing device, comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 5 to 8.

10. A storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 5 to 8.

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