Semiconductor test equipment and automatic test method and device thereof

Abstract

The invention provides semiconductor testing equipment and an automatic testing method and device thereof, and relates to the technical field of semiconductor testing. The method comprises the steps of collecting target data output by a target chip through a second thread; in the process of testing the target chip based on the target data, if it is determined that configuration modification needs to be carried out on the target chip, frame transmission time is determined based on the target data under the condition that the target chip has no frame synchronization pin; performing configuration modification on the target chip through the first thread based on the frame transmission time, so that the configuration modification performed by the target chip is completed before the frame end of the target data; and after the configuration modification of the target chip is completed, receiving new target data output by the target chip after the configuration modification is completed through the second thread, and continuing to test the target chip based on the new target data. According to the method and the device, the problem that an abnormal condition occurs in automatic testing due to the fact that the configuration write-in time sequence of the chip does not meet the requirement of the automatic testing in related technologies is solved.

Description

Technical Field

[0001] This application relates to the field of semiconductor testing technology, and more specifically, to a semiconductor testing device and its automated testing method and apparatus. Background Technology

[0002] During chip manufacturing testing, some tests require dynamically modifying the chip's configuration information, such as frame rate, exposure time, gain, and window cropping, while the chip continuously outputs multiple frames of image data. Semiconductor testing equipment (such as ATE (Automatic Test Equipment)) typically writes the corresponding configuration information to the chip's registers via I2C or SPI bus. After the configuration information is written to the registers, the chip internally initiates corresponding calculations or processing flows based on this information and outputs the calculation results or operating status for the semiconductor testing equipment to read and determine whether the chip passes the test. If the read calculation results or operating status are abnormal, the semiconductor testing equipment will usually determine that the chip has failed the test.

[0003] However, dynamically modifying the chip's configuration information during the testing process places high demands on the register write timing; that is, the semiconductor testing equipment must complete the register write before the end of the current frame of image data arrives. If the register write occurs after the end of the frame, it may cause the automated test to fail.

[0004] As can be seen from the above, the problem of abnormal situations occurring in automated testing due to the chip's configuration write timing not meeting the requirements of automated testing still needs to be resolved. Summary of the Invention

[0005] This application provides an automated testing method, apparatus, and semiconductor testing equipment, which can solve the problem in related technologies where abnormal situations occur during automated testing due to the chip's configuration write timing not meeting the automated testing requirements. The technical solution is as follows: According to one aspect of this application, an automated testing method is performed by a semiconductor testing device, the semiconductor testing device creating a first thread for performing configuration modifications and a second thread for performing data acquisition. The method includes: receiving target data output by a target chip through the second thread to test the target chip based on the target data; during the testing of the target chip based on the target data, if it is determined that configuration modifications to the target chip are required, determining a frame transmission time based on the target data when the target chip has no frame synchronization pin; the frame transmission time is used to indicate the transmission time of each frame of the target data; modifying the configuration of the target chip through the first thread based on the frame transmission time, such that the configuration modification of the target chip is completed before the end of the frame of the target data; after the target chip completes the configuration modification, receiving new target data output by the target chip after the configuration modification is completed through the second thread to continue testing the target chip based on the new target data.

[0006] According to one aspect of this application, an automated testing apparatus is deployed in a semiconductor testing device, the semiconductor testing device creating a first thread for performing configuration modifications and a second thread for performing data acquisition. The apparatus includes: a data receiving module, configured to receive target data output by a target chip through the second thread, so as to test the target chip based on the target data; a time determination module, configured to, during the testing of the target chip based on the target data, if it is determined that configuration modifications to the target chip are required, determine a frame transmission time based on the target data when the target chip has no frame synchronization pin; the frame transmission time is used to indicate the transmission time of each frame of the target data; a configuration writing module, configured to modify the configuration of the target chip through the first thread based on the frame transmission time, so that the configuration modification performed by the target chip is completed before the end of the frame of the target data; and an automated testing module, configured to, after the target chip has completed the configuration modification, receive new target data output by the target chip after the configuration modification is completed through the second thread, so as to continue testing the target chip based on the new target data.

[0007] According to one aspect of this application, a semiconductor testing apparatus includes at least one processor and at least one memory, wherein the memory stores a computer program that, when executed by the processor, implements the automated testing method as described above.

[0008] According to one aspect of this application, a storage medium having a computer program stored thereon, which, when executed by one or more processors, implements the automated testing method as described above.

[0009] According to one aspect of this application, a computer program product includes a computer program that, when executed by one or more processors, implements the automated testing method described above.

[0010] The beneficial effects of the technical solution provided in this application are: In the above technical solution, based on a first thread created by the semiconductor testing equipment for performing configuration modifications and a second thread for data acquisition, the semiconductor testing equipment continuously acquires multiple frames of target data output by the target chip through the second thread. During the testing of the target chip based on the current frame of target data, if it is determined that configuration modifications are needed, the frame transmission time is determined based on the target data, even if the target chip lacks a frame synchronization pin. Subsequently, based on the frame transmission time, the semiconductor testing equipment performs configuration modifications on the target chip through the first thread, ensuring that the configuration modifications are completed before the end of the current frame of target data. Therefore, even if the target chip does not have a reserved frame synchronization pin, the semiconductor testing equipment can still achieve precise control over the chip's configuration write timing based on the frame transmission time during the testing of the target chip based on the current frame of target data. This reduces the risk of automated test failures caused by the configuration write timing crossing the frame end boundary, improving the stability, accuracy, and production test yield of automated tests. This effectively solves the problem in related technologies where abnormal situations occur in automated tests due to the chip's configuration write timing not meeting the automated test requirements. Attached Figure Description

[0011] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments of this application will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0012] Figure 1 This is a schematic diagram based on the implementation environment involved in this application; Figure 2 yes Figure 1 A hardware structure diagram of an automated testing system used in an implementation environment, in one embodiment; Figure 3 This is a flowchart illustrating an automated testing method according to an exemplary embodiment; Figure 4 This is a flowchart illustrating another automated testing method according to an exemplary embodiment; Figure 5 yes Figure 3 A flowchart of step 350 in one embodiment corresponds to the following example; Figure 6 This is a schematic diagram illustrating the transmission timing of several frames of target data according to an exemplary embodiment; Figure 7 yes Figure 3 A flowchart of step 350 in one embodiment corresponds to the following example; Figure 8 This is a flowchart illustrating another automated testing method according to an exemplary embodiment; Figures 9 to 10 This is a schematic diagram illustrating the specific implementation of an automated testing method in an application scenario; Figure 11 This is a structural block diagram of an automated testing apparatus according to an exemplary embodiment; Figure 12 This is a structural block diagram of a semiconductor testing device according to an exemplary embodiment. Detailed Implementation

[0013] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0014] Those skilled in the art will understand that, unless specifically stated otherwise, the singular forms “a,” “an,” “the,” and “the” used herein may also include the plural forms. It should be further understood that the term “comprising” as used in this disclosure means the presence of the stated features, integers, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. It should be understood that when we say an element is “connected” or “coupled” to another element, it can be directly connected or coupled to the other element, or there may be intermediate elements. Furthermore, “connected” or “coupled” as used herein can include wireless connections or wireless coupling. The term “and / or” as used herein includes all or any units and all combinations of one or more associated listed items.

[0015] As mentioned earlier, semiconductor testing equipment needs to complete register writing before the end of the current frame of image data arrives. If register writing occurs after the end of the frame, it may cause automated testing to fail.

[0016] In other words, the testing process of dynamically modifying configuration information places high demands on register write timing. Specifically, the synchronization timing used by the chip to trigger calculations or processing flows is often related to the frame boundaries of image data. For example, using the end of the image data frame as the synchronization trigger point can be understood as the chip initiating the corresponding calculation or processing flow based on the configuration information upon detecting the end of that frame. Under this synchronization triggering mechanism, in order for the calculation or processing flow initiated by the chip to be synchronized at the end of the current frame of image data to use the new configuration information, the semiconductor testing equipment needs to complete the register writing of the configuration information before the end of the current frame of image data arrives. If the register writing of the configuration information occurs after the end of the frame, the synchronization trigger point (i.e., the end of the current frame of image data) may be missed, causing the chip to still use the old configuration information for calculations or processing flows. Consequently, the semiconductor testing equipment will be unable to obtain the calculation results or working status corresponding to the new configuration information, ultimately causing automated testing to fail.

[0017] In addition, image data often has a transmission delay inside semiconductor testing equipment, and this transmission delay is not fixed. This makes it difficult for the semiconductor testing equipment to guarantee that the writing of configuration information is completed before the end of the frame when it performs the register writing operation of configuration information after receiving the image data output by the chip.

[0018] As can be seen from the above, there are still defects in the relevant technologies, such as the chip configuration writing timing not meeting the requirements of automated testing, which leads to abnormal situations in automated testing.

[0019] Therefore, this application provides an automated testing method that can precisely control the configuration writing timing of the chip, thereby meeting the requirements of automated testing and avoiding abnormal situations during automated testing. Accordingly, the automated testing method is applicable to automated testing devices, which can be deployed on semiconductor testing equipment, such as automated test equipment (ATE), CIS (CMOS Image Sensor) testing equipment, etc.

[0020] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0021] Figure 1 This is a schematic diagram of an implementation environment involved in an automated testing method. It should be noted that this implementation environment is merely an example adapted to this application and should not be considered as providing any limitation on the scope of use of this application.

[0022] exist Figure 1The implementation environment includes an automated test system 100, which includes semiconductor test equipment 110 and a target chip 130.

[0023] Specifically, the semiconductor testing equipment 110 has a first thread for performing configuration modifications and a second thread for performing data acquisition. The second thread acquires target data output by the target chip 130 to test the target chip based on this target data. The first thread also modifies the configuration of the target chip so that, after the configuration modification is completed, the target chip outputs new target data based on the new configuration information. For example, the semiconductor testing equipment 110 can be an ATE testing equipment or a CIS testing equipment.

[0024] The target chip 130 is used to receive configuration information from the semiconductor test equipment 110, and output corresponding target data to the semiconductor test equipment 110 based on the configuration information. For example, before the configuration is modified, the target data of the current frame is output based on the old configuration information; after the configuration is modified, the target data of the next frame is output based on the new configuration information. For example, the target chip 130 can be a DUT (Device Under Test), a CIS chip, a display driver chip, etc.

[0025] In some embodiments, such as Figure 2 As shown, the semiconductor testing equipment is a CIS testing equipment, and the target chip is a CIS chip. Communication connections are established between the semiconductor testing equipment and the CIS chip through a control interface and an image transmission interface, respectively. The control interface can be an I2C interface or an SPI interface. The semiconductor testing equipment can write configuration information to the CIS chip through the control interface, and can also obtain calculation results or operating status of the CIS chip through the control interface. The image transmission interface is used to transmit the image data (i.e., target data) output by the CIS chip.

[0026] Based on this, semiconductor testing equipment can receive multiple frames of image data continuously output by the CIS chip through the image transmission interface, and acquire these multiple frames of image data through a second thread. Automated testing of the CIS chip can then be performed based on this multi-frame image data. During the automated testing of the CIS chip based on the current frame of image data, if it is determined that configuration modifications to the CIS chip are necessary, the frame transmission time can be determined based on the current frame of image data. Configuration information can then be sent to the control interface through the first thread based on this frame transmission time, and the control interface can write this configuration information to the CIS chip. This ensures that the configuration modifications to the CIS chip are completed before the end of the current frame of image data, thereby guaranteeing that the configuration writing timing meets the test requirements of the chip synchronously triggering internal calculations or processing flows at the end of the frame. This, in turn, helps improve the accuracy and success rate of automated testing.

[0027] Therefore, based on the above-mentioned automated testing system, it is possible to achieve precise control over the chip configuration write timing, reduce the risk of automated test failure caused by the configuration write timing crossing the frame tail boundary, improve the stability, accuracy and production test yield of automated testing, and thus effectively solve the problem in related technologies where abnormal situations occur in automated testing due to the chip configuration write timing not meeting the automated testing requirements.

[0028] Please see Figure 3 This application provides an automated testing method applicable to semiconductor testing equipment, such as ATE testing equipment or CIS testing equipment. See also: Figure 1 As shown in the implementation environment, this semiconductor testing equipment can be deployed in an automated testing system, the block diagram of which can be as follows: Figure 2 As shown.

[0029] In the following method embodiments, for ease of description, the semiconductor testing equipment is used as the execution subject of each step of the method, but this does not constitute a specific limitation.

[0030] like Figure 3 As shown, the method may include the following steps: Step 310: Collect the target data output by the target chip through the second thread, and test the target chip based on the target data.

[0031] First, it should be noted that the semiconductor test equipment creates a first thread for performing configuration modifications and a second thread for performing data acquisition.

[0032] Semiconductor testing equipment can refer to testing equipment used to execute automated testing processes, which can send configuration information to the target chip, read automated test results, collect target data of the target chip, etc., in order to complete the testing of the target chip.

[0033] Furthermore, the first and second threads can run within the semiconductor testing equipment to achieve parallel processing of data acquisition and configuration modification within the same equipment. This division of labor reduces the probability of configuration modification and data acquisition blocking each other, thereby improving the responsiveness and stability of the automated testing process to frame timing.

[0034] In some embodiments, the first thread can be used to perform configuration modification operations related to automated testing. For example, the configuration modification operation may be to write configuration information to the target chip to modify the target chip's configuration. In other embodiments, the first thread can also be used to perform other operations related to automated testing. These other operations include, but are not limited to, obtaining test instructions, determining whether configuration modification of the target chip is needed based on the test instructions, and reading the automated test results fed back by the target chip. It should be noted that the configuration information may include the register address of the target chip to be written and its corresponding register configuration value, used to configure the target chip's frame rate, exposure, gain, or other parameters related to the target data output. The test instructions may be test commands issued by a host computer or test commands generated locally by the semiconductor test equipment.

[0035] In some embodiments, the second thread can be used to perform data acquisition operations related to automated testing. For example, the data acquisition operations include, but are not limited to: acquiring target data output by the target chip, detecting the frame header and frame tail of the target data, recording the frame header timestamp and frame tail timestamp of the target data, etc.

[0036] Secondly, it should be noted that the target chip can refer to the chip to be tested or the module to be tested containing the chip. For example, the target chip can be an image sensor module (i.e., a CIS chip) or various display driver chips. It can output corresponding target data (such as several frames of image data) based on the configuration information issued by the semiconductor test equipment during the test process, and feed back the automated test results (such as calculation results or working status) to the semiconductor test equipment.

[0037] Step 330: During the testing of the target chip based on the target data, if it is determined that the target chip needs to be modified, then the frame transmission time is determined based on the target data if the target chip does not have a frame synchronization pin.

[0038] The frame transmission time is used to indicate the transmission time of each frame of target data.

[0039] In some embodiments, the frame transmission time of the target data is calculated based on the frame header timestamp and frame tail timestamp of the target data.

[0040] It is understandable that the target data output by the target chip can be transmitted in frames. Each frame of target data has a clear start and end boundary at the transmission level. For example, a frame of target data includes a frame header identifier, intra-frame data, and a frame tail identifier.

[0041] Therefore, when the semiconductor testing equipment acquires the target data of the current frame through the second thread, it can record the time when the target data frame header of the current frame is received (i.e., when a frame header identifier is received to indicate the target data frame header) and the time when the target data frame tail of the current frame is received (i.e., when a frame tail identifier is received to indicate the target data frame tail) and the tail of the current frame is received (i.e., when a frame tail identifier is received to indicate the target data frame tail) and the tail of the current frame is received.

[0042] In other words, the frame header timestamp of the current frame of target data can be used to characterize the time when the frame header of the current frame of target data arrives at the semiconductor test equipment, and the frame tail timestamp of the current frame of target data can be used to characterize the time when the frame tail of the current frame of target data arrives at the semiconductor test equipment. Therefore, the difference between the frame header timestamp and the frame tail timestamp of the current frame of target data reflects the duration of the current frame of target data from the time the frame header arrives at the semiconductor test equipment to the time the frame tail arrives at the semiconductor test equipment. It can also be considered that the difference between the frame header timestamp and the frame tail timestamp of the current frame of target data reflects the transmission time of the current frame of target data on the semiconductor test equipment, that is, the frame transmission time determined based on the current frame of target data.

[0043] In this way, even if the target chip does not have a reserved frame synchronization pin, the semiconductor test equipment can still provide a basis for the subsequent precise control chip configuration writing timing based on the frame transmission time of the target data.

[0044] It should be noted that in other embodiments, some target chips have a frame synchronization pin. In this case, these target chips can directly obtain the frame header of the target data through the frame synchronization pin, thereby achieving precise control of the chip's configuration write timing without having to determine the corresponding frame transmission time of the target data. This will be described in more detail below and will not be repeated here.

[0045] In some embodiments, the acquisition of the frame header timestamp and frame tail timestamp of the target data is based on the second thread registering the target event for the first thread.

[0046] Specifically, such as Figure 4 As shown, the above method may further include the following steps: Step 410: Register the target event for the first thread in the second thread.

[0047] Step 430: If the second thread is detected to have received the target data frame header, record the frame header timestamp of the target data in the target event.

[0048] Step 450: If the second thread detects that the target data frame tail has been received, record the frame tail timestamp of the target data in the target event.

[0049] As mentioned earlier, target data often experiences transmission delays within semiconductor testing equipment, and these delays are not fixed. This makes it difficult for the semiconductor testing equipment to guarantee that the configuration information is written to the register before the end of the frame when it receives the image data output by the chip and then performs the configuration information register write operation. To address this, during the transmission of target data from the driver layer to the application layer of the semiconductor testing equipment, the equipment can coordinate with interrupts generated in the driver layer and target events registered in the second thread in the application layer to carry the frame header timestamp and frame tail timestamp of the target data in the target information.

[0050] First, when the driver layer receives the target data frame header and frame tail, the driver layer generates a frame header interrupt and a frame tail interrupt respectively, and sets the frame header timestamp of the target data in the frame header interrupt and the frame tail timestamp of the target data in the frame tail interrupt respectively.

[0051] Then, in the application layer, the created second thread continuously receives target data, as well as frame header interrupts and frame tail interrupts related to the target data, from the driver layer. On the one hand, if a frame header interrupt is received, it can be determined that the second thread has received the frame header of the target data, and the frame header timestamp of the target data set in the frame header interrupt is recorded in the target event. On the other hand, if a frame tail interrupt is received, it can be determined that the second thread has received the frame tail of the target data, and the frame tail timestamp of the target data set in the frame tail interrupt is recorded in the target event.

[0052] Based on the above process, the target event carries the frame header timestamp and frame tail timestamp of the target data.

[0053] This approach not only reduces the transmission delay of target data within the semiconductor testing equipment, but also ensures the accuracy of the frame header and frame tail timestamps, thereby improving the precision of frame transmission time.

[0054] Continue reading Figure 4 After step 450, the above method may further include the following steps: Step 470: Receive at least one target event sent by the second thread through the first thread.

[0055] Step 490: Extract the frame header timestamp and frame tail timestamp of the corresponding target data from each target event.

[0056] Therefore, assuming the target event is registered by the second thread for the first thread, the semiconductor testing equipment can obtain the frame header timestamp and frame tail timestamp of at least one frame of target data through the interaction between the first and second threads. Then, based on the frame header timestamps and frame tail timestamps of several frames of target data, the corresponding frame transmission time can be calculated.

[0057] Step 350: Based on the frame transmission time, the first thread modifies the configuration of the target chip so that the configuration modification of the target chip is completed before the end of the target data frame.

[0058] As mentioned earlier, the frame transmission time essentially indicates the duration from the arrival of a target data frame at the semiconductor test equipment to its arrival at the end of the frame. Therefore, in some embodiments, the semiconductor test equipment can ensure that configuration modifications made to the target chip are completed before the end of the current frame of target data, based on the real-time calculated frame transmission time. This approach helps improve the accuracy of the frame transmission time.

[0059] Specifically, this means that during the testing of the target chip based on the current frame of target data, the configuration modification of the target chip based on the frame transmission time determined by the current frame of target data can ensure that the configuration modification of the target chip can be completed before the end of the current frame of target data reaches the semiconductor testing equipment.

[0060] In some embodiments, automated testing can predict the frame transmission times of subsequent target data frames based on the frame transmission time determined by the current frame of target data. During the testing of the target chip based on a subsequent frame of target data, the predicted frame transmission times can be used to ensure that any configuration modifications required by the target chip are completed before the end of that particular frame. This approach helps reduce computational resources and improves the efficiency of automated testing.

[0061] Specifically, such as Figure 5 As shown, in one possible implementation, step 350 may include the following steps: Step 351: Determine the frame interval based on the frame transmission time of two adjacent frames of target data.

[0062] The frame interval can refer to the periodic interval in time between two adjacent frames of target data. For example, the periodic interval can refer to the time interval between the headers of two adjacent frames of target data or the time interval between the tails of two adjacent frames of target data. No specific limitation is made here.

[0063] Since the frame transmission time reflects the duration for the frame header / frame tail of two consecutive frames of target data from the target chip to reach the semiconductor test equipment, the semiconductor test equipment can calculate the corresponding frame interval after obtaining the frame transmission time of two consecutive frames of target data.

[0064] Step 353: Based on the frame interval and the frame header timestamp and frame tail timestamp of the target data in the current frame, predict the frame header timestamp and frame tail timestamp of the target data in the next few frames.

[0065] In other words, if the frame interval is equal to the time interval between the headers of two adjacent target data frames, then the timestamp of the header of the next target data frame is equal to the timestamp of the header of the current target data frame plus the frame interval. Similarly, if the frame interval is equal to the time interval between the tails of two adjacent target data frames, then the timestamp of the tail of the next target data frame is equal to the timestamp of the tail of the current target data frame plus the frame interval.

[0066] Figure 6 The transmission timing diagram of several frames of target data is shown. Figure 6 In the diagram, the horizontal axis represents the time axis. Along the time axis, the target chip sequentially outputs the first frame, the second frame, and the third frame of target data. Correspondingly, the frame headers and frame tails of the first, second, and third frames of target data arrive at the semiconductor testing equipment in sequence.

[0067] like Figure 6 As shown, for any frame of target data, the semiconductor test equipment can obtain the frame header timestamp (vertically marked and labeled "frame header timestamp" in the figure) through the target event. Similarly, the frame tail timestamp (vertically marked and labeled "frame tail timestamp" in the figure) can be obtained through the target event. Here, the frame transmission time = frame tail timestamp of any frame of target data - frame header timestamp.

[0068] Figure 6 The document also shows a frame interval, which is determined by the difference between the frame header timestamps of two adjacent frames of target data. Of course, in other embodiments, the frame interval can also be determined by the difference between the frame tail timestamps of two adjacent frames of target data.

[0069] Therefore, based on the frame interval and the frame header and frame tail timestamps of the current frame of target data, the semiconductor testing equipment can further predict the frame header and frame tail timestamps of the following frames, so as to facilitate the subsequent determination of the chip configuration writing timing. For example, based on the frame interval and the frame header and frame tail timestamps of the first frame of target data, the frame header and frame tail timestamps of the second frame of target data, the frame header and frame tail timestamps of the third frame of target data, ..., the frame header and frame tail timestamps of the Nth frame of target data can be predicted.

[0070] Step 355: Use the frame header timestamp and / or frame tail timestamp of the target data in the following frames as the configuration write time, and modify the configuration of the target chip based on the configuration write time.

[0071] The configuration write time describes the configuration write timing of the chip and is the data basis for the semiconductor test equipment to indicate that the configuration modification of the target chip must be completed before the end of the target data frame.

[0072] As mentioned earlier, under a synchronization triggering mechanism that uses the frame end as the synchronization trigger point, the semiconductor test equipment must ensure that the configuration information is written before the end of the current frame of image data. Therefore, in some embodiments, the configuration write time is related to the frame end timestamp of the target data in the following several frames. That is to say, assuming that the target chip will modify its configuration during the testing process based on the second frame of target data, the semiconductor test equipment can ensure that the configuration modification made by the target chip can be completed before the end of the target data in a certain frame by using the pre-stored configuration write time (i.e., the predicted frame end timestamp of the second frame of target data).

[0073] Continue reading Figure 6 ,exist Figure 6 As can be seen, there is a time interval between the first and second frames of target data. During this time (i.e., the time interval), the second thread does not collect the second frame of target data output by the target chip. In other words, the target chip does not output the second frame of target data during this time. It can be understood that if the first thread continues to modify the configuration of the target chip during this time and ensures that the modification is completed within this time, it can still ensure that the target chip can output the second frame of target data based on the new configuration information. Therefore, in some embodiments, the configuration write time is related to the frame header timestamp of the subsequent several frames of target data. That is to say, assuming that the target chip will modify its configuration during the testing process based on the subsequent second frame of target data, the semiconductor testing equipment can ensure that the configuration modification of the target chip still meets the requirements of automated testing based on the pre-stored configuration write time (i.e., the predicted frame header timestamp of the subsequent third frame of target data).

[0074] Of course, in other embodiments, the configuration write time is not limited to being related to 1 times the frame interval. The configuration write time can also be determined based on the frame header or frame tail timestamp of the current frame of target data and N times the frame interval, so that the target chip has sufficient time to modify the configuration to meet the requirements of automated testing. This is not a specific limitation. It should be noted that when the configuration write time is related to N times the frame interval, for the first N frames of target data, the target chip outputs based on the old configuration information. From the (N+1)th frame of target data onwards, the target chip outputs based on the new configuration information. Here, N is a positive integer greater than 1 and can be flexibly set according to the actual needs of the application scenario; it is not limited here.

[0075] The following is combined with Figure 7 The process of modifying the configuration of a target chip based on the configuration write time is explained in detail: Specifically, such as Figure 7 As shown, in one possible implementation, step 355, which modifies the configuration of the target chip based on the configuration write time, may include the following steps: Step 510: Register a timer in the first thread based on the configuration write time.

[0076] In other words, by registering, the timer's stop timer flag is set to the configuration write time. In other words, the timer stops timing when it detects that the timer value is equal to the configuration write time, meaning that the timer's timer value does not exceed the configuration write time.

[0077] After completing the timer registration based on the configuration write time, the configuration write timing can be described using the configuration write time. In some embodiments, the configuration write time is used to instruct the first thread to end the configuration modification of the target chip, i.e., to execute step 530. In this case, the configuration write timing of the target chip ends at the end of the target data frame. In other embodiments, the configuration write time is used to instruct the first thread to start the configuration modification of the target chip, i.e., to execute step 550. In this case, the configuration write timing of the target chip starts at the beginning of the target data frame. It should be noted that regardless of whether the configuration write timing of the target chip starts at the beginning of the target data frame or ends at the end of the target data frame, the requirements for automated testing can be met, i.e., the configuration modification performed by the target chip must be completed before the end of the target data frame.

[0078] Step 530: After starting the configuration modification of the target chip through the first thread, start the timer. If the timer's count value is equal to the configuration write time, then end the configuration modification of the target chip.

[0079] In other words, when the timer's countdown value equals the configuration write time, the timer will stop counting and reset to clear the countdown value to zero. This is considered as the target chip having completed the configuration modification within the configuration write time. It can also be understood as the configuration modification performed by the target chip having been completed within the configuration write timing indicated by the configuration write time.

[0080] Step 550: After the timer completes registration, start the timer. If the timer's count value is equal to the configuration write time, start the configuration modification of the target chip through the first thread.

[0081] In other words, when the timer's countdown value equals the configuration write time, the timer will stop counting and reset to zero. At this time, the target chip starts configuration modification. Since the target chip's next configuration modification depends on the timer registered by the new configuration write time, as long as the configuration write time is not updated, it can be fully guaranteed that the configuration modification performed by the target chip will be completed within the configuration write timing indicated by the current configuration write time.

[0082] Through the above process, even if the target chip does not have a reserved frame synchronization pin, the semiconductor test equipment can still achieve precise control over the chip's configuration write timing based on the frame transmission time while the target chip is being tested based on the current frame of target data. This reduces the risk of automated test failure caused by the configuration write timing crossing the frame tail boundary, improves the stability and accuracy of automated testing, and increases the production test yield. Thus, it can effectively solve the problem in related technologies where abnormal situations occur in automated testing due to the chip's configuration write timing not meeting the automated test requirements.

[0083] Please see Figure 8 In an exemplary embodiment, prior to step 330, the method may further include the following steps: Step 610: Obtain the test instructions sent by the host computer through the first thread.

[0084] The test instructions can be used to instruct semiconductor test equipment on how to test the target chip, i.e., automated test requirements. They can also be used to indicate whether the target chip needs configuration modifications during continuous output of target data. Notably, if the target chip requires configuration modifications, the test instructions carry configuration information so that the semiconductor test equipment can write this configuration information to the target chip during the chip configuration write timing.

[0085] In this embodiment, the test command is sent by the host computer. Of course, in other embodiments, the test command can also be generated locally by the semiconductor test equipment based on the pre-set automated test requirements, which is not a specific limitation.

[0086] For semiconductor testing equipment, after receiving the test command sent by the host computer, it can obtain the test command through the first thread and perform subsequent automated test-related processing based on the test command, including but not limited to: modification of the target chip configuration.

[0087] Step 630: Determine whether the target chip needs to be configured based on the test instructions.

[0088] As mentioned earlier, the test command can indicate whether the target chip needs to be configured during the continuous output of target data. Then, the semiconductor test equipment can determine whether the target chip needs to be configured based on the test command.

[0089] If it is determined that the target chip does not require configuration modifications, then continue testing the target chip based on the target data.

[0090] If it is determined that the target chip requires configuration modifications, proceed to step 650.

[0091] Step 650: Detect whether the target chip has a frame synchronization pin.

[0092] As mentioned earlier, some target chips can reserve a frame synchronization pin at the factory. This pin allows direct access to the target data's frame header, enabling precise control of the chip's configuration write timing without needing to determine the corresponding frame transmission time. Therefore, in this embodiment, before modifying the target device's configuration via the first thread, the semiconductor testing equipment needs to determine whether the target chip has a frame synchronization pin.

[0093] If the target chip is found to have no frame synchronization pin, it means that the semiconductor test equipment needs to determine the frame transmission time based on the target data. Then, return to step 330, that is, determine the frame transmission time based on the target data, and then modify the configuration of the target chip through the first thread based on the frame transmission time, so that the configuration modification of the target chip is completed before the end of the frame of the target data.

[0094] If the target chip is detected to have a frame synchronization pin, it means that the semiconductor test equipment does not need to determine the frame transmission time based on the target data, and then steps 670 to 690 are executed.

[0095] In other words, this embodiment can be adapted to both target chips with "no frame synchronization pin" and target chips with "frame synchronization pin". It can achieve precise control of configuration writing timing under both types of hardware conditions, thereby improving the versatility and deployability of the automated testing solution.

[0096] Step 670: Identify the frame header and frame tail of the target data by monitoring the signal edge transition of the frame synchronization pin.

[0097] Here, "signal edge" can refer to the rising or falling edge of the signal corresponding to the header or tail of the target data frame; no specific limitation is made here. It should be noted that both rising and falling edge transitions can be understood as a change in the level of the frame synchronization pin. For example, a rising edge transition essentially means that the frame synchronization pin has changed from a low level to a high level.

[0098] Based on this, as the target chip outputs target data to the semiconductor test equipment, the signal edge of the frame synchronization pin configured on the target chip will change with the arrival of the frame header or frame tail of the target data. The semiconductor test equipment can then detect the arrival of the frame header or frame tail of the target data by monitoring the signal edge change.

[0099] Step 690: Based on the frame header of the identified target data, the configuration of the target chip is modified through the first thread, and based on the frame tail of the identified target data, the configuration modification of the target chip is completed before the frame tail of the target data.

[0100] In other words, based on the frame header of the identified target data, the semiconductor testing equipment determines that the current frame of target data has started to be transmitted, and can then begin to modify the configuration of the target chip. Based on the frame tail of the identified target data, the semiconductor testing equipment determines that the current frame of target data has been transmitted, and can then end the configuration modification of the target chip, which is considered to be the completion of the configuration modification of the target chip. Then, the target chip can output the next frame of target data to the semiconductor testing equipment based on the new configuration information.

[0101] Under the above embodiments, the semiconductor test equipment can use the level change of the frame synchronization pin as a reference for the configuration writing timing, and more precisely control the configuration modification operation to be completed before the end of the target data frame. This improves the certainty that the new configuration information is written and latched by the target chip before the frame end synchronization triggers the subsequent process, ensuring that the configuration modification of the target chip meets the requirements of automated testing and improving the stability and success rate of automated testing.

[0102] Figures 9 to 10 This is a schematic diagram illustrating the specific implementation of an automated testing method in an application scenario. In this scenario, the automated testing system includes a host computer, semiconductor testing equipment, and a target chip.

[0103] The system comprises a host computer for issuing test commands, a semiconductor testing device for executing configuration writing and data acquisition operations, and a target chip for continuously outputting target data (e.g., image data) and, after initiating internal calculations or processing under a frame end synchronization trigger mechanism, outputting automated test results. The semiconductor testing device can internally run a control thread (i.e., the first thread) and an image acquisition thread (i.e., the second thread). The control thread is responsible for receiving test commands and writing configuration information to the target chip via I2C or SPI. The image acquisition thread is responsible for continuously receiving target data output by the target chip and can provide feedback to the control thread based on the target data, information related to frame synchronization timing (e.g., frame header timestamp or frame end timestamp). This allows the control thread to precisely control the configuration writing timing, ensuring that the configuration information is written before the frame end of the target data.

[0104] Figure 9 This demonstrates a test procedure for a target chip with a frame synchronization pin in an application scenario, such as... Figure 9 As shown, when the target chip has a reserved frame synchronization pin, the semiconductor test equipment can use the frame synchronization pin to achieve precise control of the configuration writing timing.

[0105] Specifically, after receiving a register setting command (i.e., a test instruction indicating that the target chip needs configuration modification), the control thread continuously monitors the level changes of the frame synchronization pin. When the level change of the frame synchronization pin meets the first set condition (e.g., rising edge transition), the frame header is identified, and it can be considered that the target data has entered a new frame cycle, that is, the current frame of target data has started to be transmitted. The semiconductor test equipment can then perform the configuration modification operation of writing configuration information to the relevant registers in the target chip. When the level change of the frame synchronization pin meets the second set condition (e.g., falling edge transition), the frame tail is identified, and it can be considered that the target data has ended the current frame cycle, that is, the current frame of target data has been transmitted. The semiconductor test equipment can then stop the configuration modification operation of writing configuration information to the relevant registers in the target chip, that is, it is considered that the target chip has completed the configuration modification before the frame tail of the target data.

[0106] Figure 10 This demonstrates a test procedure for a target chip without a reserved frame synchronization pin in an application scenario, such as... Figure 10 As shown, when the target chip does not have a reserved frame synchronization pin, the semiconductor test equipment will not be able to directly obtain the frame synchronization signal. Therefore, the semiconductor test equipment can achieve precise control of the configuration writing timing by having the image acquisition thread and the control thread cooperate with each other and combining the frame transmission time.

[0107] Specifically, after receiving the set register command, the control thread can first register a target event in the image acquisition thread to obtain the frame header timestamp of the current frame of target data. The control thread then receives the target event sent by the image acquisition thread and can use the frame header timestamp of the current frame of target data carried in the target event to calculate the frame interval. Then, using the frame interval as a time base and combining it with the frame header timestamp of the current frame of target data, the frame header timestamps of the subsequent frames are predicted as the configuration write time, and a timer is registered accordingly. Finally, configuration information can be written to the target chip based on the timer's timing value and the configuration write time. Specifically, if the timer's timing value is detected to be equal to the configuration write time, the new configuration information is written to the relevant registers in the target chip through the I2C interface or SPI interface.

[0108] In this application scenario, the automated testing method exhibits good compatibility and deployability. When the target chip has a reserved frame synchronization pin, the semiconductor testing equipment can employ a synchronization triggering mechanism that monitors the level changes of the frame synchronization pin to achieve precise control of the configuration write timing. When the target chip does not have a frame synchronization pin, the semiconductor testing equipment can still ensure that the configuration modifications made by the target chip are completed before the end of the frame through a frame tail synchronization triggering mechanism determined by the frame transmission time. This allows for precise control of the configuration write timing under different hardware conditions, reducing the probability of automated test failure and improving the success rate, stability, accuracy, and versatility of automated testing.

[0109] Compared to related technologies, this technical solution can determine the frame transmission time by continuously receiving target data output by the target chip in the second thread using semiconductor testing equipment. Subsequently, based on this frame transmission time, the first thread writes configuration information to the target chip. This ensures that the configuration information is written to the target chip before the chip's internal calculation or processing flow starts under the frame tail synchronization trigger mechanism, thereby guaranteeing that the target chip can continue to output new target data using the new configuration information for subsequent automated testing. This not only helps reduce the risk of automated test failures caused by configuration write timing crossing the frame tail boundary, but also effectively improves the stability, accuracy, and production test yield of automated testing.

[0110] It should be understood that although the steps in the flowcharts of the accompanying figures are shown sequentially as indicated by the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the accompanying figures may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times, and their execution order is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the sub-steps or stages of other steps.

[0111] The following are embodiments of the apparatus described in this application, which can be used to execute the automated testing method involved in this application. For details not disclosed in the apparatus embodiments of this application, please refer to the method embodiments of the automated testing method involved in this application.

[0112] Please see Figure 11 This application provides an automated testing device 900, which is deployed on a semiconductor testing device. The semiconductor testing device has a first thread for performing configuration modifications and a second thread for performing data acquisition.

[0113] The automated testing device 900 includes, but is not limited to: a data receiving module 910, a time determination module 930, a configuration writing module 950, and an automated testing module 970.

[0114] Specifically, the data receiving module 910 is used to receive target data output by the target chip through a second thread, so as to test the target chip based on the target data.

[0115] The timing determination module 930 is used to determine the frame transmission time based on the target data when it is determined that the target chip needs to be modified during the testing of the target chip based on the target data, in the absence of a frame synchronization pin on the target chip; the frame transmission time is used to indicate the transmission time of each frame of target data.

[0116] The configuration writing module 950 is used to control the semiconductor test equipment to modify the configuration of the target chip through the first thread based on the frame transmission time, so that the configuration modification of the target chip is completed before the end of the target data frame.

[0117] The automated testing module 970 is used to receive new target data output by the target chip after the target chip has completed the configuration modification through a second thread, so as to continue testing the target chip based on the new target data.

[0118] It should be noted that the automated testing device provided in the above embodiments is only illustrated by the division of the above functional modules when performing automated testing. In actual applications, the above functions can be assigned to different functional modules as needed. That is, the internal structure of the automated testing device will be divided into different functional modules to complete all or part of the functions described above.

[0119] Furthermore, the automated testing apparatus and automated testing method embodiments provided in the above embodiments belong to the same concept, and the specific way in which each module performs operations has been described in detail in the method embodiments, and will not be repeated here.

[0120] Please see Figure 12 This application provides a semiconductor testing device 4000, which may include: ATE testing device, CIS testing device, etc.

[0121] exist Figure 12 The semiconductor testing equipment 4000 includes at least one processor 4001 and at least one memory 4003.

[0122] Data interaction between the processor 4001 and the memory 4003 can be achieved through at least one communication bus 4002. This communication bus 4002 may include a path for transmitting data between the processor 4001 and the memory 4003. The communication bus 4002 can be a PCI (Peripheral Component Interconnect) bus or an EISA (Extended Industry Standard Architecture) bus, etc. The communication bus 4002 can be divided into an address bus, a data bus, a control bus, etc. For ease of illustration, only one thick line is used to represent it in the figure, but this does not indicate that there is only one bus or one type of bus.

[0123] Optionally, the semiconductor testing equipment 4000 may further include a transceiver 4004, which can be used for data interaction between the semiconductor testing equipment and other semiconductor testing equipment, such as sending and / or receiving data. It should be noted that in practical applications, the transceiver 4004 is not limited to one unit, and the structure of the semiconductor testing equipment 4000 does not constitute a limitation on the embodiments of this application.

[0124] Processor 4001 may be a CPU (Central Processing Unit), a general-purpose processor, a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. It can implement or execute the various exemplary logic blocks, modules, and circuits described in conjunction with the disclosure of this application. Processor 4001 may also be a combination that implements computational functions, such as including one or more microprocessor combinations, a combination of a DSP and a microprocessor, etc.

[0125] The memory 4003 may be a ROM (Read Only Memory) or other type of static storage device capable of storing static information and instructions, RAM (Random Access Memory) or other type of dynamic storage device capable of storing information and instructions, or an EEPROM (Electrically Erasable Programmable Read Only Memory), CD-ROM (Compact Disc Read Only Memory) or other optical disc storage, optical disc storage (including compressed optical discs, laser discs, optical discs, digital universal optical discs, Blu-ray discs, etc.), magnetic disk storage media or other magnetic storage devices, or any other medium capable of carrying or storing computer programs in the form of instructions or data structures and accessible by the semiconductor testing equipment 400, but not limited to these.

[0126] The memory 4003 stores a computer program, and the processor 4001 can read the computer program stored in the memory 4003 through the communication bus 4002.

[0127] The computer program is executed by one or more processors 4001 to implement the automated testing methods in the above embodiments.

[0128] Furthermore, this application provides a storage medium storing a computer program, which is executed by one or more processors to implement the automated testing method described above.

[0129] This application provides a computer program product, including a computer program that is executed by one or more processors to implement the automated testing method described above.

[0130] The above description is only a partial embodiment of this application. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of this application, and these improvements and modifications should also be considered within the scope of protection of this application.

Claims

1. An automated testing method, characterized in that, Performed by a semiconductor testing device, the semiconductor testing device having created a first thread for performing configuration modifications and a second thread for performing data acquisition, the method includes: The second thread collects the target data output by the target chip, and tests the target chip based on the target data. During the testing of the target chip based on the target data, if it is determined that the target chip needs to be modified in terms of configuration, then in the case that the target chip has no frame synchronization pin, the frame transmission time is determined based on the target data; the frame transmission time is used to indicate the transmission time of each frame of the target data. Based on the frame transmission time, the first thread modifies the configuration of the target chip so that the configuration modification of the target chip is completed before the end of the frame of the target data. After the target chip completes the configuration modification, the second thread collects the new target data output by the target chip after the configuration modification is completed, so as to continue testing the target chip based on the new target data.

2. The method as described in claim 1, characterized in that, Determining the frame transmission time based on the target data includes: Obtain the frame header timestamp and frame tail timestamp of at least one frame of the target data; The frame transmission time of the target data is calculated based on the frame header timestamp and frame tail timestamp of the target data.

3. The method as described in claim 2, characterized in that, The step of obtaining at least one frame header timestamp and frame tail timestamp of the target data includes: The first thread receives at least one target event sent by the second thread; the target event carries the frame header timestamp and frame tail timestamp of the target data; The frame header timestamp and frame tail timestamp of the corresponding target data are extracted from each of the target events.

4. The method as described in claim 3, characterized in that, Before receiving at least one target event sent by the second thread through the first thread, the method further includes: The second thread registers the target event for the first thread; If it is detected that the second thread has received the target data frame header, the frame header timestamp of the target data is recorded in the target event; If the second thread detects that the target data frame tail has been received, the frame tail timestamp of the target data is recorded in the target event.

5. The method as described in claim 1, characterized in that, The configuration modification of the target chip based on the frame transmission time via the first thread includes: The frame interval is determined based on the frame transmission time of two adjacent frames of target data; the frame interval refers to the time interval between the headers of two adjacent frames of target data or the time interval between the tails of two adjacent frames of target data. Based on the frame interval and the frame header timestamp and frame tail timestamp of the target data in the current frame, predict the frame header timestamp and frame tail timestamp of the target data in the next few frames; The frame header timestamp and / or frame tail timestamp of the target data in the following several frames are used as the configuration write time, and the configuration of the target chip is modified based on the configuration write time so that the configuration modification of the target chip is completed before the frame tail of the target data.

6. The method as described in claim 5, characterized in that, The step of modifying the configuration of the target chip based on the configuration write time, so that the configuration modification of the target chip is completed before the end of the frame of the target data, includes: Register a timer in the first thread based on the configured write time; After initiating the configuration modification of the target chip via the first thread, the timer is started. If the timer's countdown value is detected to be equal to the configuration write time, the configuration modification of the target chip is terminated; or After the timer completes registration, the timer is started. If the timer's count value is detected to be equal to the configuration write time, the configuration modification of the target chip is initiated through the first thread.

7. The method according to any one of claims 1 to 6, characterized in that, Before determining the frame transmission time based on the target data, the method further includes: The test instructions sent by the host computer are obtained through the first thread; Based on the test command, determine whether the target chip needs to be configured. If yes, check whether the target chip has the frame synchronization pin. If the target chip is found to lack the frame synchronization pin, then the step of determining the frame transmission time based on the target data is executed.

8. The method as described in claim 7, characterized in that, After detecting whether the target chip has the frame synchronization pin, the method further includes: If the target chip is detected to have the frame synchronization pin, the frame header and frame tail of the target data are identified by monitoring the signal edge transition of the frame synchronization pin. Based on the identified target data frame header, the first thread modifies the configuration of the target chip, and based on the identified target data frame tail, the configuration modification of the target chip is completed before the target data frame tail.

9. An automated testing device, characterized in that, Deployed in a semiconductor test equipment, the semiconductor test equipment creating a first thread for performing configuration modifications and a second thread for performing data acquisition, the apparatus includes: The data receiving module is used to receive target data output by the target chip through the second thread, so as to test the target chip based on the target data; The timing determination module is used to determine the frame transmission time based on the target data if it is determined that the target chip needs to be modified during the testing of the target chip based on the target data, in the case that the target chip has no frame synchronization pin; the frame transmission time is used to indicate the transmission time of each frame of the target data. A configuration writing module is used to modify the configuration of the target chip through the first thread based on the frame transmission time, so that the configuration modification of the target chip is completed before the end of the frame of the target data. An automated testing module is used to receive new target data output by the target chip after the target chip has completed the configuration modification through the second thread, so as to continue testing the target chip based on the new target data.

10. A semiconductor testing device, characterized in that, include: At least one memory and at least one processor; wherein, the memory stores a computer program; and when the computer program is executed by the processor, it implements the automated testing method as described in any one of claims 1 to 8.

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