Test fixture and preparation method thereof

Abstract

The invention relates to the technical field of semiconductors, in particular to a test fixture and a preparation method thereof.The test fixture comprises a buffer layer, a rewiring layer, a plurality of sets of test bonding pads and ports arranged on the rewiring layer which are distributed in a stacked mode, and during testing, the test bonding pads are in contact connection with an LED chip; the LED chip is electrically connected with the testing machine through the testing bonding pad, a connecting circuit in the rewiring layer and a port, compared with a probe structure, the testing bonding pad in the testing jig is in the shape of a convex block and is not prone to deformation, meanwhile, the buffer layer and the rewiring layer are distributed in a stacked mode, the elasticity modulus of the buffer layer is smaller than that of the rewiring layer, and the reliability of the testing jig is improved. When the test bonding pad is in corresponding contact with the electrode of the LED chip and generates certain extrusion force, the rewiring layer and the buffer layer can generate certain deformation under the action of the extrusion force, and the elastic deformation of the buffer layer is greater than that of the rewiring layer, so that a buffer effect is achieved, the problems of deformation of the test bonding pad, electrode scratches and the like are effectively reduced, and the service life of the LED chip is prolonged. And meanwhile, the test accuracy is ensured.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a test fixture and its preparation method. Background Technology

[0002] LED chips are solid-state semiconductor devices that convert electricity into light, offering advantages such as low power consumption, high brightness, and high luminous efficiency. During LED chip manufacturing, their photoelectric properties must be tested, and qualified chips are selected based on the test results to ensure product yield.

[0003] Currently, the main LED chip testing method is the probe-based LED electroluminescence testing method. The test end of the test fixture used in this method is a probe. However, the probe is prone to the following defects: when the probe contacts the electrode of the LED chip, it needs to withstand a certain amount of pressure. If the pressure is too large, it is easy to cause problems such as probe bending and scratches on the electrode surface; conversely, if the pressure is too small, it is easy to have a loose connection, which will affect the accuracy of the test. Summary of the Invention

[0004] To address the aforementioned shortcomings in the existing technology, the present invention provides a test fixture whose test pads are less prone to deformation and can reduce scratches, thereby ensuring test accuracy.

[0005] The technical solution adopted in this application is as follows: A test fixture for testing LED chips, characterized in that it comprises: Redundancy layer, including insulating layer and connection circuits distributed in insulating layer; A buffer layer is stacked on top of the redistribution layer, and the elastic modulus of the buffer layer is less than that of the insulating layer. Several sets of test pads, each set of test pads includes a positive electrode test pad and a negative electrode test pad, the shape and size of the positive electrode test pad and the negative electrode test pad are respectively matched with the shape and size of the positive electrode and the negative electrode of the LED chip; The contact end of the test pad is flush with or protrudes from the bottom surface of the redistribution layer. A port, located on the redistribution layer, is used to connect the connection circuit to an external test machine; During testing, the test pads are in contact with the LED chip, and the LED chip is electrically connected to the test equipment through the test pads, the connection circuit, and the port.

[0006] Its further feature is that, The test fixture also includes a support substrate, which is distributed on top of the buffer layer.

[0007] Furthermore, the insulating layer may be made of materials including but not limited to polyimide (PI), benzocyclobutene (BCB), poly(p-phenylenebenzodioxazole) (PBO), or photoresist, and the buffer layer may be made of materials including but not limited to silicone resin, polyurethane, or acrylate.

[0008] Furthermore, the thickness of the redistribution layer ranges from 15μm to 30μm, and the thickness of the buffer layer ranges from 5μm to 20μm.

[0009] Furthermore, the buffer layer covers the entire surface as a first continuous region, and / or the redistribution layer covers the entire surface as a second continuous region.

[0010] Furthermore, the redistribution layer has a plurality of first through slots, which are distributed in a grid pattern or in parallel strips, and / or the buffer layer has a plurality of second through slots, which are distributed in a grid pattern or in parallel strips, and the second through slots are connected to the first through slots to form a connecting slot.

[0011] Furthermore, the LED chip is an integrated chip, which includes at least three primary color light emitters: red light emitter, green light emitter, and blue light emitter. The light emitters are arranged side by side with intervals. The negative electrodes of the light emitters in the same integrated chip are connected to form a common cathode structure, or the positive electrodes of the light emitters in the same integrated chip are connected to form a common anode structure.

[0012] Furthermore, when the negative electrodes of the light-emitting elements in the integrated chip are connected to form a common cathode structure, each group of test pads includes at least three positive test pads and one negative test pad. When the positive electrodes of the light-emitting elements in the integrated chip are connected to form a common anode structure, each test fixture includes at least three negative test pads and one positive test pad.

[0013] Furthermore, the port includes at least a current input port, a current output port, a positive voltage port, and a negative voltage port. The current input port and the current output port are connected to the test pad through the connection circuit and are used to transmit current control signals to the LED chip to control the working state of the LED chip. The positive voltage port and the negative voltage port are used to obtain the test voltage.

[0014] A method for preparing a test fixture, characterized in that the method includes: A redistribution layer is prepared, the redistribution layer comprising at least one insulating layer and connection circuits distributed on the insulating layer; A buffer layer is prepared, wherein the elastic modulus of the buffer layer is less than that of the insulating layer; Using semiconductor technology, test pads are fabricated. Each set of test pads includes a positive test pad and a negative test pad. The shape and size of the positive test pad and the negative test pad are respectively matched with the shape and size of the positive electrode and the negative electrode of the LED chip. A port is provided, which is used to connect the connection circuit to an external test machine. Preparation methods include: A buffer layer, a redistribution layer, and several sets of test pads are prepared in sequence, and ports are set on the redistribution layer. The contact end of the test pad protrudes from the bottom surface of the redistribution layer, and the non-contact end of the test pad is electrically connected to the connection circuit and the port in sequence.

[0015] Its further feature is that, The buffer layer and / or the rewire layer cover the entire surface, forming a first continuous region and / or a second continuous region, respectively.

[0016] Furthermore, the redistribution layer is etched using photolithography and etching processes to form a first through-groove, and / or the buffer layer is etched using photolithography and etching processes to form a second through-groove.

[0017] Furthermore, the preparation of the redistribution layer includes: depositing insulating material layer by layer using a coating or film-coating process to form each insulating layer; and simultaneously, filling the etched holes of each insulating layer with conductive material using photolithography, etching, and deposition processes to form the connection circuit.

[0018] Furthermore, the insulating material includes, but is not limited to, polyimide (i.e., PI), benzocyclobutene (i.e., BCB), poly(p-phenylenebenzodioxazole) (i.e., PBO), or photoresist, and the elastic modulus of the insulating material is less than or equal to 3 GPa.

[0019] Furthermore, the preparation of the buffer layer includes: depositing a buffer material using an adhesive coating or film lamination process to form the buffer layer.

[0020] Furthermore, the elastic modulus of the buffer material is less than that of the insulating material, and the buffer material includes, but is not limited to, silicone resin, polyurethane or acrylate, and the elastic modulus of the buffer material is less than or equal to 100 MPa.

[0021] Furthermore, the test pads are prepared using photolithography, deposition, and stripping processes.

[0022] The above-mentioned solution of the present invention can achieve the following beneficial effects: Compared with the probe structure, the test pad in the test fixture of this application is convex in shape. When the test pad contacts the corresponding electrode of the LED chip and is subjected to a certain compressive force, the test pad itself is not easily deformed, effectively avoiding the problem of test pad deformation affecting test accuracy. At the same time, the test fixture of this application is provided with a layered buffer layer and a redistribution layer. The elastic modulus of the buffer layer is smaller than that of the redistribution layer. When the test pad contacts the corresponding electrode of the LED chip and is subjected to a certain compressive force, the redistribution layer and the buffer layer can undergo a certain deformation under the action of the compressive force, and the elastic deformation of the buffer layer is greater than that of the redistribution layer, which plays a buffering role, thereby effectively reducing test pad deformation and / or electrode scratches, while ensuring test accuracy. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of the front view structure of the test fixture in Embodiment 1 of this application; Figure 2 This is a top view of the test fixture according to Embodiment 1 of this application; Figure 3 This is a schematic diagram of the main structure of the test fixture in Embodiment 2 of this application; Figure 4 This is a top view of the test fixture in Embodiment 2 of this application; Figure 5 This is a schematic diagram of the front view structure of the test fixture in Embodiment 3 of this application; Figure 6 This is a top view of the test fixture in Embodiment 3 of this application; Figure 7 This is a schematic diagram of the front view structure of the test fixture in Embodiment 4 of this application; Figure 8 This is a top view of the test fixture in Embodiment 4 of this application; Figure 9 This is a schematic diagram of the front view structure of the test fixture in Embodiment 5 of this application; Figure 10 This is a top view of the test fixture in Embodiment 5 of this application; Figure 11 This is a schematic diagram of the front view structure of the test fixture in Embodiment Six of this application; Figure 12 This is a top view of the test fixture in Embodiment Six of this application; Figure 13 This is a schematic diagram of the front view structure of the test fixture in Embodiment 7 of this application; Figure 14 This is a schematic diagram of the structure in the test fixture preparation method of Embodiment 1 of this application; Figure 15This is a schematic diagram of the structure in another preparation method of the test fixture of this application; Figure 16 This is a schematic diagram of the structure in the test fixture preparation method of Embodiment 2 of this application; Figure 17 This is a schematic diagram of the structure in another preparation method of the test fixture of this application; Figure 18 This is a schematic diagram of the structure in the test fixture preparation method of Embodiment 3 of this application; Figure 19 This is a schematic diagram of the structure in another preparation method of the test fixture of this application; Figure 20 This is a schematic diagram of the structure in the test fixture preparation method of Embodiment 4 of this application; Figure 21 This is a schematic diagram of the structure of the test fixture and the LED chip corresponding to Embodiment 1 of this application.

[0024] Reference numerals: 1. Test pad; 2. Redistribution layer; 3. Buffer layer; 4. LED chip; 5. Support substrate; 6. Port; 7. First temporary substrate; 8. Second temporary substrate; 9. Substrate; 10. Test module a. First groove 200, second groove 300; Connect circuit 201 and electrode 401. Detailed Implementation

[0025] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0026] It should be noted that the terms "comprising" and "having" and any variations thereof in the specification, claims and accompanying drawings of this invention are intended to cover non-exclusive inclusion. For example, a process, method, apparatus, product or device that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such process, method, product or device.

[0027] During the LED chip manufacturing process, its photoelectric properties need to be tested to ensure product quality. However, the test end of the commonly used test fixture is a probe. Due to factors such as the probe material and structure, the probe is prone to deformation or electrode scratches.

[0028] In view of the above problems, several specific embodiments of LED chip test fixtures are provided below.

[0029] Test fixture of Embodiment 1 A test fixture, referring to Figure 1 、 Figure 2 , which includes a test pad 1, a redistribution layer 2, a buffer layer 3, a support substrate 5, and a port 6 disposed on the redistribution layer 2 that are stacked in sequence. Among them, the support substrate 5 is preferably a glass substrate.

[0030] The test pad 1 includes a positive test pad and a negative test pad. The sizes and shapes of the positive test pad and the negative test pad match the sizes and shapes of the positive electrode and the negative electrode of the LED chip 4 to be tested, respectively, and their contact ends protrude from the bottom surface of the redistribution layer 2 for contact connection with the electrode 401 of the LED chip 4. In this application, the positive test pad and the negative test pad are obtained by semiconductor processes and are convex blocks. Compared with the probe structure, the convex block structure is not easily deformed under the action of extrusion force.

[0031] The distribution structures of the positive test pad and the negative test pad match the distribution structures of the positive electrode and the negative electrode of the LED chip 4. The number of positive test pads in a group of test pads 1 is the same as the number of positive electrodes in a single LED chip, and the number of negative test pads is the same as the number of negative electrodes in a single LED chip. In this embodiment, the LED chip 4 is an integrated chip. In this integrated chip, the negative electrodes of the light-emitting bodies are connected to form a common cathode structure, or the positive electrodes of the light-emitting bodies are connected to form a common anode structure. For example, the integrated chip is a MiP chip, and the MiP chip includes light-emitting bodies of three primary colors: a red light-emitting body, a green light-emitting body, and a blue light-emitting body. In this embodiment, the red light-emitting body, the green light-emitting body, and the blue light-emitting body are arranged side by side at intervals, and the negative electrodes of the red light-emitting body, the green light-emitting body, and the blue light-emitting body are connected to form a common cathode structure. In this structure, the integrated chip includes three positive electrodes and one negative electrode. Correspondingly, a group of test pads includes three positive test pads and one negative test pad. According to the distribution of the electrodes in the LED chip 4, the positive electrodes and the negative electrodes in each LED chip 4 are arranged in a rectangular shape, and then the positive test pads and the negative test pads in each group of test pads are also arranged in a rectangular shape.

[0032] It should be noted that this application does not specifically limit the light color and number of the light-emitting bodies in the LED chip 4. In the LED chip 4 of another embodiment, the red light-emitting body, the green light-emitting body, and the blue light-emitting body are arranged in a "pin" shape, or the LED chip 4 includes four light-emitting bodies: one red light-emitting body, two green light-emitting bodies, and one blue light-emitting body, and the four light-emitting bodies are arranged in a rectangular shape, then the test pad 1 is also arranged in a "pin" shape or a rectangular shape.

[0033] The redistribution layer 2 includes an insulating layer and a connection circuit distributed on the insulating layer. One end of the connection circuit is the test pad 1 with the above-mentioned structure, which is used to electrically connect the electrode 401 of the LED chip 4. The other end is a port, which is used to electrically connect the tester. It is an intermediate medium for realizing the electrical connection between the LED chip 4 and the test pad 1. The redistribution layer 2 facilitates the electrical connection between the test pad 1 and the tester.

[0034] The ports are located on the side of the redistribution layer 2 and include a current input port, a current output port, a positive voltage port, and a negative voltage port. In this embodiment, each test pad shares a set of ports, and each port is electrically connected to an external test device via an FPC connection cable. The current input port and current output port are connected to the test pad 1 via the connection circuit 201 and are used to transmit current control signals to the LED chip 4 to control the working state of the LED chip 4. The positive voltage port and negative voltage port are used to obtain the test voltage.

[0035] In this embodiment, the redistribution layer 2 covers the entire surface, extending from the left test pad to the right test pad of the test fixture to form a first continuous area. Furthermore, each insulating layer in the redistribution layer 2 is integrally prepared, which helps to improve processing efficiency.

[0036] In addition, to meet the arrangement requirements of multiple connection circuits 201, the insulating layer in the redistribution layer 4 is divided into multiple layers: the first insulating layer 201 to the Nth insulating layer 20N, where N is an integer greater than or equal to 1. The insulating layer is made of insulating material to achieve electrical isolation between each connection circuit. The insulating material includes polyimide (i.e., PI), benzocyclobutene (i.e., BCB), poly(p-phenylenebenzodioxazole) (i.e., PBO) or photoresist, with an elastic modulus less than or equal to 3 GPa. In this embodiment, polyimide is preferred.

[0037] The buffer layer 3 is stacked on top of the redistribution layer 2. The buffer material in the buffer layer 3 is silicone resin, polyurethane, or acrylate, and silicone resin is preferred in this embodiment. The elastic modulus of the buffer material is less than or equal to 100 MPa, which is less than the elastic modulus of the insulating layer.

[0038] In this embodiment, the buffer layer 3 covers the entire surface and extends from the left side to the right side of the top surface of the redistribution layer 2 of the test fixture to form a second continuous area. The buffer layer 3 includes at least one layer, and each buffer layer 3 is integrally prepared, which is beneficial to further improve processing efficiency.

[0039] In addition, the total thickness of the redistribution layer 2 in this application ranges from 15μm to 30μm, and the thickness of the buffer layer 3 ranges from 5μm to 20μm. In this first embodiment, the total thickness of the redistribution layer 2 is preferably 20μm, and the thickness of the buffer layer 3 is preferably 5μm.

[0040] Example 2 Test Fixture The test fixture in this second embodiment includes test pads 1, a redistribution layer 2, a buffer layer 3, a support substrate 5, and a port 6 disposed on the redistribution layer 2, which are stacked sequentially. The support substrate 5 is preferably a glass substrate. Figure 3 , Figure 4 The test pad 1, redistribution layer 2, buffer layer 3, and LED chip 4 are composed of the same structure as the test fixture in Embodiment 1 above, and the distribution structure of the test pad 1, buffer layer 3, and LED chip 4 is the same as the test fixture in Embodiment 1 above.

[0041] The difference between this test fixture and the one described in Embodiment 1 is that the redistribution layer 4 in this test fixture is provided with a number of first grooves. The first grooves are distributed in a grid pattern or in parallel strips, dividing the redistribution layer 4 into a number of first regions. In this embodiment, each first region includes a set of connection circuits and test pads 1, and a set of test pads 1 corresponds to one LED chip 4.

[0042] Another difference from the test fixture in Embodiment 1 is that in this test fixture in Embodiment 2, each redistribution layer of the first region is provided with a set of ports 6. The ports 6 are located on the same side of the redistribution layer 2 of each first region, including a current input port, a current output port, a positive voltage port, and a negative voltage port. A set of test pads corresponds to a set of ports, and each port is electrically connected to an external test machine via an FPC connection cable. The current input port and the current output port are connected to the test pads through the connection circuit 201 and are used to transmit current control signals to the LED chip 4 to control the working state of the LED chip 4. The positive voltage port and the negative voltage port are used to obtain the test voltage.

[0043] Example 3 Test Fixture A test fixture includes a plurality of test pads 1, a redistribution layer 2, a buffer layer 3, a support substrate 5, and ports 6 disposed on the redistribution layer 2, wherein the support substrate 5 is preferably a glass substrate. Figure 5 , Figure 6 The test pad 1, redistribution layer 2 and port 6, buffer layer 3 and LED chip 4 are composed of the same structure as the test fixture in Embodiment 1 above, and the distribution structure of the test pad 1, redistribution layer 2 and port 6 and LED chip 4 is the same as the test fixture in Embodiment 1 above.

[0044] The difference from the above embodiment one is that the buffer layer 3 of the test fixture in this embodiment three has a plurality of second grooves 300. The second grooves 300 are distributed in a grid pattern or in parallel strip pattern, dividing the buffer layer 3 into a plurality of second regions. In this embodiment two, each second region corresponds to an LED chip 4.

[0045] Example 4 Test Fixture A test fixture includes a plurality of test pads 1, a redistribution layer 2, a buffer layer 3, a support substrate 5, and ports 6 disposed on the redistribution layer 2, wherein the support substrate 5 is preferably a glass substrate. Figure 7 , Figure 8 The test pad 1, redistribution layer 2, buffer layer 3, and LED chip 4 are composed of the same structure as the test fixture in Embodiment 1 above, and the distribution structure of the test pad 1 and LED chip 4 is the same as that in the test fixture in Embodiment 1 above.

[0046] The difference between this fourth embodiment and the test fixture described in Embodiment 1 is that the redistribution layer 4 and port 6 in this fourth embodiment have the same distribution structure as in Embodiment 2: the redistribution layer 2 is divided into several first regions by the first groove 200. The distribution structure of the buffer layer 3 is the same as in Embodiment 3: the buffer layer 3 is divided into several second regions by the second groove 300, and the second groove 300 is connected to the first groove 200 to form a connecting groove.

[0047] Example 5 Test Fixture The test fixture in this embodiment includes test pads 1, a redistribution layer 2, a buffer layer 3, a support substrate 5, and a port 6 disposed on the redistribution layer 2, which are stacked sequentially. The support substrate 5 is preferably a glass substrate. Figure 9 , Figure 10 The test pad 1, redistribution layer 2, buffer layer 3, LED chip 4, and port 6 are composed of the same structure as the test fixture in Embodiment 2 above, and the distribution structure of the test pad 1, redistribution layer 2, buffer layer 3, and LED chip 4 is the same as the test fixture in Embodiment 2 above.

[0048] The difference between this fifth embodiment and the test fixture described in Embodiment 2 is that in this fifth embodiment, the port 6 is located on the side of the redistribution layer 2 of each first region and is positioned close to the edge of the test fixture. This facilitates further reducing the spacing between two adjacent first regions to meet the testing requirements of small-pitch LED chips, such as a small pitch of 0.2mm. Furthermore, the first regions are arranged in a 1*M or 2*M array structure, enabling row-by-row or column-by-column testing of the LED chips 4, or simultaneous testing of two adjacent rows or columns of the LED chips 4.

[0049] Example 6 Test Fixture The test fixture in this embodiment includes test pads 1, a redistribution layer 2, a buffer layer 3, a support substrate 5, and a port 6 disposed on the redistribution layer 2, which are stacked sequentially. The support substrate 5 is preferably a glass substrate. Figure 11 , Figure 12The test pad 1, redistribution layer 2, buffer layer 3, LED chip 4, and port have the same composition structure as the test fixture in Embodiment 4 above, and the distribution structure of the test pad 1, redistribution layer 2, buffer layer 3, and LED chip 4 is the same as the test fixture in Embodiment 4 above.

[0050] The difference between this sixth embodiment and the test fixture described in Embodiment 4 is that in this sixth embodiment, the port 6 is located on the side of the redistribution layer 2 of each first region and is positioned close to the edge of the test fixture. This helps to reduce the spacing between two adjacent first regions, thus meeting the testing requirements of small-pitch LED chips 4. Furthermore, the first regions are arranged in a 1*M or 2*M array structure, which allows for row-by-row or column-by-column testing of the LED chips 4, or simultaneous testing of two adjacent rows or columns of the LED chips 4.

[0051] In the test fixtures of Embodiments 1 to 6 described above, the support substrate 5 plays a supporting role. When the redistribution layer 2 and the buffer layer 3 are deformed due to the compressive force, the supporting role of the support substrate 5 provides the buffer layer 3 with a reverse compressive force to control the deformation within a reasonable range. This ensures that the test pad 1 and the LED chip 4 are in full contact. At the same time, it avoids the problem of excessive deformation affecting the contact effect between the test pad 1 and the LED chip 4 and / or the problem of excessive stretching and damage to the internal connection circuit of the redistribution layer 2.

[0052] It should be further noted that, in another embodiment (i.e., embodiment seven), the support substrate 5 in the test fixture of embodiment one, embodiment two, or embodiment three can be removed, for example, Figure 13 A schematic diagram of the structure of the test fixture without the support substrate 5 in Embodiment 1 is provided. Detailed structural diagrams of other embodiments without the support substrate 5 are not shown here. For test fixtures without the support substrate 5, when the redistribution layer 2 and buffer layer 3 deform under compressive force, a support device needs to be additionally provided on the surface of the buffer layer 3. This support device applies reverse compressive force to the buffer layer 3 to control the deformation within a reasonable range.

[0053] The advantages of using the test fixture described in this application are as follows: (1) In the test fixture, the above-mentioned distribution structure, thickness of each layer and elastic modulus of the redistribution layer 2 and the buffer layer 3 are coordinated with each other, so that the buffer layer 3 and the redistribution layer 2 can be reasonably deformed under the action of extrusion pressure. This deformation can not only ensure that each test pad 1 is in full contact with the electrode 401 of the corresponding LED chip 4, avoiding the problem of poor connection affecting the test accuracy; in addition, the buffering effect of the buffer layer 3 can offset the excessive extrusion pressure, avoiding the problem of electrode scratches and other damage. At the same time, it can prevent the connection circuit in the redistribution layer 2 from being damaged due to excessive deformation, further ensuring the test accuracy.

[0054] (2) The above test fixture integrates multiple test pads 1, which can meet the simultaneous testing requirements of multiple LED chips and improve testing efficiency.

[0055] (3) The above-mentioned test fixture uses a contact measurement method. The contact end of the test pad 1 is flush with or protrudes from the bottom surface of the redistribution layer 2, which facilitates the corresponding contact between the test pad 1 and the electrodes of the LED chip 4. Compared with the coupling measurement method, the contact measurement does not need to consider additional current losses such as coupling capacitors, which can reduce the influence of additional current losses.

[0056] The following discloses several methods for preparing test fixtures, including: The preparation of test pad 1 includes: A. Preparing test pad 1 using photolithography, deposition, and stripping processes. Each set of test pads 1 includes a positive electrode test pad and a negative electrode test pad. The shape and size of the positive electrode test pad and the negative electrode test pad match the electrode shape and size of the LED chip 4. The number of test pads 1 and LED chips 4 are consistent and correspond one-to-one.

[0057] Prepare a redistribution layer 2, which includes several insulating layers and connection circuits 201 distributed on the insulating layers. The redistribution layer 2 is composed of multiple layers stacked together. The redistribution layer 2 includes a first redistribution layer, a second redistribution layer to an Nth redistribution layer, and insulating layers including a first insulating layer to an Nth insulating layer, where N is an integer greater than or equal to 1. The first redistribution layer includes a first insulating layer and a first circuit distributed on the first insulating layer. The second redistribution layer includes a second insulating layer and a second connection circuit distributed on the second insulating layer. ... The Nth redistribution layer includes an Nth insulating layer and an Nth connection circuit distributed on the Nth insulating layer. B1. Prepare the first insulating layer to the Nth insulating layer in sequence, and simultaneously prepare the first connection circuit to the Nth connection circuit in each layer. B2. Prepare the Nth insulating layer to the first insulating layer in sequence, and simultaneously prepare the Nth connection circuit to the first connection circuit in each layer.

[0058] The specific preparation steps for B1 include: B11. Apply an adhesive coating process, a film lamination process, or a deposition process to coat or deposit an insulating material. The insulating material includes polyimide (i.e., PI), benzocyclobutene (i.e., BCB), poly(p-phenylenebenzodioxazole) (i.e., PBO), or photoresist, with an elastic modulus of less than or equal to 3 GPa. In this embodiment, polyimide is preferred.

[0059] The coating process is achieved using a coating machine, and the deposition process includes chemical vapor deposition or atomic layer deposition.

[0060] B12. The insulating material cures to form the first insulating layer.

[0061] B13. Using photolithography and etching processes, a local area of ​​the first insulating layer is etched to form the first etched hole.

[0062] B14. Using electron beam evaporation or magnetron sputtering deposition, conductive material is deposited in the first etched hole to form a first connection circuit. In this embodiment, the conductive material includes at least one of Cr, Ni, Ti, Au, Pt, and Al. In this embodiment, Ti is preferred, thereby obtaining a first redistribution layer.

[0063] Repeat steps B11 to B14 above to prepare a second redistribution layer on the upper surface of the first redistribution layer, and so on, until the Nth redistribution layer is prepared, thereby obtaining a redistribution layer of a certain thickness. The total thickness of the redistribution layer ranges from 15 μm to 30 μm. This application does not specify the number of redistribution layers.

[0064] The specific preparation steps of B2 include: B21, coating or depositing an insulating material using a coating process, a film-coating process, or a deposition process; B22, curing the insulating material to form the Nth insulating layer; B23, etching a local area of ​​the Nth insulating layer using photolithography and etching processes to form the Nth etched hole; B24, depositing a conductive material in the Nth etched hole using electron beam evaporation or magnetron sputtering to form the Nth connection circuit. Repeating steps B21 to B24, a (N-1)th redistribution layer is prepared on the upper surface of the Nth redistribution layer, and so on, until the first redistribution layer is prepared, thereby obtaining a relatively thick redistribution layer 2.

[0065] To prepare buffer layer 3, a buffer material is coated or deposited using a coating, lamination, or deposition process. The buffer material includes silicone resin, polyurethane, or acrylate; in this embodiment, silicone resin is preferred. The elastic modulus of the buffer material is less than or equal to 100 MPa, which is less than the elastic modulus of the insulating layer. The buffer material is then cured to form buffer layer 3.

[0066] Port 6 is provided to connect the connection circuit 201 to an external test machine. Specifically, D, several sets of ports 6 are provided, and the ports 6 are installed on the redistribution layer 2 using a transfer process, or several sets of ports 6 are prepared on the redistribution layer 2 using photolithography, etching, and deposition processes.

[0067] Arrange the above preparation steps in a reasonable order to prepare the test fixtures of Examples 1 to 4.

[0068] A method for preparing a test fixture according to an embodiment 1, the method comprising: sequentially preparing a test pad 1, a redistribution layer 2, and a buffer layer 3, with reference to... Figure 14Specifically, a first temporary substrate 7 is provided, and a test pad 1 is prepared on the first temporary substrate 7 in step A. A redistribution layer 2 is prepared on one side of the test pad in step B1. A buffer layer 3 is prepared on the redistribution layer 2 in step C. A port 6 is set on the redistribution layer 2 in step D. The first temporary substrate 7 is then removed.

[0069] Another method for preparing the test fixture, comprising: sequentially preparing a buffer layer 3, a redistribution layer 2, and a test pad 1, as shown in the reference. Figure 15 Specifically, a support substrate 5 is provided, a buffer layer 3 is prepared in the support substrate 5 in step C, a redistribution layer 2 is prepared on the buffer layer 3 in step B2, a test pad 1 is prepared on the redistribution layer 2 in step A, and a port 6 is set on the redistribution layer 2 in step D.

[0070] It should be noted that, in another embodiment, the redistribution layer 2 can be prepared by step B1 or B2, then a buffer layer 3 can be prepared in the redistribution layer 2 by step C, a test pad 1 can be prepared in the redistribution layer 3 by step A, and a port 6 can be set in the redistribution layer 3 by step D. The preparation order of the buffer layer 3, the test pad 1, and the port 6 can be flexibly adjusted according to the actual situation.

[0071] A method for preparing a test fixture according to Embodiment 2, refer to Figure 16 The method includes: sequentially proceeding through steps A and B1, or sequentially proceeding through steps B1 and A, to prepare a stacked redistribution layer 2 and test pads 1; sequentially proceeding through step D to set ports 6 on the side of the redistribution layer 2 to obtain a plurality of test modules a; arranging the test modules on a second temporary substrate 8 according to a certain structure, the distribution structure of the test modules being designed based on the distribution structure of the LED chip 4, with the test pads 1 corresponding to the second temporary substrate 8; sequentially proceeding through the film-applying process in step C to prepare a buffer layer 3 on the side of the redistribution layer 2 of the test modules away from the test pads 1; and finally removing the second temporary substrate 8.

[0072] Another method for preparing the test fixture, see [reference]. Figure 17 The method includes: sequentially passing steps A and B1, or sequentially passing steps B1 and A, to prepare a stacked redistribution layer 2 and test pads 1; sequentially passing steps D to set ports 6 on the side of the redistribution layer 2 to obtain a plurality of test modules a; sequentially passing steps C to prepare a buffer layer 3 in the support substrate 5; X3, transferring the test modules to the buffer layer 3, and setting the test pads 1 away from the buffer layer 3.

[0073] A method for preparing a test fixture according to Embodiment 3, referring to Figure 18The method includes: sequentially proceeding through steps A and B1, or sequentially proceeding through steps B1 and A, to prepare a stacked redistribution layer 2 and test pads 1, with the redistribution layer 2 covering one side of the test pads 1; in step C, preparing a buffer layer 3 on the redistribution layer 2, and using photolithography and etching processes to etch a local area of ​​the buffer layer 3 to form patterned second grooves 300 in the buffer layer 3, the second grooves 300 being distributed in a grid pattern or in parallel strip patterns, dividing the buffer layer 3 into several second regions, in this third embodiment, the second regions correspond one-to-one with the LED chips 4; coating the surface of the support substrate 5 with an adhesive material, and mounting the support substrate 5 to the buffer layer 3 using the adhesive material; in step D, setting a port 6 on the side end of the redistribution layer 2; and removing the first temporary substrate 7. It should be noted that, in another embodiment, the port 6 can be set on the side end of the redistribution layer 2 in step D before preparing the buffer layer 3.

[0074] Another method for preparing the test fixture, see [reference]. Figure 19 The method includes: sequentially proceeding through steps A and B1, or sequentially proceeding through steps B1 and A, to prepare a stacked redistribution layer 2 and test pads 1, with the redistribution layer 2 covering one side of the test pads 1; sequentially proceeding through step D to set a port 6 on the side of the redistribution layer 2 to obtain a test module; sequentially proceeding through step C to prepare a buffer layer 3 in a support substrate 5, and sequentially proceeding through photolithography and etching processes to etch a local area of ​​the buffer layer 3 to form a patterned second groove 300 in the buffer layer 3, the second groove 300 being distributed in a grid pattern or in parallel strip pattern, dividing the buffer layer 3 into several second regions, each of which corresponds one-to-one with an LED chip 4; sequentially installing the test module and the buffer layer 3, with the test pads 1 positioned away from the buffer layer 3.

[0075] A method for preparing a test fixture according to Embodiment 4, refer to Figure 20 The method includes: preparing a buffer layer 3 in a support substrate 5 in step C; etching a local area of ​​the buffer layer 3 using photolithography and etching processes to form a patterned second groove 300 in the buffer layer 3; the second groove 300 being distributed in a grid pattern or in parallel strip pattern, dividing the buffer layer 3 into several second regions, each corresponding to an LED chip 4; preparing a stacked redistribution layer 2 and test pads 1 sequentially through steps A and B1, or sequentially through steps B1 and A; setting ports 6 on the side of the redistribution layer 2 in step D to obtain several test modules a; transferring the test modules a to the buffer layer 3, with the test pads 1 positioned away from the buffer layer 3, and each test module a correspondingly connected to each second region.

[0076] When a support substrate 5 is provided in the preparation method of the test fixture in Embodiments 1 to 4, a laser lift-off process or a wet etching process can be used to remove the support substrate 5 in the corresponding steps to obtain a test fixture without a support substrate 5. For example, the support substrate 5 in the test fixture in Embodiment 1 is removed to obtain the test fixture in Embodiment 7.

[0077] It should be noted that in the preparation methods of the test fixtures in Embodiment 2 and Embodiment 4, during the preparation process, the obtained test modules are arranged in an array structure of 2*M or 1*M, and when the port 6 is set, the port 6 is installed on the side of the redistribution layer 2 and set close to the edge of the test fixture, thus preparing the test fixtures in Embodiment 5 and Embodiment 6 respectively.

[0078] During testing, the test pad 1 in the test fixture is aligned with the electrodes of the LED chip 4. Taking the testing of the LED chip 4 using the test fixture of Example 1 as an example, the LED chip 4 is arranged on the substrate 9, as shown in the reference... Figure 21 The test fixture moves relative to the LED chip 4, generating a squeezing force. Under this squeezing force, the redistribution layer 2 and the buffer layer 3 deform to a certain extent, with the elastic deformation of the buffer layer 3 being greater than that of the redistribution layer 2, thus providing a buffering effect and ensuring full contact between each test pad 1 and the corresponding LED chip 4. The main processor in the test machine sends a control signal, which is transmitted to the corresponding LED chip 4 via the FPC connection line, current input port, current output port, connection circuit, and test pad 1, controlling the LED chip 4 to turn on. The test machine connects to the positive and negative voltage ports via the FPC connection line to obtain the test voltage at both ends. Based on this test voltage, the resistance of the LED chip 4, the on-resistance of the connection circuit 201 in the redistribution layer 2, and the resistance of the test pad 1, the operating current of the LED chip 4 is calculated according to Ohm's law, thereby realizing the electrical testing of the LED chip 4.

[0079] It is understood that the above detailed description of the present invention is for illustrative purposes only and is not intended to limit the technical solutions described in the embodiments of the present invention. Those skilled in the art should understand that modifications or equivalent substitutions can still be made to the present invention to achieve the same technical effects; as long as the usage requirements are met, they are all within the protection scope of the present invention.

Claims

1. A test fixture for testing LED chips (4), characterized in that, It includes: The redistribution layer (2) includes an insulating layer and connection circuits (201) distributed on the insulating layer. A buffer layer (3) is stacked on top of the redistribution layer (2), and the elastic modulus of the buffer layer (3) is less than that of the insulating layer. Several sets of test pads (1), each set of test pads (1) includes a positive test pad and a negative test pad, the shape and size of the positive test pad and the negative test pad are respectively matched with the shape and size of the positive electrode and the negative electrode of the LED chip; The contact end of the test pad is flush with or protrudes from the bottom surface of the redistribution layer (2). Port (6), located on the redistribution layer (2), is used to connect the connection circuit (201) to an external tester; During testing, the test pad (1) is in contact with the LED chip (4), and the LED chip (4) is electrically connected to the test machine through the test pad (1), the connection circuit (201), and the port (6).

2. The test fixture according to claim 1, characterized in that, The test fixture also includes a support substrate (5) which is distributed on the top of the buffer layer (3).

3. The test fixture according to claim 1 or 2, characterized in that, The thickness of the redistribution layer (2) ranges from 15μm to 30μm, and the thickness of the buffer layer (3) ranges from 5μm to 20μm.

4. The test fixture according to claim 1, characterized in that, The rewiring layer (2) covers the entire surface and forms a first continuous area, and / or the buffer layer (3) covers the entire surface and forms a second continuous area.

5. The test fixture according to claim 1, characterized in that, The redistribution layer (2) has a plurality of first through slots (200), which are distributed in a grid pattern or in parallel strips. And / or, the buffer layer (3) has a plurality of second through slots (300), which are distributed in a grid pattern or in parallel strips. The second through slots (300) are connected to the first through slots (200) to form a connecting slot.

6. The test fixture according to claim 1, characterized in that, The port (6) includes at least a current input port, a current output port, a positive voltage port, and a negative voltage port. The current input port and the current output port are connected to the test pad (1) through the connection circuit (201) to transmit current control signals to the LED chip (4) and control the working state of the LED chip (4). The positive voltage port and the negative voltage port are used to obtain the test voltage.

7. A method for preparing a test fixture, the method being used to prepare the test fixture according to claim 1, characterized in that, The method includes: Prepare a redistribution layer (2), the redistribution layer (2) includes at least one insulating layer and connection circuits (201) distributed on the insulating layer; Prepare a buffer layer (3), wherein the elastic modulus of the buffer layer (3) is less than the elastic modulus of the insulating layer; Using semiconductor technology, test pads (1) are prepared. Each set of test pads (1) includes a positive test pad and a negative test pad. The shape and size of the positive test pad and the negative test pad are respectively matched with the shape and size of the positive electrode and the negative electrode of the LED chip (4). A port (6) is provided for connecting the connection circuit (201) to an external test equipment; Preparation methods include: Prepare a buffer layer (3), a redistribution layer (2), and several sets of test pads (1) that are stacked in sequence, and set a port (6) on the redistribution layer (2). The contact end of the test pad (1) protrudes from or is flush with the bottom surface of the redistribution layer (2). The non-contact end of the test pad (1) is electrically connected to the connection circuit (201) and the port (6) in sequence.

8. The method for preparing the test fixture according to claim 7, characterized in that, The preparation of the redistribution layer (2) includes: depositing insulating material layer by layer using a coating or film-coating process to form each insulating layer; and simultaneously filling conductive material into the etched holes of each insulating layer using photolithography, etching, and deposition processes to form the connection circuit (201); the insulating material includes polyimide, benzocyclobutene, poly(p-phenylenebenzodioxazole) fiber, or photoresist, and the elastic modulus of the insulating material is less than or equal to 3 GPa.

9. The method for preparing the test fixture according to claim 7 or 8, characterized in that, The preparation of the buffer layer (3) includes: depositing a buffer material using an adhesive coating or film lamination process to form the buffer layer (3); the buffer material includes silicone resin, polyurethane or acrylate; the elastic modulus of the buffer material is less than the elastic modulus of the insulating material, and the elastic modulus of the buffer material is less than or equal to 100 MPa.

10. The method for preparing the test fixture according to claim 7, characterized in that, The redistribution layer (2) is etched using photolithography and etching processes to form a first through-hole (200), dividing the redistribution layer (2) into several first regions (a), and / or the buffer layer (3) is etched using photolithography and etching processes to form a second through-hole (300), dividing the buffer layer (3) into several second regions (b).

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