Tape-out lithography alignment method

Abstract

The invention discloses a tape-out photoetching alignment method, relates to the technical field of tape-out photoetching, and aims to solve the problem of low tape-out photoetching generation efficiency in the prior art. The alignment method comprises the following steps: acquiring technological parameters of tape-out photoetching; based on the process parameters, identifying the alignment mark entity graph in the previous process film layer of the current process film layer of the flow sheet to obtain an identification result; if the identification result represents that the identification fails, self-aligning the current process film layer based on an alignment mark design graph in the current process film layer; the alignment mark design pattern is arranged on the periphery of the device functional area design pattern in the current process film layer. The method is used for improving the production efficiency of the tape-out photoetching process.

Description

Technical Field

[0001] This invention relates to the field of wafer fabrication lithography technology, and more particularly to wafer fabrication lithography alignment methods. Background Technology

[0002] Photolithography alignment is required during the wafer fabrication process. Existing photolithography alignment schemes are all based on the premise that the alignment marks of the previous layer can be effectively identified, and the alignment scheme is improved and optimized based on this premise.

[0003] In actual wafer fabrication, various interference scenarios exist. For example, excessively thick film layers in current processes can interfere with the recognition of previous layer markings, and film reflections and etching residues can also obscure previous layer markings. These are extreme but common realities. Current solutions for such scenarios require pausing the wafer fabrication process and redesigning the previous layer markings, which directly leads to a significant reduction in wafer fabrication production efficiency.

[0004] Therefore, there is an urgent need in the field for a new solution that can achieve accurate alignment without relying on previous layer markings, in order to solve the aforementioned efficiency bottleneck problem. Summary of the Invention

[0005] The purpose of this invention is to provide a wafer fabrication lithography alignment method to improve the production efficiency of the wafer fabrication lithography process.

[0006] To achieve the above objectives, the present invention provides the following technical solution: In a first aspect, the present invention provides a wafer fabrication photolithography alignment method, comprising: Obtain the process parameters for wafer fabrication photolithography; Based on the process parameters, the alignment mark entity pattern in the previous process film layer of the current process film layer in the wafer is identified to obtain the identification result; If the identification result indicates identification failure, then the current process film layer is self-aligned based on the alignment mark design pattern in the current process film layer; the alignment mark design pattern is set on the periphery of the device functional area design pattern in the current process film layer.

[0007] Optionally, self-aligning the current process film layer based on the alignment mark design pattern in the current process film layer includes: The mask image data corresponding to the alignment mark design pattern on the photomask and the wafer image data corresponding to the alignment mark design pattern on the wafer are obtained; both the mask image data and the wafer image data are obtained by capturing images using an optical sensor in a lithography machine; Extract the reference position of the alignment mark design pattern on the mask from the mask image data, and extract the actual position of the alignment mark design pattern on the wafer from the wafer image data; Calculate the deviation between the reference position and the actual position, and control the actual position to align with the reference position based on the deviation to achieve self-alignment of the current process film layer.

[0008] Optionally, the alignment mark design graphic includes four mark units; the four mark units are respectively disposed at the four corners of a preset rectangular area, the preset rectangular area includes a device functional area design graphic and the center of the preset rectangular area coincides with the center of the device functional area design graphic; Extracting the reference position of the alignment mark design pattern on the mask from the mask image data, and extracting the actual position of the alignment mark design pattern on the wafer from the wafer image data, includes: The Canny edge detection method is used to extract multiple edges corresponding to each of the four marker units from the mask image data and the wafer image data, respectively. For each marker unit, multiple edges are fitted with straight lines to determine the reference position corresponding to the mask image data and the actual position corresponding to the wafer image data.

[0009] Optionally, each marking unit is an L-shaped marking unit; each L-shaped marking unit includes a first checkerboard pattern extending along the X-axis and a second checkerboard pattern extending along the Y-axis; the first checkerboard pattern and the second checkerboard pattern intersect perpendicularly to form a corner; When the marker unit is an L-shaped marker unit, the Canny edge detection method is used to extract multiple edges corresponding to each of the four marker units from the mask image data and the wafer image data, including: Using the Canny edge detection method, the horizontal edge corresponding to the first checkerboard pattern and the vertical edge corresponding to the second checkerboard pattern in each L-shaped marker unit are extracted from the mask image data and the wafer image data, respectively.

[0010] Optionally, each marking unit is a long strip checkerboard marking unit; each long strip checkerboard marking unit is a third checkerboard pattern extending in a single direction; When the marking unit is a long, rectangular checkerboard marking unit, the Canny edge detection method is used to extract multiple edges corresponding to each of the four marking units from the mask image data and the wafer image data, including: Using the Canny edge detection method, two parallel edges corresponding to the third checkerboard pattern in each elongated checkerboard marker unit are extracted from the mask image data and the wafer image data, respectively.

[0011] Optionally, when the marking unit is an L-shaped marking unit, straight line fitting is performed on multiple edges corresponding to each marking unit to determine the reference position corresponding to the mask image data and the actual position corresponding to the wafer image data, including: A first fitted straight line is obtained by fitting a straight line to the horizontal edge corresponding to the first chessboard pattern. A second fitted line is obtained by fitting a straight line to the vertical edge corresponding to the second checkerboard pattern. The coordinates of the intersection point of the first fitted line and the second fitted line are determined as the first target coordinates; The reference position is determined based on the four first target coordinates corresponding to the mask image data, and the actual position is determined based on the four first target coordinates corresponding to the wafer image data; When the marking unit is a long, rectangular checkerboard marking unit, straight line fitting is performed on multiple edges corresponding to each marking unit to determine the reference position corresponding to the mask image data and the actual position corresponding to the wafer image data, including: By performing line fitting on the two parallel edges respectively, a third fitted line and a fourth fitted line are obtained; The coordinates of the midpoint of the median line between the third and fourth fitted lines are determined as the second target coordinates. The reference position is determined based on the four second target coordinates corresponding to the mask image data, and the actual position is determined based on the four second target coordinates corresponding to the wafer image data.

[0012] Optionally, calculating the deviation between the reference position and the actual position includes: Formula used: ; Calculate the single-mark deviation for each marked unit; where, For the first X-axis single-mark deviation of each marking unit; For the first Y-axis single-mark deviation of each marking unit; For the first One X-axis reference coordinate; For the first One Y-axis reference coordinate; For the first Each X-axis actual coordinate; For the first Each actual Y-axis coordinate; ; Substitute the single-mark deviation of each marker unit into the formula: ; Obtain the global offset; where, This is the global X-axis offset; This is the global Y-axis offset; Formula used: ; Calculate the global rotation angle; where, The global rotation angle; It is the arctangent function; The global offset and the global rotation angle are determined as the deviation.

[0013] Optionally, before acquiring the mask image data corresponding to the alignment mark design pattern on the mask and the wafer image data corresponding to the wafer, the method further includes: depositing the current process film layer and coating the surface of the current process film layer with photoresist; the current process film layer is a single-layer structure or a multi-layer structure; When the current process film layer is a multilayer structure, depositing the current process film layer and coating the surface of the current process film layer with photoresist includes: Based on the multilayer structure design, the bottom layer and the intermediate layer of the current process film layer are deposited sequentially. A basic marking pattern is formed around the device functional area of ​​the bottom film layer, and the position of the basic marking pattern corresponds to the position of the alignment marking design pattern of the current film layer. The top layer of a current process for depositing multilayer structures is coated with photoresist on its upper surface. When the current process film layer is a single-layer structure, depositing the current process film layer and coating the surface of the current process film layer with photoresist includes: Current process technology for depositing monolayer structures; Photoresist is coated on the upper surface of the current process film layer of the single-layer structure.

[0014] Optionally, the process parameters include the size parameters of the alignment mark entity graphic in the previous process film layer and the preset recognition standard; The preset recognition criteria include contour overlap greater than or equal to a preset percentage, signal-to-noise ratio greater than or equal to a preset value, and edge positioning deviation less than a preset length. Based on the process parameters, the alignment mark entity pattern in the previous process film layer of the current process film layer in the wafer is identified to obtain the identification result, including: The intensity of reflected light or transmitted light within a preset scanning area is collected, and the signal-to-noise ratio of the collected signal is calculated. The preset scanning area is a region that includes the area where each marker unit is located, is located within a preset rectangular area, and avoids the functional area of ​​the device. If the light intensity of a preset number of pixels continuously collected within the preset scanning area is less than the noise baseline, it is determined that no imaging signal of the alignment mark entity graphic has been received, and the recognition result is recognition failure. If an imaging signal is received, the standard outline of the alignment mark entity graphic is deduced based on the size parameters, and the actual shape outline and the standard outline are compared to obtain the outline overlap. Based on the size parameters, the standard edge coordinates of the alignment mark entity graphic are determined, and the edge positioning difference between the actual extracted edge coordinates and the standard edge coordinates is calculated. Determine whether the signal-to-noise ratio, the contour overlap, and the edge localization difference all meet the preset recognition criteria; If all conditions are met, the recognition result is considered successful; otherwise, the recognition result is considered unsuccessful.

[0015] Optionally, the wafer fabrication photolithography alignment method further includes: After the alignment mark entity pattern and the device functional area entity pattern of the current process film layer are etched and formed, the alignment mark entity pattern in the current process film layer is identified. If the identification is successful, the subsequent process film layers are aligned and photolithographically processed based on the alignment mark entity pattern in the current process film layer. If recognition fails, self-alignment and photolithography are performed based on the independent alignment mark design pattern of the next process film layer.

[0016] Compared with existing technologies, the wafer fabrication lithography alignment method provided by this invention prioritizes the identification of alignment mark entity patterns in the previous process film layer based on process parameters, so as to continue the conventional alignment logic and ensure process compatibility. When the identification of the alignment mark entity pattern fails, there is no need to pause the wafer fabrication process to improve or repair the alignment marks in the previous process film layer. Instead, the alignment mark design pattern preset on the periphery of the device functional area design pattern in the current process film layer is directly activated. The self-alignment of the current process film layer is completed based on the design pattern. This effectively avoids the efficiency bottleneck of interrupting wafer fabrication due to the failure of the previous layer mark identification in existing technologies, thereby significantly improving the production efficiency of the wafer fabrication lithography process. Attached Figure Description

[0017] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings: Figure 1 A schematic diagram of the overall flow of a wafer fabrication photolithography alignment method provided in one embodiment of the present invention; Figure 2A partial flowchart of a wafer fabrication photolithography alignment method provided in one embodiment of the present invention; Figure 3 One of the schematic diagrams of a marking unit provided in an embodiment of the present invention; Figure 4 A second schematic diagram of a marking unit provided in one embodiment of the present invention; Figure 5 A partial flowchart of a wafer fabrication photolithography alignment method provided in one embodiment of the present invention; Figure 6 A cross-sectional view of the wafer fabrication process in a back-end process provided in an embodiment of the present invention. Detailed Implementation

[0018] To facilitate a clear description of the technical solutions in the embodiments of the present invention, the terms "first" and "second" are used to distinguish identical or similar items with essentially the same function and effect. For example, the first threshold and the second threshold are merely used to distinguish different thresholds and do not limit their order. Those skilled in the art will understand that the terms "first" and "second" do not limit the quantity or execution order, and that the terms "first" and "second" are not necessarily different.

[0019] It should be noted that in this invention, the terms "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in this invention should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0020] In this invention, "at least one" means one or more, and "more than one" means two or more. "And / or" describes the relationship between the associated objects, indicating that three relationships can exist.

[0021] See Figure 1 This invention provides a wafer fabrication photolithography alignment method, applied to the control system of a photolithography machine. The method may include: Step 100: Obtain the process parameters for wafer fabrication photolithography; It should be noted that the lithography machine is the core equipment for achieving lithographic alignment, and its key components include the control system, photomask, wafer stage, and optical sensors.

[0022] As the command center of the entire photolithography process, the control system is responsible for receiving process parameters and controlling the coordinated work of other components, such as driving the wafer stage to move, controlling the optical sensors to collect data, and executing core algorithms such as mark recognition and alignment calculation. At the same time, the control system pre-stores the mask pattern of each process film layer designed by the engineer. The mask pattern of each process film layer contains the alignment mark design pattern and the device functional area design pattern of that film layer.

[0023] The functional area of ​​a device is the core value area in the tape-out process, such as the transistor or circuit interconnect area.

[0024] A photomask is a template that carries design patterns. It contains alignment marks for the current process film layer and device functional area design patterns, and is the source of patterns for photolithography exposure.

[0025] The wafer carrier stage is used to fix and support the wafer. It can move precisely according to the instructions of the control system to align the wafer with the photomask.

[0026] The wafer fabrication process requires the sequential processing of multiple process films, each of which must be patterned using photolithography. Each process film can be designed as a single-layer structure or, depending on functional requirements, as a multi-layer structure. For example, a multi-layer structure could be a metal interconnect layer consisting of a seed layer, a barrier layer, and an electroplating layer.

[0027] Process parameters are the core basis for photolithography alignment, including at least the preparation sequence of multiple process film layers. The key information used in subsequent steps to identify the previous layer markings also falls under the category of process parameters.

[0028] The wafer fabrication photolithography alignment method in this embodiment of the invention has a wide range of applications. It can be used for both front-end processes such as device active region fabrication and back-end processes such as metal interconnect layer fabrication. In the back-end process, the material of the alignment mark can be consistent with the metal layer material of the current process film to adapt to the film characteristics.

[0029] Optionally, to further ensure the accuracy of the self-alignment of the current process film layer, the physical graphic of the alignment mark design pattern in the current process film layer and the physical graphic of the alignment mark and the device functional area in the previous process film layer must maintain a non-overlapping layout in the vertical direction (i.e., the wafer thickness direction).

[0030] The core functions of this non-overlapping design are: 1) Avoiding optical interference: The physical pattern of the previous process film layer (especially the metal material mark) may have reflective or projection effects. If it overlaps vertically with the physical pattern of the current layer mark, it will cause signal superposition when the optical sensor of the lithography machine collects the image of the current layer mark, reducing the clarity of edge extraction and affecting the calculation accuracy of the reference position and the actual position; 2) Avoiding physical interference: During the wafer fabrication lithography process, the current process film layer needs to be etched. If the physical patterns of the upper and lower layers overlap vertically, the pattern of the upper layer may be damaged due to the deviation in the etching depth control, or the current layer mark pattern may be incompletely etched, which will affect the alignment reliability of the subsequent process film layers.

[0031] For example, in the back-end metal interconnect layer process, if the center coordinates of the alignment mark physical pattern of the previous process film layer are (x1, y1, z1) (the z-axis is the wafer thickness direction), then after the alignment mark design pattern of the current process film layer is materialized, the center coordinates must satisfy the condition that the difference between the z-axis coordinates z2 and z1 is greater than or equal to the thickness of the current process film layer (e.g., if the thickness of the 4-layer metal is 1μm, then z2-z1≥1μm). Simultaneously, it must maintain the layout requirements of the device functional area periphery in the xy plane, ensuring no vertical overlap. It can be understood that z2 is the coordinate value of the center of the alignment mark physical pattern of the current process film layer on the z-axis (wafer thickness direction).

[0032] For different types of process films, the optical contrast of the marking needs to be adapted to ensure recognition accuracy: (1) For example, if the current process film is a transparent dielectric film (e.g., silicon dioxide), the difference in reflectivity between the alignment mark and the film needs to be greater than or equal to a preset ratio (e.g., 40%), which can be achieved by depositing an additional 50-100nm thick TiN metal in the marking area; (2) For example, if it is a metal film such as Cu film or Al film, the difference in reflectivity between the alignment mark and the film needs to be greater than or equal to 5%, which can be achieved by performing plasma oxidation treatment on the marking area at 200-300℃ for 30-60s to form metal oxide.

[0033] Step 200: Based on the process parameters, identify the alignment mark entity pattern in the previous process film layer of the current process film layer in the wafer fabrication, and obtain the identification result.

[0034] It should be clarified here that the alignment mark entity graphic to be identified in the previous process film layer in this step refers to the entity alignment mark that has been formed after the previous process film layer has been photolithographically and etched, rather than the graphic in the design stage. It is the core reliance of photolithographic alignment in the prior art, and its graphic outline (e.g., T-shape), size and other key parameters have been pre-stored in the process parameters.

[0035] In practice, the process parameters include the dimensional parameters of the alignment mark entity graphic in the previous process film layer and the preset recognition standard. It is understood that the process parameters also include the noise baseline and the scanning area boundary of the alignment mark entity graphic in the previous process film layer. The dimensional parameters include at least the length and width of the alignment mark design graphic.

[0036] The preset recognition criteria include contour overlap greater than or equal to a preset percentage, signal-to-noise ratio greater than or equal to a preset value, and edge positioning deviation less than a preset length.

[0037] The noise baseline is the light intensity threshold corresponding to the inherent noise of the lithography machine's optical system, and it serves as a benchmark for determining whether a valid marker imaging signal has been received.

[0038] For example, the size of the preset scanning area is uniformly set to 100μm×100μm, and the scanning step size is 1μm, to ensure that the scanning covers the marker unit while avoiding redundant acquisition.

[0039] For example, the boundary of the scanning area is ≥3μm from the functional area of ​​the preceding device.

[0040] For example, the preset percentage could be 90%.

[0041] For example, the preset signal-to-noise ratio can be 20dB.

[0042] For example, the preset length of the edge positioning deviation can be 0.1 μm.

[0043] Step 200 may specifically include: The intensity of reflected light or transmitted light within a preset scanning area is collected, and the signal-to-noise ratio of the collected signal is calculated. The preset scanning area is an area that includes the area where each marker unit is located, is located within a preset rectangular area, and avoids the functional area of ​​the device. If the light intensity of a preset number of pixels collected in the preset scanning area is all less than the noise baseline, it is determined that no imaging signal of the alignment mark entity graphic has been received, and the recognition result is recognition failure. If an imaging signal is received, the standard outline of the alignment mark entity graphic is deduced based on the size parameters, and the actual shape outline and the standard outline are compared to obtain the outline overlap. Based on the size parameters, determine the standard edge coordinates of the alignment mark entity graphic, and calculate the edge positioning difference between the actual extracted edge coordinates and the standard edge coordinates; Determine whether the signal-to-noise ratio, contour overlap, and edge localization difference all meet the preset recognition criteria; If all conditions are met, the recognition result is considered successful; otherwise, the recognition result is considered unsuccessful.

[0044] It should be noted that before collecting light intensity, the precise positioning of the preset scanning area needs to be completed through “global coarse alignment → local fine scanning”: (1) Global coarse alignment: The lithography machine first completes the initial positioning through the mechanical reference of the wafer edge, such as the Flat edge or Notch notch. Combined with the preset coordinates of the front layer marking entity pattern in the process parameters, the wafer carrier stage is controlled to move to the vicinity of the front layer marking entity pattern. The coarse positioning accuracy reaches ±50μm; (2) Local fine scanning: Within the coarse positioning range, the preset rectangular scanning area, such as 100μm×100μm, is locked to avoid full wafer scanning and improve positioning efficiency.

[0045] The recognition process is illustrated below with examples from multiple scenarios.

[0046] Scenario Example 1: The previous process film layer is the metal interconnect layer in the subsequent process. The alignment mark entity pattern is a T-shaped mark entity pattern. Because the metal debris remaining after etching completely covers the mark area, the optical sensor cannot capture the mark signal.

[0047] The optical sensor is positioned according to the process parameters to a preset scanning area that "includes the T-shaped mark entity graphic and avoids the functional area of ​​the device". The optical sensor collects the reflected light intensity of the area in 1μm increments. The light intensities of 5 consecutive pixels are 12dB, 11dB, 13dB, 10dB and 12dB respectively.

[0048] The preset noise baseline in the process parameters is 15dB. The light intensity of the above 5 consecutive pixels is all less than the noise baseline. This meets the condition of "if the light intensity of 5 consecutive pixels acquired within the preset scanning area is less than the noise baseline, it is determined that no imaging signal of the alignment mark entity graphic has been received", therefore the recognition result is recognition failure.

[0049] Scenario Example 2: The previous process film layer is the active area of ​​the device in the previous process. The alignment mark entity pattern is unobstructed, the film layer surface has uniform reflection, and there are no interference factors.

[0050] Positioned according to process parameters, the optical sensor detects that the light intensity of five consecutive pixels is 15dB higher than the noise baseline.

[0051] The preset recognition criteria in the process parameters are "contour overlap ≥ 90%, signal-to-noise ratio ≥ 20dB, edge positioning deviation < 0.1μm". Based on the preset features of the aligned marker entity graphic in the process parameters (triggered feature detection), the complete contour and key position information of the marker were successfully extracted. The actual detection data are as follows: contour overlap: 93% ≥ 90%; signal-to-noise ratio: 25dB ≥ 20dB; edge positioning deviation: < 0.1μm. The above data meets all items of the preset recognition criteria, therefore the recognition result is successful.

[0052] Scenario Example 3: The previous process film layer is the silicon oxide layer of the previous process. The film layer in the area where the marked entity pattern is located is locally too thick, resulting in blurred edges and incomplete outlines of the mark.

[0053] The preset scanning area location acquisition of 5 consecutive pixels with a light intensity of 22dB is 15dB higher than the noise baseline, triggering the alignment mark feature detection; the extracted mark contour has local missing parts (discontinuous edges) and cannot completely match the standard contour in the process parameters. The actual detection data is as follows: contour overlap: 85%, lower than the preset 90%; signal-to-noise ratio: 23dB, which meets ≥20dB; edge positioning deviation: 0.09μm, which meets <0.1μm.

[0054] As can be seen from the above, the "contour overlap ≥ 90%" requirement in the preset recognition standard was not met, which meets the condition that "if any one of the requirements is not met, the recognition will be deemed to have failed". Therefore, the recognition result is recognition failure.

[0055] Step 300: If the identification result indicates that the identification has failed, then the current process film layer is self-aligned based on the alignment mark design pattern in the current process film layer; the alignment mark design pattern is set on the periphery of the device functional area design pattern in the current process film layer.

[0056] Understandably, if the recognition result indicates successful recognition, the alignment and photolithography of the current process film layer are performed based on the alignment mark entity pattern in the previous process film layer, without using the alignment mark design pattern in the current process film layer for alignment. The alignment techniques used in aligning the current process film layer based on the alignment mark entity pattern in the previous process film layer can refer to relevant technologies and will not be elaborated further.

[0057] Analysis of the beneficial effects of this embodiment: The embodiment of the present invention first attempts to identify the alignment mark entity pattern of the previous process film layer. If the identification is successful, the alignment technology in the existing technology is continued. Secondly, when the identification fails, the wafer fabrication process is not suspended. Instead, the self-alignment is achieved directly based on the alignment mark design pattern of the current process film layer. This avoids the extra operation of improving the previous layer mark and avoids process interruption, fundamentally solving the efficiency bottleneck of the existing solution, while meeting the industry demand for alignment without relying on the previous layer mark.

[0058] See Figure 2 In an optional embodiment, step 300: performing self-alignment and photolithography on the current process film layer based on the alignment mark design pattern of the current process film layer, including: Step 310: Obtain the mask image data corresponding to the alignment mark design pattern on the mask and the wafer image data corresponding to the wafer; both the mask image data and the wafer image data are obtained by capturing images using the optical sensor in the lithography machine; It should be noted that mask image data is the imaging of the "alignment mark design pattern" on the mask, while wafer image data is the imaging of the corresponding area of ​​the current process film layer on the wafer. The two are direct corresponding data of the same design pattern at the template end and the execution end.

[0059] Before taking pictures, the deposition of the current process film and the coating of photoresist must be completed to ensure that the corresponding area on the wafer is ready for imaging.

[0060] Step 320: Extract the reference position of the alignment mark design pattern on the mask from the mask image data, and extract the actual position of the alignment mark design pattern on the wafer from the wafer image data; It should be noted that the reference position is the standard coordinate of the alignment mark design pattern on the mask; the actual position is the real coordinate of the area corresponding to the current film layer on the wafer.

[0061] This step does not rely on the features of the previous layer's markers; it extracts the image based solely on the current image's own graphic contours, brightness, and contrast, ensuring complete decoupling from the entity graphics of the previous layer's markers.

[0062] Step 330: Calculate the deviation between the reference position and the actual position, and align the actual position with the reference position based on the deviation to achieve self-alignment of the current process film layer.

[0063] Deviation is the geometric difference between the reference position and the actual position, including offsets in dimensions such as translation and rotation, and is the core data for controlling wafer movement.

[0064] The beneficial effects of this embodiment are: 1) Achieving dependency-free alignment: It eliminates the need to call up the alignment mark entity pattern of the previous process film layer. Even if the previous layer mark cannot be identified due to factors such as excessive film thickness, reflection, or etching residue, wafer fabrication can continue, completely avoiding process interruptions. 2) Ensuring alignment accuracy: Through direct comparison of "template-end data - execution-end data," using the design pattern as a unified benchmark, alignment errors caused by interference from the previous layer mark are avoided, ensuring the lithography accuracy of the current film layer. 3) Improving process efficiency: It eliminates the need for redundant "improving the previous layer mark" operations, reducing wafer fabrication pause time and solving the efficiency bottleneck of existing solutions. 4) Enhancing process adaptability: It adapts to various interference scenarios during wafer fabrication, eliminating the need to adjust the process for previous layer mark issues, making the lithography process more stable and versatile.

[0065] In an alternative embodiment, see Figure 3 or Figure 4 The alignment mark design graphic includes four mark units; the four mark units are respectively set at the four corners of the preset rectangular area, the preset rectangular area contains the device functional area design graphic and the center of the preset rectangular area coincides with the center of the device functional area design graphic. Figure 3 and Figure 4The device area in the figure is the device functional area mentioned in the embodiments of the present invention.

[0066] See Figure 3 Each marking unit is an L-shaped marking unit; each L-shaped marking unit includes a first checkerboard pattern extending along the X-axis and a second checkerboard pattern extending along the Y-axis; the first checkerboard pattern and the second checkerboard pattern intersect perpendicularly to form a corner.

[0067] See Figure 4 Each marking unit is a long, rectangular checkerboard marking unit; each long, rectangular checkerboard marking unit is a third checkerboard pattern extending in a single direction; the long, rectangular checkerboard marking unit has an axis of symmetry parallel to the direction of extension; the single direction is either the X-axis or the Y-axis.

[0068] The checkerboard pattern is a grid structure with alternating light and dark areas, which can enhance the optical contrast between the marking unit and the surrounding film layer. This is because, compared with a single line, the difference between reflection and transmission of light in the checkerboard pattern is more obvious, which can ensure that the optical sensor of the lithography machine can clearly capture the marking outline, providing a clear imaging basis for subsequent edge extraction and avoiding edge recognition failure due to insufficient contrast.

[0069] In this embodiment, four marker units are evenly distributed at the four corners of a preset rectangular area, which can form a diagonal coverage in space. This avoids accidental errors when a single marker unit is positioned, such as a single marker being obscured by local stains or having unclear edges. The integrity of the position representation is improved by positioning multiple markers together.

[0070] The preset rectangle must include the device functional area and have their centers coincide. This strongly binds the positioning reference of the alignment mark to the spatial position of the device functional area, ensuring that after the alignment operation is completed, the pattern of the device functional area can be accurately placed in the preset processing area of ​​the wafer, avoiding pattern offset caused by the deviation between the alignment reference and the device area. At the same time, this design allows the marking unit to avoid the device functional area, preventing the optical signal during marking recognition from interfering with the device pattern.

[0071] See Figure 5 Step 320: Extract the reference position of the alignment mark design pattern on the mask from the mask image data, and extract the actual position of the alignment mark design pattern on the wafer from the wafer image data, including: Step 321: Using the Canny edge detection method, extract multiple edges corresponding to each of the four marked units from the mask image data and the wafer image data respectively; Each marker unit has multiple sets of contour edges. Extracting multiple edges can fully reflect the geometric shape of the marker unit and avoid positioning deviations caused by local edge defects when only a single edge is extracted.

[0072] Canny edge detection employs a multi-scale optimization scheme: multiple sets of edge results are obtained through Gaussian filtering with different standard deviations σ, and only pixels that are detected as edges under M consecutive σ are retained to construct a consistent-scale edge map, filtering out isolated false edges caused by noise; subsequently, gradient calculation is used to lock the boundaries of the checkerboard light and dark transitions, which are then refined into single-pixel edges through non-maximum suppression, and weak edges are connected through dual threshold detection to ensure the continuity and accuracy of edge extraction.

[0073] Step 322: Perform straight line fitting on the multiple edges corresponding to each marker unit to determine the reference position corresponding to the mask image data and the actual position corresponding to the wafer image data.

[0074] Understandably, the extracted edges may be discrete due to minor errors in image acquisition accuracy and label making (e.g., the edges are not perfectly regular straight lines). Line fitting can transform discrete edge points into regular straight lines, eliminate local minor errors, and make the edge representation closer to the ideal shape of the designed graphic.

[0075] The beneficial effects of this embodiment are as follows: 1) All operations are based on the alignment mark design pattern of the current process film layer itself, without the need to call the marks of the previous process film layer. Even if the previous layer mark is completely unrecognizable, positioning can be completed through the current layer mark, without pausing the wafer fabrication to improve the previous layer mark, fundamentally solving the problem of process interruption due to previous layer mark failure. 2) The four corner distribution of the four mark units can cover a larger spatial range, reducing the random error of single-point positioning; Canny edge detection combined with straight line fitting can effectively filter noise and correct edge discrete errors, ensuring the extraction accuracy of the reference position and the actual position. Compared with the alignment deviation caused by inaccurate recognition of the previous layer mark in the prior art, this solution avoids the transmission of the previous layer mark error to the current layer through autonomous positioning of the current layer, improving the accuracy of the lithography pattern.

[0076] In an optional embodiment, when each marker unit is an L-shaped marker unit, step 321: using the Canny edge detection method, extracting multiple edges corresponding to each of the four marker units from the mask image data and wafer image data, including: The Canny edge detection method is used to extract the horizontal edge corresponding to the first checkerboard pattern and the vertical edge corresponding to the second checkerboard pattern in each L-shaped marker unit from the mask image data and the wafer image data, respectively.

[0077] The horizontal and vertical edges of the L-shaped marker are regular straight lines. The Canny algorithm can accurately distinguish the edges from the background through noise suppression and gradient calculation. It is especially suitable for the high contrast characteristics of the checkerboard pattern, avoiding noise interference caused by film reflection and uneven photoresist coating. It ensures that the extracted horizontal and vertical edges are continuous and unbroken, providing reliable edge data for subsequent straight line fitting.

[0078] Step 322: Perform straight line fitting on multiple edges corresponding to each marker unit to determine the reference position corresponding to the mask image data and the actual position corresponding to the wafer image data, including: The first fitted line is obtained by fitting a straight line to the horizontal edge corresponding to the first checkerboard pattern. The second fitted line is obtained by fitting a straight line to the vertical edge corresponding to the second checkerboard pattern. The coordinates of the intersection point of the first and second fitted lines are determined as the first target coordinates; The reference position is determined based on the four first target coordinates corresponding to the mask image data, and the actual position is determined based on the four first target coordinates corresponding to the wafer image data.

[0079] The corner of an L-shaped marker is its unique geometric reference. The intersection of the horizontal edge (X-axis reference) and the vertical edge (Y-axis reference) can simultaneously represent the precise position of the marker unit on both the X and Y axes, and is the smallest positioning unit of a single L-shaped marker unit. Using the intersection point as the target coordinate, the spatial position of the marker unit can be completely characterized by a single point, which is more accurate than positioning using the edge midpoint, because the midpoint can only represent the position in a single direction, while the intersection point covers two directions. Furthermore, the coordinates of the intersection points of the subsequent four L-shaped markers can jointly constitute a stable position reference or actual position.

[0080] See Figure 3 Four L-shaped marker units are distributed at the top left, bottom left, top right, and bottom right corners of a preset rectangle. In a specific embodiment, assuming the center of the preset rectangular area is the coordinate origin (0,0) and the side length of the preset rectangle is 200μm, the four L-shaped marker units are located at: Top left corner: The first fitted line (horizontal edge) in the mask image is y=100μm, the second fitted line (vertical edge) is x=-100μm, and the intersection point is (-100,100), which is the first target coordinate of the mark; Lower left corner: The first fitted line in the mask image is y=-100μm, the second fitted line is x=-100μm, and the intersection point is (-100,-100); Top right corner: The first fitted line in the mask image is y=100μm, the second fitted line is x=100μm, and the intersection point is (100,100). Bottom right corner: The first fitted line in the mask image is y=-100μm, the second fitted line is x=100μm, and the intersection point is (100,-100).

[0081] After the actual edges extracted from the wafer image are fitted, the actual intersection coordinates of the four corners are obtained. The deviation can be calculated by comparing them with the mask reference coordinates.

[0082] The beneficial effects of this embodiment are as follows: 1) The checkerboard structure of the L-shaped mark enhances optical contrast, and the Canny algorithm can accurately extract horizontal and vertical edges, avoiding positioning deviations caused by edge blurring; 2) The intersection point after straight line fitting is used as the target coordinate, which can simultaneously lock the position in both the X and Y directions. Compared with the alignment deviation caused by inaccurate identification of the previous layer mark in the prior art, this solution completely avoids the transmission of the previous layer mark error to the current layer through autonomous positioning of the current layer, ensuring that the photolithographic pattern of the current process film layer is highly consistent with the design pattern, and improving product yield.

[0083] In an optional embodiment, when the marking unit is a long, checkerboard-shaped marking unit, step 321: using the Canny edge detection method, extract multiple edges corresponding to each of the four marking units from the mask image data and the wafer image data, including: The Canny edge detection method is used to extract the two parallel edges corresponding to the third checkerboard pattern in each long checkerboard marker unit from the mask image data and the wafer image data, respectively.

[0084] Step 322: Perform straight line fitting on multiple edges corresponding to each marker unit to determine the reference position corresponding to the mask image data and the actual position corresponding to the wafer image data, including: By fitting straight lines to the two parallel edges respectively, we obtain the third and fourth fitted lines. The midpoint coordinates of the midline between the third and fourth fitted lines are determined as the second target coordinates. Here, the midline refers to a virtual line parallel to both the third and fourth fitted lines and equidistant from their perpendicular distances. This midline is distributed along the extension direction of the elongated marker unit, and its midpoint coordinates are the coordinates of the center position of the midline within the geometric range of the marker unit, i.e., the geometric center coordinates of the elongated marker unit itself. For example, if the elongated marker unit extends along the X-axis, and the third fitted line is y=5μm and the fourth fitted line is y=15μm, then the midline is y=10μm. If the range of the marker unit on the X-axis is x=20μm to x=80μm, the midpoint coordinates of the midline are (50,10), which is also the geometric center coordinates of the elongated marker unit.

[0085] The reference position is determined based on the coordinates of the four second targets corresponding to the mask image data, and the actual position is determined based on the coordinates of the four second targets corresponding to the wafer image data.

[0086] It should be noted that the midline of the two parallel fitted lines is exactly the axis of symmetry of the elongated mark, ensuring that the positioning point is on the geometric center line of the mark and avoiding local deviations caused by the positioning point shifting to the edge area. The midpoint of the midline is the core positioning point of the entire elongated mark. The midpoint represents the spatial position of a single mark, and the coordinates of the midpoints of the four mark units can jointly constitute the reference position (mask end) or actual position (wafer end) of the current process film layer alignment mark, realizing multi-point collaborative positioning and improving the overall alignment stability.

[0087] Understandably, the elongated markers extend along a single X-axis or Y-axis, with the core purpose of allowing each marker unit to focus on a single-dimensional positioning function: for example, a marker extending along the X-axis is specifically responsible for X-direction positioning calibration, and a marker extending along the Y-axis is specifically responsible for Y-direction calibration. Combined with a layout of four marker units distributed at the four corners of a pre-defined rectangular area, the four elongated markers can cover both X and Y-dimensional positioning in the plane through "two X-directions and two Y-directions" or "a combination of all X-directions or all Y-directions," eliminating the need for a single marker to handle both dimensions, simplifying marker graphic design while avoiding dimensional interference.

[0088] For example, the marking parameters are designed as follows for different lithography machines and film types: (1) DUV lithography machine scenario: square checkerboard array with square grid side length of 3-8μm and grid spacing of 2-4μm; L-shaped marking with long arm of 10-15μm, short arm of 5-8μm and arm width of 2-3μm; long strip marking with length of 15-20μm and width of 2-3μm. (2) EUV lithography machine scenario: square checkerboard array with square grid side length of 0.3-0.8μm and grid spacing of 0.2-0.4μm; L-shaped marking with long arm of 2-5μm, short arm of 1-2.5μm and arm width of 0.3-0.5μm; long strip marking with length of 5-8μm and width of 0.3-0.5μm. (3) Optical contrast requirements: The difference between the marking and the reflectance of the transparent dielectric film is greater than or equal to 40%, which can be achieved by depositing 50-100nm TiN metal; the difference between the marking and the reflectance of the metal film is greater than or equal to 35%, which can be achieved by plasma oxidation treatment at 200-300℃ for 30-60s.

[0089] The beneficial effects of this embodiment are as follows: 1) The extraction stage focuses only on two parallel edges, avoiding redundant calculations of the edges of small internal grids and reducing algorithm time; the logic of straight line fitting, midline and midpoint calculation is simple and clear, without the need for complex feature matching (such as template matching), reducing computational power consumption; the efficiency of the overall steps reduces the time cost of alignment operations, while reducing the rework rate caused by positioning failures, further improving the overall tape-out efficiency. 2) The long strip markers support extension in a single direction of the X-axis or Y-axis, which can flexibly adapt to the layout requirements of different process film layers: for example, short long strip markers are suitable for narrow side areas, and long long strip markers are suitable for wide side areas; and the high contrast characteristics of the checkerboard pattern can adapt to different types of process film layers such as transparent dielectric films and metal films, without the need to adjust the marker design for film layer types, improving the versatility of the solution.

[0090] In an optional embodiment, step 330: calculating the deviation between the reference position and the actual position includes: Step 1: Use the formula: (1); Calculate the single-mark deviation for each marker unit; wherein, the reference position includes four reference coordinates; each reference coordinate includes an x-axis reference coordinate and a y-axis reference coordinate; the actual position has four actual coordinates; each actual coordinate includes an x-axis actual coordinate and a y-axis actual coordinate. For the first X-axis single-mark deviation of each marking unit; For the first Y-axis single-mark deviation of each marking unit; For the first One X-axis reference coordinate; For the first One Y-axis reference coordinate; For the first Each X-axis actual coordinate; For the first Each actual Y-axis coordinate; .

[0091] Understandably, It is the first one on the photomask. The reference coordinates of each marking unit are "standard positions" predetermined in the design phase. They are the target references for alignment and will not change with the actual process. It is the first on the wafer The actual coordinates of each marker unit are the "true positions" obtained by taking pictures with an optical sensor and extracting edges, and are affected by wafer placement deviations. Corresponding to the structure mentioned above where the four marker units are distributed at the four corners of a preset rectangular area, this ensures that the deviation of each marker unit is calculated individually.

[0092] The deviation is calculated for each of the four marker units first, rather than directly calculating the overall deviation. This is to preserve the local offset information of each marker. Since the four markers are distributed in different positions (the four corners) of the wafer, the deviation of a single marker may vary. For example, a slightly thicker corneal layer may cause the actual coordinates to shift. Calculating the deviation separately can prevent the error of a single marker from being masked by the overall deviation, and provide accurate raw data for subsequent global deviation calculation. Indicates the first Each marker indicates the offset of the actual position relative to the reference position in the X-axis direction (positive value = actual position to the right of the reference, negative value = actual position to the left of the reference). Similarly, the offset along the Y-axis is used to quantify the translational deviation of a single marker.

[0093] Step 2: Substitute the single-mark deviation of each marking unit into the formula: (2); Obtain the global offset; where, This is the global X-axis offset; This is the global Y-axis offset.

[0094] It should be noted that the averaging method was chosen because: the four marks are evenly distributed at the four corners of the wafer, and the deviation of a single mark may contain random errors. Averaging allows positive and negative errors to dilute each other, canceling out random errors. , It more closely approximates the actual overall translational deviation of the wafer relative to the mask. The two together constitute the global deviation of the translational dimension, solving the problem that the overall translational trend of the wafer cannot be determined by looking at a single mark.

[0095] Step 3: Use the formula: (3); Calculate the global rotation angle; where, This is the global rotation angle; It is the arctangent function; Step 4: Determine the global offset and global rotation angle as deviations.

[0096] Alignment deviations between the wafer and the photomask mainly include two types: translation and rotation. A single dimension cannot fully describe the deviation. Combining translation and rotation constitutes a complete global deviation, providing precise quantitative data for subsequent adjustments to the wafer carrier. The wafer carrier can then adjust accordingly. , Adjust the translation position according to Adjust the rotation angle to achieve full-dimensional alignment.

[0097] The beneficial effects of this embodiment are as follows: 1) The process of averaging the single mark deviation of each mark unit in multiple mark units to the global average cancels out the random error of a single mark and avoids the single mark error from being amplified into a global deviation; the rotation angle is averaged by two sets of diagonals, which dilutes the error of a single set of diagonals and ensures that the global rotation angle calculation is stable. Compared with relying on a single front-layer mark to calculate the deviation (which is easily affected by the mark error), the deviation calculation of the present invention is more reliable, reduces alignment rework caused by random errors, and further improves the chip fabrication efficiency.

[0098] 2) In the background technology, if the identification of the front-layer marking is blurry, the deviation may be unquantifiable, and adjustments can only be made based on experience, such as "approximately moving it to the right a little," which is prone to over-adjustment or under-adjustment. The solution of this invention uses a formula to accurately calculate the global deviation, providing quantitative values ​​for the adjustment of the wafer carrier stage, such as "moving it 0.15μm to the left along the X-axis and rotating it 0.03° counterclockwise," avoiding the uncertainty of experience-based adjustments, shortening the alignment time, and improving the stability of the photolithography process.

[0099] After aligning the wafer containing the current process film layer with the mask using the aforementioned global deviation, the alignment mark design pattern and device functional area design pattern on the mask are then transferred to the photoresist for exposure, development, and etching to obtain the alignment mark physical pattern and device functional area physical pattern in the current process film layer.

[0100] In an optional embodiment, before acquiring the mask image data corresponding to the alignment mark design pattern on the mask and the wafer image data corresponding to the wafer, the method further includes: depositing a current process film layer and coating the surface of the current process film layer with photoresist. This step is a physical prerequisite for acquiring the mask image data and the wafer image data, because the subsequent identification of alignment marks and deviation calculations all require the premise that "a formed current process film layer exists on the wafer and the film layer surface has photoresist": the process film layer is the carrier of the alignment mark design pattern, and the photoresist is the medium for transferring the mask pattern (alignment mark design pattern and device functional area design pattern) to the film layer, which requires exposure, development, and etching to form the physical pattern.

[0101] As mentioned above, the current process film layer is a single-layer structure or a multi-layer structure.

[0102] When the current process film layer is a multilayer structure, the current process film layer is deposited and photoresist is coated on the surface of the current process film layer, including: (1) Based on the structural design of the multilayer structure, the bottom layer (e.g., seed layer of metal interconnect layer) and the intermediate layer (e.g., barrier layer) of the current process film layer of the multilayer structure are deposited sequentially.

[0103] (2) A marking base pattern is formed on the periphery of the device functional area of ​​the bottom film layer. The position of the marking base pattern corresponds to the position of the alignment mark design pattern of the current film layer. This step is used to avoid interlayer offset of multiple film layers and ensure that the subsequent marking entity pattern is accurately formed.

[0104] Regarding the marking of the basic pattern, multilayer structures pose a risk of interlayer misalignment. During the sequential deposition of the bottom, intermediate, and top layers, slight misalignments in each layer can accumulate due to factors such as slight movement of the wafer stage and uneven film deposition. This can cause the alignment mark position of the final top layer to deviate from the design value. Marking the basic pattern on the bottom layer in advance provides a positioning reference for the subsequent deposition of the intermediate and top layers. Subsequent layers can then align around this basic pattern, preventing the cumulative effect of interlayer misalignments.

[0105] (3) The top layer of the current process film layer (e.g., the electroplated layer of the metal interconnect layer) of the multilayer structure is deposited, and photoresist is coated on the upper surface of the top layer.

[0106] When the current process film layer is a single-layer structure, the current process film layer is deposited and photoresist is coated on the surface of the current process film layer, including: Current process technology for depositing monolayer structures; Photoresist is coated on the upper surface of the current process film with a single-layer structure.

[0107] The beneficial effects of this embodiment are as follows: 1) If a multilayer film lacks a basic marking pattern, the alignment mark position is prone to deviate from the design value due to interlayer offset, leading to deviation calculation errors. This solution sets a basic marking pattern on the bottom film layer, providing a fixed reference for subsequent intermediate and top layer deposition, effectively offsetting minor deviations in interlayer deposition, and ensuring that the alignment mark physical pattern on the final top film layer is highly consistent with the design pattern. When calculating deviations based on this accurate mark, the alignment error caused by inaccurate mark position can be significantly reduced, improving the forming accuracy of the photolithography pattern and reducing yield loss caused by interlayer offset. 2) The solution clearly distinguishes the deposition and coating processes for single-layer and multilayer structures. Single-layer structures simplify the steps and do not require marking a basic pattern, adapting to film layers with simple functions; multilayer structures add a basic pattern step, adapting to film layers with complex functions, eliminating the need to design new solutions for different structures, covering common film types in the fabrication process, enhancing the process adaptability of the self-alignment solution, and reducing the complexity of technology implementation.

[0108] Combination Figure 6In one specific embodiment, the wafer fabrication photolithography alignment method of the present invention is applied to the back-end process. The process cross section from bottom to top is as follows: the previous process layer (i.e., the process layer above the current process film layer) → the previous layer marking pattern (i.e., the alignment mark entity pattern in the previous process film layer, which fails to be identified due to excessive film thickness or etching residue) → the current process film layer → the current process pattern (i.e., the device functional area entity pattern in the current process film layer) → the current process marking pattern (i.e., the alignment mark design pattern in the current process film layer, which is an L-shaped or long strip checkerboard pattern, located near the outer cutting channel of the device functional area, and does not overlap with the previous layer marking pattern in the vertical direction. After etching, it can be used as the alignment reference for the subsequent metal layer).

[0109] In an optional embodiment, the wafer fabrication photolithography alignment method further includes: after the alignment mark entity pattern and the device functional area entity pattern of the current process film layer are etched and formed, identifying the alignment mark entity pattern in the current process film layer; If the identification is successful, the subsequent process film layers are aligned and photolithographically processed based on the alignment mark entity pattern in the current process film layer. If recognition fails, self-alignment and photolithography are performed based on the independent alignment mark design pattern of the next process film layer.

[0110] The beneficial effects of this embodiment are as follows: 1) This embodiment, by "if the current layer mark is successfully identified, the subsequent film layers are directly aligned using the current layer mark," shifts the alignment reference of the subsequent film layers from the "early previous layer" to the "newly formed current layer." The current layer mark has just been etched and is not subject to interference from subsequent film layers, resulting in a clear pattern and accurate positioning. This not only reduces the dependence on the early previous layer mark but also avoids the problem of "early mark errors propagating to multiple subsequent layers," significantly improving the overall alignment accuracy of multi-film layer stacking. 2) In the scenario of "current layer mark recognition failure," there is no requirement to "repair the current layer mark." Instead, the independent alignment mark design pattern of the next film layer is directly used. The next film layer does not need to rely on any previous layer (including the currently failed layer) and can complete self-alignment through its own mark, completely avoiding the problem of the entire process being suspended due to the failure of a certain layer mark. From the perspective of operational logic, this ensures the continuity of the wafer fabrication and completely solves the efficiency bottleneck of the background technology. 3) The current layer mark is a solid pattern that has already been etched and formed. Compared with the design pattern, it is closer to the actual process state, and there is no subsequent processing interference when it is newly formed. The pattern outline is clear and the edge positioning is accurate. If subsequent film layers reuse the current layer marker for alignment, compared to relying on "early previous layer markers that have undergone multiple processes and may be damaged", the alignment error caused by marker recognition deviation can be significantly reduced, ensuring that the device functional areas of subsequent film layers are accurately aligned with the current layer, reducing chip functional failures caused by misalignment, and improving product yield. 4) During the tape-out process, the current layer marker may fail due to unexpected situations such as over-etching, photoresist residue, and film material characteristics. This embodiment adopts a dual-path design of "reuse priority + self-alignment backup", which covers both the conventional scenarios where the current layer marker can be used (reuse improves efficiency) and the special scenarios where the current layer marker fails (self-alignment backup). There is no need to adjust the overall process scheme for different marker states, which greatly enhances the adaptability of the alignment method to complex tape-out scenarios and reduces the complexity and operating cost of process adjustment.

[0111] Although the invention has been described herein in conjunction with various embodiments, those skilled in the art will understand and implement other variations of the disclosed embodiments by reviewing the accompanying drawings, the disclosure, and the appended claims in carrying out the claimed invention. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality. A single processor or other unit can implement several functions listed in the claims. While different dependent claims may recite certain measures, this does not mean that these measures cannot be combined to produce good results.

[0112] Although the invention has been described in conjunction with specific features and embodiments, it is obvious that various modifications and combinations can be made therein without departing from the spirit and scope of the invention. Accordingly, this specification and drawings are merely exemplary descriptions of the invention as defined by the appended claims, and are considered to cover any and all modifications, variations, combinations, or equivalents within the scope of the invention. Clearly, those skilled in the art can make various alterations and modifications to the invention without departing from its spirit and scope. Thus, if such modifications and modifications of the invention fall within the scope of the claims and their equivalents, the invention is also intended to include such modifications and modifications.

Claims

1. A wafer fabrication photolithography alignment method, characterized in that, include: Obtain the process parameters for wafer fabrication photolithography; Based on the process parameters, the alignment mark entity pattern in the previous process film layer of the current process film layer in the wafer is identified to obtain the identification result; If the identification result indicates that the identification has failed, then the current process film layer is self-aligned based on the alignment mark design pattern in the current process film layer; The alignment mark design pattern is set around the device functional area design pattern in the current process film layer.

2. The wafer fabrication photolithography alignment method according to claim 1, characterized in that, Self-alignment of the current process film layer based on the alignment mark design pattern in the current process film layer includes: The mask image data corresponding to the alignment mark design pattern on the photomask and the wafer image data corresponding to the alignment mark design pattern on the wafer are obtained; both the mask image data and the wafer image data are obtained by capturing images using an optical sensor in a lithography machine; Extract the reference position of the alignment mark design pattern on the mask from the mask image data, and extract the actual position of the alignment mark design pattern on the wafer from the wafer image data; Calculate the deviation between the reference position and the actual position, and control the actual position to align with the reference position based on the deviation to achieve self-alignment of the current process film layer.

3. The wafer fabrication photolithography alignment method according to claim 2, characterized in that, The alignment mark design graphic includes four mark units; the four mark units are respectively set at the four corners of a preset rectangular area, the preset rectangular area contains a device functional area design graphic and the center of the preset rectangular area coincides with the center of the device functional area design graphic; Extracting the reference position of the alignment mark design pattern on the mask from the mask image data, and extracting the actual position of the alignment mark design pattern on the wafer from the wafer image data, includes: The Canny edge detection method is used to extract multiple edges corresponding to each of the four marker units from the mask image data and the wafer image data, respectively. For each marker unit, multiple edges are fitted with straight lines to determine the reference position corresponding to the mask image data and the actual position corresponding to the wafer image data.

4. The wafer fabrication photolithography alignment method according to claim 3, characterized in that, Each marking unit is an L-shaped marking unit; each L-shaped marking unit includes a first checkerboard pattern extending along the X-axis and a second checkerboard pattern extending along the Y-axis; the first checkerboard pattern and the second checkerboard pattern intersect perpendicularly to form a corner; When the marker unit is an L-shaped marker unit, the Canny edge detection method is used to extract multiple edges corresponding to each of the four marker units from the mask image data and the wafer image data, including: Using the Canny edge detection method, the horizontal edge corresponding to the first checkerboard pattern and the vertical edge corresponding to the second checkerboard pattern in each L-shaped marker unit are extracted from the mask image data and the wafer image data, respectively.

5. The wafer fabrication photolithography alignment method according to claim 4, characterized in that, Each marking unit is a long, rectangular checkerboard marking unit; each long, rectangular checkerboard marking unit is a third checkerboard pattern extending in a single direction; When the marking unit is a long, rectangular checkerboard marking unit, the Canny edge detection method is used to extract multiple edges corresponding to each of the four marking units from the mask image data and the wafer image data, including: Using the Canny edge detection method, two parallel edges corresponding to the third checkerboard pattern in each elongated checkerboard marker unit are extracted from the mask image data and the wafer image data, respectively.

6. The wafer fabrication photolithography alignment method according to claim 5, characterized in that, When the marking unit is an L-shaped marking unit, straight line fitting is performed on multiple edges corresponding to each marking unit to determine the reference position corresponding to the mask image data and the actual position corresponding to the wafer image data, including: A first fitted straight line is obtained by fitting a straight line to the horizontal edge corresponding to the first chessboard pattern. A second fitted line is obtained by fitting a straight line to the vertical edge corresponding to the second checkerboard pattern. The coordinates of the intersection point of the first fitted line and the second fitted line are determined as the first target coordinates; The reference position is determined based on the four first target coordinates corresponding to the mask image data, and the actual position is determined based on the four first target coordinates corresponding to the wafer image data; When the marking unit is a long, rectangular checkerboard marking unit, straight line fitting is performed on multiple edges corresponding to each marking unit to determine the reference position corresponding to the mask image data and the actual position corresponding to the wafer image data, including: By performing line fitting on the two parallel edges respectively, a third fitted line and a fourth fitted line are obtained; The coordinates of the midpoint of the median line between the third and fourth fitted lines are determined as the second target coordinates. The reference position is determined based on the four second target coordinates corresponding to the mask image data, and the actual position is determined based on the four second target coordinates corresponding to the wafer image data.

7. The wafer fabrication photolithography alignment method according to claim 3, characterized in that, Calculating the deviation between the reference position and the actual position includes: Formula used: ； Calculate the single-mark deviation for each marked unit; where, For the first X-axis single-mark deviation of each marking unit; For the first Y-axis single-mark deviation of each marking unit; For the first One X-axis reference coordinate; For the first One Y-axis reference coordinate; For the first Each X-axis actual coordinate; For the first One actual Y-axis coordinate; ; Substitute the single-mark deviation of each marker unit into the formula: ； Obtain the global offset; where, This is the global X-axis offset; This is the global Y-axis offset; Formula used: ； Calculate the global rotation angle; where, The global rotation angle; It is the arctangent function; The global offset and the global rotation angle are determined as the deviation.

8. The wafer fabrication photolithography alignment method according to claim 2, characterized in that, Before acquiring the mask image data corresponding to the alignment mark design pattern on the mask and the wafer image data corresponding to the wafer, the method further includes: depositing the current process film layer and coating the surface of the current process film layer with photoresist; the current process film layer is a single-layer structure or a multi-layer structure; When the current process film layer is a multilayer structure, depositing the current process film layer and coating the surface of the current process film layer with photoresist includes: Based on the multilayer structure design, the bottom layer and the intermediate layer of the current process film layer are deposited sequentially. A basic marking pattern is formed around the device functional area of ​​the bottom film layer, and the position of the basic marking pattern corresponds to the position of the alignment marking design pattern of the current film layer. The top layer of a current process for depositing multilayer structures is coated with photoresist on its upper surface. When the current process film layer is a single-layer structure, depositing the current process film layer and coating the surface of the current process film layer with photoresist includes: Current process technology for depositing monolayer structures; Photoresist is coated on the upper surface of the current process film layer of the single-layer structure.

9. The wafer fabrication photolithography alignment method according to claim 3, characterized in that, The process parameters include the size parameters of the alignment mark entity graphic in the previous process film layer and the preset recognition standard; The preset recognition criteria include contour overlap greater than or equal to a preset percentage, signal-to-noise ratio greater than or equal to a preset value, and edge positioning deviation less than a preset length. Based on the process parameters, the alignment mark entity pattern in the previous process film layer of the current process film layer in the wafer is identified to obtain the identification result, including: The intensity of reflected light or transmitted light within a preset scanning area is collected, and the signal-to-noise ratio of the collected signal is calculated. The preset scanning area is a region that includes the area where each marker unit is located, is located within a preset rectangular area, and avoids the functional area of ​​the device. If the light intensity of a preset number of pixels continuously collected within the preset scanning area is less than the noise baseline, it is determined that no imaging signal of the alignment mark entity graphic has been received, and the recognition result is recognition failure. If an imaging signal is received, the standard outline of the alignment mark entity graphic is deduced based on the size parameters, and the actual shape outline and the standard outline are compared to obtain the outline overlap. Based on the size parameters, the standard edge coordinates of the alignment mark entity graphic are determined, and the edge positioning difference between the actual extracted edge coordinates and the standard edge coordinates is calculated. Determine whether the signal-to-noise ratio, the contour overlap, and the edge localization difference all meet the preset recognition criteria; If all conditions are met, the recognition result is considered successful; otherwise, the recognition result is considered unsuccessful.

10. The wafer fabrication photolithography alignment method according to claim 1, characterized in that, Also includes: After the alignment mark entity pattern and the device functional area entity pattern of the current process film layer are etched and formed, the alignment mark entity pattern in the current process film layer is identified. If the identification is successful, the subsequent process film layers are aligned and photolithographically processed based on the alignment mark entity pattern in the current process film layer. If recognition fails, self-alignment and photolithography are performed based on the independent alignment mark design pattern of the next process film layer.

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