Integrated layered circuit architecture of carrier rocket time sequence driving and acquisition module

Abstract

The invention belongs to the technical field of carrier rocket electrical systems, and particularly relates to an integrated layered circuit architecture of a carrier rocket time sequence driving and acquisition module and a control method. The framework adopts a vertical stacking design of a carrier plate layer and a pinch plate layer: the carrier plate layer is integrated with high-power devices, comprises an initiating explosive device driving relay, a test channel switching relay, a TVS protection circuit, an electromagnetic valve MOSFET and a fly-wheel diode, and dissipates heat through an aluminum silicon carbide metal substrate; the pinch plate layer carries an FPGA and a logic control circuit and is interconnected with the carrier plate layer through a board-to-board high-speed connector. Three-in-one function integration is innovatively provided, wherein the initiating explosive device module integrates the driving-testing-protecting function, and the electromagnetic valve module integrates the driving-collecting-follow current function. According to the control method, dynamic fault isolation is realized based on the FPGA, and the control method comprises the steps of double-path protection-releasing signal CRC verification, voltage slope real-time monitoring and two-out-of-three voting logic of the triple-redundancy MOSFETs.

Description

Technical Field

[0001] This invention relates to the field of launch vehicle electrical system technology, specifically to an integrated hierarchical circuit architecture and control method for a launch vehicle timing drive and acquisition module. Background Technology

[0002] The defects of traditional timing control systems: The current launch vehicle timing drive and acquisition system generally adopts a discrete module design, which has three major technical bottlenecks: (1) The problem of flying wires is prominent: the timing drive, pyrotechnic test protection and solenoid valve acquisition modules are arranged independently, and the modules rely on cable interconnection. The number of connecting wires in a single module is more than 50. This not only increases the weight of the system (more than 15kg for typical rockets), but also causes the failure probability to be ≥1% due to loose connectors in the vibration environment. (2) Test blind zone exists: the pyrotechnic circuit test relies on the ground pyrotechnic equivalent device, and it is impossible to diagnose open circuit / short circuit faults on the rocket in real time. For example, a certain type of rocket failed to separate between stages due to the test blind zone. The accident analysis showed that the fault latency time was 100ms and was not detected. (3) Low maintenance efficiency: the power device and logic control board are integrated into a single module. When a fault occurs, the whole module needs to be replaced. The operation time is more than 30 minutes, and there are many types of spare parts. For example, a certain rocket model requires 12 types of drive modules.

[0003] Limitations of existing patented technologies: Galaxy Power's patent (CN117055384A) proposes a safety detection method for timing control circuits, limiting false trigger current through protective resistors, but it does not solve the problem of flying wires caused by module dispersion and relies on ground monitoring equipment. Dongfang Space's patent (CN119022728A) achieves avionics system integration, but does not address the internal architecture optimization of timing drive modules; pyrotechnics and solenoid valves are still designed on separate boards. East China Institute of Computing Technology's patent (CN111142444A) improves reliability, but it does not integrate testing and protection functions and is bulky (single module > 200mm × 150mm).

[0004] Technological Evolution Requirements: Based on the trends of spacecraft miniaturization and reusability, there is an urgent need for a highly integrated, vibration-resistant, reliable, and on-orbit maintainable timing-driven architecture. Key breakthroughs include: physical layering design of power devices and logic circuits to reduce flying wires; hardware-level integration of drive, test, and protection functions; and standardized modular devices across the entire rocket to reduce maintenance costs. Summary of the Invention

[0005] This invention proposes an integrated hierarchical circuit architecture and control method for a launch vehicle timing drive and acquisition module, aiming to overcome the challenge of achieving "high reliability, miniaturization, and easy maintenance" simultaneously in aerospace electronic systems, and to provide a general-purpose hardware platform for launch vehicles, satellites, and deep space probes.

[0006] This invention is achieved using the following technical solution: a layered circuit architecture for a launch vehicle timing drive and acquisition module, the core of which lies in the carrier board-clasp board layered architecture, achieving high-density integration and vibration resistance through vertical stacking, including:

[0007] The carrier layer, which serves as both a power and protection layer, integrates:

[0008] Pyrotechnic drive branch: The pyrotechnic main circuit consists of a magnetic latching relay and a test channel switching relay connected in series, and a TVS diode array protection circuit connected in parallel across the main circuit.

[0009] The mechanical structure of the carrier layer is a multi-layer PCB board with a size of 3U (100mm×160mm). Power devices are soldered on the surface to prevent connector failure. The substrate is made of aluminum silicon carbide metal composite material.

[0010] Solenoid valve drive branch: The solenoid valve drive circuit is formed by the MOSFET of the switching device and the sampling resistor connected in series, and a freewheeling diode and an RC snubber circuit are connected in parallel across the solenoid valve coil.

[0011] The carrier layer is made of aluminum silicon carbide metal substrate and the surface is potted with thermally conductive silicone.

[0012] The cladding layer serves as the control and logic layer, housing a radiation-resistant FPGA and its peripheral circuits. The FPGA runs a real-time control algorithm with a logic resource utilization rate of ≤80% to reserve space for reconfiguration.

[0013] Connection Structure: The carrier board layer and the backing board layer are vertically interconnected via a board-to-board high-speed connector, reducing traditional cables by 90%. This allows the FPGA's control signals to drive the relays and MOSFETs on the carrier board layer and to retrieve test and sampling signals from the carrier board layer. Thermal management includes an array of copper heat sinks embedded in the PCB and localized aluminum heat sink covers.

[0014] Preferably, the magnetic latching relay in the pyrotechnic device drive branch is a dual-redundant design, including two parallel magnetic latching relay contacts, controlled by the FPGA through an independent channel. The integrated drive-test-protection system for the pyrotechnic device module includes: Drive unit: The magnetic latching relay coil is driven by the FPGA via optocoupler isolation. The contacts are connected in parallel and output to the pyrotechnic device. The dual-channel design ensures that disengagement can still be performed in case of a single-path fault. Test unit: The FPGA controls a constant current source to output test current, which is injected into the circuit through a precision resistor. The ADC collects the voltage and calculates the circuit impedance. If the circuit impedance deviates from the nominal value by ±10%, an open circuit or short circuit fault is determined. Protection unit: A TVS diode is connected across the positive and negative terminals, and a self-destructing fuse is connected in series in the circuit. It physically blows in case of overcurrent. The FPGA only enables the protection relay to engage after the test passes.

[0015] Preferably, the MOSFETs in the solenoid valve drive branch are low-resistance devices with an on-resistance Rds(on) < 2mΩ; and the solenoid valve drive branch adopts a triple-redundancy design, including three MOSFETs, whose control terminals respectively receive three independent drive signals from the FPGA, and achieve a two-out-of-three fault-tolerant output through hardware or logic voting circuits. The drive-acquisition-freewheeling fusion implementation for the solenoid valve module includes: Drive unit: The gates of the three MOSFETs are independently controlled by the FPGA, using a two-out-of-three voting logic. Acquisition unit: The sampling resistor is connected to an operational amplifier, and the FPGA determines the stall by the real-time current slope. Freewheeling unit: At the moment of turn-off, the back electromotive force of the solenoid valve coil is discharged through the freewheeling diode, and the RC circuit absorbs high-frequency oscillations and suppresses voltage spikes.

[0016] Preferably, to reduce spare parts costs and maintenance difficulty, the entire rocket timing module achieves component standardization and interface standardization; the layered circuit architecture adopts a unified design, enabling hardware compatibility and software configurability between the pyrotechnic drive branch and the acquisition module, and the solenoid valve drive branch and the acquisition module, specifically including:

[0017] Hardware compatibility: The carrier board layers of the pyrotechnic drive branch and the acquisition module, and the carrier board layers of the solenoid valve drive branch and the acquisition module, use the same physical interface, board-to-board connector model, and installation dimensions, allowing them to be interchanged and paired with a unified mounting plate layer. The carrier board layer uses a unified power device model, and the physical interface is compatible with both pyrotechnic and solenoid valve mounting plates. Changing functions only requires plugging and unplugging the mounting plate, with an operation time of less than 2 minutes.

[0018] Device standardization: The same type of FPGA and bus interface are installed on the PCB layer of the pyrotechnic drive branch and the solenoid valve module.

[0019] Functional Configurability: By programming different FPGA configuration files onto a unified PCB layer, it can be configured to function specifically for pyrotechnic drive branches and acquisition modules or for solenoid valve drive branches and acquisition modules. FPGA Firmware Supports Online Updates: Configuration files are received via the TTE bus, allowing for dynamic reconstruction of logic resources. For example, switching the pyrotechnic channel to solenoid valve drive mode responds to task change requirements.

[0020] Preferably, the FPGA is configured to perform the following dynamic fault isolation process:

[0021] Real-time diagnostic process: Before the pyrotechnic device is deactivated, the control test switching relay is used to inject a constant test current, monitor the circuit impedance in real time, and compare it with a preset threshold to diagnose open circuit or short circuit faults.

[0022] Safety unlocking procedure: For pyrotechnic devices, two consecutive encrypted pulse signals must be received and verified before a drive signal is generated to the magnetic latching relay. After the drive signal is output, the current rise rate is monitored in real time. If the deviation from the model exceeds 20%, a potential fault is identified, the current path is immediately cut off, and a backup drive path is activated. Specifically: Dual-pulse unlocking: The command requires two consecutive encrypted pulses, and the FPGA verifies the pulse code and CRC. Voltage slope monitoring: The rising edge of the current is acquired at the moment of unlocking. If the slope deviation is >20%, a poor contact is identified, and the backup channel is switched. Real-time current comparison: The actual current value is obtained via ADC. If the deviation between the actual current value and the expected value is >1%, a fault code is recorded and uploaded via the TTE bus.

[0023] Fault-tolerant control process: For solenoid valves, a three-redundant MOSFET drive signal is used for a two-out-of-three voting logic output, and the drive current is monitored in real time. When overcurrent or jamming characteristics are detected, a soft shutdown operation of the PWM duty cycle is executed. Specifically, the solenoid valve fault-tolerant control is as follows: Three-redundant voting: The FPGA compares the three MOSFET drive signals, and the output state uses a two-out-of-three voting method. Temperature compensation algorithm: The sampling resistor value is calibrated based on a pre-stored resistor-thermometer (RT meter). Overcurrent soft shutdown: During overcurrent, the PWM duty cycle linearly drops to 0 to avoid mechanical shock.

[0024] Preferably, the safety unlocking process for pyrotechnic products includes: power-on self-test stage: FPGA controls a constant current source to inject test current, and ADC monitors the circuit impedance; unlocking command verification: two encrypted pulses need to be received continuously and pass CRC verification; execution stage: after the magnetic latching relay is engaged, the actual current value is compared with the expected value in real time.

[0025] Preferably, the closed-loop control process of the solenoid valve includes PWM generation: the FPGA outputs a duty cycle adjustable signal; current feedback: a Hall sensor monitors the real-time current and triggers soft shutdown when there is overcurrent; and temperature compensation: the sampling resistor value is calibrated based on a lookup table method.

[0026] Preferably, the layered circuit architecture is used for on-rocket test integration, including: a low-voltage test circuit built into the carrier board, which constructs a loop for self-testing through a constant current source and a resistor box; and a timing acquisition circuit that directly samples back the "timing+" line voltage without the need for external ground equipment.

[0027] Preferably, the anti-interference design of the layered circuit architecture includes: signal isolation using optocouplers and digital isolators; and grounding isolation using a single-point connection between power ground and digital ground via a ferrite bead.

[0028] Compared with the prior art, the present invention has the following beneficial effects:

[0029] (1) By using a layered architecture design, the contradictions between flying wires, vibration resistance and heat dissipation are resolved, reducing the number of interconnected flying wires by 90% and improving vibration resistance reliability by 10 times;

[0030] (2) The traditional discrete modules are overturned by the integration of three functions into one;

[0031] (3) Enhance security through dynamic fault isolation technology;

[0032] (4) By unifying the design across modules, costs and maintenance difficulty are reduced, and module replacement time is shortened to 2 minutes. Attached Figure Description

[0033] The present invention can be better understood by referring to the description given below in conjunction with the accompanying drawings, which are incorporated in and form part of this specification together with the following detailed description. In the drawings:

[0034] Figure 1 This is a schematic diagram of the carrier-clasp layered architecture according to an embodiment of the present invention;

[0035] Figure 2 This is a timing control flowchart of an embodiment of the present invention. Detailed Implementation

[0036] Exemplary embodiments of the invention will be described below with reference to the accompanying drawings. For clarity and brevity, not all features of the actual embodiments are described in the specification. However, it should be understood that many embodiment-specific decisions can be made in the development of any such actual embodiment to achieve the developer’s specific objectives, and these decisions may vary as the embodiments differ.

[0037] It should also be noted that, in order to avoid obscuring the invention with unnecessary details, only the device structure closely related to the solution according to the invention is shown in the accompanying drawings, while other details that are not closely related to the invention are omitted.

[0038] It should be understood that the present invention is not limited to the described embodiments by reference to the accompanying drawings. Throughout this document, embodiments may be combined with each other, features may be substituted or borrowed between different embodiments, and one or more features may be omitted in one embodiment, where feasible.

[0039] This invention is achieved using the following technical solution: a layered circuit architecture for a launch vehicle timing drive and acquisition module, the core of which lies in the carrier board-clasp board layered architecture, achieving high-density integration and vibration resistance through vertical stacking, including:

[0040] The carrier layer, which serves as both a power and protection layer, integrates:

[0041] Pyrotechnic drive branch: The pyrotechnic main circuit consists of a magnetic latching relay and a test channel switching relay connected in series, and a TVS diode array protection circuit connected in parallel across the main circuit.

[0042] The mechanical structure of the carrier layer is a multi-layer PCB board with a size of 3U (100mm×160mm). Power devices are soldered on the surface to prevent connector failure. The substrate is made of aluminum silicon carbide metal composite material.

[0043] Solenoid valve drive branch: The solenoid valve drive circuit is formed by the MOSFET of the switching device and the sampling resistor connected in series, and a freewheeling diode and an RC snubber circuit are connected in parallel across the solenoid valve coil.

[0044] The carrier layer is made of aluminum silicon carbide metal substrate and the surface is potted with thermally conductive silicone.

[0045] The cladding layer serves as the control and logic layer, housing a radiation-resistant FPGA and its peripheral circuits. The FPGA runs a real-time control algorithm with a logic resource utilization rate of ≤80% to reserve space for reconfiguration.

[0046] Connection Structure: The carrier board layer and the backing board layer are vertically interconnected via a board-to-board high-speed connector, reducing traditional cables by 90%. This allows the FPGA's control signals to drive the relays and MOSFETs on the carrier board layer and to retrieve test and sampling signals from the carrier board layer. Thermal management includes an array of copper heat sinks embedded in the PCB and localized aluminum heat sink covers.

[0047] According to one embodiment of the present invention, the magnetic latching relay in the pyrotechnic device drive branch is a dual-redundant design, including two parallel magnetic latching relay contacts, controlled by an FPGA through an independent channel. The integrated drive-test-protection system for the pyrotechnic device module includes: Drive unit: The magnetic latching relay coil is driven by the FPGA via optocoupler isolation. The contacts are connected in parallel and output to the pyrotechnic device. The dual-channel design ensures that disengagement can still be performed in case of a single-path fault. Test unit: The FPGA controls a constant current source to output test current, which is injected into the circuit through a precision resistor. The ADC collects the voltage and calculates the circuit impedance. If the circuit impedance deviates from the nominal value by ±10%, an open circuit or short circuit fault is determined. Protection unit: A TVS diode is connected across the positive and negative terminals, and a self-destructing fuse is connected in series in the circuit. It physically melts in case of overcurrent. The FPGA only enables the protection relay to engage after the test passes.

[0048] According to one embodiment of the present invention, the MOSFET in the solenoid valve drive branch is a low internal resistance device with an on-resistance Rds(on) < 2mΩ; and the solenoid valve drive branch adopts a triple redundancy design, including three MOSFETs, whose control terminals respectively receive three independent drive signals from the FPGA, and achieve a two-out-of-three fault-tolerant output through hardware or logic voting circuits. The drive-acquisition-freewheeling fusion of the solenoid valve module includes: Drive unit: The gates of the three MOSFETs are independently controlled by the FPGA, using a two-out-of-three voting logic. Acquisition unit: The sampling resistor is connected to an operational amplifier, and the FPGA determines the stall by the real-time current slope. Freewheeling unit: At the moment of turn-off, the back electromotive force of the solenoid valve coil is discharged through the freewheeling diode, and the RC circuit absorbs high-frequency oscillations and suppresses voltage spikes.

[0049] According to one embodiment of the present invention, in order to reduce spare parts costs and maintenance difficulty, the entire rocket timing module achieves device standardization and interface standardization; the hierarchical circuit architecture adopts a unified design, enabling hardware compatibility and software configurability between the pyrotechnic drive branch and the acquisition module and the solenoid valve drive branch and the acquisition module, specifically including:

[0050] Hardware compatibility: The carrier board layers of the pyrotechnic drive branch and the acquisition module, and the carrier board layers of the solenoid valve drive branch and the acquisition module, use the same physical interface, board-to-board connector model, and installation dimensions, allowing them to be interchanged and paired with a unified mounting plate layer. The carrier board layer uses a unified power device model, and the physical interface is compatible with both pyrotechnic and solenoid valve mounting plates. Changing functions only requires plugging and unplugging the mounting plate, with an operation time of less than 2 minutes.

[0051] Device standardization: The same type of FPGA and bus interface are installed on the PCB layer of the pyrotechnic drive branch and the solenoid valve module.

[0052] Functional Configurability: By programming different FPGA configuration files onto a unified PCB layer, it can be configured to function specifically for pyrotechnic drive branches and acquisition modules or for solenoid valve drive branches and acquisition modules. FPGA Firmware Supports Online Updates: Configuration files are received via the TTE bus, allowing for dynamic reconstruction of logic resources. For example, switching the pyrotechnic channel to solenoid valve drive mode responds to task change requirements.

[0053] According to one embodiment of the present invention, the FPGA is configured to perform the following dynamic fault isolation process:

[0054] Real-time diagnostic process: Before the pyrotechnic device is deactivated, the control test switching relay is used to inject a constant test current, monitor the circuit impedance in real time, and compare it with a preset threshold to diagnose open circuit or short circuit faults.

[0055] Safety unlocking procedure: For pyrotechnic devices, two consecutive encrypted pulse signals must be received and verified before a drive signal is generated to the magnetic latching relay. After the drive signal is output, the current rise rate is monitored in real time. If the deviation from the model exceeds 20%, a potential fault is identified, the current path is immediately cut off, and a backup drive path is activated. Specifically: Dual-pulse unlocking: The command requires two consecutive encrypted pulses, and the FPGA verifies the pulse code and CRC. Voltage slope monitoring: The rising edge of the current is acquired at the moment of unlocking. If the slope deviation is >20%, a poor contact is identified, and the backup channel is switched. Real-time current comparison: The actual current value is obtained via ADC. If the deviation between the actual current value and the expected value is >1%, a fault code is recorded and uploaded via the TTE bus.

[0056] Fault-tolerant control process: For solenoid valves, a three-redundant MOSFET drive signal is used for a two-out-of-three voting logic output, and the drive current is monitored in real time. When overcurrent or jamming characteristics are detected, a soft shutdown operation of the PWM duty cycle is executed. Specifically, the solenoid valve fault-tolerant control is as follows: Three-redundant voting: The FPGA compares the three MOSFET drive signals, and the output state uses a two-out-of-three voting method. Temperature compensation algorithm: The sampling resistor value is calibrated based on a pre-stored resistor-thermometer (RT meter). Overcurrent soft shutdown: During overcurrent, the PWM duty cycle linearly drops to 0 to avoid mechanical shock.

[0057] According to an embodiment of the present invention, the safety unlocking process for pyrotechnic items includes: power-on self-test stage: FPGA controls a constant current source to inject test current, and ADC monitors the circuit impedance; unlocking command verification: two encrypted pulses need to be received continuously and pass CRC verification; execution stage: after the magnetic latching relay is engaged, the actual current value is compared with the expected value in real time.

[0058] According to one embodiment of the present invention, the closed-loop control process of the solenoid valve includes PWM generation: the FPGA outputs a duty cycle adjustable signal; current feedback: a Hall sensor monitors the real-time current and triggers soft shutdown when there is overcurrent; and temperature compensation: the sampling resistor value is calibrated based on a lookup table method.

[0059] According to one embodiment of the present invention, the layered circuit architecture is used for on-rocket test integration, including: a low-voltage test circuit built into the carrier board, which constructs a loop self-test through a constant current source and a resistor box; and a timing acquisition circuit that directly samples back the "timing+" line voltage without the need for external ground equipment.

[0060] According to one embodiment of the present invention, the anti-interference design of the hierarchical circuit architecture includes: signal isolation using optocouplers and digital isolators; and ground isolation using a single-point connection between power ground and digital ground via a ferrite bead.

[0061] The following reference Figure 1-2 The technical solution of the present invention will be illustrated with specific embodiments.

[0062] like Figure 1 As shown, in the carrier-to-backboard layered architecture, the carrier layer (power / protection layer) pyrotechnics area features: magnetic latching relays with dual contacts connected in parallel to improve reliability; test channel switching relays for physical isolation; and a TVS diode array to handle recoil voltage. The solenoid valve area uses three redundant MOSFETs to replace mechanical relays; an RC snubber circuit with a freewheeling diode in parallel; and a sampling resistor in conjunction with a differential amplifier circuit. The backing board layer (FPGA control layer) contains the FPGA running real-time control algorithms, connected to the carrier board via a board-to-board high-speed connector.

[0063] like Figure 2 As shown, the timing control flow is as follows: Stage 1, Power-on self-test: The FPGA starts the boot program and initializes peripherals such as the ADC; Pyrotechnic circuit: Outputs test current and measures circuit impedance; Solenoid valve circuit: Outputs test current and checks the consistency of current in each path. Stage 2, Flight timing execution: T+0s (ignition): The FPGA sends an encrypted pulse to the solenoid valve drive plate to open the solenoid valve; T+120s (interstage separation): Verifies the pyrotechnic protection release command, engages the relay, monitors the current rise slope, and if the current is abnormal, switches to the backup relay. Stage 3, Fault handling: Solenoid valve jamming diagnosis: If the current ripple of a certain path exceeds the threshold, it is determined that the valve core is jammed, and the FPGA triggers three PWM pulses to attempt recovery; Data recording: All fault events (time, channel, type) are encrypted and stored in the memory, and then transmitted to the ground station in real time.

[0064] This design is applicable to the timing control system of launch vehicles. It solves the contradictions between flying wires, vibration resistance and heat dissipation through a layered architecture design, reduces interconnected flying wires by 90% and improves vibration resistance reliability by 10 times. It subverts the traditional discrete modules through three-in-one functional integration. It improves safety through dynamic fault isolation technology. It reduces cost and maintenance difficulty through cross-module unified design and shortens module replacement time to 2 minutes.

[0065] The above descriptions are merely various embodiments of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A hierarchical circuit architecture for a launch vehicle timing drive and acquisition module, characterized in that, include: The carrier layer, which serves as both a power and protection layer, integrates: Pyrotechnic drive branch: The pyrotechnic main circuit consists of a magnetic latching relay and a test channel switching relay connected in series, and a TVS diode array protection circuit connected in parallel across the two ends of the main circuit; Solenoid valve drive branch: The solenoid valve drive circuit is formed by the MOSFET of the switching device and the sampling resistor connected in series, and a freewheeling diode and an RC snubber circuit are connected in parallel across the solenoid valve coil. The carrier layer is made of aluminum silicon carbide metal substrate and the surface is potted with thermally conductive silicone. The buckle layer serves as a control and logic layer, housing a radiation-resistant FPGA and its peripheral circuitry. Connection structure: The carrier board layer and the snap-on board layer are vertically interconnected through a board-to-board high-speed connector, which enables the FPGA control signals to drive the relays and MOSFETs of the carrier board layer, and to collect the test and sampling signals of the carrier board layer.

2. The layered circuit architecture according to claim 1, characterized in that, The magnetic latching relay in the pyrotechnic drive branch is a dual-redundant design, including two parallel magnetic latching relay contacts, which are controlled by the FPGA through an independent channel.

3. The layered circuit architecture according to claim 1, characterized in that, The MOSFET in the solenoid valve drive branch is a low internal resistance device with an on-resistance Rds(on) < 2mΩ; and the solenoid valve drive branch adopts a triple redundancy design, including three MOSFETs, whose control terminals receive three independent drive signals from the FPGA, and achieve a two-out-of-three fault-tolerant output through hardware or logic voting circuits.

4. The layered circuit architecture according to claim 1, characterized in that, The hierarchical circuit architecture adopts a unified design, enabling hardware compatibility and software configurability between the pyrotechnic drive branch and the acquisition module, and between the solenoid valve drive branch and the acquisition module. Specifically, this includes: Hardware compatibility: The pyrotechnic drive branch and the carrier plate layer of the acquisition module, and the solenoid valve drive branch and the carrier plate layer of the acquisition module use the same physical interface, board-to-board connector model and installation size, so that the two can be interchanged and paired with the unified buckle layer. Device standardization: The same type of FPGA and bus interface are installed on the PCB layer of the pyrotechnic drive branch and the solenoid valve module. Functional configurability: By programming different FPGA configuration files to a unified board layer, it can be configured to function as a dedicated pyrotechnic drive branch and acquisition module or a dedicated solenoid valve drive branch and acquisition module.

5. The layered circuit architecture according to any one of claims 1-4, characterized in that, The FPGA is configured to perform the following dynamic fault isolation process: Real-time diagnostic process: Before the pyrotechnic device is deactivated, the control test switching relay is used to inject a constant test current, monitor the circuit impedance in real time, and compare it with a preset threshold to diagnose open circuit or short circuit faults. Safety unlocking process: For pyrotechnic products, two encrypted pulse signals must be continuously received and verified before a drive signal is generated to the magnetic latching relay. After the drive signal is output, the current rise rate is monitored in real time. If the deviation from the model exceeds 20%, it is judged as a potential fault and the current path is immediately cut off, while the backup drive path is activated. Fault-tolerant control process: For solenoid valves, the drive signals of three redundant MOSFETs are used to perform a three-out-of-two voting logic output, and the drive current is monitored in real time. When overcurrent or jamming characteristics are detected, a soft shutdown operation of PWM duty cycle is performed.

6. The layered circuit architecture according to any one of claims 1-4, characterized in that, The safety release procedure for pyrotechnic devices includes: Power-on self-test phase: FPGA controls constant current source to inject test current, ADC monitors loop impedance; Decryption command verification: Requires receiving two consecutive encrypted pulses and passing CRC check; Execution phase: After the magnetic latching relay is engaged, the actual current value is compared with the expected value in real time.

7. The layered circuit architecture according to any one of claims 1-4, characterized in that, The closed-loop control process of the solenoid valve includes: PWM generation: FPGA outputs a signal with an adjustable duty cycle; Current feedback: Hall sensor monitors real-time current and triggers soft shutdown when overcurrent occurs; Temperature compensation: The sampling resistance value is calibrated based on the lookup table method.

8. The layered circuit architecture according to any one of claims 1-4, characterized in that, The layered circuit architecture is used for on-rocket test integration, including: The carrier board has a built-in low-voltage test circuit, which uses a constant current source and a resistor box to form a self-test circuit. The timing acquisition circuit directly samples the "timing+" line voltage, eliminating the need for external ground equipment.

9. The layered circuit architecture according to any one of claims 1-4, characterized in that, The anti-interference design of the layered circuit architecture includes: Signal isolation employs optocouplers and digital isolators; Grounding isolation is achieved by connecting the power ground and digital ground at a single point using a ferrite bead.

Images