Equipment integrated control module and control method based on ETHERCAT

Abstract

The invention relates to an ETHERCAT-based equipment integrated control module and a control method, an EtherCAT communication circuit is connected with a CPU circuit through an SPI bus, an Ethernet communication circuit is connected with the CPU circuit through an SPI, and the CPU circuit is connected with an FPGA through an SPI bus and an FSMC bus; a constant current source circuit of the light source control unit is connected with an output pin of the FPGA, a multi-signal interface of the laser control unit is connected with a corresponding pin of the FPGA, and both the digital quantity input circuit and the digital quantity output circuit are connected with the FPGA. And the master station packages and sends instructions, analyzes and distributes the instructions, the FPGA generates control signals to drive each unit, and collects states and returns the states to the master station. High-speed cooperation is realized by utilizing ETHERCAT, multi-unit control is integrated, the precision and synchronism are improved, and precise synchronization of multiple links such as high-speed data transmission, low communication delay, light source control and laser control between a control module and a master station and between control units is realized.

Description

Technical Field

[0001] This invention relates to an ETHERCAT-based integrated control module and method for equipment, which is applied to the multi-unit collaborative control of various industrial laser processing and testing equipment to achieve high-speed and precise light source adjustment, laser emission control and status feedback, belonging to the field of laser equipment control technology. Background Technology

[0002] Laser equipment is widely used in industrial applications such as laser cutting, welding, marking, and inspection. Its control system needs to simultaneously perform multiple functions, including adjusting light source parameters, controlling laser trigger timing, acquiring position feedback, and interacting with digital signals. Traditional laser equipment control modules often employ discrete circuit designs, with functional units connected via ordinary industrial buses or analog signals, which has the following drawbacks:

[0003] 1) High communication latency means that the low latency advantage of ETHERCAT technology is not utilized, and the synchronization accuracy of laser triggering, motion control, and light source adjustment is poor, affecting the processing and inspection results;

[0004] 2) The hardware interface has a low degree of standardization. The interface types of different functional units (such as light source driver, laser control, and position feedback) are not uniform, resulting in complex wiring and high maintenance costs.

[0005] 3) The selection of core chips lacks specificity, and the control logic and hardware architecture have low matching degree, resulting in insufficient control accuracy and poor scalability, making it difficult to adapt to the control needs of multi-channel light sources and multiple types of lasers.

[0006] 4) The position feedback signal processing stage lacks a professional differential-to-single-ended design, resulting in weak signal anti-interference capability, easy position data errors, and impact on the positioning accuracy of the laser equipment.

[0007] ETHERCAT, as a high-performance industrial Ethernet technology, has advantages such as microsecond-level communication cycle and high synchronization, and has been widely used in the field of industrial control. However, existing laser control modules based on ETHERCAT have not optimized the hardware architecture for the core requirements of laser equipment (such as multi-channel constant current source drive, high-precision position feedback, and dedicated laser control signal interaction), nor have they clearly defined the core chip selection and interface definition, which cannot meet the high-precision and high-integration control requirements of industrial laser equipment.

[0008] Therefore, it is necessary to design an ETHERCAT-based device integration control module with a clear hardware architecture, well-defined chip selection, and standardized interfaces. Summary of the Invention

[0009] The purpose of this invention is to overcome the shortcomings of the existing technology and provide a device integrated control module and control method based on ETHERCAT.

[0010] The objective of this invention is achieved through the following technical solution:

[0011] The integrated control module based on ETHERCAT laser equipment has the following characteristics:

[0012] The EtherCAT communication circuit is connected to the CPU circuit via the SPI bus protocol.

[0013] The CPU circuit is connected to the FPGA via SPI and FSMC dual buses;

[0014] The Ethernet communication circuit is connected to the CPU circuit via the SPI bus;

[0015] The constant current source circuit of the light source control unit is connected to the output pin of the FPGA. The control signal output by the FPGA directly drives the constant current source circuit to adjust the light source parameters. The light source channel input interface of the light source control unit is connected to the constant current source circuit, and the constant current source circuit is connected to the light source channel output interface, forming a complete link for light source driving.

[0016] The laser synchronization signal interface, PEG control signal interface, and position feedback circuit of the laser control unit are all connected to the input pins of the FPGA to receive external laser synchronization signal interface, PEG control signal interface, and position feedback signal; the PEG mode laser control signal interface and PSO mode laser control signal interface are connected to the output pins of the FPGA to output laser emission control signals.

[0017] The digital input circuit and digital output circuit are connected to the pins of the FPGA.

[0018] Furthermore, in the aforementioned ETHERCAT-based device integrated control module, the EtherCAT communication circuit includes dual input and output network ports and an ETHERCAT slave controller chip. The input and output network ports are respectively connected to the communication pins of the ETHERCAT slave controller chip, which are connected to the communication pins of the CPU circuit for ETHERCAT protocol parsing and data transmission and reception.

[0019] Furthermore, in the aforementioned ETHERCAT-based device integrated control module, the CPU circuit is an STM32F407IGT6 CPU chip, whose communication pins are connected to the communication pins of the EtherCAT communication circuit and the Ethernet communication circuit, respectively. At the same time, it is connected to the communication pins of the FPGA through the SPI / FSMC dual bus, serving as the instruction scheduling core of the module.

[0020] Furthermore, in the aforementioned ETHERCAT-based device integrated control module, the Ethernet communication circuit includes a network port and a TCP Ethernet controller chip. The network port is connected to the communication pins of the TCP Ethernet controller chip, and the communication pins of the TCP Ethernet controller chip are connected to the communication pins of the CPU circuit for auxiliary communication of the TCP / IP protocol.

[0021] Furthermore, in the aforementioned ETHERCAT-based integrated control module, the FPGA is an EP4CE15 chip. The laser synchronization signal interface, PEG control signal interface, and position feedback circuit of the laser control unit are connected to the FPGA input pins, while the PEG mode laser control signal interface and PSO mode laser control signal interface are led out from the FPGA output pins. The constant current source circuit of the light source control unit is connected to the FPGA output pins. The digital input circuit is connected to the FPGA input pins, and the digital output circuit is driven by the FPGA output pins.

[0022] Furthermore, in the aforementioned ETHERCAT-based integrated control module, the position feedback circuit of the laser control unit includes differential signal interfaces for the grating ruler's digital quantities A+ / A-, B+ / B-, and Z+ / Z-, as well as a differential-to-unipolar circuit. The differential-to-unipolar circuit uses an AM26C32 chip to convert the differential signal of the grating ruler into a single-ended signal recognizable by the FPGA. The PEG control signal interface receives the position-triggered pulse signal.

[0023] Furthermore, the aforementioned ETHERCAT-based device integrated control module includes a light source control unit comprising six light source channel input interfaces, a constant current source circuit, and a light source channel output interface. The constant current source circuit is a TPS92515QDGQRQ1 LED driver chip, which enables high-precision constant current driving of the six-channel light source.

[0024] Furthermore, the aforementioned ETHERCAT-based device integrated control module includes a digital input circuit comprising four RJ45-180 Ethernet ports and three 74HC373 8-channel D-type latches. The signal pins of the Ethernet ports are connected to the input pins of the latches, and the output pins of the latches are connected to the input pins of the FPGA, for latching and acquiring multiple digital input signals.

[0025] Furthermore, the aforementioned ETHERCAT-based device integrated control module includes a digital output circuit comprising four RJ45-180 Ethernet ports and three 74HC373 8-channel D-type latches. The signal pins of the Ethernet ports are connected to the output pins of the latches, and the input pins of the latches are connected to the output pins of the FPGA, for latching and driving multiple digital output signals.

[0026] The present invention provides a device integration control method based on ETHERCAT, comprising the following steps:

[0027] The ETHERCAT master station sends control commands through the EtherCAT communication circuit. After being parsed by the EtherCAT communication circuit, the commands are transmitted to the CPU circuit via the SPI bus. The CPU circuit then transmits the commands to the FPGA via the SPI / FSMC dual bus. The FPGA performs the following operations according to the commands:

[0028] After receiving the instruction data parsed by the CPU circuit, the FPGA outputs a PWM control signal to the constant current source circuit of the light source control unit through its high-speed I / O interface. The constant current source circuit adjusts the duty cycle of the output PWM signal in real time according to the duty cycle data of the PWM signal, and performs subdivision processing on the voltage source connected to the input interface of the light source channel. At the same time, the constant current source circuit monitors the fluctuation of the light source voltage and current in real time, performs dynamic compensation for voltage and current deviations, and performs high-precision constant current control of the six-channel LED light source through the corresponding light source channel output interface to accurately adjust the output parameters of each channel LED light source.

[0029] The FPGA receives signals from the laser synchronization signal interface and the PEG control signal interface. The FPGA performs real-time fusion calculations on the acquired signals and the mode and parameter instructions issued by the CPU circuit. Finally, the PEG mode laser control signal interface outputs a laser control TTL signal to the laser, directly controlling the laser's start or stop core actions, thus achieving precise control in PEG mode.

[0030] The FPGA receives the TTL signal of the motion platform position feedback from the position feedback circuit. This signal is converted from the differential signal of the grating ruler into a single-ended signal and then analyzed for position to provide a position reference for laser control. At the same time, the FPGA collects the signal of the laser synchronization signal interface in real time to determine the laser output timing alignment. By collecting the real-time position and triggering the laser switch by position matching, the FPGA ensures the precise synchronization of the XY axis movement of the processing platform with the laser output. The FPGA outputs a signal to the laser control signal interface.

[0031] The FPGA acquires the output signal of the latch in the digital input circuit in real time to stably monitor the input signal of the external digital device; the FPGA transmits the acquired feedback signal to the CPU circuit, which processes it and then transmits it back to the ETHERCAT master station through the EtherCAT communication circuit to realize the uploading of the status of the external digital device.

[0032] According to the instructions issued by the CPU circuit, the FPGA drives the latch of the digital output circuit and outputs control signals to accurately set the corresponding output pin to a high level or a low level, interacts with external digital devices, and reliably controls the external digital devices.

[0033] Meanwhile, the FPGA feeds back the light source status, laser control status, position data, and digital signals to the CPU circuit, which then transmits them back to the master station via EtherCAT or Ethernet communication circuits, forming a closed-loop control.

[0034] Compared with the prior art, the present invention has significant advantages and beneficial effects, specifically reflected in the following aspects:

[0035] ①This invention utilizes ETHERCAT to achieve high-speed collaboration, integrates multi-unit control, improves accuracy and synchronization, has strong anti-interference and adaptability, ensures efficient and stable operation of equipment, and is suitable for industrial scenarios such as laser processing;

[0036] ②ETHERCAT protocol communication enables high-speed data transmission between the control module and the main station, as well as between various control units. The communication latency is low, ensuring precise synchronization of multiple aspects such as light source control and laser control, thereby improving the processing accuracy and experimental results of laser equipment.

[0037] ③ Precise control and status feedback: The FPGA and CPU circuits work together to achieve precise adjustment of light source parameters and accurate control of the laser triggering process; a sound status feedback mechanism monitors the status of the light source, laser unit and external digital signals in real time, so that the main station can grasp the system operation status in a timely manner, respond quickly to faults and anomalies, and improve the system reliability and stability.

[0038] ④ The integrated and simplified structure integrates multiple control functions into a single module, reducing discrete modules and complex wiring, lowering system size and cost, and facilitating installation, maintenance, and expansion; through standardized interfaces, it adapts to different types of light source control units and laser control units, enhancing versatility.

[0039] Other features and advantages of the invention will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing specific embodiments of the invention. The objects and other advantages of the invention may be realized and obtained by means of the structures particularly pointed out in the written description and the accompanying drawings. Attached Figure Description

[0040] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0041] Figure 1 : A schematic diagram of the architecture of this invention. Detailed Implementation

[0042] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0043] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, in the description of this invention, directional and ordinal terms are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0044] like Figure 1 As shown, the integrated control module for ETHERCAT laser equipment includes an EtherCAT communication circuit 100, a CPU circuit 101, an Ethernet circuit 102, an FPGA 103, a laser control unit 104, a light source control unit 110, a digital input circuit 114, and a digital output circuit 115.

[0045] EtherCAT communication circuit 100 is connected to CPU circuit 101 via SPI bus protocol for high-speed data interaction between ETHERCAT master station and module.

[0046] CPU circuit 101 is connected to FPGA 103 via SPI and FSMC dual buses. The SPI bus is used for instruction interaction, and the FSMC bus is used for high-speed data transmission to ensure the real-time performance of control instructions and feedback data.

[0047] Ethernet communication circuit 102 is connected to CPU circuit 101 via SPI bus, serving as a redundant / auxiliary communication channel for ETHERCAT communication and compatible with TCP / IP protocol;

[0048] The constant current source circuit 112 of the light source control unit 110 is connected to the output pin of the FPGA 103. The control signal output by the FPGA directly drives the constant current source circuit to adjust the light source parameters. The light source channel input interface 111 of the light source control unit 110 is connected to the constant current source circuit 112, and the constant current source circuit 112 is connected to the light source channel output interface 113, forming a complete link for light source driving. The brightness of the light source is modulated by controlling the constant current source circuit 112 with a PWM signal.

[0049] The laser synchronization signal interface 105, PEG control signal interface 106, and position feedback circuit 108 of the laser control unit 104 are all connected to the input pins of the FPGA 103 to acquire TTL position feedback signals; and receive external laser synchronization signal interfaces, PEG control signal interfaces, and position feedback signals; the PEG mode laser control signal interface 107 and PSO mode laser control signal interface 109 are connected to the output pins of the FPGA 103 to output laser emission control signals; the TTL signals output by the FPGA 103 control the laser to realize PEG / PSO mode laser control;

[0050] Digital input circuit 114 and digital output circuit 115 are connected to the pins of FPGA103 respectively, processing digital input signals and output signals for the acquisition and output control of external digital signals.

[0051] The EtherCAT communication circuit 100 includes dual input and output network ports (model: HY951180A) and an ETHERCAT slave controller chip (model: LAN9252). The input and output network ports are connected to the communication pins of the ETHERCAT slave controller chip, which are connected to the communication pins of the CPU circuit 101 for ETHERCAT protocol parsing and data transmission and reception.

[0052] CPU circuit 101 is an STM32F407IGT6 CPU chip. Its communication pins are connected to the communication pins of EtherCAT communication circuit 100 and Ethernet communication circuit 102, respectively. It is also connected to the communication pins of FPGA 103 through SPI / FSMC dual bus, serving as the instruction scheduling core of the module.

[0053] The Ethernet communication circuit 102 includes a network port (model: HY951180A) and a TCP Ethernet controller chip (model: W5500). The network port is connected to the communication pin of the TCP Ethernet controller chip, and the communication pin of the TCP Ethernet controller chip is connected to the communication pin of the CPU circuit 101 for auxiliary communication of the TCP / IP protocol.

[0054] FPGA103 is an EP4CE15 chip. The laser synchronization signal interface 105, PEG control signal interface 106, and position feedback circuit 108 of the laser control unit 104 are connected to the FPGA input pins. The PEG mode laser control signal interface 107 and PSO mode laser control signal interface 109 are led out from the FPGA output pins. The constant current source circuit 112 of the light source control unit 110 is connected to the FPGA output pins. The digital input circuit 114 is connected to the FPGA input pins, and the digital output circuit 115 is driven by the FPGA output pins.

[0055] The position feedback circuit 108 of the laser control unit 104 includes differential signal interfaces for the grating ruler's digital quantities A+ / A-, B+ / B-, and Z+ / Z-, as well as a differential-to-unipolar circuit. The differential-to-unipolar circuit uses an AM26C32 chip to convert the differential signals of the grating ruler into single-ended signals that can be recognized by the FPGA, thereby improving anti-interference capabilities. The PEG control signal interface 106 receives the position-triggered pulse signal, which comes from the ACS-UDMxa drive module (model: UDMxa2B00NYNNNN servo driver).

[0056] The light source control unit 110 includes six light source channel input interfaces 111, a constant current source circuit 112, and a light source channel output interface 113. The constant current source circuit 112 is a TPS92515QDGQRQ1 LED driver chip, which realizes high-precision constant current driving of six-channel light sources and adapts to the adjustment requirements of multi-channel laser light sources.

[0057] The digital input circuit 114 includes four RJ45-180 Ethernet ports and three 74HC373 8-channel D-type latches. The signal pins of the Ethernet ports are connected to the input pins of the latches, and the output pins of the latches are connected to the input pins of the FPGA103, for latching and acquiring multiple digital input signals.

[0058] The digital output circuit 115 includes four RJ45-180 network ports and three 74HC373 8-channel D-type latches. The signal pins of the network ports are connected to the output pins of the latches, and the input pins of the latches are connected to the output pins of the FPGA103, which are used for latching and driving multiple digital output signals.

[0059] The ETHERCAT-based device integration control method includes the following steps:

[0060] The ETHERCAT master station sends control commands through the EtherCAT communication circuit 100. After parsing, the EtherCAT communication circuit 100 transmits the commands to the CPU circuit 101 via the SPI bus. The CPU circuit 101 then transmits the commands to the FPGA 103 via the SPI / FSMC dual bus. The FPGA 103 performs the following operations according to the commands:

[0061] After receiving the instruction data parsed by the CPU circuit 101, the FPGA 103 outputs a PWM control signal to the constant current source circuit 112 of the light source control unit 110 through its high-speed I / O interface. The constant current source circuit 112 adjusts the duty cycle of the output PWM signal in real time according to the duty cycle data of the PWM signal, and performs subdivision processing on the voltage source connected to the light source channel input interface 111. At the same time, the constant current source circuit 112 monitors the fluctuation of the light source voltage and current in real time, performs dynamic compensation for voltage and current deviations, and precisely adjusts the output parameters of each channel LED light source through the high-precision constant current control of the six-channel LED light source through the corresponding light source channel output interface 113.

[0062] FPGA103 receives signals from laser synchronization signal interface 105 and PEG control signal interface 106 (output from UDMxa2B00NYNNNN servo driver). FPGA103 performs real-time fusion calculations on the acquired signals and the mode and parameter instructions issued by CPU circuit 101. Finally, PEG mode laser control signal interface 107 outputs laser control TTL signal (high / low level trigger signal) to the laser, directly controlling the laser's start or stop core actions, thus achieving precise control in PEG mode.

[0063] FPGA103 receives the TTL signal of motion platform position feedback from position feedback circuit 108. This signal is converted from grating ruler differential signal to single-ended signal and then analyzed for position to provide position reference for laser control. At the same time, FPGA103 acquires the signal of laser synchronization signal interface 105 in real time to determine the laser output timing alignment. By acquiring real-time position and position matching to trigger laser switch, it can achieve precise synchronization between XY axis movement of processing platform and laser output. FPGA103 outputs signal to laser control signal interface 109.

[0064] FPGA103 acquires the output signal of the latch in digital input circuit 114 in real time to stably monitor the input signal of external digital device; FPGA103 transmits the acquired feedback signal to CPU circuit 10, which is then processed by CPU circuit 101 and transmitted back to ETHERCAT master station through EtherCAT communication circuit 100 to realize the uploading of the status of external digital device.

[0065] According to the instructions issued by the CPU circuit 101, the FPGA103 drives the latch of the digital output circuit 115 and outputs control signals to accurately set the corresponding output pin to a high level or a low level, interact with external digital devices, and reliably control the external digital devices.

[0066] Meanwhile, the FPGA feeds back the light source status, laser control status, position data, and digital signals to the CPU circuit 101, which then transmits them back to the master station via the EtherCAT communication circuit 100 or the Ethernet communication circuit 102, forming a closed-loop control.

[0067] In the PEG mode laser control of the laser control unit 104, the host computer first sends the coordinates of the laser on and off points of the current laser cutting path to the ACS motion control card (as the master station) via TCP / IP protocol; the ACS master station converts the received coordinate commands into position control signals that the servo system can recognize and sends them to the ACS-UDMxa2B00NYNNNN servo driver. This driver, through a fully closed-loop control architecture formed with the grating ruler / encoder, drives the cutting platform to move along the preset path. During platform movement, the servo driver acquires feedback signals from the grating ruler in real time to obtain the platform's current position and compares it with the preset laser trigger position. When the cutting platform moves to the target trigger position, the servo driver's PEG pin immediately outputs a PEG laser control signal. The FPGA103 synchronously receives two key signals: a laser synchronization signal (from the laser, used for timing alignment) and the PEG control signal interface output by the servo driver. Simultaneously, the FPGA receives mode selection instructions (such as PEG mode enable) and parameter configurations (such as laser trigger delay and pulse width) from the CPU circuit and performs real-time fusion calculations on the received signals (calibrating the PEG trigger timing through the synchronization signal and optimizing trigger accuracy according to the parameter instructions). The FPGA outputs a laser control TTL signal (high / low level trigger) through the PEG mode laser control signal interface 107 to directly control the laser's start / stop, achieving precise synchronous control of the laser and platform movement in PEG mode.

[0068] In the PSO mode laser control of the laser control unit 104, the host computer first calculates and generates the coordinate data of the laser "on point" and "off point" based on the current laser cutting path, and sends it to the ACS motion control card (as an EtherCAT master station) via TCP / IP protocol. The ACS master station encapsulates the received coordinate data into EtherCAT PDO (process data object) and sends it to the EtherCAT communication circuit 100 in real time via the EtherCAT protocol. After receiving the PDO data, the EtherCAT communication circuit 100 temporarily stores it in its own PDRAM, and then transmits the data to the CPU circuit 101 via the SPI protocol. After receiving the PDO data, the CPU circuit 101 maps the data to the specified storage address space of the FPGA 103 via the FSMC protocol. After reading the address data, the FPGA first converts the "on point / off point coordinates" into pulse count according to the grating ruler resolution, which is used as the "target trigger position" for subsequent position matching. During the movement of the cutting platform, the grating ruler acquires the platform's real-time position and outputs a differential signal. This signal is converted to a single-ended TTL signal by an AM26C32 differential-to-single-ended chip and then transmitted to the position feedback circuit 108. The FPGA 103 acquires the position TTL signal in real-time through the position feedback circuit 108, analyzing the pulse count of the current position of the processing platform as the "real-time position reference." Simultaneously, its internal high-precision counting logic uses the laser synchronization signal interface 105 as the clock reference (or trigger edge), binding the position pulse count to the phase of the laser pulse. That is, for each laser synchronization pulse received, the position count is updated synchronously and the phase deviation is calibrated, ensuring a fixed correspondence between the "real-time position pulse count" and the timing of the laser pulses. Based on this, the FPGA continuously compares the "real-time position pulse count" with the "target trigger position pulse count." When the two are consistent (or reach a preset threshold), a PSO laser control signal is immediately generated and output through the PSO mode laser control interface 109, ultimately achieving precise synchronization between the processing platform movement and the laser switching light in both "position-phase" dimensions.

[0069] The light source channel input interface 111 of the light source control unit 110 is connected to a voltage source that matches the light source. The input power supply is processed by the filter and voltage regulation circuit to power the LED light source driver chip. After receiving the control command issued by the CPU circuit, the FPGA generates a high-precision PWM signal and outputs it to the constant current source circuit. The PWM signal duty cycle is adjusted in real time to achieve precise control of the light source operating current. At the same time, the operating status information of the light source is transmitted to the CPU circuit through the feedback link to form a closed-loop control to complete the real-time adjustment.

[0070] In the digital input circuit 113, digital status signals (high / low level signals) output by external digital devices (such as sensors, device operation status sensors, manual control buttons, etc.) are connected to the module internally through a standardized RJ45 network port (model: RJ45-180). The network port acts as a signal conversion interface, transmitting the electrical signals from external devices in a standardized physical layer, directly guiding them to the corresponding data input pins (D0-D7) of the 74HC373 latch in the digital input circuit. The output pins (Q0-Q7) of the 74HC373 latch are directly connected to the digital input pins of the FPGA. The latched stable signal is acquired by the FPGA in real time and temporarily stored in its internal data register. The FPGA uses a dual-bus architecture of SPI and FSMC to format and transmit the acquired multi-channel digital feedback signals to the CPU circuit 101. After receiving the signals, the CPU circuit classifies and packages the signals according to the process data object (PDO) mapping rules specified by the ETHERCAT protocol (such as distinguishing sensor fault signals, button trigger signals, etc.), generates standardized ETHERCAT data frames, and finally sends the data back to the host computer.

[0071] In the digital output circuit 114, the ETHERCAT master station generates digital control commands according to the device control requirements (such as triggering relays to engage, illuminating running status indicator lights, etc.) and follows the preset PDO mapping rules. These commands are then transmitted to the EtherCAT communication circuit 100 via the ETHERCAT bus. The EtherCAT communication circuit 100 parses the command data frame and transmits the command to the CPU circuit 101 via the SPI bus. The CPU circuit verifies and classifies the command, identifying the external device number to be controlled and the target status (high / low level). Subsequently, it sends the standardized control commands to the FPGA 103 via the SPI and FSMC dual buses. After receiving the control commands from the CPU circuit, the FPGA 103 converts the commands into digital signals (high / low level) for the corresponding channel and transmits them to the data input pins (D0-D7) of the 74HC373 latch. The output pins (Q0-Q7) of the 74HC373 latch are then connected to the RJ45-180 network port via an optocoupler isolation circuit (such as the TLP521 series). The network port transmits the latched, stable control signal to external digital devices: for relays, a high-level signal energizes the coil and engages, while a low-level signal releases it; for indicator lights, a high-level signal illuminates them, while a low-level signal extinguishes them. Through precise level control, the integrated control module reliably drives external devices, completing the closed-loop execution of master station commands.

[0072] In summary, this invention utilizes ETHERCAT to achieve high-speed collaboration, integrates multi-unit control, improves accuracy and synchronization, possesses strong anti-interference and adaptability, ensures efficient and stable operation of equipment, and is suitable for industrial scenarios such as laser processing.

[0073] The ETHERCAT protocol enables high-speed data transmission between the control module, the master station, and various control units. It features low communication latency, ensuring precise synchronization of multiple aspects such as light source control and laser control, thereby improving the processing accuracy and experimental results of laser equipment.

[0074] Precise control and status feedback: The FPGA and CPU circuits work together to achieve precise adjustment of light source parameters (such as power and brightness) and precise control of the laser triggering process (synchronization, frequency, power, etc.); A comprehensive status feedback mechanism monitors the status of the light source, laser unit and external digital signals in real time, so that the master station can grasp the system operation status in a timely manner, respond quickly to faults and anomalies, and improve the system reliability and stability.

[0075] The integrated and simplified structure combines multiple control functions into a single module, reducing discrete modules and complex wiring, lowering system size and cost, and facilitating installation, maintenance, and expansion. Through standardized interfaces, it adapts to different types of light source control units and laser control units, enhancing versatility.

[0076] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the invention should be included within the scope of protection of the invention. It should be noted that similar reference numerals and letters in the following figures denote similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0077] The above are merely specific embodiments of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention.

[0078] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

Claims

1. An integrated control module based on ETHERCAT laser equipment, characterized in that: The EtherCAT communication circuit (100) is connected to the CPU circuit (101) via the SPI bus protocol; The CPU circuit (101) is connected to the FPGA (103) via SPI and FSMC dual buses; The Ethernet communication circuit (102) is connected to the CPU circuit (101) via the SPI bus; The constant current source circuit (112) of the light source control unit (110) is connected to the output pin of the FPGA (103). The control signal output by the FPGA directly drives the constant current source circuit to adjust the light source parameters. The light source channel input interface (111) of the light source control unit (110) is connected to the constant current source circuit (112), and the constant current source circuit (112) is connected to the light source channel output interface (113), forming a complete link for light source driving. The laser synchronization signal interface (105), PEG control signal interface (106), and position feedback circuit (108) of the laser control unit (104) are all connected to the input pins of the FPGA (103) to receive external laser synchronization signal interface, PEG control signal interface and position feedback signal; the PEG mode laser control signal interface (107) and PSO mode laser control signal interface (109) are connected to the output pins of the FPGA (103) to output laser emission control signal; The digital input circuit (114) and the digital output circuit (115) are respectively connected to the pins of the FPGA (103).

2. The ETHERCAT-based device integration control module according to claim 1, characterized in that: The EtherCAT communication circuit (100) includes dual input and output network ports and an ETHERCAT slave controller chip. The input and output network ports are respectively connected to the communication pins of the ETHERCAT slave controller chip. The communication pins of the ETHERCAT slave controller chip are connected to the communication pins of the CPU circuit (101) for parsing the ETHERCAT protocol and sending and receiving data.

3. The ETHERCAT-based device integration control module according to claim 1, characterized in that: The CPU circuit (101) is an STM32F407IGT6 CPU chip. Its communication pins are connected to the communication pins of the EtherCAT communication circuit (100) and the Ethernet communication circuit (102), respectively. At the same time, it is connected to the communication pins of the FPGA (103) through the SPI / FSMC dual bus, serving as the instruction scheduling core of the module.

4. The ETHERCAT-based device integration control module according to claim 1, characterized in that: The Ethernet communication circuit (102) includes a network port and a TCP Ethernet controller chip. The network port is connected to the communication pin of the TCP Ethernet controller chip, and the communication pin of the TCP Ethernet controller chip is connected to the communication pin of the CPU circuit (101) for auxiliary communication of the TCP / IP protocol.

5. The ETHERCAT-based device integration control module according to claim 1, characterized in that: The FPGA (103) is an EP4CE15 chip. The laser synchronization signal interface (105), PEG control signal interface (106), and position feedback circuit (108) of the laser control unit (104) are connected to the FPGA input pins. The PEG mode laser control signal interface (107) and PSO mode laser control signal interface (109) are led out from the FPGA output pins. The constant current source circuit (112) of the light source control unit (110) is connected to the FPGA output pins. The digital input circuit (114) is connected to the FPGA input pins, and the digital output circuit (115) is driven by the FPGA output pins.

6. The ETHERCAT-based device integration control module according to claim 1, characterized in that: The position feedback circuit (108) of the laser control unit (104) includes differential signal interfaces for the digital quantities A+ / A-, B+ / B-, and Z+ / Z- of the grating ruler and a differential-to-unipolar circuit. The differential-to-unipolar circuit is an AM26C32 chip that converts the differential signal of the grating ruler into a single-ended signal that can be recognized by the FPGA. The PEG control signal interface (106) receives the position-triggered pulse signal.

7. The ETHERCAT-based device integration control module according to claim 1, characterized in that: The light source control unit (110) includes six light source channel input interfaces (111), a constant current source circuit (112), and a light source channel output interface (113). The constant current source circuit (112) is a TPS92515QDGQRQ1 LED driver chip, which realizes high-precision constant current driving of the six-channel light source.

8. The ETHERCAT-based device integration control module according to claim 1, characterized in that: The digital input circuit (114) includes four RJ45-180 network ports and three 74HC373 8-channel D-type latches. The signal pins of the network ports are connected to the input pins of the latches, and the output pins of the latches are connected to the input pins of the FPGA (103) for latching and acquiring multiple digital input signals.

9. The ETHERCAT-based device integration control module according to claim 1, characterized in that: The digital output circuit (115) includes four RJ45-180 network ports and three 74HC373 8-channel D-type latches. The signal pins of the network ports are connected to the output pins of the latches, and the input pins of the latches are connected to the output pins of the FPGA (103) for latching and driving multiple digital output signals.

10. A device integration control method based on ETHERCAT, characterized in that: Includes the following steps: The ETHERCAT master station sends control commands through the EtherCAT communication circuit (100). After parsing, the EtherCAT communication circuit (100) transmits the commands to the CPU circuit (101) via the SPI bus. The CPU circuit (101) transmits the commands to the FPGA (103) via the SPI / FSMC dual bus. The FPGA (103) performs the following operations according to the commands: After receiving the instruction data parsed by the CPU circuit (101), the FPGA (103) outputs a PWM control signal to the constant current source circuit (112) of the light source control unit (110) through its high-speed I / O interface. The constant current source circuit (112) adjusts the duty cycle of the output PWM signal in real time according to the duty cycle data of the PWM signal, and performs subdivision processing on the voltage source connected to the light source channel input interface (111). At the same time, the constant current source circuit (112) monitors the fluctuation of the light source voltage and current in real time, performs dynamic compensation for voltage and current deviations, and precisely adjusts the output parameters of each channel LED light source through the corresponding light source channel output interface (113) with high-precision constant current control. The FPGA (103) receives signals from the laser synchronization signal interface (105) and the PEG control signal interface (106). The FPGA (103) performs real-time fusion calculations on the collected signals and the mode and parameter instructions issued by the CPU circuit (101). Finally, the PEG mode laser control signal interface (107) outputs a laser control TTL signal to the laser, directly controlling the laser's start or stop core actions, thus achieving precise control in PEG mode. The FPGA (103) receives the motion platform position feedback TTL signal from the position feedback circuit (108). This signal is converted from the differential signal of the grating ruler into a single-ended signal and then analyzed for position, providing a position reference for laser control. At the same time, the FPGA (103) collects the signal from the laser synchronization signal interface (105) in real time, determines the laser output timing alignment, and triggers the laser switch by collecting the real-time position and position matching to achieve precise synchronization between the XY axis movement of the processing platform and the laser output. The FPGA (103) outputs a signal to the laser control signal interface (109). The FPGA (103) acquires the output signal of the latch in the digital input circuit (114) in real time and monitors the input signal of the external digital device stably. The FPGA (103) transmits the acquired feedback signal to the CPU circuit (101), and after processing by the CPU circuit (101), it is transmitted back to the ETHERCAT master station through the EtherCAT communication circuit (100) to realize the uploading of the status of the external digital device. According to the instructions issued by the CPU circuit (101), the FPGA (103) drives the latch of the digital output circuit (115) and outputs control signals to accurately set the corresponding output pin to a high level or a low level, interact with external digital devices, and reliably control external digital devices. Meanwhile, the FPGA feeds back the light source status, laser control status, position data, and digital signals to the CPU circuit (101), and the CPU circuit (101) transmits them back to the master station via the EtherCAT communication circuit (100) or the Ethernet communication circuit (102), forming a closed-loop control.

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