A low output voltage detection circuit based on low dropout linear regulator

Abstract

The application discloses a low-output-voltage detection circuit based on a low-dropout linear voltage regulator, relates to the technical field of power supply detection, and realizes accurate detection of an output voltage rising stage through cooperation of a first amplification delay circuit, a second amplification circuit and a first comparison circuit; reliable monitoring of an output voltage falling stage is completed through cooperation of a third amplification circuit, a fourth amplification delay circuit and a second comparison circuit. The amplification circuit can flexibly adjust an amplification multiple, is suitable for wide-range output voltage detection; the delay circuit can accurately control signal flip timing, and meets system control requirements; the comparison circuit and an AND gate circuit construct a rigorous logic control system, and guarantee the accuracy of signal output. Through the creative combination of the above-mentioned circuit modules, an efficient low-output-voltage detection scheme is formed, a technical problem that voltage establishment state cannot be reflected under a low-voltage scene is completely solved, and accurate detection of LDO low output voltage is realized.

Description

Technical Field

[0001] This application relates to the field of power supply detection technology, and in particular to a low output voltage detection circuit based on a low dropout linear regulator. Background Technology

[0002] With improvements in semiconductor manufacturing processes, semiconductor chips are becoming increasingly miniaturized. The size of transistors inside the chip is decreasing, but their voltage withstand capability is also decreasing, leading to more stringent requirements on the supply voltage. Low-dropout linear regulators (LDOs) suppress power supply noise through negative feedback mechanisms, exhibiting a high power supply rejection ratio (PSRR). They effectively filter out ripple and interference signals from the input power supply, making them suitable for noise-sensitive power supply scenarios.

[0003] The PG (Power Good) pin of an LDO power supply chip is used to characterize whether the output voltage has been established. The Power Good signal output needs to be transmitted to a system monitoring chip (such as an MCU chip) to monitor the power output status. Existing PG signal detection schemes have significant drawbacks: Scheme 1 amplifies the PG signal through a level conversion circuit, but when the LDO output voltage is lower than the transistor's emitter junction turn-on voltage (approximately 0.7V), the transistor cannot conduct properly, and the Power Good signal cannot follow voltage changes; Scheme 2 samples the output voltage through a voltage monitoring chip, but the internal reference voltage of commercially available monitoring chips is typically 0.5V. When the output voltage is lower than 0.5V, the chip fails and cannot reflect the actual voltage status. Summary of the Invention

[0004] This application provides a low output voltage detection circuit based on a low dropout linear regulator to at least solve the problem in related technologies where the Power Good signal cannot reflect whether the output voltage has been established in application scenarios where the output voltage is below 0.5V.

[0005] This application provides a low output voltage detection circuit based on a low dropout linear regulator, comprising: a first amplification delay circuit, a second amplification circuit, a third amplification circuit, a fourth amplification delay circuit, a voltage divider sampling circuit, a first comparator circuit, a second comparator circuit, and an AND gate circuit, wherein...

[0006] The input terminal of the first amplification delay circuit is connected to the output terminal of the low dropout linear regulator, and the output terminal of the first amplification delay circuit is connected to the first input terminal of the first comparator circuit.

[0007] The input terminal of the third amplifier circuit is connected to the output terminal of the low dropout linear regulator, and the output terminal of the third amplifier circuit is connected to the first input terminal of the second comparator circuit.

[0008] The input terminal of the voltage divider sampling circuit is connected to the output terminal of the low dropout linear regulator, and the output terminal of the voltage divider sampling circuit is connected to the input terminal of the second amplifier circuit and the input terminal of the fourth amplifier delay circuit, respectively.

[0009] The output terminal of the second amplifier circuit is connected to the second input terminal of the first comparator circuit.

[0010] The output of the fourth amplification and delay circuit is connected to the second input of the second comparator circuit;

[0011] The first input terminal of the AND gate is connected to the output terminal of the first comparator circuit, the second input terminal of the AND gate is connected to the output terminal of the second comparator circuit, and the output terminal of the AND gate is connected to the input terminal of the system monitoring chip.

[0012] This application achieves accurate detection of the output voltage rise phase through the synergy of a first amplification delay circuit, a second amplification circuit, and a first comparator circuit; and achieves reliable monitoring of the output voltage fall phase through the cooperation of a third amplification circuit, a fourth amplification delay circuit, and a second comparator circuit. The amplification circuits can flexibly adjust the amplification factor to adapt to a wide range of output voltage detection; the delay circuits can precisely control the PWRGD signal flipping timing to meet system control requirements; and the comparator circuits and AND gate circuits construct a rigorous logic control system to ensure the accuracy of the signal output. Through the creative combination of these circuit modules, a highly efficient low output voltage detection scheme is formed, completely solving the technical problem that the PWRGD signal cannot reflect the voltage build-up state in low-voltage scenarios, and achieving stable and accurate detection of low output voltage from LDOs. Attached Figure Description

[0013] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0014] Figure 1 This is a circuit diagram of the existing technical solution 1;

[0015] Figure 2 This is a circuit diagram of the existing technical solution two;

[0016] Figure 3 This is a schematic diagram of a first type of functional module provided in an embodiment of this application;

[0017] Figure 4 This is a circuit diagram provided for an embodiment of this application;

[0018] Figure 5 This is a schematic diagram of a second functional module provided in an embodiment of this application. Detailed Implementation

[0019] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0020] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0021] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0022] In the existing technical solution 1, the PG pin of the LDO chip is typically externally pulled up to the LDO's output voltage Vout. Since monitoring chips are generally powered by 3.3V, in some low-output voltage applications, the Power Good signal pulled up to Vout cannot be directly sent to the monitoring chip; the Power Good signal needs to be sent to the monitoring chip after a level conversion circuit. The schematic diagram of this solution is attached. Figure 1As shown, the specific working principle is as follows: When the EN signal is low, the LDO output voltage Vout is zero. The base of the NPN transistor Q1 is pulled low by resistor R1, and the emitter junction voltage of Q1 is zero, failing to meet the conduction condition and thus turning off. The base of the NPN transistor Q2 is pulled up to the power supply P3V3_STBY through resistor R2. The emitter junction of Q2 experiences a forward voltage and conducts. The collector of Q2 is connected to the PWRGD signal of the monitoring chip, which is pulled low by the conducting Q2. When the EN signal becomes high, and the output voltage Vout gradually increases to about 90% of the set value, the N-channel MOSFET switch Q3 inside the PG pin of the LDO chip turns off. The Power Good signal is pulled up to the output voltage Vout through resistor R1. Vout is greater than the emitter junction voltage of Q1, so the emitter junction of Q1 experiences a forward voltage and conducts. The base of Q2 is pulled down to ground by the conducting Q1, and Q2 turns off. The PWRGD signal is then pulled up to P3V3_STBY by resistor R3, becoming high. Therefore, when the LDO output voltage Vout is established, the output voltage establishment completion indicator signal PWRGD is pulled high. This signal is sent to the monitoring chip to monitor the LDO output voltage.

[0023] In the aforementioned prior art solution one, a level conversion circuit is used to amplify the PowerGood signal at the PG pin of the LDO chip to meet the sampling level requirements of the system monitoring chip. However, when the normal output voltage Vout of the LDO power supply is lower than the emitter junction turn-on voltage of transistor Q1 (typically, the PN junction voltage of a transistor is 0.7V), Q1 will be cut off because the voltage across the emitter junction is less than the PN junction turn-on voltage. The PWRGD signal will be low and will not change with the change in Vout, rendering this solution ineffective.

[0024] In the existing technical solution two, instead of using the signal output from the LDO's PG pin as a marker of output voltage establishment completion, a voltage monitoring chip is added to sample and process the output voltage. The processed output signal meets the input sampling voltage requirements of the system monitoring chip. The schematic diagram of this solution is attached. Figure 2As shown, the specific working principle is as follows: When the EN signal is low, the LDO output voltage Vout is zero, and the Vout_SENSE signal on the SENSE pin of the voltage monitoring chip U2 is zero. Since the Vout_SENSE voltage is less than the internal reference voltage Vref = 0.5V of U2, the internal pull-down switch Q1 on the OUT pin of U2 is in a conducting state, and the PWRGD signal output from the OUT pin of U2 is pulled down to a low level by Q1. When the EN signal becomes high, the output voltage Vout gradually increases. When the Vout_SENSE signal voltage is greater than the internal reference voltage Vref = 0.5V of U2, the internal switch Q1 of U2 is turned off, and the PWRGD signal is pulled up to the P3V3_VCC voltage by resistor R3. At this time, the PWRGD signal becomes high, indicating that the output voltage has been established. The PWRGD signal is sent to the monitoring chip to monitor the LDO output voltage.

[0025] In the aforementioned prior art solution two, a voltage monitoring chip is used to compare the sampled signal of the output voltage with the internal reference voltage Vref to monitor the LDO output voltage. Based on the above analysis, the lowest output voltage that the voltage monitoring chip can effectively monitor is Vout_min = Vref. Currently, the internal reference voltage Vref of commercially available voltage monitoring chips is 0.5V. This means that the minimum monitorable voltage using a voltage monitoring chip is 0.5V. When the LDO power supply output voltage Vout is lower than Vref = 0.5V, the PWRGD signal remains low and does not change with the change in Vout, causing the voltage monitoring chip to fail.

[0026] When the output voltage of the LDO power supply chip drops below approximately 0.7V, the transistor in the level conversion circuit of Existing Solution 1 cannot conduct properly, rendering Solution 1 ineffective. When the output voltage of the LDO power supply chip drops below approximately 0.5V, the voltage monitoring chip in Existing Solution 2 will also fail.

[0027] To address the aforementioned problems, this application provides a low output voltage detection circuit based on a low dropout linear regulator. For example... Figure 3As shown, the circuit includes: a first amplification delay circuit 1, a second amplification circuit 2, a third amplification circuit 3, a fourth amplification delay circuit 4, a voltage divider sampling circuit 5, a first comparator circuit 6, a second comparator circuit 7, and an AND gate circuit 8. The input terminal of the first amplification delay circuit 1 is connected to the output terminal of the low-dropout linear regulator, and the output terminal of the first amplification delay circuit 1 is connected to the first input terminal of the first comparator circuit 6. The input terminal of the third amplification circuit 3 is connected to the output terminal of the low-dropout linear regulator, and the output terminal of the third amplification circuit 3 is connected to the first input terminal of the second comparator circuit 7. The input terminal of the voltage divider sampling circuit 5 is connected to the output terminal of the low-dropout linear regulator, and the output terminal of the voltage divider sampling circuit 5 is connected to the input terminals of both the second amplification circuit 2 and the fourth amplification delay circuit 4. The output terminal of the second amplification circuit 2 is connected to the second input terminal of the first comparator circuit 6. The output terminal of the fourth amplification delay circuit 4 is connected to the second input terminal of the second comparator circuit 7. The first input terminal of AND gate 8 is connected to the output terminal of the first comparator circuit 6, the second input terminal of AND gate 8 is connected to the output terminal of the second comparator circuit 7, and the output terminal of AND gate 8 is connected to the input terminal of the system monitoring chip.

[0028] Specifically, the output voltage of the low-dropout linear regulator is Vout. The Vout signal is directly amplified and delayed by the first amplification and delay circuit 1, and then directly amplified by the third amplification circuit 3. The Vout signal also serves as the input to the sampling circuit. The output signal processed by the voltage divider sampling circuit 5 is connected to the input terminals of the second amplification circuit 2 and the fourth amplification and delay circuit 4. The amplified and delayed signal output by the first amplification and delay circuit 1 is sent to the first comparator circuit 6. The output signal of the second amplification circuit 2 is directly sent to the first comparator circuit 6. The output signal of the third amplification circuit 3 is directly sent to the second comparator circuit 7, and the amplified and delayed signal output by the fourth amplification and delay circuit 4 is sent to the second comparator circuit 7. The output signals of the first comparator circuit 6 and the second comparator circuit 7 are sent to the input terminals of the AND gate circuit 8. When both input signals of the AND gate circuit 8 are simultaneously high, the output Power Good signal is high. The Power Good signal is sent to the system monitoring chip to enable real-time monitoring of this signal by the system.

[0029] Based on the change of the LDO power chip's enable signal EN, the specific working principle is mainly explained in the following three stages:

[0030] (i) When the enable signal EN of the LDO power chip is low, the LDO output voltage Vout is zero. At this time, the operating states of each module are as follows: The first amplification and delay circuit 1 amplifies, delays, and pulls up the zero-voltage signal internally, then outputs the corresponding voltage to the non-inverting input of the first comparator circuit 6; the second amplification circuit 2, because its input signal is zero, outputs zero voltage to the inverting input of the first comparator circuit 6. Since the non-inverting input voltage of the first comparator circuit 6 is greater than the inverting input voltage, it outputs a high-level signal. The third amplification circuit 3, with zero input voltage, outputs zero voltage to the non-inverting input of the second comparator circuit 7; the fourth amplification and delay circuit 4 amplifies, delays, and pulls up the zero-voltage signal internally, then outputs the corresponding voltage to the inverting input of the second comparator circuit 7. Since the non-inverting input voltage of the second comparator circuit 7 is less than the inverting input voltage, it outputs a low-level signal. The AND gate circuit 8 receives two sets of input signals, one high-level and one low-level, and according to the AND gate logic characteristics, finally outputs a low-level PWRGD signal.

[0031] (II) When the enable signal EN of the LDO power chip switches to a high level, the LDO output voltage Vout gradually increases. The collaborative workflow of each module is as follows: The first amplification and delay circuit 1 internally amplifies and delays the increased Vout signal, and then outputs the voltage to the non-inverting input of the first comparator circuit 6; the voltage divider sampling circuit 5 synchronously samples Vout, and the second amplification circuit 2 outputs the corresponding voltage to the inverting input of the first comparator circuit 6 based on the sampled signal. The third amplification circuit 3 amplifies the Vout signal and then outputs the voltage to the non-inverting input of the second comparator circuit 7; the fourth amplification and delay circuit 4 internally amplifies and delays the output signal of the voltage divider sampling circuit 5 and then outputs the voltage to the inverting input of the second comparator circuit 7.

[0032] Because the non-inverting input voltage of the first comparator circuit 6 and the inverting input voltage of the second comparator circuit 7 are both delayed, there is a significant timing difference: the rise rate of the non-inverting input voltage of the first comparator circuit 6 is slower than that of the inverting input voltage, so it always outputs a low level during the rising phase of Vout; the rise rate of the non-inverting input voltage of the second comparator circuit 7 is faster than that of the inverting input voltage, so it always outputs a high level during the rising phase of Vout. At this time, the AND gate circuit 8 maintains a low-level output PWRGD signal because the input signals are one low and one high.

[0033] When the LDO output voltage Vout rises to the preset target value, the non-inverting input voltage of the first comparator circuit 6, after a set delay, is higher than the inverting input voltage, and its output signal flips to a high level. Since the second comparator circuit 7 still maintains a high-level output at this time, the AND gate circuit 8 receives two sets of high-level input signals, and the output PWRGD signal flips to a high level synchronously, indicating that the LDO output voltage has been stabilized.

[0034] (III) When the enable signal EN of the LDO power chip switches from high to low, the LDO output voltage Vout gradually decreases, and the circuit operating state changes as follows: the inverting input voltage of the first comparator circuit 6 and the non-inverting input voltage of the second comparator circuit 7 gradually decrease synchronously with Vout; due to the influence of the RC delay circuit, the non-inverting input voltage of the first comparator circuit 6 and the inverting input voltage of the second comparator circuit 7 decrease more slowly. The non-inverting input voltage of the first comparator circuit 6 decreases slower than the inverting input voltage, thus maintaining a high output level; the non-inverting input voltage of the second comparator circuit 7 decreases faster than the inverting input voltage, and when the non-inverting input voltage is lower than the inverting input voltage, its output signal flips to a low level. As the second comparator circuit 7 outputs a low level, the PWRGD signal output by the AND gate circuit 8 synchronously flips to a low level, promptly indicating that the LDO output voltage has failed.

[0035] This application provides a low output voltage detection circuit based on a low dropout linear regulator (LDO). Through the synergy of a first amplification delay circuit 1, a second amplification circuit 2, and a first comparator circuit 6, accurate detection of the output voltage rise phase is achieved. Through the cooperation of a third amplification circuit 3, a fourth amplification delay circuit 4, and a second comparator circuit 7, reliable monitoring of the output voltage fall phase is achieved. The amplification circuits can flexibly adjust their amplification factor to adapt to a wide range of output voltage detection (especially suitable for low-voltage scenarios below 0.5V). The delay circuits can precisely control the PWRGD signal switching timing to meet system control requirements. The comparator circuits and AND gate circuits construct a rigorous logic control system to ensure the accuracy of the signal output. Through the creative combination of these circuit modules, a highly efficient low output voltage detection scheme is formed, completely solving the technical problem that the PWRGD signal cannot reflect the voltage build-up state in low-voltage scenarios, and achieving stable and accurate detection of low output voltage from the LDO.

[0036] In one alternative implementation, such as Figure 4As shown, the voltage divider sampling circuit 5 includes a first resistor R1 and a second resistor R2. One end of the first resistor R1 is connected to the output terminal of the low dropout linear regulator, and the other end of the first resistor R1 is connected to one end of the second resistor R2, the input terminal of the second amplifier circuit 2, and the input terminal of the fourth amplification delay circuit 4. The other end of the second resistor R2 is grounded.

[0037] Specifically, the core function of this circuit is to perform voltage division sampling on the LDO output voltage Vout, especially suitable for low-voltage scenarios below 0.5V. The specific logic is as follows: When the LDO outputs Vout (regardless of whether it is a normal voltage or a low voltage below 0.5V), the current flows from the LDO output terminal through the first resistor R1 to the common connection terminal, and then through the second resistor R2 to the ground. The first resistor R1 and the second resistor R2 form a series voltage divider structure. According to the principle of series voltage divider, the voltage at the common connection terminal (i.e., the sampling voltage V_samp) is related to Vout as follows: V_samp = Vout × [R2 / (R1+R2)]. By properly selecting the resistance values ​​of the first resistor R1 and the second resistor R2, the amplitude of the sampling voltage can be precisely adjusted. For Vout below 0.5V, by optimizing the resistance ratio of the first resistor R1 and the second resistor R2, it can be ensured that the sampled V_samp is still within the effective recognition range of the subsequent second amplifier circuit 2 and the fourth amplifier delay circuit 4, thus avoiding the low voltage signal being unable to be processed by the subsequent modules due to its small amplitude.

[0038] In one alternative implementation, such as Figure 5 As shown, the first amplification and delay circuit 1 includes a first amplification circuit 11 and a first delay discharge circuit 12. The input terminal of the first amplification circuit 11 is connected to the output terminal of the low-dropout linear regulator, the output terminal of the first amplification circuit 11 is connected to the input terminal of the first delay discharge circuit 12, and the output terminal of the first delay discharge circuit 12 is connected to the first input terminal of the first comparator circuit 6.

[0039] Specifically, the first amplifier circuit 11 adopts a non-inverting proportional amplifier topology. By pre-setting a fixed amplification factor, it linearly amplifies the weak Vout signal (including low voltage signals below 0.5V) to a voltage amplitude suitable for the operating threshold of subsequent modules. During amplification, it maintains the signal's changing trend and timing synchronization, without introducing additional distortion, thus ensuring the original authenticity of the low voltage signal. The first delayed discharge circuit 12, on the one hand, adds a precise delay to the amplified low voltage signal to match the timing characteristics of the slow rise of the low voltage; on the other hand, it provides a fast discharge path to ensure that the signal is quickly reset during the Vout decline phase, effectively avoiding the risk of logic misjudgment.

[0040] In one alternative implementation, such as Figure 4As shown, the first amplifier circuit 11 includes: a first operational amplifier U1, a third resistor R3, and a fourth resistor R4. The non-inverting input of the first operational amplifier U1 is connected to the output of the low-dropout linear regulator; the inverting input of the first operational amplifier U1 is connected to one end of the third resistor R3 and one end of the fourth resistor R4; the output of the first operational amplifier U1 is connected to the other end of the third resistor R3 and the input of the first delayed discharge circuit 12; and the fourth resistor R4 is grounded.

[0041] Specifically, the first operational amplifier U1, together with the third resistor R3 and the fourth resistor R4, forms a non-inverting amplifier circuit. The amplification factor is determined by the resistance ratio of the third resistor R3 and the fourth resistor R4. For weak Vout signals below 0.5V, by appropriately setting the resistance values ​​of the third resistor R3 and the fourth resistor R4, the low-voltage signal can be linearly amplified to a range that the subsequent comparator circuit can recognize, thus preventing the low-voltage signal from being undetectable due to its small amplitude.

[0042] In one alternative implementation, such as Figure 4 As shown, the first delayed discharge circuit 12 includes: a fifth resistor R5, a sixth resistor R6, a first capacitor C1, and a first diode D1. One end of the fifth resistor R5 is connected to the output terminal of the first operational amplifier U1, the other end of the third resistor R3, and the cathode of the first diode D1. The other end of the fifth resistor R5 is connected to one end of the first capacitor C1, the anode of the first diode D1, one end of the sixth resistor R6, and the first input terminal of the first comparator circuit 6. The other end of the sixth resistor R6 is connected to the DC power supply P3V3_STBY, and the first capacitor C1 is grounded.

[0043] Specifically, the fifth resistor R5 and the first capacitor C1 form an RC delay network. The amplified signal output from the first operational amplifier U1 charges the first capacitor C1 through the fifth resistor R5, resulting in a delay in the signal output to the first comparator circuit 6. This design is adapted to the slow rise of the low voltage Vout, avoiding misjudgment by the comparator circuit due to Vout rising too slowly, and ensuring that a valid signal is only output to the comparator circuit after Vout has stably reached the target low voltage value.

[0044] The first diode D1 is a fast discharge channel. When the LDO output voltage Vout drops (especially from a low voltage value), the charge stored on the first capacitor C1 can be quickly discharged to the output of the first operational amplifier U1 through the first diode D1, which accelerates the drop speed of the common terminal signal and avoids the signal lag caused by the slow discharge of the RC network. This ensures that the circuit can be quickly reset when the EN signal changes from high to low, preventing logic errors in the PWRGD signal.

[0045] The sixth resistor R6 is connected to the P3V3_STBY power supply and acts as a pull-up resistor. When Vout is zero (EN is low), the sixth resistor R6 can pull the common terminal voltage to a stable level, ensuring the stability of the input signal of the first comparator circuit 6 and avoiding signal drift in zero-voltage scenarios.

[0046] In one alternative implementation, such as Figure 4 As shown, the second amplifier circuit 2 includes: a second operational amplifier U2, a seventh resistor R7, and an eighth resistor R8. The non-inverting input of the second operational amplifier U2 is connected to the other end of the first resistor R1 and one end of the second resistor R2. The inverting input of the second operational amplifier U2 is connected to one end of the seventh resistor R7 and one end of the eighth resistor R8. The output of the second operational amplifier U2 is connected to the other end of the seventh resistor R7 and the second input of the first comparator circuit 6. The other end of the eighth resistor R8 is grounded.

[0047] Specifically, the second operational amplifier U2, together with the seventh resistor R7 and the eighth resistor R8, forms a non-inverting proportional amplifier circuit. Since the input signal is a low-voltage sampling signal V_samp after voltage division, by reasonably setting the resistance ratio of the seventh resistor R7 and the eighth resistor R8, the weak V_samp can be linearly amplified to an amplitude that matches the output signal of the first amplification delay circuit 1, ensuring that the two can be effectively compared in the first comparison circuit 6.

[0048] Compared to conventional amplifier circuits, this design eliminates the need for additional bias circuitry, directly receiving low-voltage sampling signals via non-inverting input, thus avoiding the problem of low-voltage signals being overwhelmed by bias voltage. Simultaneously, operational amplifier U2 is selected with low input offset voltage and high common-mode rejection ratio, ensuring that excessive noise is not introduced when amplifying weak signals below 0.5V, guaranteeing the accuracy of the amplified signal.

[0049] In one alternative implementation, such as Figure 4 As shown, the third amplifier circuit 3 includes: a third operational amplifier U3, a ninth resistor R9, and a tenth resistor R10. The non-inverting input of the third operational amplifier U3 is connected to the output of the low-dropout linear regulator; the inverting input of the third operational amplifier U3 is connected to one end of the ninth resistor R9 and one end of the tenth resistor R10; the output of the third operational amplifier U3 is connected to the other end of the ninth resistor R9 and the first input of the second comparator circuit 7; and the other end of the tenth resistor R10 is grounded.

[0050] Specifically, the third operational amplifier U3, together with the ninth resistor R9 and the tenth resistor R10, forms a non-inverting amplifier circuit. For weak Vout signals below 0.5V, by appropriately matching the resistance values ​​of the ninth resistor R9 and the tenth resistor R10, the low-voltage signal can be linearly amplified to a range that the second comparator circuit 7 can accurately identify, preventing detection failure due to the low-voltage signal's insufficient amplitude. Since the non-inverting input of the third operational amplifier U3 is directly connected to the LDO output, without additional delay or sampling, its output signal can follow the changing trend of Vout in real time.

[0051] In one alternative implementation, such as Figure 5 As shown, the fourth amplification and delay circuit 4 includes a fourth amplification circuit 41 and a second delay circuit 42. The input terminal of the fourth amplification circuit 41 is connected to the output terminal of the voltage divider sampling circuit, the output terminal of the fourth amplification circuit 41 is connected to the input terminal of the second delay circuit 42, and the output terminal of the second delay circuit 42 is connected to the second input terminal of the second comparator circuit 7.

[0052] Specifically, the fourth amplifier circuit 41 adopts a non-inverting proportional amplifier topology to linearly amplify the weak low-voltage sampling signal after voltage division, solving the problem that the low-voltage signal amplitude is too small to be effectively identified by subsequent delay circuits and comparator circuits. The second delay circuit 42 adds a precise delay to the amplified low-voltage sampling signal, constructing a timing reference for detecting the falling phase, and forming a timing difference with the real-time amplified signal output by the third amplifier circuit 3, ensuring that the second comparator circuit 7 can accurately capture the true falling state of Vout.

[0053] In one alternative implementation, such as Figure 4 As shown, the fourth amplifier circuit 41 includes: a fourth operational amplifier U4, an eleventh resistor R11, and a twelfth resistor R12. The non-inverting input of the fourth operational amplifier U4 is connected to the other end of the first resistor R1 and one end of the second resistor R2. The inverting input of the fourth operational amplifier U4 is connected to one end of the eleventh resistor R11 and one end of the twelfth resistor R12. The output of the fourth operational amplifier U4 is connected to the other end of the eleventh resistor R11 and the input of the second delay circuit 42. The twelfth resistor R12 is grounded.

[0054] Specifically, the fourth operational amplifier U4, together with the eleventh resistor R11 and the twelfth resistor R12, forms a non-inverting amplifier circuit. For the weak low-voltage sampling signal after voltage division, by appropriately setting the resistance ratio of the eleventh resistor R11 and the twelfth resistor R12, it can be linearly amplified to an amplitude that matches the output signal of the third amplifier circuit 3. This ensures effective comparison between the two in the second comparator circuit 7, preventing comparison failure due to the low-voltage signal's insufficient amplitude.

[0055] In one alternative implementation, such as Figure 4 As shown, the second delay circuit 42 includes: a thirteenth resistor R13, a fourteenth resistor R14, and a second capacitor C2. One end of the thirteenth resistor R13 is connected to the output terminal of the fourth operational amplifier U4 and the other end of the eleventh resistor R11. The other end of the thirteenth resistor R13 is connected to one end of the fourteenth resistor R14, one end of the second capacitor C2, and the second input terminal of the second comparator circuit. The other end of the fourteenth resistor R14 is connected to the DC power supply P3V3_STBY. The second capacitor C2 is grounded.

[0056] Specifically, the thirteenth resistor R13 and the second capacitor C2 form an RC delay network. The amplified signal output from the fourth operational amplifier U4 charges / discharges the second capacitor C2 via the thirteenth resistor R13, causing a delay in the signal output to the second comparator circuit 7. This design is adapted to the characteristic of a slow decrease in low voltage Vout. When Vout decreases from the target voltage value, the delayed signal and the real-time amplified signal output from the third amplifier circuit 3 form a timing difference, ensuring that the second comparator circuit 7 can accurately capture the true decreasing state of Vout and avoid misjudgments caused by voltage fluctuations.

[0057] The fourteenth resistor, R14, is connected to the DC power supply P3V3_STBY and acts as a pull-up resistor. When Vout is zero or at an extremely low voltage, the fourteenth resistor, R14, can pull the common terminal voltage to a stable level, preventing signal drift and ensuring the stability of the input signal of the second comparator circuit 7, thus guaranteeing the reliability of the detection logic in low-voltage scenarios.

[0058] In one alternative implementation, such as Figure 4 As shown, the first comparison circuit 6 is composed of comparator U5, the second comparison circuit 7 is composed of comparator U6, and the AND gate circuit 8 is composed of AND gate U7.

[0059] In one exemplary embodiment, the specific working principle, based on the change of the LDO power chip enable signal EN, is mainly described in detail in the following three stages:

[0060] (a) When the enable signal EN of the LDO power supply chip is low, the output voltage Vout of the LDO power supply is zero. At this time, the output voltages of the four operational amplifiers are all zero. Since the output voltage of U1 is zero, resistors R5 and R6 form a voltage divider circuit. The voltage after voltage division is also the positive input voltage of comparator U5, Vr_comp1 = 3.3 * (R5 / (R5 + R6)). The voltage Vr_comp1 is less than the forward voltage of diode D1, so D1 is cut off. Since the output voltage of U2 is zero, the inverting input voltage of comparator U5, Vr_comp2 = 0; the positive input voltage of U5 is greater than the inverting input voltage, so U5 outputs a high-level signal. Since the output voltage of U3 is zero, the positive input voltage of comparator U6, Vf_comp1 = 0. Since the output voltage of U4 is zero, resistors R13 and R14 form a voltage divider circuit. The voltage after voltage division is also the voltage at the inverting input of comparator U6, Vf_comp2 = 3.3 * (R13 / (R13 + R14)). The positive input voltage of U6 is less than the inverting input voltage, so U6 outputs a low-level signal. At this time, the two input signals to the AND gate chip U7 are one high level and one low level. The PWRGD signal output by U7 is a low-level signal, which satisfies the logic level when EN is low.

[0061] In the above analysis, resistors R6 and R14 are pulled up to the P3V3_STBY power supply. This is to ensure a significant difference between the two input signals of comparators U5 and U6 when Vout is zero, guaranteeing that U5 and U6 output different high and low level signals, thus making the PWRGD signal output by the AND gate chip U7 low. The values ​​of resistors R6 and R14 should be much larger than the values ​​of the resistors in the proportional amplifier circuit and the delay circuit.

[0062] (II) When the enable signal EN of the LDO power chip is high, the output voltage Vout of the LDO gradually increases. Vout is amplified by the non-inverting amplifier circuit composed of U1, R3, and R4. The relationship between the output voltage Vopa1 of U1 and Vout is: Vopa1 = Vout * (1 + R3 / R4). Resistor R5 and capacitor C1 form an RC delay network to delay the Vopa1 signal. The signal after processing by the RC delay network is Vr_comp1. Since the value of resistor R5 is much smaller than the value of resistor R6, the signals Vr_comp1 and Vopa1 satisfy: Vr_comp1 ≈ Vopa1. Resistor R1 and R2 form a voltage divider sampling circuit to sample Vout. Since we assume that the PWRGD signal becomes high when the LDO output voltage reaches 90% of the target value, R1 and R2 must satisfy: R2 = 9 * R1, and the voltage across resistor R2 Vout_samp = 0.9 * Vout. The output voltage Vopa2 of operational amplifier U2 is equal to Vout_samp*(1+R7 / R8), which is also equal to the inverting input voltage Vr_comp2 of comparator U5. The output voltage Vopa3 of operational amplifier U3 is equal to Vout*(1+R9 / R10), which is also equal to the non-inverting input voltage Vf_comp1 of comparator U6. The output voltage Vopa4 of operational amplifier U4 is equal to Vout_samp*(1+R11 / R12). The Vopa4 signal is delayed by an RC delay network composed of resistor R13 and capacitor C2, outputting the signal Vf_comp2, which is then sent to the inverting input of U6. Since the value of resistor R13 is much smaller than the value of resistor R14, the signals Vf_comp2 and Vopa4 satisfy: Vf_comp2≈Vopa4. Signals Vr_comp1 and Vf_comp2 are obtained after an RC delay circuit, so the rise time of Vr_comp1 is slower than that of Vr_comp2. During the rise phase of Vout, comparator U5 will continuously output a low level. The rise time of Vf_comp1 is faster than that of Vf_comp2. During the rise phase of Vout, comparator U6 will continuously output a high level, and AND gate chip U7 will maintain a low-level output signal. When the LDO output voltage rises to the target value Vout_ob, the Vr_comp1 signal will only exceed Vr_comp2 after an RC delay time Td, after which comparator U5 will output a high level. At the same time, because U6 continuously outputs a high level during the rise phase of Vout, both input signals of U7 are at a high level, and the output signal PWRGD of U7 flips to a high level, indicating that the LDO output voltage has been established.

[0063] In the above analysis, the amplification factor of the non-inverting amplifier circuit is the same, and the magnitude of the amplification factor can be reasonably adjusted according to the target value of the output voltage. After the LDO output voltage is established, all signals analyzed above will remain unchanged; unless the EN signal goes low or other reasons cause the output voltage to go low, the PWRGD signal will follow the decrease in output voltage and go low, otherwise it will remain high.

[0064] (III) When the enable signal EN of the LDO power chip changes from high to low, the LDO output voltage Vout gradually decreases, and the comparator input signals Vr_comp2 and Vf_comp1 will also gradually decrease along with Vout. Similarly, due to the presence of the RC delay circuit, signals Vr_comp1 and Vf_comp2 will decrease slowly. The Vr_comp1 signal decreases more slowly than the Vr_comp2 signal, so comparator U5 outputs a high level. The Vf_comp1 signal decreases more quickly than the Vf_comp2 signal, and when the Vf_comp1 voltage drops below the Vf_comp2 voltage, comparator U6 outputs a low level. Since the Vf_comp1 signal decreases much faster than the Vf_comp2 signal, the output voltage corresponding to the U6 output turning low is approximately 0.9*Vout_ob. When the U6 output signal turns low, the output signal PWRGD of the AND gate chip U7 will synchronously turn low.

[0065] To ensure the correctness of the PWRGD signal following logic when the EN signal returns to a high level shortly after changing from high to low, a diode D1 needs to be connected in parallel with resistor R5. The function of diode D1 is to conduct based on the voltage difference between Vr_comp1 and Vopa1 during the Vout decrease process, bypassing resistor R5 and causing the Vr_comp1 signal to decrease rapidly following the Vopa1 signal. When the EN signal returns to a high level again shortly, this ensures that the output signal of U5 has already gone low before the output signal of U6 goes high, thus guaranteeing the correctness of the PWRGD signal level logic and the feasibility of this scheme. To accelerate the Vr_comp1 descent speed, diode D1 needs to be selected as a device with a low on-state voltage drop.

[0066] Existing solutions focus on detecting low output voltages of a single LDO. However, in practical precision electronic systems, multiple LDOs are often connected in parallel to improve power supply stability. To address the issues of signal conflict and timing asynchrony when multiple LDOs are detected independently, this application employs an analog switching chip (such as CD4051). The input terminal corresponds to the output voltages Vout1, Vout2…Voutn of multiple LDOs, and the output terminal is connected to the sampling terminal of an existing detection circuit. This enables a single detection circuit to perform time-division sampling of multiple Vout values, or to connect multiple independent detection circuits in parallel.

[0067] Taking two LDOs connected in parallel as an example, the EN signals of both LDOs are enabled simultaneously. Vout1 and Vout2 are connected to the detection circuit in a time-division multiplexing manner via analog switches (or through two sets of detection circuits in parallel), each completing low-voltage detection. The synchronization logic unit receives the PWRGD1 and PWRGD2 signals, eliminates the timing difference between the two signals through an RC delay network, and outputs a high level to the system monitoring chip when both signals are high. If the Vout of one LDO drops, its corresponding PWRGD1 goes low, and the synchronization logic unit immediately pulls PWRGD_SYNC low, while simultaneously feeding back the fault channel address to the system through the address encoding interface for quick troubleshooting.

[0068] The low output voltage detection circuit based on a low dropout linear regulator provided in this application has been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only for the purpose of helping to understand the method and core ideas of this application. It should be noted that those skilled in the art can make several improvements and modifications to this application without departing from the principles of this application, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A low output voltage detection circuit based on a low dropout linear regulator, characterized in that, include: The circuit comprises a first amplification delay circuit, a second amplification circuit, a third amplification circuit, a fourth amplification delay circuit, a voltage divider sampling circuit, a first comparator circuit, a second comparator circuit, and an AND gate circuit, wherein... The input terminal of the first amplification delay circuit is connected to the output terminal of the low dropout linear regulator, and the output terminal of the first amplification delay circuit is connected to the first input terminal of the first comparator circuit. The input terminal of the third amplifier circuit is connected to the output terminal of the low dropout linear regulator, and the output terminal of the third amplifier circuit is connected to the first input terminal of the second comparator circuit. The input terminal of the voltage divider sampling circuit is connected to the output terminal of the low dropout linear regulator, and the output terminal of the voltage divider sampling circuit is connected to the input terminal of the second amplifier circuit and the input terminal of the fourth amplifier delay circuit, respectively. The output terminal of the second amplifier circuit is connected to the second input terminal of the first comparator circuit; The output terminal of the fourth amplification delay circuit is connected to the second input terminal of the second comparator circuit. The first input terminal of the AND gate circuit is connected to the output terminal of the first comparator circuit, the second input terminal of the AND gate circuit is connected to the output terminal of the second comparator circuit, and the output terminal of the AND gate circuit is connected to the input terminal of the system monitoring chip.

2. The low output voltage detection circuit based on a low dropout linear regulator according to claim 1, characterized in that, The voltage divider sampling circuit includes: a first resistor and a second resistor, wherein, One end of the first resistor is connected to the output terminal of the low dropout linear regulator, and the other end of the first resistor is connected to one end of the second resistor, the input terminal of the second amplifier circuit, and the input terminal of the fourth amplification delay circuit, respectively. The other end of the second resistor is grounded.

3. The low output voltage detection circuit based on a low dropout linear regulator according to claim 1, characterized in that, The first amplification and delay circuit includes: a first amplification circuit and a first delay discharge circuit, wherein, The input terminal of the first amplifier circuit is connected to the output terminal of the low dropout linear regulator, the output terminal of the first amplifier circuit is connected to the input terminal of the first delayed discharge circuit, and the output terminal of the first delayed discharge circuit is connected to the first input terminal of the first comparator circuit.

4. The low output voltage detection circuit based on a low dropout linear regulator according to claim 3, characterized in that, The first amplifier circuit includes: a first operational amplifier, a third resistor, and a fourth resistor, wherein, The non-inverting input of the first operational amplifier is connected to the output of the low-dropout linear regulator. The inverting input of the first operational amplifier is connected to one end of the third resistor and one end of the fourth resistor. The output of the first operational amplifier is connected to the other end of the third resistor and the input of the first time-delay discharge circuit. The fourth resistor is grounded.

5. The low output voltage detection circuit based on a low dropout linear regulator according to claim 4, characterized in that, The first delayed discharge circuit includes: a fifth resistor, a sixth resistor, a first capacitor, and a first diode, wherein, One end of the fifth resistor is connected to the output terminal of the first operational amplifier, the other end of the third resistor, and the cathode of the first diode. The other end of the fifth resistor is connected to one end of the first capacitor, the anode of the first diode, one end of the sixth resistor, and the first input terminal of the first comparator circuit. The other end of the sixth resistor is connected to a DC power supply, and the first capacitor is grounded.

6. The low output voltage detection circuit based on a low dropout linear regulator according to claim 2, characterized in that, The second amplifier circuit includes: a second operational amplifier, a seventh resistor, and an eighth resistor, wherein, The non-inverting input of the second operational amplifier is connected to the other end of the first resistor and one end of the second resistor, respectively. The inverting input of the second operational amplifier is connected to one end of the seventh resistor and one end of the eighth resistor, respectively. The output of the second operational amplifier is connected to the other end of the seventh resistor and the second input of the first comparator circuit, respectively. The other end of the eighth resistor is grounded.

7. The low output voltage detection circuit based on a low dropout linear regulator according to claim 1, characterized in that, The third amplifier circuit includes: a third operational amplifier, a ninth resistor, and a tenth resistor, wherein, The non-inverting input of the third operational amplifier is connected to the output of the low-dropout linear regulator. The inverting input of the third operational amplifier is connected to one end of the ninth resistor and one end of the tenth resistor. The output of the third operational amplifier is connected to the other end of the ninth resistor and the first input of the second comparator circuit. The other end of the tenth resistor is grounded.

8. The low output voltage detection circuit based on a low dropout linear regulator according to claim 2, characterized in that, The fourth amplification and delay circuit includes: a fourth amplification circuit and a second delay circuit, wherein... The input terminal of the fourth amplifier circuit is connected to the output terminal of the voltage divider sampling circuit, the output terminal of the fourth amplifier circuit is connected to the input terminal of the second delay circuit, and the output terminal of the second delay circuit is connected to the second input terminal of the second comparator circuit.

9. The low output voltage detection circuit based on a low dropout linear regulator according to claim 8, characterized in that, The fourth amplifier circuit includes: a fourth operational amplifier, an eleventh resistor, and a twelfth resistor, wherein, The non-inverting input terminal of the fourth operational amplifier is connected to the other end of the first resistor and one end of the second resistor, respectively. The inverting input terminal of the fourth operational amplifier is connected to one end of the eleventh resistor and one end of the twelfth resistor, respectively. The output terminal of the fourth operational amplifier is connected to the other end of the eleventh resistor and the input terminal of the second delay circuit, respectively. The twelfth resistor is grounded.

10. The low output voltage detection circuit based on a low dropout linear regulator according to claim 9, characterized in that, The second delay circuit includes: a thirteenth resistor, a fourteenth resistor, and a second capacitor, wherein, One end of the thirteenth resistor is connected to the output terminal of the fourth operational amplifier and the other end of the eleventh resistor. The other end of the thirteenth resistor is connected to one end of the fourteenth resistor, one end of the second capacitor, and the second input terminal of the second comparator circuit. The other end of the fourteenth resistor is connected to a DC power supply. The second capacitor is grounded.

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