LDO circuit based on level conversion and pre-adjustment module

Abstract

The application discloses a kind of LDO circuit based on level conversion and pre-adjustment module.The LDO circuit includes reference source, error amplifier, pre-adjustment module, level conversion module, power switch tube P1, power circuit tube N1 and resistance feedback network R1 and R2.Pre-adjustment module carries out step-down processing to input high-voltage power supply, level conversion module generates bias voltage according to enable signal and high-voltage power supply, controls power switch and switch inside operational amplifier, ensures that circuit is high-voltage and drain electrode is low.Error amplifier adjusts the gate voltage of power circuit according to the difference of feedback and reference voltage, controls current stable output voltage.Resistance feedback network realizes closed-loop regulation of output voltage.In the case where LDO is enabled to be closed, whether it is at 3V or 5V operating voltage, it can ensure that power tube is completely closed, so as to greatly improve the leakage of LDO itself, and has low leakage characteristics.

Description

Technical Field

[0001] This application relates to the field of analog circuit chip design technology, and in particular to an LDO circuit based on a level conversion and pre-adjustment module. Background Technology

[0002] Currently, LDO (Linear Regulator) technology has evolved from a single traditional structure to a diversified approach tailored to different application scenarios. Its development has consistently revolved around the core objectives of "lower quiescent power consumption, higher frequency stability, smaller area, and larger load current." A typical LDO circuit mainly consists of an "error amplifier, power circuit, feedback resistor network, and reference source," where the power circuit can use either P-MOSFET or N-MOSFET power transistors. P-MOSFET power transistors offer lower drop-out voltage but have lower power supply rejection ratio (PSRR), while N-MOSFET power transistors offer higher response speed and PSRR, but have a larger drop-out voltage.

[0003] LDO circuits implemented with PMOS power transistors are more suitable for low-voltage input power supply scenarios, where the circuit can be easily turned off with minimal leakage current. LDOs implemented with NMOS power transistors are more suitable for high-voltage input power supply scenarios, where complete shutdown is difficult, especially in circuits designed for high voltage but using low-voltage processes. The leakage current during shutdown can be significant; some chips cannot be turned off at all and therefore lack a shutdown mode. Even chips with a shutdown mode still exhibit substantial leakage current (tens or hundreds of µA).

[0004] In the current technology, on the 3.3V process platform, there are very few chip designs with a 5V withstand voltage. Usually, the 5V process is directly selected. This design is simpler, but the process compatibility is worse, the logic can support a lower speed, the design cycle of the series products is longer, and the cost will also increase.

[0005] There are also technologies that design only 3.3V chips on a 3.3V process platform, reducing the chip's operating voltage range. While this avoids the high voltage resistance problem, it narrows the chip's application scenarios and makes it unusable for high-voltage power supply applications.

[0006] A very small number of chips also use 3.3V process to achieve 5V withstand voltage design, but the chips either cannot be turned off during shutdown, or the leakage current during shutdown reaches more than 10uA, which is very unfriendly to low power consumption application scenarios. Summary of the Invention

[0007] Based on this, this application provides an LDO circuit based on a level conversion and pre-adjustment module. This not only solves the process compatibility problem, achieving a 5V withstand voltage design using a 3.3V process, but also allows for circuit reuse, significantly reducing the design cycle, design costs, and risks. Furthermore, this application is designed to meet the requirements of a wide power supply voltage range of 2.8V to 5V, and can turn off the LDO during shutdown, with the LDO's shutdown leakage current in the nA range.

[0008] In a first aspect, an LDO circuit based on a level shifting and pre-adjustment module is provided, the LDO circuit comprising:

[0009] A reference source is used to provide a stable reference voltage VREF as a reference signal for output voltage regulation;

[0010] An error amplifier receives a reference voltage VREF and a feedback voltage VFB from a feedback network at its input, and its output is connected to the gate of a power circuit N1. It is used to adjust the gate voltage of the power circuit N1 according to the difference between the feedback voltage VFB and the reference voltage VREF, thereby controlling the current flowing through the power circuit.

[0011] The pre-adjustment module receives a high-voltage power supply VDDH at its input, performs a step-down pre-adjustment on the high-voltage power supply VDDH, and outputs a fixed level VN and a stepped-down voltage VDDL.

[0012] The level conversion module receives a fixed level VN output from the pre-adjustment module, an external enable signal E, and a high-voltage power supply VDDH at its input terminal. After processing by the internal logic circuit, it outputs a bias voltage Vg1. The bias voltage Vg1 is used to control the conduction and cutoff of the power switch P1 and the power circuit transistor N1.

[0013] The power switch P1 receives the bias voltage Vg1 output by the level conversion module at its gate, connects to the stepped-down voltage VDDL output by the pre-adjustment module at its drain, and connects to the drain of the power circuit transistor N1 at its source, and is used to realize power transmission under the control of the level conversion module.

[0014] The power circuit transistor N1 has its drain connected to the source of the power switching transistor P1, and its source is grounded. It is used to realize power transmission under the control of the level conversion module and to provide a stable low-voltage output voltage VOUT.

[0015] The resistive feedback network, consisting of resistors R1 and R2, is connected between the output voltage VOUT and the error amplifier. It is used to divide the output voltage VOUT and feed it back to the error amplifier to achieve closed-loop regulation of the output voltage.

[0016] Optionally, the pre-adjustment module specifically includes:

[0017] A circuit for generating a fixed level VN includes multiple MOSFETs connected in series to form a diode connection, and at least one MOSFET for pull-down to ensure that the fixed level VN is in a low state;

[0018] A circuit for generating a bucked voltage VDDL includes at least one PMOS transistor and at least one NMOS transistor, as well as at least one resistor for forming a current path and generating VDDL.

[0019] The first negative feedback loop includes at least one PMOS transistor and at least one resistor, used to sample changes in VN and reverse the adjustment of the VN current to stabilize VN;

[0020] The second negative feedback loop includes at least one NMOS transistor and at least one resistor, used to sample changes in VDDL and reverse adjust the VDDL current to compensate for the downward trend of VDDL and stabilize VDDL.

[0021] Specifically, when VDDH is 3V, VN output is 2.5V; when VDDH is 5V, VN output is 3V, to adapt to different input voltage conditions.

[0022] Optionally, the level conversion module specifically includes:

[0023] The input terminal is used to receive the input enable signal E and the input of the high-voltage power supply VDDH;

[0024] The logic circuit used to generate the bias voltage Vg1 for controlling the power switches and the internal switches of the operational amplifier.

[0025] At least two MOSFETs are used to control the generation of bias voltage Vg1 in response to an enable signal E and a preset threshold voltage;

[0026] At least one MOSFET is provided to provide a path for the shutdown bias voltage Vg1 when the enable signal E is low;

[0027] At least one MOSFET, whose gate is connected to a bias voltage Vg1, is used to control the turn-on and turn-off of power switch P1 and power circuit transistor N1.

[0028] Optionally, the error amplifier specifically includes:

[0029] A dual-terminal P-MOSFET input structure is used to receive the feedback voltage VFB and the reference voltage VREF;

[0030] A folded cascode amplifier structure is used to amplify the difference between VFB and VREF;

[0031] A single-stage output structure is used to output the amplified signal to the gate of the control power transistor;

[0032] At least four PMOS transistors controlled by Vg1 are used to provide withstand voltage protection in the high voltage domain;

[0033] A current source transistor is turned off when the enable signal E is low to prevent leakage current.

[0034] A common-source cascode current mirror structure, formed by a PMOS transistor controlled by Vg1 and a current mirror transistor, is used to improve the circuit's withstand voltage and stability.

[0035] The error amplifier can adjust the gate voltage of the power transistor through the PMOS transistor controlled by Vg1 under different enable signal E conditions.

[0036] Optionally, the resistive feedback network specifically includes:

[0037] The resistors R1 and R2 are determined according to the preset values ​​to ensure accurate voltage division and stability of the output voltage VOUT.

[0038] Optionally, the error amplifier specifically includes:

[0039] Used to turn off the current source transistor when the enable signal E is 0, so as to avoid leakage current.

[0040] This is used to form a common-source, common-gate current mirror structure with four PMOS transistors controlled by Vg1 when the enable signal E is 1, thereby improving the circuit's withstand voltage and stability.

[0041] Optionally, the level conversion module specifically includes:

[0042] Used to process the output bias voltage Vg1 through internal logic circuitry under different combinations of VDDH and E conditions, so as to ensure that the circuit avoids high voltage resistance problems and to make the leakage current reach an extremely low level when the circuit is turned off.

[0043] Optionally, the switching on and off of the power switch P1 and the power circuit transistor N1 are controlled by the bias voltage Vg1 to achieve power transmission under the control of the level conversion module and provide a stable low-voltage output voltage VOUT.

[0044] Optionally, the LDO circuit specifically includes:

[0045] The enable control circuit is used to control the logic level of the external enable signal E to enable and disable the LDO circuit.

[0046] The enable control circuit can automatically shut down the LDO circuit when the enable signal E is low, thereby reducing power consumption.

[0047] In a second aspect, an electronic device is provided, which implements an LDO circuit in any of the level conversion and pre-adjustment modules of the first aspect, for converting an externally input high-voltage power supply into a low-voltage linear power supply to power the internal modules of the chip.

[0048] The beneficial effects of the technical solutions provided in this application include at least the following:

[0049] Compared to traditional LDOs, this design can withstand a 5V power supply input without overvoltage issues under 3.3V CMOS technology, thus ensuring and extending the chip's lifespan under high-voltage environments and exhibiting high-voltage resistance. Furthermore, most leakage current in LDOs is generated by the large-area power transistor. This design, with the LDO enabled but disabled, ensures the power transistor is completely shut off regardless of whether the operating voltage is 3V or 5V, significantly improving the LDO's leakage current and resulting in lower leakage characteristics. Attached Figure Description

[0050] To more clearly illustrate the embodiments of this application or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are merely exemplary, and those skilled in the art can derive other embodiments based on the provided drawings without creative effort.

[0051] Figure 1 The circuit structure diagram of the low leakage current and high withstand voltage LDO provided in the embodiments of this application;

[0052] Figure 2 A pre-adjustment module circuit diagram provided for embodiments of this application;

[0053] Figure 3 A circuit diagram of a level conversion module provided in an embodiment of this application;

[0054] Figure 4 A flowchart illustrating the operation of the level conversion module provided in this application embodiment;

[0055] Figure 5 A circuit diagram of an error amplifier provided in an embodiment of this application. Detailed Implementation

[0056] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0057] In the description of this application, the terms "comprising," "having," and any variations thereof are intended to cover non-exclusive inclusion, such as a process, method, system, product, or apparatus that includes a series of steps or units, not necessarily limited to those steps or units that are expressly listed, but may also include other steps or units that are not expressly listed but are inherent to these processes, methods, products, or apparatuses, or steps or units added based on further optimizations conceived in this application.

[0058] Figure 1 The circuit diagram of the low-leakage, high-voltage LDO provided in this embodiment illustrates the basic principle of the LDO design: the LDO consists of a reference source, an error amplifier, a pre-adjustment module, a level shifting module, a power switch P1, a power circuit transistor N1, and resistor feedback networks R1 and R2. The LDO circuit includes:

[0059] A reference source is used to provide a stable reference voltage VREF as a reference signal for output voltage regulation;

[0060] An error amplifier receives a reference voltage VREF and a feedback voltage VFB from a feedback network at its input, and its output is connected to the gate of a power circuit N1. It is used to adjust the gate voltage of the power circuit N1 according to the difference between the feedback voltage VFB and the reference voltage VREF, thereby controlling the current flowing through the power circuit.

[0061] The pre-adjustment module receives a high-voltage power supply VDDH at its input, performs a step-down pre-adjustment on the high-voltage power supply VDDH, and outputs a fixed level VN and a stepped-down voltage VDDL.

[0062] The level conversion module receives a fixed level VN output from the pre-adjustment module, an external enable signal E, and a high-voltage power supply VDDH at its input terminal. After processing by the internal logic circuit, it outputs a bias voltage Vg1. The bias voltage Vg1 is used to control the conduction and cutoff of the power switch P1 and the power circuit transistor N1.

[0063] The power switch P1 receives the bias voltage Vg1 output by the level conversion module at its gate, connects to the stepped-down voltage VDDL output by the pre-adjustment module at its drain, and connects to the drain of the power circuit transistor N1 at its source, and is used to realize power transmission under the control of the level conversion module.

[0064] The power circuit transistor N1 has its drain connected to the source of the power switching transistor P1, and its source is grounded. It is used to realize power transmission under the control of the level conversion module and to provide a stable low-voltage output voltage VOUT.

[0065] The resistive feedback network, consisting of resistors R1 and R2, is connected between the output voltage VOUT and the error amplifier. It is used to divide the output voltage VOUT and feed it back to the error amplifier to achieve closed-loop regulation of the output voltage.

[0066] In this embodiment, VDDH is an external high-voltage power supply, and VOUT is the output voltage of the LDO. The reference source provides the error amplifier with a reference voltage VREF and a bias current Ibias. When the circuit is working normally, the feedback network composed of R1 and R2 samples the VOUT voltage. When the sampled voltage VFB decreases (or increases), the error amplifier amplifies the difference between VFB and VREF, thereby increasing (or decreasing) the output voltage of the error amplifier. This increases (or decreases) the gate voltage of N1, thereby increasing (or decreasing) the current flowing through N1. This causes the voltage of VOUT to increase (or decrease) again, compensating for the previous decrease (or increase). That is, the entire system is a negative feedback loop, ultimately achieving a stable output voltage VOUT.

[0067] A PMOS transistor P1 connected in series at the drain of power transistor N1 acts as a switch, responsible for turning the power branch on and off. The pre-adjustment module first steps down the input VDDH to pre-adjust it, outputting a voltage VDDL. VDDL fluctuates significantly depending on the process, power supply voltage, and temperature, and its load capacity is typically weak (around 100uA), making it unsuitable as a standard LDO. However, it can serve as the power supply for the reference module and level conversion module. Based on the voltage relationship between VDDL and VDDH, the level conversion module converts the input enable signal E into a bias voltage Vg1, used to control the power switch and the internal switches of the amplifier. E can be an externally input enable signal or an enable signal from the SOC chip's control system to the LDO. Vg1 has two important functions: first, it ensures that all transistors do not exceed the process withstand voltage during normal operation and does not affect the current in each branch; second, it ensures that the LDO can be completely turned off, with the leakage current in the nA range.

[0068] Figure 2 The schematic of the pre-adjustment circuit is shown. Its main function is to process VDDH and step down the output voltage to a certain range. It's worth noting that M43, M49, M55, and M56 are all native MOSFETs, used to provide stronger load-carrying capacity. For this module, Vg1 is the input, ensuring that the branch current generating VDDL is shut off when E=0; while VN and VDDL are the outputs, which are processed and stepped down to output a constant voltage. VN is independent of the overall LDO enable switch because the application circuit still requires a fixed power supply to power the level shifting circuit and other logic circuits when the enable signal changes from 0 to 1.

[0069] The circuit generating VN: M39~42 form a diode connection, making ZP approximately VDDH minus 4 times Vth. Simultaneously, M43 has strong pull-down capability, ensuring ZP remains low. When ZP is low, M47 conducts, and ZN is approximately the sum of the voltage drop across M47 and the voltage drop across VDDH minus Vth. The VN level is approximately equal to ZN minus Vth, placing it in a source follower state. The presence of M50, M51, and M52 ensures ZN doesn't drop too low to prevent M55 from conducting, thus affecting VDDL generation. There is a certain negative feedback between ZN and VN: when ZN decreases, the current in the branch containing M49 decreases. Because M45 and M52 are connected via a current mirror, the current in the branch containing M45 also decreases, causing ZN to rise, thus compensating for the decreasing trend and stabilizing it. The same applies to VN. In this application, VN = 2.5V when VDDH = 3V; and VN = 3V when VDDH = 5V.

[0070] The circuit generating VDDL: When Vg1 is low, as mentioned earlier, after ZN is established, M55 is turned on. Assuming no current is generated at this time, S1 is pulled up by R4. At this time, M56 is turned on, and M54 is pulled down by R5 and is also turned on. The branch containing M56 forms a current path, and through the current mirror connection, the branch containing M55 also generates current. At this time, VDDL is initially generated, and its lowest point is determined by the sum of the threshold voltages of M53 and M54. The stability of VDDL is jointly undertaken by a negative feedback circuit generated by a set of transistors and resistors: when VDDL drops for some reason, the gate voltage of M54 will drop simultaneously. At this time, since M53 and M54 share a gate, their conduction is suppressed. The current in the path containing M53 will decrease because the gate voltage of M56 is determined by the current and R4. Then S1 rises, and VDDL is pulled up by M56, finally compensating for the downward trend of VDDL, and VDDL is stable.

[0071] Figure 3 The demonstrated level conversion module's main function is to generate a bias voltage Vg1 by converting the input enable signal E and VDDH. This bias voltage is used to control the power switch and the internal switches of the operational amplifier, ensuring that all transistors in the circuit can withstand high voltage and that the drain electrode of the turn-off circuit is kept low. The level conversion circuit is a unique and important invention.

[0072] For ease of explanation, the threshold voltages of transistors M3, M9, and M12 are defined as V, respectively. th3 V th9 V th12 .

[0073] like Figure 4 A flowchart of the level conversion module is provided. The circuit's operation process is discussed below in four scenarios.

[0074] 1. When VDDH=3V and E=1:

[0075] Due to the characteristics of N-channel MOSFETs, M7 and M10 will be directly turned on. As mentioned earlier, VN is a fixed level generated by the preprocessing module, its value is approximately equal to VDDH minus two threshold voltages, allowing M1, M2, and M12 to be turned on. M12 is in subthreshold conduction, considered to be in the off state. Vg2 will be pulled low by M10 (i.e., Vg2=0), turning on M3 and M4. At this time, the branch containing M3 is connected to ground, thereby pulling down Vg1 to Vgs3 (i.e., Vg1=Vth3). Since Vg1 is connected to the gate of M6, M6 is turned on and pulls Vgb1 up to VDDH, thus turning off M5. Therefore, Vg1 is now stable at a low potential Vgs3, approximately equal to the threshold voltage of a P-MOSFET. In this way, this module generates a gate voltage that can turn on all P-MOSFETs that are also below the VDDH voltage threshold. Since VDDH is low, there is no risk of exceeding the overvoltage limit.

[0076] 2. When VDDH=3V and E=0:

[0077] Due to the characteristics of N-channel MOSFETs, M8 is directly turned on, while M7 and M10 are turned off, and the voltage detection circuit remains off. Vg2, under the combined effect of the upper and lower circuits, is slightly higher than Vth9 (i.e., Vg2 > Vth9), allowing M3 and M4 to still conduct. The branch containing M4 is grounded, pulling Vgb1 down to Vg2 + Vgs4, thus turning on M5. Vg1 is pulled up by M5 to the VDDH level and output (i.e., Vg1 = 3V). Simultaneously, Vg1 causes M6 to turn off, and Vgb1 remains low. In this way, the module generates a gate voltage capable of turning off all P-MOSFETs with the same voltage threshold, thus avoiding both overvoltage issues and ensuring no leakage current in the target MOSFET.

[0078] 3. When VDDH=5V and E=1:

[0079] For the same reasoning as above, M7 and M10 are directly conducting, and VN is at an intermediate level. Since Vgs12 is relatively large, the voltage detection circuit is in a strong conducting state, forming a current path together with M9 and M10. The level of Vg2 is determined by the strength of the pull-up and pull-down circuits. Considering that the process used in this application has a withstand voltage of 3.63V, Vg2 is controlled within a reasonable range (i.e., Vg2 > 1.4V) by adjusting the circuit dimensions. At this time, M3 and M4 are conducting. In the circuit, the branch containing M3 is connected to ground, thereby pulling down Vg1 to Vg2 + Vgs3. The intermediate level Vg1 will cause M6 to conduct, Vgb1 to be pulled up to VDDH, M5 to be cut off, and the output of Vg1 remains constant at Vg2 + Vgs3 (i.e., Vg1 = Vg2 + Vth3). In this way, the module generates an intermediate level slightly higher than 1.4V, which allows it to turn on the target MOSFET without the risk of overvoltage when applied to the gate of the P-MOSFET in the 5V voltage domain.

[0080] 4. When VDDH=5V and E=0:

[0081] Similarly, M8 and M2 are in the ON state, while M7 and M10 are in the OFF state. The voltage detection circuit will turn on and pull up Vg2, forming a conducting circuit with M9. The circuit size of this path is designed so that Vg2 exceeds 1.4V (i.e., Vg2>1.4V). In this way, M4 turns on, and its circuit forms a path to ground, pulling down Vgb1 to Vg2+Vgs4, and turning on M5. Vg1 is pulled up to VDDH by M5 (i.e., Vg1=5V), causing M6 to turn off, and Vgb1 to be approximately Vg1+Vgs4, completing the output establishment. In this case, this module generates a level approximately equal to VDDH to turn off the P-MOSFET below the 5V voltage threshold and ensure that it does not generate leakage current. Table 1 shows the circuit's operating data.

[0082] Table 1

[0083]

[0084] Figure 5 The structure of the error amplifier used in the LDO circuit of this application is shown. It is a folded common-source common-gate amplifier with dual-ended P-MOSFET inputs. After a single-stage output, it passes through a P-MOSFET source follower structure before being output to the gate of the control power transistor. This is a commonly used and ordinary op-amp circuit, but it cannot withstand a 5V high voltage under 3.3V technology. To meet the 5V withstand voltage requirement, four PMOS transistors M37, M31, M17, and M25 controlled by Vg1 are added. By properly designing the Vg1 voltage, high voltage withstand can be achieved. The following mainly discusses how Vg1 is addressed. Figure 1 and Figure 5 High voltage withstand issue when operating at 5V.

[0085] When E=0, the current source transistor in the operational amplifier circuit is turned off, and no current is generated in the circuit. The Vg1 generated by the level conversion module is approximately equal to 5V, i.e., VDDH, which ensures that M37, M31, M17, and M25 are completely cut off, avoiding leakage current and overvoltage issues. Figure 1 Furthermore, P1 on the LDO's power circuit can be completely turned off by Vg1, giving the LDO circuit an ultra-low leakage current structure. Before using the Vg1-controlled P1 switch, N1 was a native NMOS power transistor, which, while having strong load-carrying capacity, inevitably had leakage current issues. The presence of P1 controlled by Vg1 avoids the leakage current problem inherent in its structure.

[0086] When E=1, the op-amp circuit operates normally, and Vg1 is at an intermediate level >1.4V. The four PMOS transistors controlled by Vg1 form a common-source, common-gate current mirror structure with the current mirror transistor. This structure has a certain voltage withstand capability and more stable circuit performance. Therefore, the op-amp circuit does not have an overvoltage problem. At this time, the switch P1 of the LDO circuit's power transistor N1, controlled by Vg1, can also be in a normal conducting state. The intermediate level ensures that P1, while conducting normally, will not experience an overvoltage (3.63V) problem. This solves the overvoltage problem that is difficult to directly handle when using a 5V voltage domain in a 3.3V CMOS process.

[0087] The high-voltage, low-leakage LDO design method proposed in this application allows low-voltage processes to be directly applied to high-voltage environments, reducing design costs; and it can completely shut down the LDO circuit, reducing quiescent current. It can be used in the PMU of most SOC chips, or the internal power supply of RF chips, and other consumer electronics products, with a very wide range of applications. Our company has already implemented this solution on an RF chip.

[0088] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A level shifting and pre-adjustment module based LDO circuit, characterized in that, The LDO circuit comprises: a reference source for providing a stable reference voltage VREF as a reference signal for output voltage regulation; an error amplifier having an input end receiving the reference voltage VREF and a feedback voltage VFB from a feedback network and an output end connected to a gate of the power circuit N1 for regulating the gate voltage of the power circuit N1 according to the difference between the feedback voltage VFB and the reference voltage VREF, thereby controlling the current flowing through the power circuit; a pre-adjustment module having an input end receiving a high-voltage power supply VDDH and performing voltage reduction pre-adjustment on the high-voltage power supply VDDH to output a fixed voltage VN and a voltage VDDL after voltage reduction; a level conversion module having an input end receiving the fixed voltage VN output by the pre-adjustment module, an external enable signal E and the high-voltage power supply VDDH and outputting a bias voltage Vg1 after processing by an internal logic circuit, wherein the bias voltage Vg1 is used to control the turn-on and turn-off of the power switch P1 and the power circuit N1; a power switch P1 having a gate receiving the bias voltage Vg1 output by the level conversion module, a drain connected to the voltage VDDL after voltage reduction output by the pre-adjustment module and a source connected to a drain of the power circuit N1, for realizing power transmission under the control of the level conversion module; a power circuit N1 having a drain connected to the source of the power switch P1 and a source connected to ground, for realizing power transmission under the control of the level conversion module and providing a stable low-voltage output voltage VOUT; a resistive feedback network composed of resistors R1 and R2 and connected between the output voltage VOUT and the error amplifier, for realizing closed-loop regulation of the output voltage by feeding back the output voltage VOUT after voltage division to the error amplifier.

2. The LDO circuit of claim 1, wherein, The pre-adjustment module specifically comprises: a circuit for generating a fixed voltage VN, comprising a plurality of MOS transistors connected in series to form a diode connection and at least one MOS transistor for pull-down to ensure that the fixed voltage VN is in a low voltage state; a circuit for generating a voltage VDDL after voltage reduction, comprising at least one PMOS transistor and at least one NMOS transistor and at least one resistor for forming a current path and generating VDDL; a first negative feedback loop comprising at least one PMOS transistor and at least one resistor for sampling VN changes and inversely regulating VN current to stabilize VN; a second negative feedback loop comprising at least one NMOS transistor and at least one resistor for sampling VDDL changes and inversely regulating VDDL current to compensate for the downward trend of VDDL and stabilize VDDL; wherein when VDDH is 3V, VN output is 2.5V; and when VDDH is 5V, VN output is 3V, to adapt to different input voltage conditions.

3. The LDO circuit of claim 1, wherein, The level conversion module specifically comprises: an input end for receiving an input enable signal E and a high-voltage power supply VDDH; a logic circuit for generating a bias voltage Vg1 for controlling the power switch and the internal switch of the operational amplifier; at least two MOSFETs for responding to the enable signal E and a preset threshold voltage to control the generation of the bias voltage Vg1; at least one MOSFET for providing a path for the off bias voltage Vg1 when the enable signal E is low; at least one MOSFET with its gate connected to the bias voltage Vg1 for controlling the turn-on and turn-off of the power switch P1 and the power circuit N1.

4. The LDO circuit of claim 1, wherein, The error amplifier specifically includes: a double-ended P-MOSFET input structure for receiving the feedback voltage VFB and the reference voltage VREF; a folded cascode amplifier structure for amplifying the difference between VFB and VREF; a single-stage output structure for outputting the amplified signal to the gate of the power transistor; at least four PMOS transistors controlled by Vg1 for providing voltage withstand protection in the high voltage domain; a current source transistor that is turned off when the enable signal E is low to avoid leakage current; a cascode current mirror structure formed by the PMOS transistor controlled by Vg1 and the current mirror transistor for improving the voltage withstand capability and stability of the circuit; The error amplifier can adjust the gate voltage of the power transistor through the PMOS transistor controlled by Vg1 under different enable signal E conditions.

5. The LDO circuit of claim 1, wherein, The resistance feedback network specifically includes: The resistors R1 and R2 are determined according to the preset value to ensure accurate voltage division and stability of the output voltage VOUT.

6. The LDO circuit of claim 1, wherein, The error amplifier specifically includes: for turning off the current source transistor when the enable signal E is 0 to avoid leakage current; for forming a cascode current mirror structure by the four PMOS transistors controlled by Vg1 and the current mirror transistor when the enable signal E is 1 to improve the voltage withstand capability and stability of the circuit.

7. The LDO circuit of claim 1, wherein, The level conversion module specifically includes: for outputting the bias voltage Vg1 through internal logic circuit processing under different combinations of VDDH and E to ensure that the circuit avoids high voltage withstand problems and that the leakage current is extremely low when the circuit is turned off.

8. The LDO circuit of claim 1, wherein, The turn-on and turn-off of the power switch P1 and the power circuit N1 are controlled by the bias voltage Vg1 to realize power transmission under the control of the level conversion module and provide a stable low voltage output VOUT.

9. The LDO circuit of claim 1, wherein, The LDO circuit specifically includes: an enable control circuit for controlling the logic level of the external enable signal E to realize the opening and closing of the LDO circuit; wherein the enable control circuit can automatically turn off the LDO circuit when the enable signal E is low to reduce power consumption.

10. An electronic device, comprising: The LDO circuit based on the level conversion and pre-adjustment module as claimed in any one of claims 1 to 9 is used to convert an externally input high voltage power supply into a low voltage linear power supply to power the internal modules of the chip.

Images