Memory management method and memory controller

Abstract

The invention provides a memory management method and a memory controller. The method comprises the following steps of: counting the reading times of each logical address range in a plurality of logical address ranges in a storage device in a statistical period; based on the reading times of each logical address range, determining a target logical address range, and caching corresponding target address mapping information; after the target address mapping information is cached, updating a corresponding target reading popularity value based on a first preset threshold value and another reading times in the target logic address range after the target address mapping information is cached; and when the target reading popularity value is lower than a popularity value lower limit, removing the cached target address mapping information. According to the method and the device, a quantitative popularity updating mechanism based on the relationship between the reading times and the preset threshold is established, so that dynamic and self-adaptive management of the cache resources is realized, and the cache hit rate and the overall working performance of the storage system are further improved.

Description

Technical Field

[0001] This disclosure relates to the field of storage technology, and in particular to a cache management method for flash memory and a corresponding memory controller, as well as a memory management method and a memory controller. Background Technology

[0002] Flash memory, as a non-volatile storage medium, is widely used in storage devices such as solid-state drives (SSDs), embedded multi-media cards (eMMCs), and universal flash storage (UFS) due to its advantages such as low power consumption, strong shock resistance, and fast read and write speeds.

[0003] To further improve storage device performance, the industry has introduced various caching technologies, such as Host Performance Booster (HPB). This technology allows storage devices to use a portion of host memory to cache their internal logical address-to-physical address mapping information (L2P Table). By placing frequently accessed address mapping information in the cache, the number of accesses to the storage medium can be reduced, thereby speeding up data read operations.

[0004] However, existing cache management strategies for address mapping information are often mechanical and rigid. For example, some methods use a fixed threshold of read counts to determine whether to cache the mapping information of a certain logical address range. This static threshold cannot adapt to dynamic changes in system load. Furthermore, regarding cache eviction, the traditional Least Recently Used (LRU) algorithm only considers the temporal locality of access, failing to effectively identify and retain frequently accessed but recently unaccessed "hot" data. This can easily lead to low utilization of cache resources and performance improvements that do not meet expectations. Summary of the Invention

[0005] In view of this, the present disclosure provides a memory management method and a memory controller, which aims to solve the problem of rigid cache management strategies in the prior art.

[0006] One or more embodiments of this disclosure provide a memory management method applied to a memory controller, which controls a storage device configured with memory modules. The method includes: within a statistical period, counting the number of reads for each logical address range among multiple logical address ranges within the storage device; determining a target logical address range based on the number of reads for each logical address range, and caching target address image information corresponding to the target logical address range; after the target address image information is cached: updating a target read heat value for the corresponding target logical address range based on a first preset threshold and another number of reads for the target logical address range after the target address image information is cached; and removing the cached target address image information when the target read heat value is lower than a lower limit of heat value.

[0007] One or more embodiments of this disclosure provide a memory controller for controlling a storage device configured with a memory module. The memory controller includes: a memory interface control circuit electrically connected to the memory module; and a processor electrically connected to the memory interface control circuit. The processor is configured to: count the number of reads of each logical address range among multiple logical address ranges within the storage device in a statistical period; determine a target logical address range based on the number of reads of each logical address range, and cache target address image information corresponding to the target logical address range; after the target address image information is cached: update a target read heat value for the corresponding target logical address range based on a first preset threshold and another number of reads of the target logical address range after the target address image information is cached; and remove the cached target address image information when the target read heat value is lower than a lower limit of heat value.

[0008] Based on the above, the memory management method and memory controller provided in this disclosure can achieve the following technical effects:

[0009] First, by counting the number of reads for each logical address range within multiple logical address ranges in the storage device over a statistical period, and determining the target logical address range to be cached based on this count, the method disclosed in this paper establishes a cache admission mechanism based on actual access frequency. This mechanism ensures that only logical address ranges with high access frequency that have been verified through data statistics are eligible to enter the cache, thereby avoiding cache space pollution caused by accidental, single read operations from the source, and laying a data foundation for subsequent efficient cache management. Attached Figure Description

[0010] Figure 1 This is a block diagram illustrating a host system and a storage device according to an embodiment of the present invention;

[0011] Figure 2This is a flowchart illustrating a memory management method according to an embodiment of the present invention;

[0012] Figure 3 This is a flowchart illustrating the dynamic adjustment of the cache trigger threshold according to an embodiment of the present invention;

[0013] Figure 4 This is a flowchart illustrating the updating target reading heat value according to an embodiment of the present invention;

[0014] Figure 5 This is a flowchart illustrating the attenuation process of the read heat value according to an embodiment of the present invention;

[0015] Figure 6 According to a flowchart of batch heat update and decay based on statistical period shown in an embodiment of the present invention;

[0016] Figure 7 According to a schematic diagram illustrating bottom-up updating of heat values ​​using a binary tree structure, as shown in an embodiment of the present invention;

[0017] Figure 8 According to a schematic diagram illustrating the change of read popularity value over time and access frequency in an embodiment of the present invention;

[0018] Figure 9 The data structure diagram of the heat information table shown in one embodiment of the present invention is illustrated. Detailed Implementation

[0019] Reference will now be made in detail to exemplary embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, the same component reference numerals are used in the drawings and description to denote the same or similar parts.

[0020] Figure 1 This is a block diagram illustrating a host system and storage device according to an embodiment of the present disclosure.

[0021] Please refer to Figure 1The host system 10 is, for example, a personal computer, a laptop computer, or a server. The host system 10 includes a processor 110 (also called a second processor), host memory 120 (also called host RAM), and a data transfer interface circuit 130. In this embodiment, the processor 110 is coupled (also called electrically connected) to the host memory 120 and the data transfer interface circuit 130. In another embodiment, the processor 110, host memory 120, and data transfer interface circuit 130 are electrically connected to each other via a system bus. In this embodiment, the processor 110, host memory 120, and data transfer interface circuit 130 may be located on the motherboard of the host system 10.

[0022] The storage device 20 includes a memory controller 210, a memory module 220 (also known as a rewritable non-volatile memory module), and a connection interface circuit 230. The memory controller 210 includes a processor 211 (also known as a first processor), a data management circuit 212, a memory interface control circuit 213, and a buffer memory 214.

[0023] In this embodiment, the host system 10 is electrically connected to the storage device 20 via a data transmission interface circuit 130 and a connection interface circuit 230 to perform data access operations. For example, the host system 10 can store data to or read data from the storage device 20 via the data transmission interface circuit 130.

[0024] In this embodiment, the number of data transmission interface circuits 130 can be one or more. Through the data transmission interface circuits 130, the motherboard can be electrically connected to the storage device 20 via wired or wireless means. The storage device 20 can be, for example, a USB flash drive, memory card, solid-state drive (SSD), or wireless storage device. The wireless storage device can be, for example, a Near Field Communication (NFC) storage device, a WiFi storage device, a Bluetooth storage device, or a Bluetooth Low Energy storage device (e.g., iBeacon), or other storage devices based on various wireless communication technologies. Furthermore, the motherboard can also be electrically connected via the system bus to various I / O devices such as a Global Positioning System (GPS) module, network interface card, wireless transmission device, keyboard, screen, and speaker.

[0025] In this embodiment, the data transmission interface circuit 130 and the connection interface circuit 230 are interface circuits compatible with the Peripheral Component Interconnect Express (PCI Express) standard. Furthermore, data transmission between the data transmission interface circuit 130 and the connection interface circuit 230 utilizes the Non-Volatile Memory Express (NVMe) communication protocol.

[0026] In another embodiment, the connection interface circuit 230 may be packaged in a chip with the memory controller 210, or the connection interface circuit 230 may be disposed outside a chip containing the memory controller 210.

[0027] In this embodiment, the host memory 120 is used to temporarily store instructions or data executed by the processor 110. In this embodiment, the host memory 120 may be Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), etc. However, it should be understood that this disclosure is not limited to this, and the host memory 120 may also be other suitable memories.

[0028] The memory controller 210 executes multiple logic gates or control instructions implemented in hardware or firmware, and performs corresponding data writing, data reading, and data erasure operations in the memory module 220 according to the instructions of the host system 10. In particular, the memory controller 210 implements a memory management method provided in this disclosure to dynamically manage the cache of address map information corresponding to logical address ranges, thereby improving the overall performance of the storage device 20.

[0029] More specifically, the processor 211 in the memory controller 210 is hardware with computing capabilities, used to control the overall operation of the memory controller 210. Specifically, the processor 211 is configured to execute the memory management method provided in this disclosure. For example, within a statistical cycle, the processor 211 counts the number of reads for each logical address range among multiple logical address ranges within the storage device 20. Then, based on the number of reads for each logical address range, the processor 211 determines a target logical address range and caches the target address image information corresponding to the target logical address range. After the target address image information is cached, the processor 211 updates the target read heat value for the corresponding target logical address range based on a first preset threshold and another subsequent read count. Finally, when the processor 211 determines that the target read heat value is lower than the lower limit of the heat value, it removes the cached target address image information.

[0030] It is worth mentioning that, in this embodiment, the processor 110 and the processor 211 are, for example, a central processing unit (CPU), a microprocessor, or other programmable processing units (microprocessor), digital signal processor (DSP), programmable controller, application specific integrated circuits (ASIC), programmable logic device (PLD), or other similar circuit components, and this disclosure is not limited thereto.

[0031] In this embodiment, as described above, the memory controller 210 further includes a data management circuit 212 and a memory interface control circuit 213. It should be noted that the operations performed by each component of the memory controller 210 can also be considered as operations performed by the memory controller 210 itself.

[0032] The data management circuit 212 is electrically connected to the processor 211, the memory interface control circuit 213, and the connection interface circuit 230. The data management circuit 212 receives instructions from the processor 211 to perform data transmission. For example, it reads data from the host system 10 (e.g., host memory 120) via the connection interface circuit 230 and writes the read data into the memory module 220 via the memory interface control circuit 213. Alternatively, it performs a read operation according to a read instruction from the host system 10, reading data from one or more physical units of the memory module 220 via the memory interface control circuit 213 and writing the read data into the host system 10 via the connection interface circuit 230.

[0033] In another embodiment, the data management circuit 212 may also be integrated into the processor 211. The memory interface control circuit 213 is used to receive instructions from the processor 211 and, in conjunction with the data management circuit 212, to perform physical operations such as writing (also known as programming), reading, or erasing on the memory module 220.

[0034] Furthermore, data to be written to memory module 220 is converted into a format acceptable to memory module 220 via memory interface control circuit 213. Specifically, if processor 211 needs to access memory module 220, processor 211 transmits a corresponding instruction sequence to memory interface control circuit 213 to instruct memory interface control circuit 213 to perform the corresponding operation. For example, these instruction sequences may include write instruction sequences indicating the writing of data, read instruction sequences indicating the reading of data, erase instruction sequences indicating the erasure of data, and corresponding instruction sequences for indicating various memory operations. These instruction sequences may include one or more signals, or data on the bus. These signals or data may include instruction codes or program codes. For example, a read instruction sequence may include information such as the read identification code, memory address, and physical address.

[0035] Furthermore, the memory controller 210 establishes a logical-to-physical address mapping table and a physical-to-logical address mapping table to record the mapping relationship between the logical addresses of logical units (e.g., logical blocks, logical pages) and the physical addresses (physical addresses) of physical units (e.g., physical erase units / physical blocks, physical pages) configured for the memory module 220. In other words, the memory controller 210 can use the logical-to-physical address mapping table (also called the logical-to-physical mapping table) to look up the physical unit mapped to a logical unit (e.g., look up the physical page mapped to a logical page; look up the physical address mapped to a logical address), and the memory controller 210 can use the physical-to-logical address mapping table (also called the physical-to-logical mapping table) to look up the logical unit mapped to a physical unit (e.g., look up the logical page mapped to a physical page; look up the logical address mapped to a physical address).

[0036] Buffer memory 214 is electrically connected to processor 211 and is used to temporarily store data and instructions from host system 10, data from memory module 220, and various system data for managing storage device 20. In embodiments of this disclosure, one of the core uses of buffer memory 214 is as a data and status management center for the memory management method of this invention. Specifically, processor 211 establishes and maintains corresponding data structures in buffer memory 214 to support the heat management process.

[0037] In one embodiment, the data structure can be a heat information table (e.g., Figure 9 The HVT (Hardware Temperature Detection Table) records multiple logical address ranges (e.g., HPB region IDs) and their corresponding read counts (e.g., RC1, RC2), read heat values ​​(e.g., HV1, HV2), cache status (e.g., "01" indicates cached), and access times (e.g., ACT1, ACT2). The processor 211 maintains the HVT to perform a series of operations disclosed herein, including cache admission, heat update, heat decay, and cache eviction.

[0038] The memory module 220 is electrically connected to the memory controller 210 (specifically, the memory interface control circuit 213) and is used to store user data sent by the host system 10. The memory module 220 includes multiple physical blocks, each physical block consisting of multiple physical pages, and each physical page containing multiple storage units. It should be noted that this disclosure is not limited to the specific capacity or the specific number of physical pages of the memory module 220.

[0039] The memory module 220 is electrically connected to the memory controller 210 (specifically, the memory interface control circuit 213) and is used to store user data sent by the host system 10. The memory module 220 includes multiple physical blocks, each physical block consisting of multiple physical pages, and each physical page containing multiple storage units. It should be noted that this disclosure is not limited to the specific capacity or the specific number of physical pages of the memory module 220.

[0040] In some embodiments, the memory module 220 may be composed of various types of non-volatile storage media. Specifically, the memory module 220 may include 3D NAND flash memory, 2D NAND flash memory, NOR flash memory, resistive random-access memory (RRAM), magnetoresistive random-access memory (MRAM), or phase-change memory (PCM), etc. The memory management method disclosed herein is not limited to a specific type of storage medium; it is applicable as long as the medium requires the conversion between logical and physical addresses through address mapping information.

[0041] Figure 2 This is a flowchart illustrating a memory management method according to embodiments of the present disclosure.

[0042] Reference Figure 2 In one embodiment, the memory management method of this disclosure can be provided by... Figure 1 The memory controller 210 shown is specifically implemented by its processor 211 loading and executing firmware code.

[0043] The process begins at step S210, where, within a statistical cycle, processor 211 counts the number of reads for each logical address range within the multiple logical address ranges in memory device 20. The statistical cycle can be a preset time length, such as 100 milliseconds; or it can be a preset total number of read operations, for example, a statistical cycle is considered to end after 10,000 read operations are completed. Processor 211 accumulates and records the read count values ​​associated with each logical address range by monitoring all read commands received via the connection interface circuit 230.

[0044] Next, in step S220, the processor 211 determines the target logical address range based on the number of reads for each logical address range, and caches the target address image information corresponding to the target logical address range.

[0045] Specifically, processor 211 uses the number of reads obtained in step S210 as the basis for determining whether a logical address range is a "hotspot" region. If a logical address range is accessed frequently, processor 211 identifies it as the target logical address range and loads its corresponding address mapping information (e.g., a logical-to-physical address translation table) into the cache. This cache may be part of the host memory 120 within the host system 10, or the buffer memory 214 inside the storage device 20.

[0046] In one embodiment, the processor 211 can compare each logical address range with a specific read count threshold (also known as a first preset threshold) to determine whether there is a target logical address range with a high access frequency that needs to be cached.

[0047] Figure 3 This is a flowchart illustrating the dynamic adjustment of the cache trigger threshold according to an embodiment of the present invention.

[0048] Reference Figure 3 In one embodiment, during a work cycle, processor 211 first performs a read count acquisition operation in step S310. Specifically, processor 211 will, for a specific logical address range, retrieve the read count from its maintained hotness information table (e.g., ...). Figure 9 You can query the HVT in the data or accumulate the corresponding number of reads within the current statistical period.

[0049] It is worth noting that, in one embodiment, this process may also include a parallel, continuously running control step, namely step S340. To further enhance the adaptive capability of cache management, the processor 211 dynamically adjusts the first preset threshold used in step S320 based on the real-time system load of the storage device 20. After dynamic adjustment, steps S310 and S320 are executed to determine the heat of each logical address range more suitable for the current system environment using the adjusted first preset threshold.

[0050] More specifically, in one embodiment, the processor 211 continuously monitors the length of the command processing queue within the storage device 20. The length of this queue is a direct and effective indicator of the current system load: the longer the queue, the more read and write commands are waiting to be processed, and the busier the system is; conversely, the shorter the queue, the less busy the system is.

[0051] In one embodiment, processor 211 may implement an adjustment algorithm such that a first preset threshold is positively correlated with the system load. For example, processor 211 may set a base threshold and a load factor weight, and calculate a new first preset threshold according to the following formula:

[0052] Dynamic threshold = base threshold × (1 + load factor weight × queue length).

[0053] In this way, when the storage device 20 is under high load, the entry threshold for the cache will be automatically raised; when the system load is low, the entry threshold will be lowered accordingly.

[0054] After obtaining the number of reads, in step S320, the processor 211 compares the obtained number of reads with a first preset threshold. This step is a key decision point in determining whether the logical address range has sufficient access heat to warrant caching.

[0055] In a more refined embodiment, the processor 211's dynamic adjustment decisions are based not only on the current system load but also on the effects of historical caching decisions. For example, the processor 211 may maintain two counters: one to count the number of events where caching was not performed due to insufficient read counts (corresponding to...). Figure 3 The A31 feedback in the middle), another is used to count the number of events that are successfully triggered in the cache (corresponding to Figure 3 (A32 feedback in the code). At the end of each statistical cycle, the processor 211 analyzes the ratio of the two counters. If the processor 211 finds that the number of events that have not triggered the cache has increased significantly recently, it may indicate that the current first preset threshold is set too high, causing potential hot data to not be effectively cached. In this case, even if the current system load has not changed significantly, the processor 211 can proactively and moderately lower the "base threshold" used to calculate the dynamic threshold in order to capture more hot data in the next cycle. Conversely, if the number of events that have successfully triggered the cache is too high, it may indicate that the threshold is too low, and the processor 211 can correspondingly increase the "base threshold" to tighten the cache admission policy and prevent cache pollution.

[0056] In another embodiment, after caching is completed, as shown by arrow A32, the process returns to step S340 to continue determining whether to adjust the first preset threshold based on system load.

[0057] On the other hand, if the processor 211 determines that the number of reads has not reached the first preset threshold (i.e., the "no" path of S320), it means that the current access popularity of the logical address range is insufficient, and no cache operation is performed. The process returns to S310 to judge other logical address ranges.

[0058] In another embodiment, as shown by arrow A31, if the processor 211 determines that the number of reads has not reached the first preset threshold, the process can return to step S340.

[0059] Meanwhile, the event results in the main process (such as the status feedback shown in A31 and A32) can also serve as input information for the adjustment decision in step S340.

[0060] Specifically, in one embodiment, the processor 211's dynamic adjustment decision is based not only on the current system load but also on the historical caching decision effects. For example, the processor 211 may maintain two counters: one for counting the number of events where caching was not performed due to insufficient read counts (corresponding to...). Figure 3 The A31 feedback in the middle), another is used to count the number of events that are successfully triggered in the cache (corresponding to Figure 3 (A32 feedback in the code). At the end of each statistical cycle, the processor 211 analyzes the ratio of the two counters. For example, if the processor 211 finds that the number of events that have not triggered the cache has increased significantly recently, it may indicate that the current first preset threshold is set too high, causing potential hot data to not be effectively cached. In this case, even if the current system load has not changed significantly, the processor 211 can proactively and moderately lower the "base threshold" used to calculate the dynamic threshold in order to capture more hot data in the next cycle. Conversely, if the number of events that have successfully triggered the cache is too high, it may indicate that the threshold is too low, and the processor 211 can correspondingly increase the "base threshold" to tighten the caching strategy.

[0061] Based on the above process methods, this disclosure establishes a closed-loop feedback system that enables the caching admission threshold to float intelligently and in real time according to the system's workload, rather than using a fixed and rigid standard.

[0062] Back Figure 2 Next, in step S230, after the target address image information is cached, the processor 211 updates the target read heat value of the corresponding target logical address range based on the first preset threshold and another number of reads of the target logical address range after the target address image information is cached.

[0063] This step is the core of the quantitative management of access frequency in this disclosure. In one embodiment, the processor 211 not only counts the number of reads in subsequent cycles, but also compares and calculates them with a baseline threshold to obtain a quantitative value that more accurately reflects the access "heat". This target read heat value, compared to a simple number of reads, can more effectively prioritize multiple cached regions. The following utilizes... Figures 4-8 The following examples will be used to illustrate the point.

[0064] Figure 4 This is a flowchart illustrating the updating of target reading heat value according to an embodiment of the present invention.

[0065] Reference Figure 4In one embodiment, Figure 4 This is a detailed flowchart illustrating the process of updating the target read popularity value in this disclosure. This process is executed by the processor 211 after the target address image information is cached, in order to achieve a quantitative assessment of the popularity.

[0066] The process begins at step S410, when the processor 211 first caches the target address image information corresponding to a target logical address range, it sets an initial target read heat value for that target logical address range. This initial value can be a preset non-zero positive number, such as 5, and its purpose is to provide a basic cache priority for newly cached items, preventing them from being immediately evicted due to zero heat before obtaining sufficient access statistics.

[0067] Next, in subsequent statistical cycles, the process proceeds to step S420. The processor 211 calculates the ratio of the number of reads of the target logical address range after it has been cached in the current statistical cycle to the currently valid first preset threshold. This ratio directly reflects the degree to which the access frequency of this range exceeds the cache admission threshold and is a key indicator for measuring its "hotness".

[0068] Subsequently, in step S430, the processor 211 obtains a heat increment based on the ratio calculated in step S420, and updates the target read heat value based on this heat increment. Specifically, the processor 211 can directly use the calculated ratio as the heat increment for this update. For example, if another read count is 1200 times and the first preset threshold is 120 times, then the ratio is 10, and the heat increment is 10. The processor 211 will add this heat increment to the current target read heat value for that range. In this way, the more frequently accessed a region is, the faster its read heat value grows, thus obtaining a higher priority in cache management.

[0069] In another embodiment, to prevent previously frequently accessed data from occupying cache resources for an extended period due to decreased access frequency, the method of this disclosure further includes a mechanism for attenuating the target read popularity value. The processor 211 performs this attenuation process based on access time information associated with the cached target address image information, to simulate the natural cooling of popularity over time.

[0070] Specifically, the processor 211 will, for each cached target logical address range, enter its corresponding heat information table entry (e.g., Figure 9The processor 211 records and maintains a last access timestamp in the HVT (Hardware Virtualization Unit). This last access timestamp is a specific access time information. When attenuation calculation is required (e.g., at the end of a statistical period), the processor 211 performs the following steps: First, it obtains the current system time and calculates the time interval between the current time and the last access timestamp of the range. Next, the processor 211 calculates the amount of heat attenuation to be deducted based on the calculated time interval and a preset heat attenuation rate. For example, if the heat attenuation rate is 0.1 points / second and the time interval is 5 seconds, the heat attenuation is 0.5 points. Finally, the processor 211 subtracts the calculated heat attenuation from the current target read heat value of the range to complete one attenuation process. Through this mechanism, if a logical address range is not accessed for a long time, its time interval will continue to accumulate, causing its read heat value to steadily decrease, and eventually it will be identified and eliminated by the system because it is below the lower limit of the heat value.

[0071] Figure 5 This is a flowchart illustrating the attenuation process of reading heat values ​​according to an embodiment of the present invention.

[0072] Reference Figure 5 In one embodiment, the processor 211 ensures that the hotness information in the cache reflects the temporal locality of access and promptly evicts data that has become cold.

[0073] Specifically, the process begins at step S510. When it is necessary to perform attenuation calculations on a cached target logical address range, the processor 211 first obtains the last access time of the target logical address range. This last access time can be recorded in a corresponding data structure, such as... Figure 9 The "Access Time" field (e.g., ACT1) in the HVT popularity information table is shown.

[0074] Next, in step S520, processor 211 calculates the access time interval Δt. Specifically, processor 211 obtains the current system timestamp and subtracts it from the last access timestamp obtained in step S510; the difference is the access time interval Δt. This time interval Δt precisely quantifies the length of time that has elapsed since the logical address range was last accessed.

[0075] Subsequently, in step S530, processor 211 calculates the heat decay amount based on the time interval Δt calculated in step S520 and a preset heat decay rate. The heat decay rate is a configurable parameter used to define the rate at which the heat decreases over time. For example, processor 211 can multiply the time interval Δt by the heat decay rate to obtain a heat decay amount proportional to the idle time.

[0076] Finally, in step S540, the processor 211 subtracts the heat decay amount calculated in step S530 from the current target read heat value of the target logical address range to complete the decay process of the target read heat value. By periodically executing this process, it can be ensured that the read heat value of any cache item that has not been accessed for a long time will steadily decrease, eventually triggering the eviction mechanism, thereby maintaining the efficient utilization of cache space.

[0077] In another embodiment, to reduce the system performance overhead that may result from frequent updates to individual read popularity values, the processor 211 employs a batch update mechanism to centrally handle changes in popularity. Specifically, the processor 211 does not perform update or decay calculations of the read popularity value after every read operation or at every moment. Instead, the processor 211 delays and aggregates these calculation tasks, performing a unified, batch processing on all currently cached target address image information and their corresponding target logical address ranges at the end of each preset statistical period. This batch processing includes both an update step that increases the popularity of ranges that meet the conditions and a decay processing step that decreases the popularity of all ranges. In this way, a large amount of computation is concentrated and completed all at once at the end of the period, thereby minimizing the performance impact of popularity management tasks on the real-time data access path and ensuring the response stability of the storage device 20 under high load.

[0078] In one embodiment employing a batch update mechanism, processor 211 implements an efficient batch decay algorithm based on statistical periods. In this embodiment, when a statistical period ends and batch decay processing needs to be performed, processor 211 first obtains the duration of the just-ended statistical period. Then, based on this duration and a preset decay factor, processor 211 calculates a uniform heat decay amount applicable to all cached items in this batch processing. For example, if the statistical period duration is 100 milliseconds and the decay factor is 0.01 points / millisecond, the calculated heat decay amount is 1 point. Finally, processor 211 performs an efficient batch operation, uniformly and comprehensively subtracting the calculated heat decay amount from the target read heat values ​​corresponding to all currently cached target address image information. The advantage of this algorithm is that the calculation of the heat decay amount is completely decoupled from the access history of any individual cached item, and is only related to the global period duration, thereby avoiding the overhead of traversing and querying the last access time of each cached item, greatly improving the computational efficiency of batch decay processing.

[0079] It is worth mentioning that, in another embodiment, in order to enable the heat decay mechanism to more intelligently adapt to the dynamic operating state of the storage device 20, the processor 211 is also configured to dynamically adjust the decay factor used to calculate the heat decay amount according to preset adjustment conditions. By adjusting the decay factor, the processor 211 can control the speed at which data in the cache "cools down," thereby optimizing the caching strategy in different scenarios.

[0080] The adjustment conditions may include one or a combination of one or more of the following: the current system load of storage device 20, cache hit rate, and data write frequency.

[0081] In one specific implementation, processor 211 monitors the length of its internal command processing queue as an indicator of the current system load. When processor 211 detects that the system load remains high, it indicates that system resources are strained. At this time, processor 211 can appropriately increase the decay factor. A larger decay factor will accelerate the decay of all cached items, allowing non-core hot data to be evicted more quickly, thereby freeing up cache space for new, potentially more important hot data.

[0082] In another specific implementation, processor 211 will statistically analyze recent cache hit rates. If processor 211 finds that the cache hit rate has been declining continuously over a period of time, it may mean that the data in the current cache deviates from the actual user access patterns. In response, processor 211 can increase the decay factor to accelerate the "refreshing" of cache content, eliminating old hotspots that may have become obsolete, and improving cache adaptability.

[0083] Furthermore, the processor 211 can also monitor the data write frequency. Under a write-intensive workload, the data and address mapping relationship in the memory module 220 may change frequently. In this case, the processor 211 can increase the decay factor to reduce the residence time of address image information that may soon become invalid in the cache, thus avoiding cache pollution. Conversely, in read-intensive scenarios with stable data, the processor 211 can decrease the decay factor, allowing effective hot data to remain in the cache for a longer time, thereby maximizing the gain in read performance. Through this multi-dimensional dynamic adjustment mechanism, the decay strategy of this disclosure is no longer immutable, but rather an intelligent system capable of self-optimization based on system behavior.

[0084] Figure 6 The flowchart illustrates a batch heat update and decay based on a statistical period, as shown in an embodiment of the present invention.

[0085] Reference Figure 6First, after each statistical cycle ends, in step S610, the processor 211 starts a traversal process to obtain the number of reads accumulated in the just-ended statistical cycle for each currently cached target logical address range.

[0086] Next, for each target logical address range traversed, the process proceeds to step S620. Processor 211 calculates the ratio of the number of reads of that range to the current first preset threshold. This step aims to quantify the access intensity of that range within this cycle.

[0087] Subsequently, in step S630, the processor 211 obtains a heat increment based on the ratio calculated in step S620, and uses this increment to update the read heat value for that range. For example, the ratio can be directly added to the current read heat value as an increment. It is worth noting that in some implementations, if the number of reads has not reached a first preset threshold, the heat increment in this step can be zero or skipped.

[0088] After completing the heat increase processing, the process proceeds to step S640. The processor 211 reduces the read heat value after the heat increase processing based on the heat decay amount corresponding to each statistical period. This heat decay amount can be calculated based on the duration of the statistical period and a preset decay factor. By combining the item-by-item processing of heat increase with the batch processing of heat decay, this embodiment can optimize the utilization of system resources while ensuring the accuracy of heat management. In other words, through... Figure 6 The process method allows the processor 211 to uniformly decay each cached data according to the passage of time, so as to avoid the resource consumption caused by frequent calculation of access time difference.

[0089] It should be noted that, in one embodiment, after completing the heat update and decay processing for all cached ranges, the processor 211 will also reset the read count field used for statistics, for example, by clearing it to zero, in order to prepare for the next new statistical cycle.

[0090] Figure 8 The diagram illustrates the change in read popularity value over time and access frequency, as shown in an embodiment of the present invention.

[0091] Reference Figure 8 , Figure 8 It describes the entire process of a target logical address range changing dynamically from being cached to its read popularity value.

[0092] For example, at time point T1, as shown by arrow A81, a target address image is cached. At this time, processor 211 sets an initial read heat value HV1 for its corresponding target logical address range, as shown by point P1.

[0093] Between time points T1 and T3, two statistical cycles (ΔT) occurred. During these two cycles, the target logical address range was continuously read at a high frequency. Therefore, at the end of each cycle (time points T2 and T3), the processor 211 performed calculations with increased heat.

[0094] Specifically, at time point T2, after the first statistical period, the read popularity value within this range increases from point P1 (read popularity value HV1) before the update to point P21 (read popularity value HV21). The increase in read popularity value (HV21 – HV1) is calculated based on the ratio of the number of high-frequency reads within this period (T2-T1) to a first preset threshold. The difference in popularity between point P21 and point P22 (read popularity value HV22) (HV21 – HV22) reflects the decrease in popularity that occurred during this period.

[0095] Similarly, at time point T3, after the second statistical period, the read popularity value in this range increases from point P22 (read popularity value HV22) to point P31 (read popularity value HV31). The increase in read popularity value (HV31 – HV22) is calculated based on the ratio of the number of high-frequency reads within this period (T3-T2) to a first preset threshold. The difference in popularity between point P31 and point P32 (HV31 – HV32) reflects the decrease in popularity that occurs within this period.

[0096] However, during the statistical period from time T3 to T4, this target logical address range is no longer read frequently. Therefore, at time T4, when processor 211 performs a batch update, this range cannot effectively increase its read heat value because the read count condition is not met, such as at point P41 (read heat value HV41 = HV32). The heat difference (HV41 – HV42) between point P41 and point P42 (read heat value HV42) reflects the heat decay that occurs in this period. It should be noted that the read heat value (HV42) of the final update at time T4 is significantly smaller than the read heat value (HV32) of the final update at time T3. This phenomenon indicates that this mechanism can effectively decay read heat values ​​that do not increase heat.

[0097] pass Figure 8 The mechanism shown in this disclosure implements a dynamic heat management method that can sensitively reflect changes in access frequency and combines periodic increases with continuous decreases.

[0098] Back Figure 2 Finally, in step S240, when the target read heat value is lower than the heat value lower limit, the processor 211 removes the cached target address image information.

[0099] This step defines the basic triggering conditions for cache eviction. For example, the lower limit of the hot access value can be set to 0. When a cached address image is not frequently accessed for a long time, causing its target read hot value to continuously decay and eventually reach the lower limit, the processor 211 will initiate a reclamation process to remove it from the cache, thereby freeing up valuable cache resources for new hot data.

[0100] In another embodiment, not only can the first preset threshold for determining cache admission and the decay factor for calculating the amount of heat decay be dynamically adjusted, but the lower limit of the heat value used to determine whether to remove a cache item can also be adaptively adjusted by the processor 211. By dynamically adjusting the lower limit of the heat value, the cache eviction policy of this disclosure can more flexibly respond to different system resource conditions and performance goals.

[0101] Specifically, processor 211 can adjust the lower limit of the heat value based on the current available space rate of the cache memory. For example, the system can set a default lower limit of the heat value to 0. When processor 211 detects that the available space of the cache memory is below a warning level (e.g., below 20%), it indicates that cache resources are becoming strained. At this time, processor 211 can temporarily and moderately increase the lower limit of the heat value, for example, by adjusting it from 0 to 2.

[0102] This adjustment will have a direct technical effect: those "mild" cached items with a popularity value between 1 and 2 will be immediately identified as meeting the eviction criteria under the new lower limit standard, and thus be reclaimed more quickly. This is equivalent to tightening the "eviction" threshold when resources are scarce, accelerating the clearing of low-value cached items, and thus quickly freeing up some valuable cache space for the system.

[0103] Conversely, when the processor 211 detects that the available space in the cache memory is very ample (e.g., above 80%), it can restore the lower limit of the hotness value to the default 0, or even a lower value (if negative hotness is supported). This is equivalent to relaxing the eviction criteria, allowing more data, even data with low hotness, to remain in the cache for a longer period to handle occasional access requests. In this way, the dynamic adjustment mechanism of the lower limit of the hotness value enables the cache eviction policy to achieve a finer balance between system performance and resource utilization based on the environment (resource status).

[0104] Figure 7 The diagram illustrates a bottom-up update of heat values ​​using a binary tree structure, as shown in an embodiment of the present invention.

[0105] Reference Figure 7 and Figure 9 In another embodiment, in order to efficiently manage the heat information of a large range of logical addresses, the processor 211 employs a data structure that combines a hash table and a binary tree.

[0106] First, the processor 211 further divides the multiple logical address ranges corresponding to the entire storage space into multiple sub-regions of preset size with smaller granularity. Then, the processor 211 uses a hash table (whose logical structure can be shown as a heat information table HVT) to store and look up detailed status information corresponding to these sub-regions, such as the number of reads and the read heat value. The advantage of the hash table lies in its efficient lookup performance. When a read request arrives, the processor 211 can quickly locate the sub-region entry to which the logical address belongs in the hash table by calculating the hash function based on the logical address corresponding to the request, and directly update its read count or read heat value without performing a time-consuming traversal search.

[0107] Building upon this, the processor 211 also uses a binary tree structure to maintain the hierarchical relationships between these sub-regions, thereby enabling aggregated management of heat information. For example... Figure 7 As shown, the leaf nodes of the binary tree (e.g., C11, C12, C21, C22) correspond one-to-one with the sub-regions stored in the hash table. The value of each parent node in the binary tree (e.g., P1, P2) is the result of a specific function operation on the read popularity values ​​of all its sub-regions, such as the sum of the popularity values ​​of its child nodes. In this way, the value of each parent node can represent the aggregate popularity of a larger granularity logical address range consisting of multiple sub-regions. For example, the popularity value of parent node P1 (popularity value: 80) is the sum of the popularity values ​​of its child nodes C11 (popularity value: 50) and C12 (popularity value: 30).

[0108] A key feature of this binary tree structure is its bottom-up update mechanism. When the read popularity value of a sub-region in the hash table is updated—for example, as shown by arrow A71, the popularity value of sub-region C11 changes from 50 to 60—this change triggers a cascading update. As shown by arrows A72, A73, and A74, processor 211 recalculates and updates the values ​​of all parent nodes along the path from the bottom up based on the updated read popularity value of sub-region C11. Specifically, the value of parent node P1 is recalculated to 90 (60+30) based on its new child node popularity values, and the value of root node R1 is updated accordingly to 140 (90+50). Through this collaborative work of the hash table and the binary tree, processor 211 can not only achieve fast single-point updates of fine-grained region popularity but also efficiently generate and maintain popularity views with different aggregation granularities, providing data support for more complex cache management and prefetching strategies.

[0109] It should be noted that, in one embodiment, after each preset decay period, the processor 211 halves the read heat value of each sub-region to simplify the complexity of the decay operation.

[0110] It is worth mentioning that the connection relationships between child nodes and parent nodes, as well as between the root node and parent node, can be pre-configured into different forms according to requirements. To achieve differentiated and refined heat monitoring of different types of data regions, this disclosure provides a configurable tree-like heat aggregation scheme. In this scheme, the processor 211 does not use a fixed binary tree structure, but rather dynamically constructs a tree structure to maintain hierarchical relationships based on preset configuration information.

[0111] Specifically, processor 211 can load a "hot tree configuration table" from memory module 220 or host system 10. This configuration table defines in detail the tree's topology and the mapping relationship between leaf nodes and logical address sub-regions. For example, the configuration table may include the following information:

[0112] 1. Node definition: Define each node in the tree (including leaf nodes and parent nodes).

[0113] 2. Parent-child relationship definition: Clearly identify the parent node of each node, thus constructing the connection relationship of the tree. This relationship is not limited to binary; a parent node can have any number of child nodes.

[0114] 3. Leaf node mapping: For each leaf node, define one or more sub-regions corresponding to it. These sub-regions can even be non-contiguous in logical address.

[0115] By loading and parsing this configuration table, processor 211 can construct a highly customized, potentially asymmetric, tree structure.

[0116] For example, suppose storage device 20 stores both operating system metadata and large user video files. The metadata area, though small, is critically accessible; while the video file area is vast and typically accessed sequentially. In this case, the following configuration information can be provided:

[0117] Create a parent node named "Metadata Popularity" with multiple leaf nodes attached to it. Each leaf node is precisely mapped to a very small metadata sub-region.

[0118] Create a parent node named "User Data Popularity" with only one leaf node attached to it. However, this leaf node maps to a very large, contiguous logical address range that covers the entire video file.

[0119] In this way, the processor 211 can aggregate the heat of data of different natures at different monitoring granularities based on the logical state of the data, thereby obtaining a multi-level heat view that more accurately reflects the actual operating status of the system. This configurability provides novel flexibility for storage system optimization, enabling heat management strategies to adapt to different types of workloads, thereby optimizing memory usage and computational overhead while obtaining more accurate heat analysis results.

[0120] On the other hand, in another embodiment, the processor 211 utilizes the heat values ​​of nodes at different levels (leaf nodes, parent nodes, root nodes) in the binary tree structure to implement a hierarchical and efficient cache management decision-making process.

[0121] Specifically, firstly, the processor 211 can use the root node's heat value as a regulator of the global caching strategy. The root node's heat value reflects the overall access intensity of the entire storage device 20. The processor 211 can set a "system heat state threshold." When the root node's heat value exceeds this threshold, it indicates that the system is in a high IOPS (Input / Output Operations Per Second) "active period." At this time, the processor 211 can automatically and globally increase the first preset threshold used for cache admission, or increase the heat decay factor, to adapt to this high-intensity access pattern. Conversely, when the root node's heat value is very low, the relevant parameters can be relaxed. By monitoring this single value of the root node, the processor 211 can achieve macroscopic control of the "tightness" of the entire caching system without analyzing tens of thousands of leaf nodes.

[0122] In another embodiment, processor 211 can also utilize the heat value of parent nodes to perform regional, coarse-grained caching or prefetching decisions. For example, when the heat value of a parent node becomes very high, even if some of its leaf nodes (child regions) are not yet hot, the high heat of this parent node strongly suggests that the entire logical address range it represents is a "hot zone." Based on this "regional feedback," processor 211 can make more advanced decisions:

[0123] 1. Regional caching: Instead of caching address image information of individual sub-regions in a scattered manner, this method decides to cache the entire range of address image information represented by the parent node all at once. This can significantly reduce cache management overhead and improve the overall cache hit rate for scenarios such as sequential reading of large files.

[0124] 2. Intelligent Prefetching: When the temperature of a leaf node (e.g., C11) under a parent node increases sharply, processor 211 can check the temperature of its parent node (P1). If the temperature of parent node P1 is also high, this indicates that access to that region exhibits strong spatial locality. Therefore, processor 211 can make a high-confidence prefetching decision, proactively loading the address image information of C11's sibling node (C12) into the cache in advance, thereby "predicting" the host's next read behavior and further improving performance.

[0125] Finally, the heat value of the leaf nodes is used to perform the most granular, regular cache admission and eviction decisions.

[0126] Through the above approach, processor 211 establishes a three-tiered decision-making system, from macroscopic (root node) to regional (parent node) and then to microscopic (leaf node). This hierarchical management method greatly simplifies the decision-making logic, enabling processor 211 to perform the most efficient management actions at different granularities based on information from different levels, thereby achieving the best balance between cache performance and management overhead under complex access patterns.

[0127] Figure 9 The data structure diagram of the heat information table shown in one embodiment of the present invention is illustrated.

[0128] Reference Figure 9 In order to implement the memory management method of this disclosure, the processor 211 may establish and maintain one or more data structures similar to the heat information table HVT in its internal buffer memory 214 or host memory 120.

[0129] like Figure 9 As shown, the HVT (Heat Values) table can contain multiple entries, each corresponding to a monitored logical address range (specifically represented as HPB region ID in the diagram). Each entry contains multiple fields to record the dynamic status information of that logical address range.

[0130] Specifically, these fields may include:

[0131] The "HPB Region ID" field is used to uniquely identify a logical address range, such as HPB1, HPB2, and HPB3.

[0132] The "Read Count" field records the cumulative number of reads for this region within the current statistical period, such as RC1, RC2, and RC3. This field is the basic data for determining whether caching is triggered and for updating popularity.

[0133] The "Read Popularity Value" field records the current quantized popularity value of this region, such as HV1, HV2, and HV3. This field is the core basis for this disclosure to prioritize caches and make eviction decisions.

[0134] The "Cache Status" field records the current caching stage of this area. For example, different codes can be used to represent it: "01" represents that the corresponding address image information is "cached"; "10" represents "not cached"; and "00" represents "reclaimed", that is, it was once cached but has now been evicted.

[0135] The "Access Time" field records the timestamp of the most recent access to this area, such as ACT1, ACT2, and ACT3. This field is a key input for performing time-based decay processing.

[0136] By continuously and in real-time updating these fields in the HVT (Hotness Information Table), the processor 211 can fully grasp the historical and current status of each logical address range, thereby providing accurate and complete data support for a series of complex management decisions such as cache admission, hotness update, dynamic decay, and intelligent eviction as disclosed in this disclosure.

[0137] It is worth mentioning that, in one embodiment, this disclosure provides an intelligent eviction mechanism when buffer memory resources are scarce. After the storage device 20 has been running at high intensity for a long time, the storage space of the buffer memory may become insufficient. At this time, even if the popularity value of many cached items has not yet dropped to the lower limit of popularity value, the processor 211 must actively select one or more cached items with the lowest current value to remove in order to free up space.

[0138] To make the optimal decision, processor 211 executes a comprehensive evaluation process to determine the removal priority of each cached target address image. This evaluation considers three key dimensions: First, the current target read heat value of its corresponding target logical address range; the lower the heat value, the higher the priority. Second, the number of reads in the most recent statistical period; the fewer the reads, the higher the priority. Finally, the residence time of the target address image itself in the cache memory, i.e., the time elapsed since it was cached; the longer the residence time, the lower the probability of it being accessed recently, and the higher the removal priority.

[0139] In a specific implementation, processor 211 can calculate an eviction priority score for each cache entry, for example, using a weighted formula: "Score = (W1 / Hotness Value) + (W2 / Number of Reads) + (W3 / Number of Reads) + (W4 / Number of Reads) + (W5 / Number of Reads) + (W6 / Number of Reads) + (W7 / Number of Reads) + (W8 / Number of Reads) + (W9 / Number of Reads) + (W1 / Number of Reads) + (W1 / Number of Reads) + (W2 ...1 / Number of Reads) + (W1 / N "Station time", where W1, W2, and W3 are different preset weighting factors. The processor 211 will select the item with the highest score for elimination.

[0140] Through this multi-dimensional comprehensive evaluation, the processor 211 can avoid the limitation of traditional LRU algorithms that rely solely on time, ensuring that even when forced eviction is necessary, high-value data that is frequently accessed and has been frequently accessed recently can be retained first, thereby minimizing the impact of forced eviction on system performance.

[0141] In addition to the primary eviction criterion of having a popularity value below a lower limit, this disclosure also provides an auxiliary eviction criterion based on access frequency to clean up cached items that have been in a "half-hot" state for a long time.

[0142] Specifically, in another embodiment, the processor 211 sets a relatively low second preset threshold, such as 10 times, as the minimum access frequency threshold for determining whether a cached item still has value. During batch updates at the end of each statistical period, the processor 211 checks each cached target logical address range to obtain its other read count within that statistical period. If the processor 211 finds that the other read count for a target logical address range is consistently lower than this second preset threshold, it can classify it as "zombie" data or "cold" data with extremely low access value.

[0143] In this scenario, even if the target read popularity value of the logical address range has not yet reached the lower limit due to slow decay, the processor 211 can still make a proactive eviction decision, directly removing the corresponding cached target address image information. This mechanism effectively prevents cache entries with extremely low access frequency but insufficient to quickly reduce their popularity from occupying cache space for extended periods, further improving cache space utilization efficiency and liquidity.

[0144] It should be noted that in a specific application scenario, such as Figure 1 As shown, the buffer memory associated with storage device 20 can be configured within the host system 10, for example, using a portion of host memory 120 as cache space. This architecture is widely used in the HPB (Host Performance Enhancer) feature of the UFS standard.

[0145] In this master-slave cache architecture, although the memory controller 210 is responsible for executing all cache management algorithms (including admission, hot update, eviction decisions, etc.), it does not have direct physical access to the host memory 120. Therefore, when the processor 211 determines that a cached target address image needs to be removed according to the method of this disclosure (e.g., because the hot value is below the lower limit, or other eviction conditions are met), the removal step includes an interaction process with the host system 10.

[0146] Specifically, processor 211 sends a clear request to host system 10 via connection interface circuit 230 and data transmission interface circuit 130. This clear request includes identifiers related to the target address image information to be removed. Upon receiving the clear request, the processor 110 or its driver in host system 10 performs corresponding operations, releasing or marking the corresponding cache space in host memory 120 as invalid, thus completing the removal operation. Through this request-response mechanism, the method of this disclosure is compatible with and applicable to master-slave cache system architectures.

[0147] In another embodiment, to enhance the flexibility and configurability of the memory management method disclosed herein, the processor 211 also maintains a global configuration table in the buffer memory 214. This global configuration table centrally stores multiple adjustable parameters upon which the method relies, such as the base threshold and load factor weights used to calculate the dynamic threshold, the initial heat value, the base decay factor, and the second preset threshold for eviction. By configuring these parameters, the manufacturer or system integrator of the storage device 20 can easily fine-tune the behavior of the cache management algorithm according to different hardware specifications or application scenarios without modifying the core firmware code. When the processor 211 performs dynamic adjustments (e.g., adjusting the first preset threshold based on system load, or adjusting the decay factor based on cache hit rate), its specific operation is to update the corresponding values ​​in this global configuration table.

[0148] This embodiment also provides a computer program product, including computer-readable code or a non-volatile computer-readable storage medium carrying computer-readable code. When the computer-readable code is executed in a processor, the processor performs the steps of the memory management method described above. This computer program product can be implemented specifically through hardware, firmware, software, or a combination thereof. In one optional embodiment, the computer program product is specifically embodied as a computer storage medium; in another optional embodiment, the computer program product is specifically embodied as a software product, such as a software development kit (SDK), etc.

[0149] In summary, the memory management method and memory controller provided in this disclosure effectively solve the problems of rigid caching strategies and low resource utilization in existing technologies by constructing a multi-dimensional, adaptive heat management mechanism. This disclosure not only ensures the effectiveness of cache admission by statistically analyzing read counts, but more importantly, it introduces a quantitative heat update method based on the relationship between read counts and preset thresholds, making cache priority management more precise. Furthermore, by combining dynamic threshold adjustment based on system load, heat decay based on access time or period, and a multi-dimensional comprehensive eviction strategy, the cache management system of this disclosure can intelligently adapt to dynamically changing workloads, ensuring that limited cache resources always serve the most valuable data at present. Ultimately, this disclosure can improve cache hit rate and accelerate data access speed while reducing unnecessary cache management overhead, thereby comprehensively improving the overall performance of the storage device and the user experience.

[0150] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and not to limit them; although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this disclosure.

Claims

1. A memory management method applied to a memory controller, the memory controller being used to control a storage device configured with a memory module, characterized in that, The method includes: Within a statistical period, the number of reads for each logical address range in the multiple logical address ranges within the storage device is counted. Based on the number of reads for each logical address range, a target logical address range is determined, and target address image information corresponding to the target logical address range is cached. Based on a first preset threshold and another number of reads of the target logical address range after the target address image information is cached, update the target read heat value corresponding to the target logical address range.

2. The method according to claim 1, characterized in that, The step of determining the target logical address range based on the number of reads for each logical address range, and caching the target address image information corresponding to the target logical address range, includes: The logical address range that reaches the first preset threshold number of reads is determined as the target logical address range; The target address image information of the target logical address range is cached in a buffer memory associated with the storage device.

3. The method according to claim 1, characterized in that, The method further includes: Adjust the first preset threshold based on the current system load of the storage device.

4. The method according to claim 1, characterized in that, The method further includes: Calculate the ratio of the other read count to the first preset threshold, wherein the other read count corresponds to another statistical period after the target address image information is cached; and Based on the ratio, the heat increment is obtained and the heat increment is added to the current target read heat value to update the target read heat value.

5. The method according to claim 1, characterized in that, The method further includes: Based on the access time information of the target address image information, the target read popularity value is attenuated.

6. The method according to claim 5, characterized in that, The access time information is the last access time of the target logical address range, and the step of attenuating the target read heat value based on the access time information associated with the cached target address image information includes: Calculate the heat decay amount based on the time interval between the current time and the last access time and the preset heat decay rate; and Subtract the heat decay amount from the target heat value.

7. The method according to claim 5, characterized in that, The steps of updating the target read heat value and the steps of attenuating the target read heat value are performed in batches at the end of each statistical period for all cached target address image information and their corresponding target logical address ranges.

8. The method according to claim 7, characterized in that, The step of performing the attenuation processing on the target read heat value includes: Obtain the duration of the statistical period; Calculate the heat decay based on the duration and a preset decay factor; and Subtract the aforementioned heat decay amount from the target read heat values ​​corresponding to all cached target address image information.

9. The method according to claim 8, characterized in that, The method further includes: The attenuation factor is adjusted according to preset adjustment conditions; The adjustment conditions mentioned above include one or more of the following: The current system load of the storage device; Cache hit rate; and Data write frequency.

10. The method according to claim 1, characterized in that, The method further includes: Hash tables are used to store and look up the number of reads and read popularity values ​​corresponding to the multiple logical address ranges, respectively. The step of updating the target read popularity value includes: updating the read popularity value of the corresponding sub-region in the hash table according to the logical address corresponding to each read request.

11. The method according to claim 10, characterized in that, The method further includes: The plurality of logical address ranges are divided into a plurality of sub-regions of a preset size; A binary tree structure is used to maintain the hierarchical relationship between the multiple sub-regions, generating parent nodes that represent the aggregated heat of logical address ranges at different granularities, wherein each parent node value is the result of a specific function operation on the read heat values ​​of all its contained sub-regions; and After the read popularity value of the sub-region is updated, the values ​​of all parent nodes are recalculated and updated from bottom to top based on the updated read popularity value of the sub-region.

12. The method according to claim 11, characterized in that, The method further includes: After each preset decay period, the read heat value of each sub-region is halved.

13. The method according to claim 1, characterized in that, When the buffer memory is insufficient, the method further includes: The removal priority of the target address image information is determined based on the target read heat value and the other read count of the target logical address range corresponding to each cached target address image information, as well as the residence time of the target address image information in the buffer memory.

14. The method according to claim 1, characterized in that, The method further includes: When the number of reads for the target logical address range is less than a second preset threshold, the cached target address image information is removed; or, When the target read popularity value is lower than the lower limit of popularity value, the cached target address image information is removed.

15. The method according to claim 1, characterized in that, The buffer memory is configured in the host system, and the step of removing the cached target address image information includes: A clear request is sent to the host system so that the host system removes the target address image information from the buffer memory.

16. A memory controller for controlling a storage device configured with a memory module, characterized in that, The memory controller includes: A memory interface control circuit, for electrically connecting to the memory module; and A processor, electrically connected to the memory interface control circuit, wherein the processor is configured to: Within a statistical period, the number of reads for each logical address range in the multiple logical address ranges within the storage device is counted. Based on the number of reads for each logical address range, a target logical address range is determined, and target address image information corresponding to the target logical address range is cached. After the target address image information is cached: Based on a first preset threshold and another number of reads of the target logical address range after the target address image information is cached, update the target read heat value corresponding to the target logical address range; and When the target read popularity value is lower than the lower limit of popularity value, the cached target address image information is removed.

17. The memory controller according to claim 16, characterized in that, The processor is also configured to: Adjust the first preset threshold based on the current system load of the storage device.

18. The memory controller according to claim 16, characterized in that, The step of configuring the processor to update the target read heat value includes: Calculate the ratio of the other number of reads to the first preset threshold; and Based on the ratio, the heat increment is obtained, and the heat increment is added to the current target read heat value.

19. The memory controller according to claim 16, characterized in that, The processor is configured to update the target read heat value and to perform a decay process step, which is performed in batches at the end of each statistical period for all cached target address mapping information and their corresponding target logical address ranges.

20. The memory controller according to claim 16, characterized in that, The memory controller also includes a buffer memory configured to store hash tables and binary tree structures; The processor is further configured to: The multiple logical address ranges are divided into multiple sub-regions, and the hash table is used to store and look up the read popularity values ​​corresponding to the sub-regions respectively. as well as The binary tree structure is used to maintain the hierarchical relationship between the sub-regions to generate parent nodes that represent the aggregation heat of logical address ranges at different granularities. Furthermore, after the read popularity value of the sub-region is updated, the values ​​of all parent nodes are recalculated and updated from the bottom up.

Images