First-in first-out device, control method thereof and chip

Abstract

The invention relates to a first-in first-out device, a control method thereof and a chip. The first-in first-out device comprises a read interface module, a control module and a memory, the control module obtains a current sequential read address according to values of a plurality of bits in the occupation vector data structure, controls the memory to read read data from a corresponding storage address according to the current sequential read address, and updates the occupation vector data structure after reading the read data; the occupancy vector data structure comprises a plurality of bits in one-to-one correspondence with a plurality of storage addresses of the memory, and each bit indicates whether the corresponding storage address can be sequentially read or not; the read interface module sends the read data and the current sequential read address to downstream equipment; and the read interface module also receives a read-back enable signal and a read-back address input by the downstream equipment, reads corresponding read-back data from the memory according to the read-back enable signal and the read-back address, and sends the read-back data to the downstream equipment. According to the method and the device, the backward reading of the historical data of the first-in first-out device can be realized, and the hardware cost and the area of the first-in first-out device are reduced.

Description

Technical Field

[0001] This application relates to the field of First In First Out (FIFO) structure technology, specifically to a FIFO device and its control method and chip. Background Technology

[0002] First-In-First-Out (FIFO) devices are commonly used circuit structures in modern digital circuits. Their core function is to sequentially store and retrieve data, ensuring the timing consistency of the data stream. Figure 1 As shown, unlike traditional memory (such as RAM), FIFO does not require external address lines to control the read and write positions. Instead, it manages data by automatically incrementing the internal read and write pointers. This feature makes it widely used in scenarios involving cross-clock data transmission, data caching, and data bit width matching.

[0003] The current circuit structure of FIFOs that support readback is as follows: Figure 2 As shown, Figure 2 The FIFO achieves readback functionality by introducing redundant hardware resources. It copies a complete data copy (Copy Memory Array) of the data cached in the dual-port RAM (Dualport Memory Array) for readback, resulting in a storage resource consumption increase of over 200%, higher hardware costs, and a larger FIFO area. At the same time, since the Copy Memory Array is only a snapshot of the Dualport Memory Array, its readback timeline is short. When all the data inside the Dualport Memory Array is read out, the original data will be overwritten. At this point, it is impossible to read back the data before it was overwritten. Summary of the Invention

[0004] The purpose of this application is to propose a first-in-first-out (FIFO) device and its control method and chip, so as to realize the reading back of historical data of the FIFO device and reduce the hardware cost and area of ​​the FIFO device.

[0005] To achieve the above objectives, according to the first aspect of this application, a first-in-first-out (FIFO) device is proposed, comprising a read interface module, a control module, and a memory; The control module is used to obtain the current sequential read address based on the values ​​of multiple bits in the occupancy vector data structure, control the memory to read data from the corresponding memory address based on the current sequential read address, and update the occupancy vector data structure after reading the data; wherein, the occupancy vector data structure includes multiple bits that correspond one-to-one with multiple memory addresses, and each bit is used to indicate whether the corresponding memory address can be read sequentially; The read interface module is used to send the read data and the current sequential read address to the downstream device; The read interface module is also used to receive a readback enable signal and a readback address input by the downstream device, read the corresponding readback data from the memory according to the readback enable signal and the readback address, and send the readback data to the downstream device.

[0006] In some embodiments, the first-in-first-out device further includes a write interface module; The write interface module is used to receive the write enable signal and the data to be written from the upstream device; The control module is further configured to obtain the current write address based on the values ​​of multiple bits in the empty vector data structure according to the write enable signal, and control the memory to write the data to be written to the memory address corresponding to the current write address; wherein, the empty vector data structure includes multiple bits that correspond one-to-one with multiple memory addresses, and each bit is used to indicate whether the corresponding memory address is occupied.

[0007] In some embodiments, the read interface module is used to cache the read data and the current sequential read address, and when it receives a sequential read enable signal sent by a downstream device, it sends the read data and the current sequential read address to the downstream device.

[0008] In some embodiments, the read interface module is further configured to receive a release address input by the downstream device; The control module is also used to update the null vector data structure according to the release address.

[0009] In some embodiments, the control module includes a control unit, an occupancy vector data structure, and a read vector to address unit; The control unit is used to query the occupancy vector data structure to obtain the next bit that indicates the corresponding storage address can be read sequentially, and to obtain the current sequential read vector in one-hot binary code format based on the next bit that indicates the corresponding storage address can be read sequentially; The read vector to address unit is used to convert the current sequential read vector in the one-hot binary code format into a current sequential read address in a preset format, and input the current sequential read address into the memory, so that the memory reads the read data from the corresponding memory address according to the current sequential read address; The control unit is also used to update the occupancy vector data structure after reading the read data.

[0010] In some embodiments, the control module further includes a write vector to address unit, an empty vector data structure, and a release address to redirection unit; The control unit is also used to query the empty vector data structure to obtain the next unoccupied bit, and obtain the current write vector in one-hot binary code format based on the next unoccupied bit; The write vector to address unit is used to convert the current write vector in the one-hot binary code format into the current write address in a preset format, and input the current write address into the memory so that the memory writes the data to be written to the corresponding memory address according to the current write address; The release address redirection unit is used to convert the preset format release address into a one-hot binary code format release vector; The control unit is used to update the null vector data structure according to the release vector.

[0011] In some embodiments, the control unit is further configured to send a memory full signal to the upstream device according to the empty vector data structure, and to send a memory empty signal to the downstream device according to the occupied vector data structure.

[0012] According to a second aspect of this application, a control method for a first-in-first-out (FIFO) device is proposed, wherein the FIFO device includes a read interface module, a control module, and a memory. The control method includes: The control module obtains the current sequential read address based on the values ​​of multiple bits in the occupancy vector data structure, controls the memory to read data from the corresponding memory address based on the current sequential read address, and updates the occupancy vector data structure after reading the data; wherein, the occupancy vector data structure includes multiple bits that correspond one-to-one with multiple memory addresses, and each bit is used to indicate whether the corresponding memory address can be read sequentially; The read interface module sends the read data and the current sequential read address to the downstream device; The read interface module receives the readback enable signal and readback address input by the downstream device, reads the corresponding readback data from the memory according to the readback enable signal and readback address, and sends the readback data to the downstream device.

[0013] In some embodiments, the first-in-first-out device further includes a write interface module; The control method further includes: The write interface module receives the write enable signal and the data to be written from the upstream device; The control module obtains the current write address based on the values ​​of multiple bits in the empty vector data structure according to the write enable signal, and controls the memory to write the data to be written to the memory address corresponding to the current write address; the empty vector data structure includes multiple bits that correspond one-to-one with multiple memory addresses, and each bit indicates whether the corresponding memory address is occupied.

[0014] In some embodiments, the control method includes: The read interface module caches the read data and the current sequential read address, and sends the read data and the current sequential read address to the downstream device when it receives the sequential read enable signal sent by the downstream device. The read interface module receives the release address input by the downstream device; The control module updates the null vector data structure according to the release address.

[0015] According to a third aspect of this application, a chip is proposed that includes the first-in-first-out device described in the first aspect of this application.

[0016] The aforementioned first-in-first-out device, its control method, and the chip have the following beneficial effects: During sequential read operations, the occupancy vector data structure indicates which memory addresses can be read sequentially and which can be used for readback. The control module obtains the current sequential read address (i.e., the memory address where the next read data to be output to the downstream device is located) based on the values ​​of multiple bits in the occupancy vector data structure. Based on this current sequential read address, the control module reads the data from the corresponding memory address and updates the occupancy vector data structure after reading the data. The read interface module outputs the read data and the current sequential read address to the downstream external device. The downstream external device records the current sequential read address for subsequent readback to the FIFO device. When the downstream external device needs to read back historical data, it sends a readback enable signal and a readback address to the read interface module. The read interface module reads the corresponding readback data from the memory based on the readback enable signal and readback address and sends it to the downstream external device, thus realizing the historical data readback of the FIFO device. Compared to... Figure 2 Compared to conventional FIFOs that support readback functionality, the FIFO device of this application can significantly reduce the hardware cost and area of ​​the FIFO device because it does not require copying a complete data copy (Copy MemoryArray) of the data cached in the dual-port RAM (Dualport memory array) for readback. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings required in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a structural diagram of a traditional first-in-first-out (FIFO) device disclosed in the background art.

[0019] Figure 2 This is a structural diagram of the first-in-first-out device supporting readback disclosed in the background art.

[0020] Figure 3 This is a structural diagram of a first-in-first-out (FIFO) device according to an embodiment of this application.

[0021] Figure 4 This is a schematic diagram illustrating the application of a first-in-first-out (FIFO) device in an embodiment of this application.

[0022] Figure 5 This is a flowchart of a control method for a first-in-first-out (FIFO) device according to an embodiment of this application. Detailed Implementation

[0023] The detailed description of the accompanying drawings is intended to illustrate the present embodiments of this application and is not intended to represent only the forms in which this application can be implemented. It should be understood that the same or equivalent functions can be accomplished by different embodiments intended to be included within the spirit and scope of this application.

[0024] See Figure 2 One embodiment of this application provides a first-in, first-out (FIFO) device, including a read interface module, a control module, and a memory, wherein the memory may be a dual-port SRAM.

[0025] The control module obtains the current sequential read address based on the values ​​of multiple bits in the occupancy vector data structure, controls the memory to read read data from the corresponding memory address based on the current sequential read address, and updates the occupancy vector data structure after reading the read data. The occupancy vector data structure includes multiple bits that correspond one-to-one with multiple memory addresses. Each bit is used to indicate whether the corresponding memory address can be read sequentially. Specifically, the value of each bit in the occupancy vector data structure is 0 or 1. When any bit is 1, it indicates that the data at the memory address corresponding to that bit can be read sequentially. When any bit is 0, it indicates that the data at the memory address corresponding to that bit cannot be read sequentially. The control module determines the memory address corresponding to bit_n as the current sequential read address by finding the next bit with a value of 1 in the occupancy vector data structure. The control module manages the values ​​of multiple bits in the occupancy vector data structure according to the read and write operations of the memory.

[0026] The read interface module is also used to receive the read back enable signal and read back address input by the downstream device, read the corresponding read back data from the memory according to the read back enable signal and read back address, and send the read back data to the downstream device.

[0027] Specifically, as described above, during sequential read operations, the FIFO device in this embodiment, in addition to returning the read data to the downstream device, also returns the current sequential read address to the downstream device. Therefore, the downstream device records the current sequential read address. When it needs to read back the read data, it sends a read-back enable signal and a read-back address (i.e., the current sequential read address) to the read interface module of the FIFO device in this embodiment. The read interface module can input the read-back enable signal and the read-back address into the memory, read the corresponding read-back data from the memory, and send the read-back data to the downstream device. Specifically, when the read interface module receives the read-back data, it sends the read-back data to the downstream device. At this time, it is not necessary to send the address again, which is different from the sequential read operation.

[0028] During sequential read operations, the occupancy vector data structure indicates which memory addresses can be read sequentially and which can be used for readback. The control module obtains the current sequential read address (i.e., the memory address where the next read data to be output to the downstream device is located) based on the values ​​of multiple bits in the occupancy vector data structure. Based on this current sequential read address, the control module reads the data from the corresponding memory address and updates the occupancy vector data structure after reading the data. The read interface module outputs the read data and the current sequential read address to the downstream external device. The downstream external device records the current sequential read address for subsequent readback to the FIFO device. When the downstream external device needs to read back historical data, it sends a readback enable signal and a readback address to the read interface module. The read interface module reads the corresponding readback data from the memory based on the readback enable signal and readback address and sends it to the downstream external device, thus realizing the historical data readback of the FIFO device. Compared to... Figure 2 Compared to conventional FIFOs that support readback functionality, the FIFO device of this application can significantly reduce the hardware cost and area of ​​the FIFO device because it does not require copying a complete data copy (Copy Memory Array) of the data cached in the dual-port RAM (Dualport memory array) for readback.

[0029] In some embodiments, the first-in-first-out device further includes a write interface module.

[0030] The write interface module is used to receive the write enable signal and write data input from the upstream device. Specifically, in this embodiment, the upstream and downstream devices are defined based on the data flow direction. The device that writes data to the FIFO device is upstream in the data flow direction, and the device that receives the data output from the FIFO device is downstream in the data flow direction.

[0031] The control module is further configured to obtain the current write address based on the values ​​of multiple bits in the Empty Vector data structure according to the write enable signal, and control the memory to write the data to be written to the memory address corresponding to the current write address. The Empty Vector data structure includes multiple bits that correspond one-to-one with multiple memory addresses, each bit indicating whether the corresponding memory address is occupied. Specifically, the value of each bit in the Empty Vector data structure is 0 or 1. When any bit is 1, it indicates that the memory address corresponding to that bit is not occupied and data can be written. When any bit is 0, it indicates that the memory address corresponding to that bit is occupied and data cannot be written. The control module determines the memory address corresponding to bit_m by finding the next bit with a value of 1 in the Empty Vector data structure. The control module manages the values ​​of multiple bits in the Empty Vector data structure according to the read and write operations of the memory. The memory receives the write enable signal, the data to be written, and the current write address through different ports.

[0032] In some embodiments, the read interface module is used to cache the read data and the current sequential read address, and when it receives a sequential read enable signal sent by a downstream device, it sends the read data and the current sequential read address to the downstream device.

[0033] Specifically, it should be noted that in this embodiment, since the read data and the current read address are pre-registered in the read interface module, the read operation and the readback operation can be performed synchronously. That is, while sending the pre-registered read data and the current read address to the downstream device, the memory can normally output the readback data to the read interface module according to the readback address. The sequential read operation and the readback operation will not conflict, thus realizing the synchronous performance of the sequential read operation and the readback operation and reducing the readback latency.

[0034] In some embodiments, the read interface module is further configured to receive a release address input by the downstream device; specifically, the read interface module receives a sequential read enable signal, a read back enable signal, a read back address, and a release address through different ports. The control module is also used to update the empty vector data structure according to the release address; specifically, the control module determines that the bit in the empty vector data structure corresponding to the release address is bit_g, sets the value of bit_g to 1, indicating that bit_g is not occupied and can be written with data.

[0035] In some embodiments, the control module includes a control unit, an occupancy vector data structure, and a read vector to address unit; The control unit is used to query the occupancy vector data structure to obtain the next bit that indicates the corresponding storage address can be read sequentially, and to obtain the current sequential read vector in one-hot binary code format based on the next bit that indicates the corresponding storage address can be read sequentially (i.e., the next bit with a value of 1). Specifically, in one-hot binary code, at any given time, only one bit is "1" and all other bits are "0". For example, for four states, the one-hot code is represented as: 0001, 0010, 0100, 1000. The current sequential read vector includes the values ​​of multiple bits, of which only the bit corresponding to the current sequential read address has a value of 1, and the other bits have a value of 0. Assuming that the FIFO depth of this design is Max, then each vector is Max bits, and the pseudocode for maintaining the current sequential read vector is as follows: Read Vector <= {Read Vector[Max-i-1:0], Read Vector[Max-1: Max-i]}; Here, i is the lowest bit in Occupy Vector that is 1, starting from the bit that is 1 in Read Vector. For example, if Read Vector = 0b00000100 and Occupy Vector = 0b00110010, then i = 2.

[0036] The read vector to address unit is used to convert the current sequential read vector (ReadVector) in the one-hot binary code format into a current sequential read address (Read Address) in a preset format, and input the current sequential read address into the memory so that the memory reads the read data from the corresponding memory address according to the current sequential read address. Specifically, the preset format can be decimal, octal, hexadecimal, etc., and can be selected according to technical requirements. This embodiment does not impose a specific limitation. For example, when the vector 0b00001000 is received, it needs to be converted into the decimal address 3. The control unit is also used to update the occupancy vector data structure after reading the read data; specifically, the pseudocode for maintaining the occupancy vector is as follows: Occupy Vector<= (Occupy Vector | Write Vector)&(~Read Vector); In some embodiments, the control module further includes a write vector to address unit, an empty vector data structure, and a release address to redirection unit; The control unit is also used to query the empty vector data structure to obtain the next unoccupied bit (i.e., the next bit with a value of 1), and obtain the current write vector in one-hot binary code format based on the next unoccupied bit. Specifically, the current write vector includes the values ​​of multiple bits, of which only the bit corresponding to the current write address has a value of 1, and the values ​​of the remaining bits are 0. Assuming that the FIFO depth of this design is Max, then each vector is Max bits, and the pseudocode for maintaining the corresponding current write vector is as follows: Write Vector<= {Write Vector[Max-i-1:0], Write Vector[Max-1: Max-i]}; Here, i is the lowest bit in Empty Vector that is 1, starting from the bits that are 1 in Write Vector. For example, if Write Vector = 0b00000010 and Empty Vector = 0b11001001, then i=2.

[0037] The write vector to address unit is used to convert the current write vector in one-hot binary code format into a current write address in a preset format, and input the current write address into the memory so that the memory writes the data to be written into the corresponding memory address according to the current write address. Specifically, the preset format can be decimal, octal, hexadecimal, etc., which can be selected according to technical requirements. This embodiment does not impose a specific limitation. For example, when the vector 0b00001000 is received, it needs to be converted into the decimal address 3.

[0038] The release address redirection unit is used to convert the release address in the preset format into a release vector in one-hot binary code format. Specifically, the preset format can be decimal, octal, hexadecimal, etc., which can be selected according to technical requirements. This embodiment does not impose specific limitations. For example, when the vector 0b00001000 is received, it needs to be converted into the decimal address 3. The release vector includes multiple bit values, of which only the bit corresponding to the release address has a value of 1, and the other bits have a value of 0.

[0039] The control unit is used to update the empty vector data structure according to the release vector; specifically, the control unit finds the bit with a value of 1 in the release vector as bit_k, and sets the value of the bit corresponding to bit_k in the empty vector data structure to 1, so as to indicate that the release address is not occupied and data can be written; The pseudocode for maintaining an empty vector is as follows: Empty Vector<= (Empty Vector&(~Write Vector))| Release Vector.

[0040] In some embodiments, the control unit is further configured to send a memory full signal (Full) to the upstream device according to the Empty Vector data structure to notify the upstream device that it is currently unable to continue writing data to the FIFO device, and to send a memory empty signal (Empty) to the downstream device according to the Occupy Vector data structure to notify the downstream device that the FIFO device currently has no data to read.

[0041] Specifically, when the upstream device receives the memory full signal (Full), it will pause sending write operation requests to the FIFO device; when the downstream device receives the memory empty signal (Empty), it will pause sending read operation requests to the FIFO device. The pseudocode for the memory full signal (Full) is: Full=! (|Empty Vector); The pseudocode for the memory empty signal is: Empty = ! (|Occupy Vector).

[0042] For example, such as Figure 3As shown, the FIFO device in this embodiment is applied to an upper-level buffer module that implements AXI protocol transmission. This upper-level buffer module needs to implement data retransmission functionality (such as implementing the PCIe protocol's Retry function). Its specific workflow is as follows: At the start of operation, all vectors in the FIFO device will be initialized as follows (assuming the designed FIFO device has a depth of 8): EmptyVector = 0b1111 1111; OccupyVector = 0b0000 0000; WriteVector = 0b0000 0001; ReadVector = 0b0000 0000; Write Address = 0; Read Address = 0; Empty = 1; Full = 0; When an application needs to transmit data downstream via the AXI protocol, it first writes the data into the FIFO device. At this time, all vectors inside the FIFO device will become: EmptyVector = 0b1111 1110; OccupyVector = 0b0000 0001; WriteVector = 0b0000 0010; ReadVector = 0b0000 0001; Write Address = 1; Read Address = 0; Empty = 0; Full = 0; At this time, the written data will be immediately read into the read data and registered in the read interface module. At this time, the read data valid bit in the read interface module is set to 1, indicating that there is valid read data in the register of the read interface module. When the downstream AXI Master detects Empty=0, it understands that there is valid data in the FIFO device. When the AXI bus is idle, it can set the sequential read enable signal (Read Enable) to 1. At this time, the read interface module will detect Read DataValid=1, indicating that the current sequential read address (Read Address) and read data (Read Data) can be used immediately, and send the Read Address and Read Data to the downstream AXI Master.

[0043] After the AXI Master obtains the Read Address and Read Data, it can map the ReadAddress to an AWID using the Addr Map ID module. This example uses the Addr Map ID module to record the readback address; in practical applications, other technologies can be used. The Read Data is then sent downstream. After the AXI Master obtains the ReadAddress and Read Data, the internal states of the FIFO device are as follows: EmptyVector = 0b1111 1110; OccupyVector = 0b0000 0000; WriteVector = 0b0000 0010; ReadVector = 0b0000 0001 (The original value is retained because there is no valid data inside the FIFO). Write Address = 1; Read Address = 0; Empty = 1; Full = 0; The upstream device writes data again, and the internal state changes as follows: EmptyVector = 0b1111 1100; OccupyVector = 0b0000 0010; WriteVector = 0b0000 0100; ReadVector = 0b0000 0010; Write Address = 2; Read Address = 1; Empty = 0; Full = 0; Suppose that at this point, the AXI Master decides not to transmit the data. If the AXI Master encounters an error while sending the first piece of data and needs to retransmit it, the AXI Master maps the corresponding Read Address to be sent back based on the AXI BID, places it on the Read Back Address, and sets the Read Back Enable signal to 1. In the next cycle, the FIFO device will place the read-back data on the Read Back Data, and the AXI can then retransmit the data. Assuming the second AXI Master retransmission of data is successful, the AXI Master can now release the corresponding FIFO device space. The AXI Master can then map the corresponding Read Address using the AXI BID and place it at the Release Address. At this point, the internal states of the FIFO device become: EmptyVector = 0b1111 1101; OccupyVector = 0b0000 0010; WriteVector = 0b0000 0100; ReadVector = 0b0000 0010; Write Address = 2; Read Address = 1; Empty = 0; Full = 0.

[0044] like Figure 4 As shown, another embodiment of this application proposes a control method for the first-in-first-out device described in the above embodiments, the control method comprising the following steps: Step S10: The control module obtains the current sequential read address based on the values ​​of multiple bits in the occupancy vector data structure, controls the memory to read data from the corresponding memory address based on the current sequential read address, and updates the occupancy vector data structure after reading the data; wherein, the occupancy vector data structure includes multiple bits that correspond one-to-one with multiple memory addresses, and each bit is used to indicate whether the corresponding memory address can be read sequentially; Step S20: The read interface module sends the read data and the current sequential read address to the downstream device; In step S30, the read interface module receives the readback enable signal and readback address input by the downstream device, reads the corresponding readback data from the memory according to the readback enable signal and readback address, and sends the readback data to the downstream device.

[0045] In some embodiments, the first-in-first-out device further includes a write interface module; The control method further includes the following steps: Step S40: The write interface module receives the write enable signal and the data to be written from the upstream device. In step S50, the control module obtains the current write address based on the values ​​of multiple bits in the empty vector data structure according to the write enable signal, and controls the memory to write the data to be written to the memory address corresponding to the current write address; the empty vector data structure includes multiple bits that correspond one-to-one with multiple memory addresses, and each bit indicates whether the corresponding memory address is occupied.

[0046] In some embodiments, the control method further includes the following steps: Step S60: The read interface module caches the read data and the current sequential read address, and when it receives the sequential read enable signal sent by the downstream device, it sends the read data and the current sequential read address to the downstream device. Step S70: The read interface module receives the release address input by the downstream device; In step S80, the control module updates the null vector data structure according to the release address.

[0047] It should be noted that the content of the method in this embodiment corresponds to the FIFO device in the above embodiment. The content not described in detail in this embodiment can be obtained by referring to the FIFO device in the above embodiment, so it will not be described again in this embodiment.

[0048] Another embodiment of this application provides a chip including the first-in-first-out device described in the above embodiments.

[0049] The various embodiments of this application have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical applications, or technological improvements to the embodiments in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A first-in, first-out (FIFO) device, characterized in that, It includes a read interface module, a control module, and a memory; The control module is used to obtain the current sequential read address based on the values ​​of multiple bits in the occupancy vector data structure, control the memory to read data from the corresponding memory address based on the current sequential read address, and update the occupancy vector data structure after reading the data; wherein, the occupancy vector data structure includes multiple bits that correspond one-to-one with multiple memory addresses, and each bit is used to indicate whether the corresponding memory address can be read sequentially; The read interface module is used to send the read data and the current sequential read address to the downstream device; The read interface module is also used to receive a readback enable signal and a readback address input by the downstream device, read the corresponding readback data from the memory according to the readback enable signal and the readback address, and send the readback data to the downstream device.

2. The first-in, first-out device according to claim 1, characterized in that, The first-in-first-out device also includes a write interface module; The write interface module is used to receive the write enable signal and the data to be written from the upstream device; The control module is further configured to obtain the current write address based on the values ​​of multiple bits in the empty vector data structure according to the write enable signal, and control the memory to write the data to be written to the memory address corresponding to the current write address; wherein, the empty vector data structure includes multiple bits that correspond one-to-one with multiple memory addresses, and each bit is used to indicate whether the corresponding memory address is occupied.

3. The first-in, first-out device according to claim 1 or 2, characterized in that, The read interface module is used to cache the read data and the current sequential read address, and when it receives the sequential read enable signal sent by the downstream device, it sends the read data and the current sequential read address to the downstream device.

4. The first-in, first-out device according to claim 3, characterized in that, The read interface module is also used to receive the release address input by the downstream device; The control module is also used to update the null vector data structure according to the release address.

5. The first-in, first-out device according to claim 4, characterized in that, The control module includes a control unit, an occupation vector data structure, and a read vector to address unit; The control unit is used to query the occupancy vector data structure to obtain the next bit that indicates the corresponding storage address can be read sequentially, and to obtain the current sequential read vector in one-hot binary code format based on the next bit that indicates the corresponding storage address can be read sequentially; The read vector to address unit is used to convert the current sequential read vector in the one-hot binary code format into a current sequential read address in a preset format, and input the current sequential read address into the memory, so that the memory reads the read data from the corresponding memory address according to the current sequential read address; The control unit is also used to update the occupancy vector data structure after reading the read data.

6. The first-in, first-out device according to claim 5, characterized in that, The control module also includes a write vector to address unit, an empty vector data structure, and a release address to redirection unit; The control unit is also used to query the empty vector data structure to obtain the next unoccupied bit, and obtain the current write vector in one-hot binary code format based on the next unoccupied bit; The write vector to address unit is used to convert the current write vector in the one-hot binary code format into the current write address in a preset format, and input the current write address into the memory so that the memory writes the data to be written to the corresponding memory address according to the current write address; The release address redirection unit is used to convert the preset format release address into a one-hot binary code format release vector; The control unit is used to update the null vector data structure according to the release vector.

7. The first-in, first-out device according to claim 6, characterized in that, The control unit is also configured to send a memory full signal to the upstream device according to the empty vector data structure, and to send a memory empty signal to the downstream device according to the occupied vector data structure.

8. A control method for a first-in, first-out (FIFO) device, characterized in that, The first-in-first-out device includes a read interface module, a control module, and a memory; The control method includes: The control module obtains the current sequential read address based on the values ​​of multiple bits in the occupancy vector data structure, controls the memory to read data from the corresponding memory address based on the current sequential read address, and updates the occupancy vector data structure after reading the data; wherein, the occupancy vector data structure includes multiple bits that correspond one-to-one with multiple memory addresses, and each bit is used to indicate whether the corresponding memory address can be read sequentially; The read interface module sends the read data and the current sequential read address to the downstream device; The read interface module receives the readback enable signal and readback address input by the downstream device, reads the corresponding readback data from the memory according to the readback enable signal and readback address, and sends the readback data to the downstream device.

9. The control method according to claim 8, characterized in that, The first-in-first-out device also includes a write interface module; The control method further includes: The write interface module receives the write enable signal and the data to be written from the upstream device; The control module obtains the current write address based on the values ​​of multiple bits in the empty vector data structure according to the write enable signal, and controls the memory to write the data to be written to the memory address corresponding to the current write address; the empty vector data structure includes multiple bits that correspond one-to-one with multiple memory addresses, and each bit indicates whether the corresponding memory address is occupied.

10. The control method according to claim 9, characterized in that, The control method includes: The read interface module caches the read data and the current sequential read address, and sends the read data and the current sequential read address to the downstream device when it receives the sequential read enable signal sent by the downstream device. The read interface module receives the release address input by the downstream device; The control module updates the null vector data structure according to the release address.

11. A chip, characterized in that, Includes the first-in, first-out device according to any one of claims 1 to 7.

Images