A multi-dimensional data logic processing method based on an artificial intelligence algorithm

Abstract

The application relates to the technical field of electric digital data processing, and discloses a multi-dimensional data logic processing method based on an artificial intelligence algorithm, which comprises the following steps: receiving a target discrete data packet, extracting metadata and calculating a dimension entropy feature vector representing data logic complexity; inputting the vector into a preset topological mapping model to output an initial adjacency matrix; calling a feedback inhibition mask matrix generated based on a historical operator utility state, performing bitwise logical AND operation on the initial adjacency matrix to generate a corrected effective topological matrix; analyzing the matrix, dynamically indexing a logical operator function pointer in an instruction cache, and constructing a directed acyclic execution linked list; and driving a processor to sequentially call logical operator execution operation, wherein the application determines redundant logic nodes in AI prediction through a bitwise operation mask mechanism based on historical feedback, realizes the deterministic convergence of processing delay and the optimal matching of algorithm resource.

Description

Technical Field

[0001] This invention relates to a multidimensional data logic processing method based on artificial intelligence algorithms, belonging to the field of electronic digital data processing technology. Background Technology

[0002] In the current field of digital data processing, for multi-dimensional and heterogeneous data streams, static predefined control flow is often used to organize logical judgments. Fixed nested conditions or responsibility chains are pre-built during compilation to cover expected business scenarios. The processor runs according to the instruction counter, traversing or jumping to execute static instruction sequences to parse data. This static architecture ensures the completeness of logical coverage and is a general standard for processing routine transactional data. In the Internet of Things and distributed computing environments, input data streams exhibit both high throughput and feature sparsity. Static control flow faces instruction execution efficiency issues. The static code structure is designed defensively based on worst-case complexity. Even when processing routine data packets that only require simple logic, it still loads complex full logic verification contexts to cover a very small number of abnormal conditions, which lengthens the routine processing path. The central processing unit performs invalid branch prediction and status checks in a large number of clock cycles, reducing the utilization of the instruction pipeline. Even if the data information entropy is low, the rigid program structure consumes fixed computing resources, and the system throughput cannot increase linearly with the decrease in data complexity.

[0003] To address the issue of computing power lock-in, the industry has attempted to increase the number of hardware cores or introduce general-purpose rule engines. While simply increasing processor cores improves concurrency, it does not address instruction redundancy within a single thread and increases hardware costs and energy consumption. Traditional rule engines offer configuration flexibility, but their underlying reliance on interpreted matching algorithms introduces parsing latency in the face of high-frequency data streams, making it impossible to achieve physical simplification of execution paths at the instruction set architecture level. While end-to-end deep learning models can replace logical judgments and handle non-linear features, their inherent inference latency and probabilistic outputs make it difficult to meet the deterministic logic execution requirements of industrial-grade control. Not only are there shortcomings in system data processing and task scheduling, but there are also bottlenecks in the underlying algorithm optimization and dynamic adaptability of these core processes. For example, Chinese invention patent application CN119671160A discloses an inspection based on artificial intelligence and the Internet of Things. The service management system includes modules such as data acquisition, edge computing, task allocation, and path planning. It feeds back information to the task allocation module through an early warning module to adjust task plans. However, the task allocation and path planning logic is mainly based on preset rules and priority evaluation for sorting and optimization, which is a relatively rigid upper-level strategy adjustment. Although the system can adjust tasks based on abnormal data, the core logic execution topology is still pre-set or generated by a probability model. It cannot physically remove redundant logic nodes at the instruction execution level based on minor changes in data characteristics. When facing high-throughput, low-value-density multidimensional data streams, this architecture still needs to load and execute a large number of idle logic instructions, causing the central processing unit (CPU) to waste too many clock cycles in the regular processing path, reducing the utilization of the instruction pipeline, and failing to achieve on-demand matching of computing resources and data logic complexity.

[0004] Therefore, the technical problem to be solved by this invention is how to construct a minimum complete set of dynamic execution paths in real time during runtime based on the instantaneous multidimensional characteristics of the data stream, eliminate invalid calculations at the instruction execution level, and improve system throughput. Summary of the Invention

[0005] To address the problems mentioned in the background art, the technical solution of the present invention is as follows: A multi-dimensional data logic processing method based on artificial intelligence algorithms, comprising the following steps:

[0006] The dimension entropy feature vector generation step involves receiving the target discrete data packet to be processed, calling a preset sparse sampling mask to extract metadata of the target discrete data packet in multiple predefined logical dimensions, calculating the information entropy value of each dimension based on the metadata, and generating a dimension entropy feature vector that represents the logical complexity of the data.

[0007] The initial logical topology prediction step inputs the dimensional entropy feature vector into a pre-set topology mapping model. The topology mapping model outputs an initial adjacency matrix that defines a subset of logical operators and the execution dependencies between operators. The initial adjacency matrix contains candidate logical nodes generated based on probability prediction.

[0008] The topology mask deterministic correction step retrieves the feedback suppression mask matrix generated based on the historical operator utility state and associated with the dimensional entropy feature vector. The initial adjacency matrix and the feedback suppression mask matrix are subjected to a bitwise logical AND operation to generate the corrected effective topology matrix. The bitwise logical AND operation is based on the suppression bits in the feedback suppression mask matrix to remove logical operator nodes in the initial adjacency matrix that are predicted to be activated but have a historical low utility state.

[0009] The process involves dynamically executing the linked list construction steps, parsing the valid topology matrix, dynamically indexing the function pointers of the corresponding logical operators in the instruction cache based on the execution dependencies, and constructing a directed acyclic execution linked list composed of subsets of logical operators in memory.

[0010] The instruction stream drives the execution steps, which in turn drive the processor to call the corresponding logical operators to perform logical operations on the target discrete data packets according to the physical address order locked by the directed acyclic execution list.

[0011] Preferably, the method further includes establishing an operator utility feedback mechanism to update the feedback suppression mask matrix, specifically including: in the instruction flow driven execution step, monitoring the running return status of each logical operator; when the running of a logical operator does not change the data status of the target discrete data packet or returns a preset invalid flag, marking the logical operator as a low-utility state; establishing a mapping relationship between the dimensional entropy feature vector and the feedback suppression mask matrix; updating the feedback suppression mask matrix corresponding to the current dimensional entropy feature vector based on the low-utility state; setting the mask value at the position of the logical operator corresponding to the low-utility state to the suppression state; and in the subsequent execution of the topology mask deterministic correction step, calling the updated feedback suppression mask matrix to perform logical pruning at the instruction execution level on the initial adjacency matrix.

[0012] Preferably, the dynamic execution linked list construction step specifically includes a runtime isomorphic subgraph vectorization mapping process: traversing the effective topology matrix, identifying multiple candidate logical operators that satisfy preset isomorphic conditions, whereby the candidate logical operators are at the same topological level in the logical topology, correspond to the same logical processing function, and have no data dependency relationship with each other; merging multiple candidate logical operators into vectorized execution nodes, and mapping the data input addresses corresponding to the multiple candidate logical operators to a continuous memory vector space; the scheduling execution engine, for the vectorized execution nodes, calls a preset single instruction multiple data stream instruction set to perform parallel logical operations on the data in the memory vector space, and splits and maps the resulting state vector back to the corresponding logical processing result.

[0013] Preferably, after the dimensional entropy feature vector generation step and before the initial logical topology prediction step, a fast and slow path hierarchical arbitration step based on feature fingerprints is further included: performing a hash operation on the dimensional entropy feature vector to generate feature fingerprints; matching the feature fingerprints with a pre-set topology fast lookup table, which stores the mapping relationship between high-frequency feature fingerprints and historically verified valid logical operator adjacency matrices; when the match is successful, directly extracting the corresponding logical operator adjacency matrix as a valid topology matrix, and directly entering the dynamic execution linked list construction step, bypassing the inference operation of the topology mapping model; when the match fails, executing the step of inputting the dimensional entropy feature vector into the pre-set topology mapping model, and writing the subsequently verified valid logical operator adjacency matrix and its corresponding feature fingerprint into the topology fast lookup table.

[0014] Preferably, the method further includes a compliance circuit breaker step based on topological invariants: retrieving a preset rigid constraint matrix, in which preset key logic operator nodes and insurmountable execution order are marked as mandatory bits; after generating a valid topology matrix in the topology mask deterministic correction step, performing a bitwise logical OR operation between the valid topology matrix and the rigid constraint matrix to generate a compliant adjacency matrix; using the compliant adjacency matrix to replace the valid topology matrix to drive the dynamic execution linked list construction step, and including key logic operator nodes in the directed acyclic execution linked list through a bitwise logical OR operation.

[0015] Preferably, the information entropy value in the dimensional entropy feature vector represents the degree of uncertainty of the data in the corresponding logical dimension. The logical dimension includes the temporal distribution dimension, the numerical dispersion dimension, and the data structure integrity dimension. The dimensional entropy feature vector generation step includes, for the numerical dispersion dimension, statistically analyzing the distribution histogram of numerical fields in the target discrete data packet, and calculating the normalized information entropy as the feature component of the dimension based on the distribution histogram.

[0016] Preferably, the training objective function of the topology mapping model includes a computational cost constraint term, which is defined as the sum of the preset computational overhead weights of the activated logical operators. The parameter update process of the topology mapping model follows the principle of minimizing the computational cost constraint term while minimizing the error of the logical processing result, so as to drive the topology mapping model to generate an initial adjacency matrix that tends to be sparse.

[0017] Preferably, in the dynamic execution linked list construction step, the directed acyclic execution linked list consists of a series of instruction blocks containing opcodes and pointers to the next node; the construction process includes directly writing the instruction blocks into the processor's instruction cache line and using pointer jump instructions to link the instruction blocks, so as to eliminate the blocking effect of branch prediction failure on the instruction pipeline.

[0018] Preferably, in the step of updating the feedback suppression mask matrix corresponding to the current dimensional entropy feature vector based on the inefficient state, a time-decay-based cumulative update strategy is adopted; for the feedback suppression mask matrix, the first... Line number Column mask value Its update rules follow the following mathematical relationship: ,in, Indicates at time Updated mask value, Represents the suppressed state. Represents the active state; Indicates time The single-run utility state of the corresponding logical operator takes the value of Time indicates inefficiency; This indicates the cumulative number of times the logical operator has been consecutively judged as inefficient; This indicates the preset threshold for suppressing triggering.

[0019] Preferably, the method further includes a bypass benchmark verification step: extracting target discrete data packets that have completed the instruction flow-driven execution step according to a preset sampling probability; sending the extracted target discrete data packets into the full logic processing path to perform benchmark operations and obtain benchmark truth results; comparing the benchmark truth results with the logic operation results output by the instruction flow-driven execution step, and if the two are inconsistent, generating a penalty signal and backpropagating it to the topology mapping model to trigger the online fine-tuning update of the model weights.

[0020] Compared with the prior art, the beneficial effects of the present invention are:

[0021] 1. In the multidimensional data of artificial intelligence algorithms, the dimensional entropy feature vector of the data packet is calculated and mapped to generate the adjacency matrix of logical operators. A directed acyclic execution list containing only necessary nodes is constructed in memory in real time. This changes the traditional data processing mode that relies on static predefined code branch traversal. The timing of control flow generation is postponed from the compile time to the runtime. For high-dimensional sparse data streams, the dynamic topology structure ensures that the processor only indexes and links the logical function pointers necessary for the current data features. Redundant defensive check branches are directly skipped, and execution paths are generated on demand. This physically eliminates the invalid instruction loading and execution caused by static full logic coverage, reduces the CPU clock cycle consumption of regular data processing, and reduces the blocking effect of branch prediction failure on the instruction pipeline.

[0022] 2. Maintain historical operator utility state bitmap records and generate negative feedback mask matrices. In the logical topology generation stage, introduce a hard correction step based on bitwise AND operation. Do not rely on iterative training of neural network parameters. Use the actual execution result of logical operators, i.e. whether a state change occurs, as physical feedback. At the adjacency matrix level, remove zombie nodes that are predicted to be activated but are actually idle. Use the underlying Boolean algebra to constrain the upper-level probabilistic inference technology architecture to solve the problem of excessive defensive computation caused by long-tailed data. Without increasing the model inference overhead, ensure the simplicity of the execution list and the stability of system throughput through nanosecond-level bit operations.

[0023] 3. Identify isomorphic logical operators at the same topological level in the adjacency matrix that are independent of each other, merge the original discrete scalar logical judgments into vectorized supernodes, map the corresponding discrete data fields to a continuous memory vector space, drive the processor to call the Single Instruction Multiple Data Stream (SIMD) instruction set, and complete multi-dimensional logical operations in parallel within a single instruction cycle. Transform the logical topology into a vectorized memory access mode, improve the CPU cache line hit rate, break through the memory bandwidth bottleneck when processing multi-dimensional heterogeneous data using traditional serial logical judgments, and achieve a doubling of data processing throughput. Attached Figure Description

[0024] Figure 1 This is a flowchart of the multi-dimensional data logic processing for the feedback suppression mask of the present invention;

[0025] Figure 2 This is a comparison curve of processing delay convergence under the feedback suppression mechanism of this invention;

[0026] Figure 3 This is a schematic diagram of the dynamic logical topology construction architecture and data flow of the present invention. Detailed Implementation

[0027] The following embodiments are further detailed descriptions of the technical solutions of the present invention. It should be understood that these embodiments are only used to illustrate the present invention and are not intended to limit the present invention.

[0028] This invention proposes a multidimensional data logic processing method based on artificial intelligence algorithms. By reconstructing the computation graph in real-time during runtime, it achieves dynamic matching of computing resources and data features. The method execution process involves four core stages: dimensional entropy feature extraction, logical topology prediction, feedback suppression mask correction, and dynamic instruction stream construction. For the target discrete data packet flowing into the processor, the system initiates a feature vectorization procedure. Given that full parsing of the data packet header and payload introduces processing latency, the system calls a preset sparse sampling mask to directly read byte fragments at specific offset addresses of the data packet in memory. Regarding the feature representation of the data packet in the numerical discreteness dimension, the system sets a feature vectorization procedure that includes... The system generates a histogram template for the numerical distribution of each interval, reads sampled values ​​of specified numerical fields from the data packet, maps them to the corresponding histogram template intervals, and calculates the frequency distribution. Based on this frequency distribution, the system calculates the normalized information entropy value for that dimension using the following formula. : ,in, Indicates the first The numerical sampling frequency within each interval The system synchronously calculates the entropy value of the data packet in the temporal distribution dimension (based on timestamp intervals) and the entropy value in the data structure integrity dimension (based on the existence of key fields). The system combines the entropy values ​​of the above dimensions to generate a dimensional entropy feature vector that characterizes the logical complexity of the target discrete data packet. This vector transforms the unstructured features of the data packet into a fixed-length numerical tensor input that can be parsed by a neural network.

[0029] Dimensional entropy feature vector In the process of generation, temporal distribution entropy Calculation through continuous reception Data packet timestamp difference Statistics will Discretization mapping to preset Calculate the interval within each time interval. Frequency of occurrence Then calculate the normalized Data structure integrity entropy Calculation based on predefined Key metadata fields Existence state Quantification, when Take when it is a missing or invalid identifier Take when it exists and is valid ,according to Statistical distribution of each field Calculations show that Entropy values ​​of each dimension , and When the system is initially deployed or when there are significant changes in traffic characteristics, a baseline calibration procedure should be executed, based on the components. Lossless sampling of all samples within the time window; calculation of global statistical variance of entropy values ​​for each dimension; and setting weighting coefficients. The inverse of the variance is obtained by... To ensure that the topological mapping model has an approximate input dynamic range when inputting features of each dimension; and to obtain the dimensional entropy feature vector. The system then inputs this data into a pre-defined topology mapping model to generate an initial logical topology. The mapping model employs a fully connected multilayer perceptron structure, with the number of input layer nodes corresponding to... The dimension of the output layer corresponds to the adjacency matrix vector formed by the complete set of logical operators. During the inference phase, the model outputs the probability values ​​of activation of each logical operator node and the connection weights between operators. The system sets a hard threshold. For example, the value is , will output vectors greater than Set the element to The rest are set to This allows for the reconstruction of the initial adjacency matrix that defines the subset of candidate logical operators and their execution dependencies. .

[0030] Topology mapping model Employing a fully connected multilayer perceptron architecture, parameters Training objective function Minimize the prediction error of the logic processing and computational cost loss function Expressed as , The binary cross-entropy loss function is used to measure the candidate adjacency matrix output by the model. With the actual sparsed topological matrix The differences between them use matrix Norm, i.e. The driving model output tends to be sparse, and the regularization coefficient The range of values ​​is specified in ,ensure Convergence while reducing computational cost Suppression, feedback suppression mask matrix Update key parameters to suppress trigger threshold Following the adaptive calibration procedure and based on historical execution data, the logical operators are... Statistical analysis of the average number of packets processed between two valid triggers Among them, logical operators The first character in the predefined set of logical operators k A logical operator node, k Use positive integer indices; set Initial value equals Between 5% and 10%, the system executes a tentative recovery mechanism. Each time reached Each data packet processing cycle Temporarily activate once for a canary test; initial recovery period. Set as Data packets, with a maximum of [number] packets. Each data packet dynamically adapts to changes in data characteristics. To eliminate redundant nodes that might be introduced by probabilistic prediction, the system then performs a deterministic correction step based on bitwise operations for the topology mask. The system retrieves the data associated with the current data from memory. Feedback suppression mask matrix Each element in this matrix corresponds to a node or edge in the adjacency matrix, and its value is... Represents the suppressed state, which is Indicating a pass state, the system performs the following bitwise AND operation to generate the corrected valid topology matrix. : This operation utilizes Boolean algebra constraints to remove logical operator nodes that were historically predicted to be activated by the model but were deemed inefficient in actual execution, based on the generated effective topology matrix. The system enters the dynamic execution linked list construction phase, and the system parses... The directed acyclic graph structure in the instruction cache allocates contiguous memory space and writes the entry address pointers of the corresponding logical operator functions in sequence according to the topological sorting result, thus constructing a function pointer array. The system starts the instruction flow driving engine, loads the function pointers from the array in sequence and jumps to execute them until the end of the linked list, thus completing the logical processing of the target discrete data packet.

[0031] During data processing, the system synchronously runs an operator utility feedback mechanism to dynamically update the feedback suppression mask matrix. For each invoked logical operator, the system monitors its return status. and data packet status change identifier If the operator is executed For default invalid identifiers, such as null values ​​or Boolean false values, and The system determines that the operator is in an inefficient state during this execution because the content of the displayed data packet has not changed. The system updates the corresponding mask value based on a time-decay cumulative update strategy. For the feedback suppression mask matrix, the [missing information - likely a specific value or parameter]... Line number Column elements The update follows the discrete-time evolution rule as follows: ,in This represents a cumulative counter indicating that the logic position has been continuously judged as an inefficient state. This indicates a preset suppression threshold. When a logical node is repeatedly verified as invalid during the processing of specific feature data, this mechanism permanently sets the corresponding mask bit to 0. To address the isomorphic logical operation requirements in data processing, the system performs a runtime vectorized mapping of the isomorphic subgraph. Specifically, the system first performs a vectorized mapping of the effective topological matrix. A breadth-first search-based topology sorting algorithm is executed, assigning a topology depth value to each logical operator based on the longest path distance of the node in the directed acyclic graph. Subsequently, the system traverses the set of nodes with the same topology depth value, filtering out similar operators by comparing the consistency of function pointer addresses or opcodes, and then re-searching the matrix. To confirm that there are no directional connections between the selected operator nodes (i.e., all elements at corresponding positions in the matrix are 0), multiple independent nodes satisfying the isomorphism condition are identified. The system merges these discrete nodes into vectorized execution nodes and maps the data memory addresses of their respective operations to contiguous vector register load buffers. During the execution phase, the system calls the processor's single-instruction multiple-data instruction set, such as the AVX-512 instruction set, to load the data in the above buffers in parallel. The logical operations of all merged nodes are completed in a single instruction cycle, and the result vector is split and written back to their respective status bits. To ensure the compliance of the system under dynamic logical scheduling, this method also includes a compliance circuit breaker step based on topological invariants. The system pre-sets a rigid constraint matrix. The system marks the node positions corresponding to the preset key business logic as 1. Key logic operators are defined as operations that are mandatory in the business specifications and cannot be skipped due to AI prediction optimization. These include, but are not limited to: cyclic redundancy check (CRC) operators, security audit log recording operators, and data boundary compliance check operators. These operators correspond to fixed indexes in the system's initial configuration table, regardless of the dimensional entropy characteristics of the input data. The corresponding bits in the matrix are always hard-coded as active states, in generating an effective topology matrix. Then, the system performs a bitwise OR operation: This operation ensures that critical logical operators are always included in the final execution list.

[0032] Example 1: In the data processing environment of a high-throughput industrial IoT gateway, the processor needs to concurrently process mixed data streams from heterogeneous sensors, including high-frequency routine telemetry data, occasional control commands, and potential anomaly detection data. When the system faces a massive influx of discrete data packets, the traditional static control flow processing method requires full protocol parsing and defensive logic verification for each data packet. This results in the central processing unit consuming excessive clock cycles when processing a large number of inefficient data packets that only need to be simply forwarded or discarded, causing instruction pipeline blockage and system response delay jitter. In this environment, the solution of this invention directly extracts the metadata of the target discrete data packet at a predefined offset position through a pre-set sparse sampling mask and calculates and generates a dimensional entropy feature vector. This step avoids the memory bandwidth consumption caused by full payload parsing; for logical path planning of data packets, the system will calculate the... Input a topology mapping model, and the model outputs an initial adjacency matrix containing multiple candidate logical nodes. At this stage, if the data packet is an anomaly detection payload with high randomness, its normalized information entropy value in the dimension of numerical dispersion is... The high probability of this leads neural network models, based on probabilistic prediction, to tend to activate complex logical paths, including deep unpacking, format cleaning, and full verification. It contains a large number of nodes that are set to the active state. At this time, the system retrieves the nodes associated with that node. Feedback suppression mask matrix This matrix records the historical execution utility state corresponding to the feature vector. If the historical record shows that such high-entropy data packets have not changed the system state or returned an invalid flag after deep verification, then... The position corresponding to the depth verification logic is marked as the suppressed state. The system then performs a bitwise AND operation. Before instruction construction, redundant deep verification nodes introduced by neural network predictions are physically removed, generating an effective topology matrix containing only necessary processing nodes. .

[0033] In generating an effective topology matrix Subsequently, the system further applies compliance-based circuit breaker procedures based on topological invariants to... With the preset rigid constraint matrix Perform bitwise OR operation This ensures that critical logical nodes, such as security log records, are retained regardless of the prediction outcome, and the system analyzes them. In the instruction cache, a directed acyclic execution list composed of function pointers is dynamically constructed. For multiple isomorphic nodes in the list that perform the same numerical range verification for different sensor data fields, the system performs a vectorized mapping of the isomorphic subgraph at runtime, merges these scattered scalar verification logics into vectorized execution nodes, and drives the processor to call the single instruction multiple data stream instruction set to perform the verification operation in parallel.

[0034] Example 2: In an industrial IoT data processing simulation platform used to verify the effectiveness of the technical solution of the present invention, a test environment capable of simulating high-concurrency heterogeneous data streams was constructed. The physical host server selected for the test platform is equipped with an Intel Xeon Gold 6248R central processing unit supporting the AVX-512F instruction set extension. This processor has 24 computing cores and a main frequency of 3.0 GHz. The server is also equipped with 128 GB of DDR4 ECC memory and runs on the Ubuntu 20.04 LTS operating system. The platform integrates a data generator, a dynamic logic processing engine built based on the method of the present invention, and a benchmark processing engine based on traditional static control flow. The experiment aims to compare and evaluate the processing latency and throughput performance of the two processing modes when facing data streams with different logical complexities and characteristic distributions. The data generator is configured to generate mixed traffic including regular telemetry data, control commands, and anomaly detection data. The generated data packets adopt the UDP protocol format, and the effective payload length follows a normal distribution with a mean of 512 bytes and a variance of 128 bytes. The length range covers 64 bytes to 1400 bytes to simulate real working conditions. The proportion of anomaly detection data can be adjusted. to The signal-to-noise ratio is dynamically adjusted to simulate sudden conditions such as network attacks or equipment failures. To realistically simulate signal interference in the real environment, the signal-to-noise ratio superimposed in the data stream is [value missing]. Gaussian white noise is introduced, along with random packet loss and out-of-order delivery.

[0035] The experiment verifies the accuracy of dimensional entropy feature extraction and logical topology prediction. The system sampling period is set to [value missing]. And continuing Within the test window, feature vector data after sparse sampling and dimensional entropy calculation is collected, and the normalized information entropy value for the numerical discreteness dimension is calculated. Set the number of histogram intervals During the experiment, the system monitored in real time. The changing trend and its impact on the initial adjacency matrix The impact of generation, when the input data packet is conventional telemetry data with low entropy, the model output The model exhibits highly sparsity, activating only the necessary format parsing and store-and-forward nodes. However, when the input data packet is high-entropy anomaly detection data, the model tends to activate all logical nodes, including deep verification. To verify the effectiveness of the feedback suppression masking mechanism, a comparative sample was introduced, namely, the open-loop prediction mode without mask correction. In the comparative sample, when faced with high-entropy but actually invalid malicious detection packets, the system always performs full verification, leading to increased processing latency. In the sample of this invention, as the processing progresses, the feedback suppression masking matrix... The test gradually learns and suppresses invalid deep verification nodes. To quantify the performance advantages of the present invention, the test design includes a comparative test between the present invention sample group and the control sample group. The control sample group adopts a traditional static predefined control flow architecture and performs fixed full logic verification on all data packets. The test records the average processing latency and maximum throughput of the two schemes under different abnormal data ratios. The key test data are shown in Table 1.

[0036] Table 1: Comparison of Processing Performance under Different Proportions of Abnormal Data

[0037]

[0038] Referring to Table 1, the data shows that the proportion of abnormal data increased from... Upgraded to During the process, the average processing delay of the comparison group remained consistently at The above, and the decreasing throughput, indicate that the static architecture cannot effectively handle the computational overhead of high-entropy data. The average processing latency of the sample group in this invention remains at [a certain level]. to In the lower range, the throughput increased by approximately 1.3 to 1.5 times compared to the control group, and the CPU utilization decreased, confirming that... The system's computational mechanism effectively eliminates redundant logical nodes, achieving dynamic matching of computing resources and data value. Furthermore, regarding the vectorized mapping effect of homogeneous logical operations, experimental data further shows that after enabling SIMD instruction set parallel processing, the processing speed of modules involving batch numerical verification is approximately 2.8 times faster than scalar serial processing. Specifically, by comparing the clock cycle consumption of scalar serial processing and SIMD vectorized parallel processing when performing numerical verification of 1024 sets of sample data, the experiment measured the total execution cycle of the scalar serial mode. The total execution cycle is 18250, while the total execution cycle of the SIMD vectorized mode is... With only 4802 cycles, the processing speed is a multiple of scalar serial processing speed, as shown by the formula. The calculated ratio is approximately 3.8 times, verifying the gain of runtime topology reconfiguration in instruction-level parallelism.

[0039] Example 3: This example combines Figures 1 to 3 This section describes a multidimensional data logic processing method based on artificial intelligence algorithms, such as... Figure 1As shown, the process begins by receiving multidimensional heterogeneous data to be processed as the target discrete data packet. It then enters the dimensional entropy feature vector generation step to extract metadata and calculate normalized information entropy. Based on this, a vector is generated, leading to the initial logical topology prediction stage. An initial adjacency matrix is ​​generated through a topology mapping model. The process then branches into a topology mask deterministic correction step. This step combines logic with input, using a feedback suppression mask matrix based on historical operator utility state records to perform a bitwise logical AND operation to eliminate inefficient nodes. The mask matrix is ​​dynamically corrected by monitoring its state and dynamically updating the mask threshold through an operator utility feedback mechanism. The corrected effective topology matrix then enters the compliance circuit breaker step based on topological invariants. This step combines preset key logic and a rigid constraint matrix of an insurmountable order to perform a bitwise logical OR operation. The key logic is defined as follows: For audit log recording or compliance verification operators that must be executed according to the system security policy, the inviolable order is defined as the inherent data dependency edges between nodes based on causality, such as decryption must precede parsing; the construction and maintenance mechanism of this rigid constraint matrix is ​​as follows: during the system initialization phase, a pre-set static configuration file is read to generate a full baseline bitmap, the positions of the above nodes and edges are locked as mandatory bits, i.e., logic 1, and maintained as read-only constants during subsequent runtime, not updated with real-time changes in data characteristics, and a compliance adjacency matrix is ​​generated after including key logic; this compliance matrix drives the dynamic execution of the linked list construction steps, during which runtime isomorphic subgraph vectorization is performed and a directed acyclic execution linked list (DAG) is constructed, and finally the instruction flow drives the execution steps to call operator function pointers and perform parallel logical operations, outputting the processed data state as the result of the logical operation.

[0040] like Figure 2 As shown in the figure, the batch size is plotted on the x-axis, and the average processing latency (in μs) is plotted on the y-axis, creating two performance curves. The dashed line represents the control group without masking (open-loop prediction), whose average processing latency remains high at around 130 μs without any downward trend. The solid line represents the experimental group with feedback suppression masking enabled, showing that as the batch size increases, the average processing latency rapidly decreases from the initial 135 μs and converges to around 50 μs. Figure 3 As shown, after the target discrete data packet is input into the system, a dimensional entropy feature vector is generated. Then, it enters the fast and slow path arbitration stage of the feature fingerprint. If the matching fails, it enters the initial logical topology prediction driven by AI probabilistic reasoning, and performs dynamic correction by combining operator utility feedback update. The topology mask is then performed to perform deterministic correction to remove redundant nodes. At this time, the system introduces a rigid constraint matrix to provide constraints, performs compliance circuit breaking to ensure that key logic is included, and identifies the runtime isomorphic subgraph for vectorization processing. Finally, a directed acyclic execution list is constructed to drive the central processing unit supporting the SIMD instruction set to complete the logical operation.

[0041] Example 4: This example aims to supplement and verify the parameter setting and state update logic of the operator utility feedback mechanism involved in the aforementioned specific embodiments. In the dynamic topology correction process based on the feedback suppression mask matrix, the mask value... The update logic determines the system's suppression speed and recovery sensitivity to invalid logical nodes, as stated in the aforementioned formula. Dependent on cumulative counter With preset threshold The comparison, among which The value of this parameter lacks clear engineering calibration basis. To eliminate the empirical dependence on the setting of this parameter, this embodiment constructs a parameter based on historical statistics. The adaptive adjustment procedure, targeting historical data streams in the target application scenario, extracts the state reversal statistical characteristics of various logical operators under full verification mode, and defines the operators. Distribution of effective intervals This refers to the time interval distribution between two valid triggers of the operator. For anomaly detection data with long-tail distribution characteristics, the corresponding depth verification operator often exhibits an extremely long validity interval. Based on this distribution, an initial... The average number of data packets corresponding to the average validity interval of this operator. .

[0042] Introducing a tentative recovery mechanism to address static issues Potential problems with over-inhibition, when Set to the suppressed state Then, the system starts an independent recovery counter. Whenever passing by In each data packet processing cycle, the system will Temporarily set to the active state, i.e. Once, the canary test is performed. If the operator returns a valid state in this test, it is reset. for and maintain If it is still invalid, then Exponential increase, that is The maximum limit shall not exceed the preset limit. This mechanism ensures that the mask matrix can both quickly respond to the decrease in operator utility and dynamically adapt to the drift of data features. To verify the effectiveness of the above-mentioned adaptive parameter adjustment procedure, supplementary tests were conducted on the same simulation platform as in Example 2. When the data stream characteristics changed abruptly, switching suddenly from high-proportion anomaly detection data to full-volume normal data, the adaptive adjustment was activated. Compared to the prototype of this invention with a trial-and-error recovery mechanism, the convergence recovery time of the logic topology is faster than that of a fixed-time approach. The control group shortened by approximately In this test, when the percentage of anomaly detection packets suddenly dropped from 50% to 0%, a fixed... The control group required processing approximately 2500 data packets to reset the suppressed conventional path mask bits to the active state; while the sample group of this invention quickly captured the operator utility recovery through the canary test, and only required processing approximately 1000 data packets to complete convergence. The convergence recovery time was shortened from 2500 cycles to 1000 cycles, and the calculated reduction ratio was (2500-1000) / 2500×100%=60%. This mechanism enables the feedback suppression mask matrix to maintain higher logic coverage and adaptability under non-steady-state data flow.

[0043] Example 5: This example aims to supplement and verify the baseline calibration procedure for dimensional entropy feature vectors involved in the actual deployment of the aforementioned technical solutions. It addresses the aforementioned dimensional entropy calculation formula. In this process, the normalization process depends on the logarithmic sampling frequency. According to statistics, The accuracy is limited by the interval division strategy of the numerical distribution histogram template. If the preset histogram intervals... If the boundary settings fail to adapt to the actual data distribution characteristics of the target environment, it will lead to an inefficient dimensionality entropy feature vector. The reduced distinguishability of the parameter affects the accuracy of logical topology prediction. To eliminate the environmental dependence of this parameter setting, this embodiment constructs a baseline adaptive calibration procedure based on field data sampling.

[0044] When the system first connects to the target network environment or when there are significant changes in network traffic characteristics, the offline calibration mode is activated. In this mode, the system continuously... Within the calibration window, lossless sampling is performed on the entire data packet to obtain the raw distribution data of the numerical fields. Based on the sampled raw data, the maximum entropy principle is used to adaptively divide the histogram intervals, that is, the boundary values ​​of each interval are adjusted to make the number of sampling points in each interval as uniform as possible, thereby maximizing the histogram's ability to express the details of the data distribution. The system records the determined interval boundaries and the total number of intervals at this time. As a fixed histogram template for subsequent online operation, the system analyzes the statistical characteristics of the arrival time interval of data packets within the calibration window, calculates the peak and long-tail truncation point of its probability density function, and sets the time window width and discretization granularity for calculating temporal entropy. After calibration, the system recalculates the dimensional entropy feature vector of the calibration data using the updated parameter configuration and clusters it into several typical baseline vectors, storing them in the feature library as a reference benchmark for subsequent anomaly detection. To verify the effectiveness of the above baseline calibration procedure, two network environments with different distributions are simulated in the simulation platform: Environment A is a sensor network dominated by periodic short packets, and Environment B is a video surveillance network dominated by bursty long packets. The experiment shows that, without performing adaptive calibration, directly reusing the parameter configuration of Environment A in Environment B results in the inter-class variance of the dimensional entropy feature being only [missing information]. It is difficult to distinguish between normal and abnormal traffic; however, after executing the on-site calibration procedure of this embodiment, the inter-class variance of dimensional entropy in environment B increases to This enhances the ability of feature vectors to represent logical complexity. Inter-class variance refers to the variance of the distance distribution between the set of dimensional entropy feature vectors generated by normal telemetry data and the set of dimensional entropy feature vectors generated by anomaly detection data in the feature space. Without calibration, the histogram interval division could not adapt to the data packet length distribution of environment B, resulting in a high degree of overlap between the two types of feature vectors in space, with a measured variance value of only 0.15. After performing on-site calibration and redrawing the histogram boundaries using the maximum entropy principle, the feature discrimination between the two types of data in the temporal distribution dimension and the numerical dispersion dimension increased significantly, with the measured variance value increasing to 0.68, thereby improving the prediction accuracy of the topology mapping model.

[0045] Example 6: This example aims to establish an adaptive calibration procedure for key parameters in the operator utility feedback mechanism for different computing platforms and application scenarios, in order to achieve optimal system performance configuration. (The formula is missing from the original text.) In the update logic, suppress the trigger threshold. and recovery counter growth step size These parameters directly affect the system's response speed to invalid logic and its ability to recover from misjudgments. If these parameters are set improperly, the system may become sluggish when facing high-frequency attacks or overly suppress normal fluctuations, thereby reducing overall performance. To solve this problem, this embodiment constructs a parameter offline calibration and online fine-tuning procedure based on scenario characteristics.

[0046] Before system deployment, offline benchmark testing is conducted on a specific target platform, using a standard dataset containing typical business traffic and simulated attack traffic, and iterating through... The range of values, for example from to Step size is For each candidate Record the system's average response time when processing attack traffic. and the false suppression rate when processing normal traffic Constructing an effectiveness evaluation function ,in, and To select based on the weighting coefficients set according to the business's preferences for security and availability. Maximize As the initial configuration values ​​for the platform, secondly, for the online operation phase, establish... The dynamic adjustment mechanism monitors the system's recovery success rate during the canary test. ,like If the value is below a preset threshold, it indicates that the logical failure in the current environment is persistent, and the system will automatically increase the threshold. The growth factor, from the default Adjusted to To reduce the computational cost of invalid probes; if If it is too high, reduce the growth factor or reset it. To accelerate the recovery speed of effective logic; finally, through verification in a heterogeneous environment including ARM architecture edge gateways and x86 architecture high-performance servers, the results show that the system calibrated according to the above procedures reduces the peak CPU utilization on the edge gateway to cope with high-frequency attacks. On high-performance servers, the false suppression rate of normal business operations is controlled within a certain range. In the following example, when the edge gateway is dealing with a simulated DDoS attack, the system without mask correction has a peak CPU utilization rate of 40% due to the execution of a large number of idle logic instructions. However, after enabling the procedure of this invention, the peak CPU utilization rate drops to 30% due to the physical removal of redundant nodes. The reduction ratio is calculated as (40%-30%) / (40%)=25%. In the test of processing 1,000,000 normal business samples on a high-performance server, the system only generated about 950 logical operator false suppressions in the initial environmental drift stage, with a measured false suppression rate of 0.095%, which meets the preset industrial-grade compliance standard of less than 0.1%.

[0047] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the present invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the present invention.

[0048] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention.

Claims

1. A multidimensional data logic processing method based on artificial intelligence algorithms, characterized in that, Includes the following steps: The dimension entropy feature vector generation step involves receiving the target discrete data packet to be processed, calling a preset sparse sampling mask pointing to a specific offset address, directly reading byte fragments to extract metadata of the target discrete data packet in multiple predefined logical dimensions, including temporal distribution, numerical dispersion and data structure integrity, and calculating the information entropy value of each dimension based on the metadata to generate a dimension entropy feature vector that characterizes the logical complexity of the data. The initial logical topology prediction step inputs the dimensional entropy feature vector into a preset topology mapping model. The topology mapping model outputs an initial adjacency matrix that defines a subset of logical operators and the execution dependencies between operators. The initial adjacency matrix contains candidate logical nodes generated based on probability prediction. The topology mask deterministic correction step retrieves the feedback suppression mask matrix generated based on the historical operator utility state and associated with the dimensional entropy feature vector. The initial adjacency matrix and the feedback suppression mask matrix are subjected to a bitwise logical AND operation to generate the corrected effective topology matrix. The bitwise logical AND operation is based on the suppression bits in the feedback suppression mask matrix to remove logical operator nodes in the initial adjacency matrix that are predicted to be activated but have a historical low utility state. The process involves dynamically executing the linked list construction steps, parsing the valid topology matrix, dynamically indexing the function pointers of the corresponding logical operators in the instruction cache based on the execution dependencies, and constructing a directed acyclic execution linked list composed of subsets of logical operators in memory. The instruction stream drives the execution steps, which in turn drive the processor to call the corresponding logical operators to perform logical operations on the target discrete data packets according to the physical address order locked by the directed acyclic execution list. Furthermore, the dynamic execution linked list construction steps specifically include the vectorized mapping process of the runtime isomorphic subgraph: traversing the effective topology matrix, identifying multiple candidate logical operators that satisfy the preset isomorphic conditions, whereby the candidate logical operators are limited to being at the same topological level in the logical topology, corresponding to the same logical processing function, and having no data dependency relationship with each other; merging multiple candidate logical operators into vectorized execution nodes, and mapping the data input addresses corresponding to the multiple candidate logical operators to a continuous memory vector space; the scheduling execution engine, for the vectorized execution nodes, calls the preset single instruction multiple data stream instruction set to perform parallel logical operations on the data in the memory vector space, and splits and maps the state vectors generated by the operations back to the corresponding logical processing results; In the dynamic execution linked list construction step, the directed acyclic execution linked list consists of a series of instruction blocks containing opcodes and pointers to the next node; the construction process includes writing the instruction blocks directly into the processor's instruction cache line and using pointer jump instructions to link the instruction blocks; The method further includes establishing an operator utility feedback mechanism to update the feedback suppression mask matrix. Specifically, this includes: in the instruction flow-driven execution step, monitoring the return status of each logical operator; when the execution of a logical operator does not change the data state of the target discrete data packet or returns a preset invalid flag, marking the logical operator as inefficient; establishing a mapping relationship between the dimensional entropy feature vector and the feedback suppression mask matrix; updating the feedback suppression mask matrix corresponding to the current dimensional entropy feature vector based on the inefficient state; setting the mask value at the position of the logical operator corresponding to the inefficient state to the suppressed state; and in the subsequent execution of the topology mask deterministic correction step, calling the updated feedback suppression mask matrix to perform logical pruning at the instruction execution level on the initial adjacency matrix.

2. The multidimensional data logic processing method based on artificial intelligence algorithms according to claim 1, characterized in that, Following the dimensional entropy feature vector generation step and preceding the initial logical topology prediction step, a fast-slow path hierarchical arbitration step based on feature fingerprints is also included: performing a hash operation on the dimensional entropy feature vector to generate feature fingerprints; matching the feature fingerprints with a pre-set topology fast lookup table, which stores the mapping relationship between high-frequency feature fingerprints and historically verified valid logical operator adjacency matrices; when a match is successful, the corresponding logical operator adjacency matrix is ​​directly extracted as a valid topology matrix, and the dynamic execution linked list construction step is directly entered, bypassing the inference operation of the topology mapping model; when a match fails, the step of inputting the dimensional entropy feature vector into the pre-set topology mapping model is executed, and the subsequently verified valid logical operator adjacency matrix and its corresponding feature fingerprint are written into the topology fast lookup table.

3. The multidimensional data logic processing method based on artificial intelligence algorithms according to claim 1, characterized in that, The method also includes a compliance circuit breaker step based on topological invariants: a preset rigid constraint matrix is ​​retrieved, in which the preset key logic operator nodes and the execution order that cannot be surpassed are marked as mandatory bits; after the topology mask deterministic correction step generates a valid topology matrix, the valid topology matrix and the rigid constraint matrix are subjected to a bitwise logical OR operation to generate a compliant adjacency matrix; the compliant adjacency matrix is ​​used to replace the valid topology matrix to drive the dynamic execution linked list construction step, and the key logic operator nodes are included in the directed acyclic execution linked list through a bitwise logical OR operation.

4. The multidimensional data logic processing method based on artificial intelligence algorithms according to claim 1, characterized in that, The information entropy value in the dimensional entropy feature vector represents the degree of uncertainty of the data in the corresponding logical dimension. The logical dimensions include the temporal distribution dimension, the numerical dispersion dimension, and the data structure integrity dimension. The steps for generating the dimensional entropy feature vector include, for the numerical dispersion dimension, statistically analyzing the distribution histogram of the numerical fields in the target discrete data packet, and calculating the normalized information entropy as the feature component of this dimension based on the distribution histogram.

5. The multidimensional data logic processing method based on artificial intelligence algorithms according to claim 1, characterized in that, The training objective function of the topology mapping model includes a computational cost constraint, which is defined as the sum of the preset computational cost weights of the activated logical operators. The parameter update process of the topology mapping model follows the principle of minimizing the error of the logical processing result while minimizing the computational cost constraint term, so as to drive the topology mapping model to generate an initial adjacency matrix that tends to be sparse.

6. The multidimensional data logic processing method based on artificial intelligence algorithms according to claim 1, characterized in that, In the step of updating the feedback suppression mask matrix corresponding to the current dimensional entropy feature vector based on the inefficient state, a cumulative update strategy based on time decay is adopted; for the th in the feedback suppression mask matrix Line number Column mask value Its update rules follow the following mathematical relationship: ,in, Indicates at time Updated mask value, Represents the suppressed state. Represents the active state; Indicates time The single-run utility state of the corresponding logical operator takes the value of Time indicates inefficiency; This indicates the cumulative number of times the logical operator has been consecutively judged as inefficient; This indicates the preset threshold for suppressing triggering.

7. The multidimensional data logic processing method based on artificial intelligence algorithms according to claim 1, characterized in that, The method also includes a bypass benchmark verification step: extracting target discrete data packets that have completed the instruction stream drive execution step according to a preset sampling probability; The extracted target discrete data packets are sent to the full logic processing path to perform benchmark calculations and obtain benchmark truth results. The baseline truth result is compared with the logical operation result output by the instruction flow-driven execution step. If the two are inconsistent, a penalty signal is generated and backpropagated to the topology mapping model to trigger the online fine-tuning update of the model weights.

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