Memory sharing system, shared memory synchronization method and electronic equipment

Abstract

The invention discloses a memory sharing system, a shared memory synchronization method and electronic equipment, and relates to the technical field of computers, the memory sharing system comprises hosts, switching equipment, a storage module and a directory-based consistency engine arranged in the storage module, the directory-based consistency engine is in communication connection with the output end of at least one host, and the switching equipment is connected with the storage module. The directory-based consistency engine is configured to determine a target host with a backup fault memory page corresponding to fault information according to the fault information of at least one host; the switching equipment is in communication connection with at least one host and the directory-based consistency engine, and the switching equipment is configured to send a first page message generated by the fault memory page to a target host, so that the target host is offline from the fault memory page. Therefore, the problem that other hosts continuously access wrong pages due to the fact that fault information cannot be synchronized when any host has a fault in accessing the shared memory is solved, the fault information can be synchronized across hosts, and the system stability is improved.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and in particular to memory sharing systems, methods for synchronizing shared memory, and electronic devices. Background Technology

[0002] Based on Compute Express Link (CXL) shared memory technology, all hosts are connected to the same shared memory through a CXL switch, enabling global sharing of device memory, improving data flow efficiency and memory utilization. At the same time, it supports each host to maintain a consistent copy of the data locally, and the hardware automatically completes the synchronization between copies, ensuring the consistency of data and cache, and adapting to multi-host collaborative access scenarios.

[0003] However, when a host accesses memory, memory failures may occur. For example, if an Uncorrectable Error (UCE) or a high-probability Correctable Error (CE) occurs in a shared memory page of any host, the page failure isolation action triggered by the host is only effective locally. Other hosts cannot know the abnormal state of the page and may continue to access the erroneous page, ultimately causing cross-host memory-related downtime risks. The memory failure handling solutions in related technologies are not applicable to this scenario and urgently need to be solved. Summary of the Invention

[0004] This invention provides a memory sharing system, a method for synchronizing shared memory, and an electronic device to at least solve the problem that when a shared memory accessed by any host fails, the failure information cannot be synchronized across hosts, causing other hosts to continuously access the erroneous page, which in turn leads to cross-host memory-related downtime. This application can realize real-time synchronization of fault information across hosts, avoid other hosts continuously accessing the erroneous shared memory, and improve system stability and fault tolerance.

[0005] This invention provides a memory sharing system, comprising: a host, a switching device, a storage module, and a directory-based consistency engine disposed in the storage module, wherein... The directory-based consistency engine is communicatively connected to the output of at least one of the hosts, and the directory-based consistency engine is configured to determine the target host that has backed up the faulty memory pages corresponding to the fault information based on the fault information of at least one of the hosts. The switching device is communicatively connected to at least one of the hosts and the directory-based consistency engine, and the switching device is configured to send a first page message generated by the faulty memory page to the target host, causing the target host to take the faulty memory page offline.

[0006] The present invention also provides a method for synchronizing shared memory, the method being applied to the aforementioned memory sharing system, wherein the method includes the following steps: Determine whether the directory-based consistency engine has received at least one fault message sent by the host, the fault message including a faulty memory page; When the directory-based consistency engine receives fault information sent by at least one of the hosts, it queries the global page directory through the directory-based consistency engine to determine the target host that has backed up the faulty memory page, and sends a first page message generated based on the faulty memory page to the target host through the switching device. The target host is controlled to take the faulty memory page offline based on the first page message.

[0007] The present invention also provides an electronic device, comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the shared memory synchronization method as described in the above embodiments.

[0008] This invention determines whether a directory-based consistency engine has received fault information from at least one host. The fault information includes faulty memory pages. If the directory-based consistency engine receives fault information from at least one host, it queries the global page directory to identify the target host that has backed up the faulty memory page. Then, it sends a first page message generated based on the faulty memory page to the target host via a switching device and controls the target host to take the faulty memory page offline based on the first page message. This solves the problem that when shared memory accessed by any host fails, the fault information cannot be synchronized across hosts, leading to other hosts continuously accessing the erroneous page and causing cross-host memory-related downtime. This application enables real-time synchronization of fault information across hosts, preventing other hosts from continuously accessing erroneous shared memory and improving system stability and fault tolerance. Attached Figure Description

[0009] To more clearly illustrate the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0010] Figure 1 This is a schematic diagram of a memory-sharing system based on related technologies. Figure 2 A schematic diagram of a memory-sharing system where related technologies experience downtime. Figure 3A block diagram of a memory sharing system provided in an embodiment of the present invention; Figure 4 A schematic diagram of a memory sharing system provided in one embodiment of the present invention; Figure 5 A flowchart illustrating a shared memory synchronization method provided in an embodiment of the present invention; Figure 6 A schematic diagram illustrating the principle of a shared memory synchronization method provided in one embodiment of the present invention; Figure 7 A schematic diagram of a main control host provided according to an embodiment of the present invention; Figure 8 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention. Detailed Implementation

[0011] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present invention.

[0012] It should be noted that, in the description of this invention, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., used in this invention are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0013] Before introducing the embodiments of the present invention, let's first introduce the related technologies of the embodiments of the present invention.

[0014] First, let me introduce CXL technology. CXL is a cache coherence interconnect protocol that can directly reuse the physical layer of PCIe. However, the implementation of this invention requires the additional provision of three sub-protocol stacks to achieve cache coherence functionality. The three sub-protocol stacks include the CXL input / output protocol (CXL.io), the CXL cache protocol (CXL.cache), and the CXL memory protocol (CXL.mem).

[0015] CXL.io is primarily used for basic management operations such as device discovery, enumeration, and error reporting.

[0016] CXL.cache can solve the device cache consistency problem and enable low-latency access to host memory.

[0017] CXL.mem allows the host to access the device's memory directly, just like accessing its own local memory.

[0018] CXL memory pooling technology addresses three core pain points in data center memory usage: First, it breaks through the ceiling of single-machine memory capacity. In related technologies, servers are limited by the number of DIMM (Dual In-Line Memory Module) slots on the motherboard and the memory channels of the CPU (Central Processing Unit), with the maximum capacity of DRAM (Dynamic Random Access Memory) per node being only 2–4TB. CXL memory pooling, however, uses CXLSwitch (CXL switch) to map remote DRAM to local NUMA (Non-Uniform Memory) on multiple hosts. The CXL memory pool addresses several key challenges. First, it addresses the issue of memory silos in data centers and improves memory utilization. First, it pools and shares all DRAM, dynamically allocating it to different hosts on demand, increasing memory utilization from 60% to over 90% while reducing hardware capital expenditure (CAPEX) by 5-10%. Second, it enables elastic scaling and hot-swapping of memory. Traditional server memory hot-upgrades or fault recovery require downtime for DIMM insertion and removal, leading to service interruptions. CXL memory pools support online hot-add / hot-remove operations, allowing 100GB of memory to be added to or removed from any host in seconds, achieving elastic scaling with zero service interruption.

[0019] However, the CXL shared memory system in related technologies has the following drawbacks. For example... Figure 1As shown, all hosts are connected to the same shared memory via a CXL switch (CXLSwitch), enabling shared use of device memory. This improves data flow efficiency and memory utilization, and allows each host to maintain a consistent copy of the shared data locally (i.e., S1 copy block and S2 copy block, with hardware automatically ensuring synchronization between copies). However, this CXL shared memory system has a flaw in memory fault address isolation. It only focuses on ensuring data transmission and cache consistency, and does not design a cross-host synchronization mechanism for memory fault addresses. For example, when a memory page encounters an uncorrectable error (UCE) or a high probability correctable error (CE) in Host1, it will trigger a page fault isolation action on Host1. However, this isolation action only applies to Host1, and other hosts cannot know that the memory page has been isolated. They may still continue to access the faulty memory page, which could lead to cross-host downtime due to memory problems.

[0020] like Figure 2 As shown, when page 1 is found to have an uncorrectable memory error by the inspection engine on host 1, the page is invalidated and taken offline on host 1. However, this memory segment is not invalidated and taken offline on host 2. When it is consumed by the processor on host 2, a crash will occur.

[0021] To address the aforementioned issues, embodiments of this invention combine a Directory-based Coherency Engine (DCE) with a page-by-page failure mechanism to directly resolve the offline / online page synchronization problem across hosts in CXL shared memory scenarios at the hardware level. This provides low-latency, high-reliability underlying technology support for scenarios such as memory pooling, hot migration, and data deduplication. In power-down recovery scenarios, a button-triggered restart and re-isolation mechanism is employed. By forcing a global mode, pages at risk of failure are taken offline uniformly, ensuring that all hosts can recognize the page's status after recovery, thus completely avoiding the risk of cross-host downtime.

[0022] To enable those skilled in the art to better understand the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0023] An embodiment of the present invention provides a memory sharing system.

[0024] like Figure 3 As shown, the memory sharing system 10 includes: a host 100, a switching device 200, a storage module 300, and a directory-based consistency engine 301 configured in the storage module 300.

[0025] The directory-based consistency engine 301 is communicatively connected to the output of at least one host 100. The directory-based consistency engine 301 is configured to determine the target host with the faulty memory page corresponding to the fault information based on the fault information of at least one host 100. The switching device 200 is communicatively connected to at least one host 100 and the directory-based consistency engine 301. The switching device 200 is configured to send a first page message generated by the faulty memory page to the target host, so that the target host takes the faulty memory page offline.

[0026] Combination Figure 4 As shown, Figure 4 This is a schematic diagram of a memory sharing system according to an embodiment of the present invention. The directory-based coherency engine 301 is a hardware module (i.e., Directory-based Coherency Engine, DCE) deployed inside the CXL controller. It maintains the Global Page Directory (GPD) at 4KB page granularity, records the shared memory accessed by each host, and tracks page status (e.g., whether it is contaminated or needs to be taken offline). The switching device 200 can be a CXL Switch, serving as an interconnection hub connecting multiple hosts 100 and the CXL shared memory device. The first page message can be a Page Offline / Online Invalidate (POI) message, a custom control message transmitted via the CXL.mem protocol S2M channel, used to notify the target host to perform a local invalidation operation on a specific faulty memory page.

[0027] Specifically, when any host 100 detects an uncorrectable error (UCE) or a high-probability correctable error (CE) in the CXL shared memory page it accesses, it writes an instruction to the PCR (Page Control Register) in the directory-based consistency engine 301 via MMIO (Memory-Mapped I / O), triggering the page's failure process. The DCE, based on the Host-bitmap recorded in the global page directory, accurately identifies all target hosts that have backed up or cached the failed memory page. Then, through the switching device 200 (i.e., the CXL Switch), it uses the S2M BISnp (S2M Back-Invalidate Snoop) channel of CXL.mem to send a POI message containing the failed page address to these target hosts. Upon receiving the message, the POI decoder on the target host translates the CXL address into a local system address and notifies the operating system kernel to perform offline isolation of the page, thereby preventing subsequent access from causing a system crash.

[0028] In actual implementation, embodiments of the present invention add a DCE (Directory-based Coherency Engine) inside the CXL controller to maintain GPD (Global Page Directory) at a granularity of 4 KB per page. The directory entries include: shared memory page address, Host-bitmap (host-memory page mapping graph used to record shared memory pages of the host), page sharing valid bit, and page invalidation taint bit.

[0029] DCE can send page messages, or POIs (PageOffline / Online Invalidate) to all shared hosts via the existing CXL.mem S2M channel. These page messages can be custom-added messages. It should be noted that embodiments of this invention can add a POIDecoder (POI decoder) on the host side. This decoder translates the received POI message and the CXL memory address into a local system address.

[0030] It should be noted that this embodiment of the invention supports dynamic joining / leaving of the shared group by the Host: DCE maintains a HostBitmap for each page in GPD, sets it when joining, clears it when leaving, and immediately pushes an Invalidate for that Host. A PCR is added to DCE to indicate that the page is contaminated and needs to be taken offline.

[0031] In addition, in the CXL.mem protocol, S2MBISnp is a dedicated uplink message. Its core function is: before performing modification operations on the target data, devices with their own memory (such as Type-2 / Type-3 accelerators, memory extenders, etc.) actively send this message to the CPU, requesting the CPU to invalidate or downgrade the cache line in its local cache corresponding to the target data in order to ensure data consistency.

[0032] Therefore, the embodiments of the present invention solve the problem in the prior art where single-machine isolation alone can cause other hosts to still access corrupted memory pages and crash, by working together with the directory-based consistency engine and the switching device, and ensure that fault information is synchronized to the relevant hosts.

[0033] According to one embodiment of the present invention, the storage module 300 further includes at least one memory unit.

[0034] In this configuration, at least one memory unit is communicatively connected to at least one host via a switching device, and the memory unit is configured to store information to be stored by at least one host.

[0035] The storage module 300 is the core hardware component for implementing the shared memory function, and contains one or more memory units; the information to be stored refers to the data that needs to be temporarily stored or persistently saved during the operation of the host.

[0036] Specifically, in one embodiment of the present invention, the storage module 300 integrates at least one memory unit. This memory unit establishes a communication connection with multiple hosts 100 through a CXL Switch (switching device 200) to form a shared memory pool architecture. Each host writes the data it needs to store into this memory unit through the CXL.mem protocol, just like accessing local memory. Since the CXL protocol supports cache consistency, multiple hosts can read and write to the same memory area simultaneously, and the hardware automatically maintains data consistency. In addition, combined with the aforementioned directory-based consistency engine 301, when a specific page in a memory unit fails, the system can accurately locate and notify all hosts that have accessed that page to go offline simultaneously, ensuring data reliability.

[0037] Therefore, the embodiments of the present invention achieve high-density, high-utilization pooled memory resource management, breaking through the memory capacity limitations of a single server machine and supporting multiple hosts to dynamically share the same physical memory unit on demand. This significantly improves the DRAM utilization rate of data centers.

[0038] The memory sharing system proposed in this embodiment of the invention includes: a host, a switching device, a storage module, and a directory-based consistency engine disposed in the storage module. The directory-based consistency engine is communicatively connected to the output of at least one host and is configured to determine a target host containing a backup of a faulty memory page corresponding to the fault information based on fault information from at least one host. The switching device is communicatively connected to both the at least one host and the directory-based consistency engine and is configured to send a first page message generated by the faulty memory page to the target host, causing the target host to remove the faulty memory page. This solves the problem that when any host accesses shared memory and encounters a fault, the inability to synchronize fault information leads to other hosts continuously accessing the wrong page. It enables cross-host synchronization of fault information, improving system stability.

[0039] Embodiments of the present invention also provide a method for synchronizing shared memory, and the method is described in detail below in conjunction with the execution flow of the method for synchronizing shared memory.

[0040] Specifically, Figure 5 This is a flowchart illustrating a shared memory synchronization method provided in an embodiment of the present invention, applied to the aforementioned shared memory system. The method includes the following steps: In step S101, it is determined whether the directory-based consistency engine has received fault information sent by at least one host, including faulty memory pages.

[0041] The fault information is an exception report generated by any host after detecting an uncorrectable memory error (UCE) or a high probability correctable error (CE). It explicitly contains the physical memory address where the fault occurred, i.e., the faulty memory page. This information is usually transmitted by writing PCR in the DCE through MMIO.

[0042] Specifically, the system continuously monitors whether the DCE receives fault information sent by any host through the MMIO channel. For example, when the memory inspection mechanism or ECC error correction unit of any host (such as Host 1) finds that a specific memory page has a serious error that needs to be isolated, it will actively write an instruction to the PCR register of the DCE. This instruction carries the CXL global address of the faulty memory page. Once the DCE detects that the PCR has been written with a valid value, it determines that "fault information has been received" and triggers the subsequent processing flow.

[0043] In actual execution, when any host experiences a non-fatal memory error or a severe memory failure is predicted that page failure isolation is required, the BIOS (Basic Input / Output System) or OS (Operating System) of any host writes a value to the PageControl Register (PCR) in the DCE of the CXL controller via MMIO, indicating that a failure isolation operation needs to be performed on the memory page corresponding to the memory failure storage unit.

[0044] Therefore, embodiments of the present invention ensure that the failure synchronization operation is activated only when a real memory failure occurs, avoiding unnecessary broadcast overhead and improving the fault tolerance and operational reliability of the CXL shared memory system.

[0045] In step S102, when the directory-based consistency engine receives fault information sent by at least one host, the global page directory is queried through the directory-based consistency engine to determine the target host with the backed-up faulty memory page, and the first page message generated based on the faulty memory page is sent to the target host through the switching device.

[0046] The global page directory is a data structure maintained by a directory-based consistency engine. It records the shared state of each page in 4KB memory pages, including the page's CXL global address, valid bit, pollution flag, and Host-bitmap. The target host refers to the host that has a valid bit marked in the Host-bitmap, i.e., the host that is actually backing up, caching, or using the failed memory page. The first page message is a POI message generated by the DEC, transmitted through the S2M BISnp channel in the CXL.mem protocol, used to notify the target host to perform a local invalidation operation on the specified memory page. The switching device, i.e., the CXL Switch, is responsible for routing this control message between the DCE and each host.

[0047] Specifically, in combination Figure 6 As shown, when the DCE confirms receipt of a fault information report from any host containing the address of a faulty memory page, it immediately queries the GPD based on that address to locate the corresponding directory entry and extracts the Host-bitmap field. This field precisely identifies all target hosts that have accessed or cached the faulty page. Subsequently, the DCE generates a POI message (i.e., the first page message) for the faulty memory page and broadcasts it to all target hosts via the existing CXL.mem S2M channel through the CXL switching device. This process does not require modification of the CXL.cache protocol stack, fully reusing the existing consistent message path to ensure low-latency and highly reliable delivery of failure instructions.

[0048] In actual execution, the DCE in the CXL controller uses the corresponding GPD form to match the host-bitmap it marks, and sends POI messages to all hosts sharing the page through the existing CXL.mem S2M channel. The messages are directly put into the CXL.mem S2M channel without touching the CXL.cache format. At the same time, an S2M BISnp message is sent during this process to instruct the host to invalidate the local cache corresponding to the memory.

[0049] Therefore, even if a faulty memory page is detected on only one host, the system can ensure that all other hosts that may access the page take it offline in a timely manner, fundamentally eliminating the risk of multiple nodes crashing due to shared memory page corruption.

[0050] In step S103, the target host is controlled to take the faulty memory page offline based on the first page message.

[0051] Specifically, in this embodiment of the application, a POI Decoder can be added to the host side to translate the memory address of CXL into a local system address after receiving the POI information. After receiving the POI message, the target host instructs the operating system kernel to take the faulty memory page offline.

[0052] Therefore, this embodiment of the invention achieves cross-host collaborative faulty memory page security isolation, enabling all hosts that have shared the page to synchronously complete local offline operations. This not only prevents a single point of failure from spreading to the entire CXL shared memory system, but also ensures business continuity and system stability.

[0053] According to one embodiment of the present invention, the first page message includes the address of the faulty memory page in the storage module. The target host is configured with a page message decoder. Controlling the target host to take the faulty memory page offline based on the first page message includes: converting the address of the faulty memory page in the memory device into a target address of the faulty memory page in the target host based on the page message decoder corresponding to the target host; and controlling the target host to take the faulty memory page offline according to the target address.

[0054] The page message decoder is a hardware or firmware logic unit (i.e., POIDecoder) deployed on the target host side. It is used to parse the received POI message and convert the global address mapping in the CXL memory device into a physical address that can be recognized by the host's local system, i.e., the target address.

[0055] Specifically, when the target host receives the first page message, its built-in page message decoder first extracts the CXL global address of the faulty memory page carried in the message in the storage module. Subsequently, the decoder, according to the CXL memory mapping rules configured on the local machine, accurately translates the global address into the target address corresponding to the physical address space of the local host system. The operating system kernel or platform firmware then locates the local page table entry based on the target address and performs a standard memory page offline operation.

[0056] Therefore, since different hosts may map the same CXL memory page to different local addresses, address translation is completed through the page message decoder, ensuring that the failure instruction is correctly implemented on each host, avoiding missed isolation or false isolation due to address misalignment, and significantly improving the fault tolerance and operational reliability of the CXL shared memory system.

[0057] According to an embodiment of the present invention, the above-described shared memory synchronization method further includes: determining whether a directory-based consistency engine has received online information sent by at least one host; if the directory-based consistency engine receives online information sent by at least one host, then based on the online information, querying the global page directory through the directory-based consistency engine to determine known failed memory pages, and sending a second page message generated based on the known failed memory pages to at least one host through a switching device; and controlling at least one host to take the known failed memory pages offline based on the second page message.

[0058] The online information is the information sent to the directory-based consistency engine (DCE) when any host rejoins the shared memory system; the known failed memory page refers to a memory page that has been marked as offline or unavailable in the global page directory (GPD); the second page message is used to notify the host to perform a local synchronization offline operation on a specific known failed page.

[0059] It is understandable that when a failure occurs during system operation, the above mechanism can be used to perform pageoff. However, if a host system is restarted or all hosts sharing memory are restarted at the same time, it is necessary to check the historical failures after the restart and perform the pageoff function in advance. This can improve system stability. The embodiments of the present invention can provide a restart and isolation measure.

[0060] Specifically, the process first checks if the DCE has received any online notification from any host. Upon detecting a new host online, the DCE immediately traverses the Global Page Directory (GPD) and filters out all memory page entries with a status of "invalid" or "offline." Subsequently, the DCE generates second page messages for each of these known invalid memory pages and forwards these messages to all relevant hosts, including the newly online host, via the CXL switching device. Upon receiving these messages, the page message decoders on each host convert the CXL global address in the message to a local destination address and trigger the operating system to perform the corresponding page offline operation, ensuring that the new host does not mistakenly use memory pages that have been determined to be corrupted by the system.

[0061] In actual execution, when a host is running in the shared memory system and a new host comes online, the isolation steps for the new host are as follows: (1) The new host writes a PCR value to the DCE of the CXL controller through MMIO to indicate that a host has come online. The DCE needs to update the host-bitmap of all forms; (2) The CXL controller sends a POI message to the newly added host through the S2M channel of the existing CXL.mem; the message is directly put into the S2M channel of CXL.mem without touching the CXL.cache format; (3) After the new host receives the POI information, the POI decoder translates the received POI information into the memory address of CXL into the local system address and instructs the operating system kernel to take the page offline.

[0062] Therefore, even if a new host is connected to the system after a failure occurs, it can automatically obtain information about historical failed pages and complete local isolation through the online synchronization process, thereby improving the overall reliability and operational security of the shared memory system.

[0063] According to an embodiment of the present invention, the above-described shared memory synchronization method further includes: determining a master host from at least one host, wherein the master host stores historical failure files; restarting the memory sharing system; and, when the master host is online, determining whether the directory-based consistency engine has received online information from the remaining hosts other than the master host within a preset time period; if the directory-based consistency engine has not received online information from the remaining hosts other than the master host within the preset time period, parsing the historical failure files to determine historical failure memory pages, and sending a third page message generated based on the historical failure memory pages to the online hosts through a switching device, thereby causing the online hosts to take the historical failure memory pages offline.

[0064] The master host is a designated host that continuously records and persistently stores all memory failure information that has occurred during system operation, forming a historical failure file. The third page message is used to proactively notify the online host to perform offline operations on historically failed memory pages during the system recovery phase. The preset duration refers to the system-defined host online waiting window (e.g., 5 minutes).

[0065] Specifically, the system first designates one of multiple hosts as the master host and ensures that it persistently stores historical failure files locally. When the CXL shared memory system restarts due to maintenance or failure, the DCE initiates a monitoring process after the master host comes online: within a preset time period, it checks if any other non-master hosts send online information. If no online information is received from a non-master host within the preset time period, the DCE actively reads the historical failure files provided by the master host, parses out the addresses of all memory pages that were previously marked as failed, generates corresponding third-page messages, and broadcasts these messages to all currently online hosts (at least including the master host) through the switching device (CXLSwitch). Upon receiving the messages, each online host completes the local synchronization and offline of the historically failed memory pages according to the message content.

[0066] In actual implementation, such as Figure 7As shown, host A belongs to master host 101, and the other hosts, including host N, belong to slave host 103, and CXL controller 102. The master host contains all memory address information containing CXL memory isolation, which is stored in the operating system file, named file P here. The slave hosts do not contain it. The specific isolation steps are as follows: (1) Wait for the master host, i.e. host A, to come online. In order to reduce the number of broadcasts, after the master host comes online, wait for the other hosts to come online for 5 minutes. If a slave host comes online within 5 minutes, wait for another 5 minutes until all hosts are identified as online (the rule is to detect that the online interval between any two hosts does not exceed 5 minutes, and no specific time limit is made here). (2) The historical fault isolation process of the operating system parses file P. For each CXL memory address fault parsed, the PCR value is written to the DCE of the CXL controller through MMIO, indicating that the page offline message needs to be sent to all hosts. (3) The CXL controller sends the message to all hosts through the existing S2M channel of CXL.mem. (4) All hosts that receive the POI message will have the message decoded by the POI decoder, and the memory address of the CXL will be translated into the local system address after receiving the POI information, instructing the operating system kernel to take the page offline. (5) After the operating system kernel of the master host takes the page offline, it will write the Dirty value in the PCR form of the DCE of the CXL controller through MMIO, indicating that the page has broadcast information and has been taken offline. (6) When a new fault occurs and the page needs to be taken offline, after the faulty page has been taken offline, the file P needs to be updated synchronously to re-isolate the data source after all hosts are restarted.

[0067] Therefore, the embodiments of the present invention effectively solve the problem of loss or asynchrony of fault status after system-level restart. By using the historical failure files of the master host, the system can still ensure that the online host does not misuse memory pages that have been confirmed to be damaged in the past, even in the absence of global real-time status, thereby preventing the recurrence of old faults and the occurrence of secondary crashes.

[0068] According to an embodiment of the present invention, the above-described shared memory synchronization method further includes: determining whether a directory-based consistency engine has received fault information sent by at least one host, the fault information including faulty memory pages; if the directory-based consistency engine has received fault information sent by at least one host, then performing page failure isolation on the faulty memory pages.

[0069] Specifically, the system continuously monitors whether the DCE receives fault information from any host. Once the DCE confirms that it has received a valid report containing the address of the faulty memory page, it triggers the page failure isolation process: First, it marks the page's status as "failed" in the Global Page Directory (GPD) and records its Host-bitmap to identify all associated hosts; then, it generates a first page message (such as a POI message) and broadcasts it to the relevant hosts through the switching device (CXL Switch), instructing them to take the local page offline; at the same time, the DCE itself also prohibits new access requests to the page.

[0070] Therefore, by isolating faulty memory pages within the storage module, the system effectively prevents multi-host system crashes or data corruption caused by single-point memory failure, thus improving isolation efficiency.

[0071] According to an embodiment of the present invention, the above-described shared memory synchronization method further includes: obtaining a storage instruction from at least one host, the storage instruction including identification information of at least one host and information to be stored; determining a target memory unit corresponding to at least one host from the storage module based on the identification information of at least one host, and storing the information to be stored into the target memory unit through a switching device.

[0072] The storage instruction is a write request initiated by the host to the shared memory system, which includes two key fields: one is the host's identification information used to uniquely identify the host that initiated the request; the other is the information to be stored, i.e. the content that the host needs to write to the shared memory; the target memory unit refers to the physical DRAM area in the storage module 300 that is pre-allocated or dynamically mapped to a specific host, and it has a logical binding relationship with the host identifier.

[0073] Specifically, the system first receives a storage instruction from at least one host and parses out the host identification information and the information to be stored. A directory-based consistency engine or memory management unit then queries a pre-defined mapping table based on this identification information to determine the target memory unit corresponding to that host. For example, Memory Unit A is allocated to Host 1, and Memory Unit B is allocated to Host 2. Subsequently, the system establishes a data path between the host and the target memory unit through a switching device and writes the information to be stored to the designated location via the CXL.mem protocol.

[0074] Therefore, embodiments of the present invention support concurrent writing by multiple hosts to their respective dedicated or shared memory regions, while DCE maintains a consistent state to ensure data isolation and access correctness.

[0075] According to one embodiment of the present invention, after storing the information to be stored into the target memory unit through a switching device, the method includes: obtaining a read instruction from at least one host, the read instruction including identification information of at least one host; determining the memory address of the target memory unit based on the identification information and according to a preset identification information-memory address mapping table; and reading the stored content from the target memory unit through the switching device according to the memory address.

[0076] The read instruction is a data access request initiated by the host to the CXL shared memory system, containing the host identifier information of the initiator to indicate the source of the request. The identifier-memory address mapping table is a metadata structure that is preset or dynamically maintained by the system. It records the correspondence between each host and the target memory unit it is authorized to access, mapping the host identifier to the specific CXL global physical memory address range.

[0077] Specifically, when the system receives a read command from at least one host, it first parses the host identification information. Then, based on the directory-based consistency engine or memory management unit, it queries a pre-defined identifier-memory address mapping table to accurately locate the CXL global memory address corresponding to the target memory unit for that host. Next, the system initiates a read operation based on this address via a CXL switch, extracting the previously stored information to be stored from the target memory unit and returning the data to the requesting host via the CXL.mem protocol channel. This entire process ensures that the host can only access its authorized memory regions, achieving identity-driven targeted reading.

[0078] Therefore, host identity-based reading ensures that the host can only access its authorized memory area, realizing identity-driven targeted reading. Under the shared memory pool architecture, this guarantees data isolation and access controllability in multi-tenant or multi-host environments.

[0079] In summary, the embodiments of the present invention can achieve page-by-page failure push without modifying the CXL.cache link layer, based on the cache consistency mechanism built into the CXL controller, ensuring that all shared hosts immediately and accurately invalidate their local TLB / Cache when a page goes offline / online.

[0080] The shared memory synchronization method proposed in this embodiment of the invention determines whether a directory-based consistency engine has received fault information from at least one host. The fault information includes faulty memory pages. If the directory-based consistency engine has received fault information from at least one host, it queries the global page directory to identify the target host that has backed up the faulty memory pages. Then, it sends a first page message generated based on the faulty memory pages to the target host via a switching device and controls the target host to take the faulty memory pages offline based on the first page message. This solves the problem that when shared memory accessed by any host fails, the fault information cannot be synchronized across hosts, leading to other hosts continuously accessing erroneous pages and causing cross-host memory-related crashes. This application can achieve real-time cross-host synchronization of fault information, preventing other hosts from continuously accessing erroneous shared memory and improving system stability and fault tolerance.

[0081] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method.

[0082] Embodiments of the present invention also provide an electronic device, which may include: The memory 801, the processor 802, and the computer program stored on the memory 801 and capable of running on the processor 802.

[0083] When the processor 802 executes the program, it implements the shared memory synchronization method provided in the above embodiments.

[0084] Furthermore, electronic devices also include: Communication interface 803 is used for communication between memory 801 and processor 802.

[0085] The memory 801 is used to store computer programs that can run on the processor 802.

[0086] The memory 801 may include high-speed RAM memory, and may also include non-volatile memory, such as at least one disk storage device.

[0087] If the memory 801, processor 802, and communication interface 803 are implemented independently, then the communication interface 803, memory 801, and processor 802 can be interconnected via a bus to complete communication between them. The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized into address buses, data buses, control buses, etc. For ease of representation, Figure 8 The bus is represented by a single thick line, but this does not mean that there is only one bus or one type of bus.

[0088] Optionally, in a specific implementation, if the memory 801, processor 802, and communication interface 803 are integrated on a single chip, then the memory 801, processor 802, and communication interface 803 can communicate with each other through an internal interface.

[0089] The processor 802 may be a central processing unit (CPU), an application specific integrated circuit (ASIC), or one or more integrated circuits configured to implement embodiments of the present invention.

[0090] Embodiments of the present invention also provide a computer-readable storage medium storing a computer program configured to execute the steps in any of the above-described shared memory synchronization method embodiments when run.

[0091] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0092] Embodiments of the present invention also provide a computer program product, which includes a computer program that, when executed by a processor, implements the steps in any of the above-described shared memory synchronization method embodiments.

[0093] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0094] The above provides a detailed description of a shared memory synchronization method provided by the present invention. Specific examples have been used to illustrate the principles and implementation methods of the invention. The descriptions of the embodiments above are merely for the purpose of helping to understand the method and core ideas of the present invention. It should be noted that those skilled in the art can make various improvements and modifications to the present invention without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of the present invention.

Claims

1. A memory-sharing system, characterized in that, include: The host, switching device, storage module, and directory-based consistency engine configured in the storage module, wherein, The directory-based consistency engine is communicatively connected to the output of at least one of the hosts, and the directory-based consistency engine is configured to determine the target host that has backed up the faulty memory pages corresponding to the fault information based on the fault information of at least one of the hosts. The switching device is communicatively connected to at least one of the hosts and the directory-based consistency engine, and the switching device is configured to send a first page message generated by the faulty memory page to the target host, causing the target host to take the faulty memory page offline.

2. The memory sharing system according to claim 1, characterized in that, The storage module further includes: At least one memory unit, which is communicatively connected to at least one host via the switching device, is configured to store information to be stored by at least one of the hosts.

3. A method for synchronizing shared memory, characterized in that, The method is applied to the memory sharing system as described in claim 1 or 2, wherein the method includes the following steps: Determine whether the directory-based consistency engine has received at least one fault message sent by the host, the fault message including a faulty memory page; When the directory-based consistency engine receives fault information sent by at least one of the hosts, it queries the global page directory through the directory-based consistency engine to determine the target host that has backed up the faulty memory page, and sends a first page message generated based on the faulty memory page to the target host through the switching device. The target host is controlled to take the faulty memory page offline based on the first page message.

4. The method according to claim 3, characterized in that, The first page message includes the address of the faulty memory page in the storage module. The target host is configured with a page message decoder. Controlling the target host to take the faulty memory page offline based on the first page message includes: Based on the page message decoder corresponding to the target host, the address of the faulty memory page in the memory device is converted into the target address of the faulty memory page in the target host; The target host is controlled to remove the faulty memory page from the target address.

5. The method according to claim 3, characterized in that, Also includes: Determine whether the directory-based consistency engine has received online information from at least one of the hosts; When the directory-based consistency engine receives online information from at least one of the hosts, it queries the global page directory based on the online information to determine known failed memory pages, and sends a second page message generated based on the known failed memory pages to at least one of the hosts through the switching device. Control at least one of the hosts to take the known faulty memory page offline based on the second page message.

6. The method according to claim 3, characterized in that, Also includes: A master host is determined from at least one of the hosts, wherein the master host stores historical failure files; Restart the memory sharing system. If the master host is online, determine whether the directory-based consistency engine has received online information from the remaining hosts other than the master host within a preset time period. If the directory-based consistency engine does not receive online information from the remaining hosts other than the master host within the preset time period, it parses the historical failure file to determine the historical failure memory page, and sends a third page message generated based on the historical failure memory page to the online hosts through the switching device, so that the online hosts take the historical failure memory page offline.

7. The method according to claim 3, characterized in that, Also includes: Determine whether the directory-based consistency engine has received at least one fault message sent by the host, the fault message including a faulty memory page; If the directory-based consistency engine receives fault information from at least one of the hosts, it will isolate the faulty memory page from page failure.

8. The method according to claim 3, characterized in that, Also includes: Obtain at least one storage instruction from the host, the storage instruction including at least one identification information of the host and information to be stored; Based on the identification information of the at least one host, a target memory unit corresponding to the at least one host is determined from the storage module, and the information to be stored is stored in the target memory unit through the switching device.

9. The method according to claim 8, characterized in that, After storing the information to be stored into the target memory unit via the switching device, the process includes: Obtain a read instruction from at least one of the hosts, the read instruction including identification information of at least one of the hosts; Based on the identification information, the memory address of the target memory unit is determined according to a preset identification information-memory address mapping table, and the storage content is read from the target memory unit by the switching device according to the memory address.

10. An electronic device, characterized in that, include: A memory, a processor, and a computer program stored in the memory and executable on the processor, the processor executing the program to implement the shared memory synchronization method as described in any one of claims 1-9.

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