A restart control method and an electronic device

Abstract

The application discloses a restart control method and electronic equipment, and relates to the technical field of server hardware management. The method comprises the following steps: when a server system is restarted, a logical control device sends a power-off instruction to a target voltage regulator corresponding to a target bus device to cut off the power supply to the target bus device; meanwhile, a baseboard controller stops the access operation to the target bus device; and during the server system restart process, the data on the bus between the baseboard controller and the target bus device is captured in real time; whether the baseboard controller has stopped accessing the target bus device is detected; if there is no data transmission on the bus, a power-on instruction is sent to the target voltage regulator to restore the power supply to the target bus device; and after the baseboard controller detects that the power-on self-test operation is completed, the access and monitoring to the target bus device are restored. The abnormal state of the target bus device can be cleared, and through the active intervention mechanism of the power supply time sequence, the problem of restart failure can be fundamentally solved.

Description

Technical Field

[0001] This application relates to the field of server hardware management technology, and in particular to a restart control method and electronic device. Background Technology

[0002] With the rapid development of cloud computing, big data, and artificial intelligence technologies, server systems, as the core hardware for data processing and storage, typically incorporate various bus devices such as network interface cards (NICs), GPU accelerator cards, and storage controllers. As the number of bus devices increases, the requirements for their stable operation also become more stringent. However, server system restarts are a frequent operation, but communication between the bus devices and the server motherboard during restarts may become abnormal due to signal interference, timing conflicts, or other reasons. This can cause the bus devices to enter a suspended state and fail to initialize properly, ultimately leading to the entire server system failing to boot and resulting in a system crash.

[0003] Existing technologies often rely on automatic reset of the server system to solve the problem of bus devices failing to initialize properly during the restart process, thus avoiding the failure of the entire server system to start up and the occurrence of a crash.

[0004] However, existing technical solutions rely on automatic reset of the server system, which cannot effectively clear abnormal states of bus devices, and lack an active intervention mechanism for power supply timing, thus failing to fundamentally solve the problem of restart failure. Summary of the Invention

[0005] This application provides a restart control method and electronic device to effectively clear the abnormal state of bus devices and fundamentally solve the problem of restart failure through an active intervention mechanism for power supply timing.

[0006] This application provides a restart control method, comprising: when the server system restarts, a logic controller sends a power-off command to the target voltage regulator corresponding to the target bus device to control the target voltage regulator to cut off the power supply to the target bus device; simultaneously, the baseboard controller stops accessing the target bus device; during the server system restart process, the logic controller captures data on the bus between the baseboard controller and the target bus device in real time; based on the data on the bus, it detects whether the baseboard controller has stopped accessing the target bus device; if there is no data transmission on the bus, a power-on command is sent to the target voltage regulator to control the target voltage regulator to restore the power supply to the target bus device; when the baseboard controller detects that the power-on self-test operation has ended, it resumes access to and monitoring of the target bus device.

[0007] This application also provides an electronic device, including: a memory for storing a computer program; and a processor for implementing the steps of any of the above-described restart control methods when executing the computer program.

[0008] This application also provides a computer-readable storage medium storing a computer program, wherein the computer program, when executed by a processor, implements the steps of any of the above-described restart control methods.

[0009] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of any of the above-described restart control methods.

[0010] This application discloses a restart control method and an electronic device, wherein the method includes:

[0011] When the server system restarts, the logic controller sends a power-off command to the target voltage regulator corresponding to the target bus device. This controls the target voltage regulator to actively cut off the power supply to the target bus device, directly clearing the abnormal state of the target bus device caused by signal interference and timing conflicts, thus solving the limitation of passively waiting for automatic reset in existing technologies. At the same time, the baseboard controller stops accessing the target bus device to avoid timing conflicts between access actions and power supply switching. During the server system restart process, the logic controller captures data on the bus between the baseboard controller and the target bus device in real time through a preset high-impedance buffer. This real-time detection replaces traditional software polling, ensuring accurate judgment of the access status and solving the problems of detection delay or misjudgment in existing technologies. Then, based on the data on the bus, it detects whether the baseboard controller has stopped accessing the target bus device. If there is no data transmission on the bus, it means that the abnormal state of the device has been completely cleared and there is no risk of access conflict. At this time, the logic controller sends a power-on command to the target voltage regulator to control the target voltage regulator to restore the power supply to the target bus device, avoiding secondary abnormalities caused by blind power-on. When the baseboard controller detects that the power-on self-test operation has ended, it resumes access to and monitoring of the target bus device. Therefore, the restart control method of this application, by first actively powering off to clear the abnormal state, then monitoring in real time to prevent access conflicts, and finally powering on the target bus device, fundamentally solves the problem of abnormal hanging of the target bus device during the restart process in the prior art, and greatly improves the server system restart success rate and the operational stability of the target bus device. Attached Figure Description

[0012] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0013] Figure 1 This application provides a schematic diagram of the structure of a server system according to an embodiment of the present application.

[0014] Figure 2 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application;

[0015] Figure 3 A flowchart illustrating a restart control method provided in this application embodiment. Figure 1 ;

[0016] Figure 4 A flowchart illustrating a restart control method provided in this application embodiment. Figure 2 ;

[0017] Figure 5 A flowchart illustrating a restart control method provided in this application embodiment. Figure 3 ;

[0018] Figure 6 A flowchart illustrating a restart control method provided in this application embodiment. Figure 4 ;

[0019] Figure 7 A flowchart illustrating a restart control method provided in this application embodiment. Figure 5 ;

[0020] Figure 8 A flowchart illustrating a restart control method provided in this application embodiment. Figure 6 . Detailed Implementation

[0021] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0022] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0023] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0024] The specific application environment architecture or specific hardware architecture on which the execution of the restart control method depends is described here.

[0025] Figure 1 This is a schematic diagram of the structure of a server system provided in an embodiment of this application. Figure 1 As shown, the server system 100 includes at least: a baseboard controller (BMC), a logic controller (CPLD), multiple bus devices (PCIe), multiple voltage regulators (VR), a platform control hub (PCH), and a power supply unit (PSU).

[0026] The Baseboard Controller (BMC) is communicatively connected to the Logic Controller (CPLD), multiple PCIe bus devices, and multiple voltage regulators (VRs). It is used to issue commands to the CPLD, PCIe bus devices, and VRs, and to acquire information uploaded by these devices. For example, the BMC communicates with the CPLD to issue configuration commands, such as target bus device identifiers and power-on / off timing parameters; it communicates with the PCIe bus devices for routine access, such as status queries and firmware upgrades; and it communicates with the VRs to obtain power supply status (such as output voltage and current), thus enabling full lifecycle management of the PCIe bus devices.

[0027] Among them, the PCIe bus devices, as external devices of the server system 100, directly affect the server performance due to their operational stability. Each voltage regulator VR is electrically connected to each PCIe bus device to control the power supply to each PCIe bus device, thereby achieving power supply isolation. This means that the power supply control of a single PCIe bus device will not affect other devices, solving the problem of synergistic damage caused by a single device's failure in traditional unified power supply systems.

[0028] The power supply unit (PSU) serves as the power source for the server system 100. The PSU's input is connected to a preset external power supply, which can be selected based on actual needs. For example, the preset external power supply can be 220V AC. The PSU's output is electrically connected to multiple voltage regulators (VRs) to convert the electrical signals from the preset external power supply into the appropriate voltages required by various components in the server system 100. For instance, the CPU in the server system 100 requires 5V, while the baseboard controller (BMC) and memory require 3V. The power requirements of different PCIe bus devices may also vary, therefore each voltage regulator (VR) will be different.

[0029] It should be noted that, since this application focuses on the restart control of the server system 100, the voltage regulator VR mentioned in the following discussion specifically refers to the voltage regulator VR corresponding to each bus device PCIe.

[0030] In addition, it should be noted that the power supply unit (PSU) also feeds back the power supply status to the logic controller (CPLD) through power timing signals (such as PWR_GOOD) to ensure that the CPLD only performs the power-on operation when the power supply is stable, thus avoiding equipment damage caused by voltage fluctuations.

[0031] The output of the CPLD (Content Logic Controller) is electrically connected to the control terminals of multiple voltage regulators (VRs), allowing it to directly drive the switching states of the voltage regulators, such as triggering power-off with a low output level and power-on with a high output level, avoiding software scheduling delays. The CPLD connects to the first preset communication bus between the baseboard controller (BMC) and multiple PCIe devices via a preset high-impedance buffer. This allows for real-time capture of communication data on the bus (such as access frames from the BMC) while maintaining the original bus signal level and communication impedance due to its high impedance, ensuring accurate detection and secure communication. Both the first preset communication bus and the preset high-impedance buffer can be selected based on actual conditions; for example, the first preset communication bus can be an I2C bus. The preset high-impedance buffer, due to its high impedance, does not alter the signal level, communication impedance, or transmission timing of the first preset communication bus, ensuring uninterrupted communication between the baseboard controller and the target bus devices. Furthermore, the preset high-impedance buffer can copy the communication data on the first preset communication bus (such as I2C bus start signals, device addresses, read / write commands, and data frames) in real time and transmit this data to the CPLD, providing the original data for subsequent detection.

[0032] The platform control hub (PCH) serves as the distribution device for the system reset signal of the server system 100. It connects to the baseboard controller (BMC) via a second preset communication bus to send a global reset signal (such as LRESET#) to the BMC. The second preset communication bus can be selected based on actual needs. For example, it can be an LPC (Low Pin Count) bus. When the server system 100 restarts, the platform control hub (PCH) triggers the baseboard controller (BMC) to synchronously stop accessing the devices on the second preset communication bus (such as the baseboard controller), thus avoiding timing conflicts between the baseboard controller's access operations and the device reset sequence.

[0033] Among them, the logic control device CPLD is used to execute the steps of the restart control method.

[0034] The server system provided in this application comprises at least a baseboard controller, logic controllers, multiple bus devices, multiple voltage regulators, a platform control center, and a power supply unit. The baseboard controller is communicatively connected to the logic controllers, multiple bus devices, and multiple voltage regulators, enabling monitoring of the status of multiple bus devices and issuing commands, thus laying the foundation for coordinated restart control. Each voltage regulator is electrically connected to each bus device, achieving independent power supply isolation for each bus device, preventing the reset of a single bus device from affecting the operation of other devices, and improving the flexibility of the server system. The output of the power supply unit is electrically connected to multiple voltage regulators to provide a stable and continuous power supply to each bus device, ensuring power supply during restart. The reliability of the switching is ensured. The output of the logic controller is electrically connected to the control terminals of multiple voltage regulators, which can directly drive the power supply switch to achieve timing response and meet the requirements of rapid power-off and power-on during restart. The logic controller is connected to the first preset communication bus between the baseboard controller and multiple bus devices through a preset high-impedance buffer. This allows it to capture bus communication data in real time to determine the access status of the baseboard controller, and its high impedance characteristics do not interfere with the normal communication of the original first preset communication bus, ensuring detection accuracy and communication security. The platform control center is connected to the baseboard controller through a second preset communication bus, which can synchronously distribute system reset signals to ensure that the reset timing of the baseboard controller and the target bus devices is coordinated, avoiding conflicts between access operations and reset processes. Therefore, the server system of this application can realize the integrated execution of signal detection and power supply control, fundamentally solving the problems of high latency and easy timing mismatch in traditional software control, and significantly improving the success rate of bus device restart initialization and the operational stability of the server system.

[0035] Optionally, Figure 2 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Figure 2 As shown, the electronic device 200 may include a processor 210 and a memory 220.

[0036] The memory 220 stores machine-executable instructions that can be executed by the processor 210. When the electronic device 200 is running, these machine-executable instructions are executed. The processor 210 and the memory 220 communicate via a bus. The processor 210 can execute these machine-executable instructions to implement a restart control method.

[0037] The memory 220, processor 210, and bus components are electrically connected directly or indirectly to enable data transmission or interaction. For example, these components can be electrically connected to each other via one or more communication buses or signal lines. The mobile storage device includes at least one software function module that can be stored in the memory 220 or embedded in the operating system (OS) of the electronic device in the form of software or firmware. The processor 210 is used to execute executable modules stored in the memory 220, such as software function modules and computer programs included in the restart control method of the mobile storage medium.

[0038] The memory 220 may be, but is not limited to, random access memory (RAM), read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), etc.

[0039] The electronic device 200 is embedded in the baseboard controller (BMC) and is the core functional unit of the BMC. The electronic device 200's memory stores a computer program (or embedded software) capable of executing a restart control method. Its processor executes this program to make strategy decisions and generate instructions for the restart control process, providing software-level decision support for the overall control logic.

[0040] It should be noted that the aforementioned electronic device 200 and logic controller CPLD have a clear division of labor in terms of function: the electronic device 200 focuses on program storage and software logic execution, undertaking decision-making tasks with high strategic and flexible requirements; while the logic controller CPLD focuses on operation, responsible for handling core steps with extremely high real-time requirements. Together, they form a complete execution chain for the restart control method.

[0041] The restart control method provided in the embodiments of this application will be explained further below. Figure 3 A flowchart illustrating a restart control method provided in this application embodiment. Figure 1 .like Figure 3 As shown, the method may include:

[0042] S310. When the server system restarts, the logic controller sends a power-off command to the target voltage regulator corresponding to the target bus device to control the target voltage regulator to cut off the power supply to the target bus device; at the same time, the baseboard controller stops accessing the target bus device.

[0043] In one possible implementation, when the server system restarts, the corresponding server restart event is caused by routine maintenance, firmware upgrades, or fault recovery. In this case, it is necessary to prioritize resolving the abnormal state of the target bus device (such as a PCIe device) due to signal interference or timing conflicts to avoid initialization failure after restarting. Therefore, the following two actions need to be performed simultaneously: the logic controller generates a power-off command and sends it to the target voltage regulator. After receiving the command, the target voltage regulator directly drives the target voltage regulator to cut off the power supply link of the target bus device. This active power-off clears the abnormal state of the target bus device (such as register lock-up, abnormal link communication, etc.), breaking the limitation of passively waiting for automatic reset in existing technologies. Moreover, due to the power supply isolation design, it will not affect the normal operation of other bus devices.

[0044] Simultaneously, the baseboard controller maintains a communication connection with the target bus device via a first preset communication bus (such as an I2C bus) for daily access and monitoring. When the logic controller sends a power-off command, the baseboard controller responds to the LPC reset signal from the platform control center, actively ceasing to send access commands to the target bus device, such as status queries and data read / write operations. This avoids timing conflicts where the target bus device is powered off while the baseboard controller is still accessing it, preventing deadlock or signal interference on the first preset communication bus (such as an I2C bus), and clearing obstacles for the subsequent complete reset and precise power-on of the target bus device. The LPC reset signal is used to indicate that the device on the LPC bus has entered a reset state.

[0045] S320. During the server system restart process, the logic controller captures data on the bus between the baseboard controller and the target bus device in real time.

[0046] S330. Based on the data on the bus, detect whether the board controller has stopped accessing the target bus device.

[0047] The access operations include at least the following communication behaviors: read / write commands, status queries, etc.

[0048] In one possible implementation, during the server system restart process, the server system first initiates a Power-On Self-Test (POST) operation and initializes all devices in the server system. Then, the logic controller uses a preset high-impedance buffer to capture data on the bus between the baseboard controller and the target bus device in real time, and parses the captured bus data in real time. Based on the parsed bus data, it checks whether the baseboard controller has stopped accessing the target bus device. If so, step S340 is executed; otherwise, it is determined that the baseboard controller has not stopped accessing the target bus device, and the system continues to wait.

[0049] S340. If there is no data transmission on the bus, a power-on command is sent to the target voltage regulator to control the target voltage regulator to restore power supply to the target bus device.

[0050] In one possible implementation, if there is no data transmission on the bus, it is determined that the baseboard controller has stopped accessing the target bus device. The logic controller then sends a power-on command to the unique target voltage regulator corresponding to the target bus device to control the target voltage regulator to restore power supply to the target bus device. This avoids the problem of blindly following the server system reset sequence for power-on in the prior art, which leads to access conflicts during power-on. This ensures the timeliness of power restoration, allowing the target bus device to start initialization in an environment without communication interference. From the perspective of power supply and communication coordination, this completely solves the problem of the target bus device easily getting stuck during restart, and improves reset reliability.

[0051] S350. When the baseboard controller detects that the power-on self-test operation has ended, it restores access to and monitoring of the target bus device.

[0052] In one possible implementation, when the baseboard controller receives a Power-On Self-Test (POST) end signal via a second preset communication bus with the platform control center, it determines that the POST operation has ended. This means that the target bus device has completed hardware initialization and is ready for normal communication. At this point, the baseboard controller resumes access to and monitoring of the target bus device, which may include sending status query commands, verifying device configuration parameters, and collecting real-time operating data (such as temperature and link bandwidth).

[0053] The restart control method provided in this application involves the following steps: When the server system restarts, the logic controller sends a power-off command to the target voltage regulator corresponding to the target bus device. This commands the target voltage regulator to actively cut off the power supply to the target bus device, directly clearing the abnormal state of the target bus device caused by signal interference and timing conflicts, thus solving the limitation of passively waiting for automatic reset in existing technologies. Simultaneously, the baseboard controller stops accessing the target bus device to avoid timing conflicts between access actions and power supply switching. During the server system restart process, the logic controller uses a preset high-impedance buffer to capture data on the bus between the baseboard controller and the target bus device in real time. This real-time detection replaces traditional software polling, ensuring accurate judgment of the access status and solving the problems of detection delay or misjudgment in existing technologies. Based on the data on the bus, the logic controller checks whether it has stopped accessing the target bus device. If there is no data transmission on the bus, it indicates that the abnormal state of the device has been completely cleared and there is no risk of access conflict. At this time, the logic controller sends a power-on command to the target voltage regulator to restore the power supply to the target bus device, avoiding secondary abnormalities caused by blind power-on. When the baseboard controller detects that the power-on self-test operation has ended, it resumes access to and monitoring of the target bus device. Therefore, the restart control method of this application, by first actively powering off to clear the abnormal state, then monitoring in real time to prevent access conflicts, and finally powering on the target bus device, fundamentally solves the problem of abnormal hanging of the target bus device during the restart process in the prior art, and greatly improves the server system restart success rate and the operational stability of the target bus device.

[0054] Optionally, the above restart control method further includes:

[0055] The logic controller uses a global reset signal to detect whether the server system has restarted.

[0056] The global reset signal is a hardware synchronization signal in the server system used to characterize a restart event. When the server system is restarted due to maintenance, upgrade or failure, the global reset signal will generate a specific level change (such as an edge signal that jumps from high level to low level) to synchronously transmit the instruction that the server system is about to restart to each hardware component.

[0057] In one possible implementation, the logic controller directly accesses the global reset signal through a preset signal detection circuit. Utilizing the characteristics of the global reset signal itself, its status is monitored in real time. When a transition or a valid low level is detected in the global reset signal, it is determined that the server system has restarted. The preset signal detection circuit can be selected based on the specific circumstances.

[0058] The restart control method provided in this application uses a logic controller device based on a global reset signal to detect whether the server system has restarted. This triggers subsequent operations as soon as a restart event occurs, ensuring immediate intervention in the restart process. This lays the foundation for clearing target bus device anomalies and avoiding timing conflicts, thus ensuring the real-time performance and accuracy of restart control from the triggering source.

[0059] Optionally, the global reset signal includes the server system reset signal SYS_RST#.

[0060] Among them, the server system reset signal SYS_RST# is a global synchronous reset hardware signal. Its function is: when the server system needs to restart due to user-initiated restart, hardware failure (such as abnormal voltage, overheat protection, etc.), firmware initialization, etc., the platform control center or motherboard reset controller generates and distributes this global reset signal to the server system, notifying each device in the server system to enter the reset state, ensuring that each device synchronously terminates the current operation and clears abnormal states (such as register lock-up, link conflict, etc.), laying the foundation for the initialization after the server system restarts.

[0061] In the above method, the logic controller detects whether the server system has restarted based on a global reset signal, including:

[0062] If the logic controller detects that the server system reset signal changes from high to low and remains low for a first preset time period, it determines that the server system has restarted.

[0063] The first preset time period can be selected according to the actual situation. For example, the first preset time period can be selected as 50ms.

[0064] In one possible implementation, the logic controller detects the level of the server system reset signal SYS_RST#. When it detects that the server system reset signal SYS_RST# changes from a high level during normal operation to a low level when the reset is effective, and the duration of this low level state meets a first preset time period (e.g., 50ms), it can determine that the server system has restarted.

[0065] The low-level state is maintained for a first preset time period to filter out false triggers caused by transient noise.

[0066] The restart control method provided in this application uses a global reset signal, which is the server system reset signal. When the logic controller detects that the server system reset signal changes from a high level to a low level and the low level persists for a first preset time period, it determines that the server system has restarted. Through the dual judgment mechanism of level state transition recognition and the first preset time period, the true restart trigger event is effectively captured, eliminating false detections caused by noise interference. This ensures that the logic controller can reliably start subsequent restart processes such as power-off control and access status monitoring. The accuracy and stability of restart control are guaranteed from the trigger source, avoiding abnormal power-off or control failure of the target bus device due to misjudgment.

[0067] Optionally, the global reset signal includes: a server system reset signal and a power timing signal.

[0068] Among them, the power timing signal PWR_GOOD is a power supply status feedback signal output by the power supply unit. It is typically active high. When the output voltage of the power supply unit is stable within a preset range and the power supply capacity meets the requirements of the server system, the power timing signal PWR_GOOD is generated and sent to components such as logic controllers and board controllers to indicate that the power supply system is ready. This provides a basis for subsequent power-on, power supply switching and other operations. The power timing signal PWR_GOOD is used to provide real-time feedback on the power supply status, avoiding blind power-on due to voltage fluctuations, which could lead to damage to the target bus devices. It provides a reliable guarantee for accurate power-on in restart control.

[0069] Among them, the global synchronization characteristic of the server system reset signal SYS_RST# can be used to capture real restart events, and the transition of the power timing signal PWR_GOOD can verify the power supply stability.

[0070] Figure 4 A flowchart illustrating a restart control method provided in this application embodiment. Figure 2 .like Figure 4 As shown, in the above method, the logic controller detects whether the server system has restarted based on a global reset signal, including:

[0071] S410, the logic controller detects that the server system reset signal changes from a first high level to a first low level, and the first low level lasts for a first preset time period.

[0072] The first preset time period can be selected according to the actual situation. For example, the first preset time period can be selected as 100ms.

[0073] In one possible implementation, the logic controller first monitors the server system reset signal SYS_RST# in real time. When it detects that the server system reset signal SYS_RST# changes from the first high level of normal operation to the first low level of reset effectiveness, and the duration of the first low level reaches a first preset time period (e.g., 100ms), secondary verification is initiated.

[0074] The first low level lasts for a first preset time period to confirm that the server system reset signal SYS_RST# is not transient noise.

[0075] S420. If the power timing signal undergoes a signal transition for a second preset time period during the first low-level duration, it is determined that the server system has restarted.

[0076] The first preset time period is longer than the second preset time period. The second preset time period is used for the brief switching process of the power supply system during restart. The second preset time period can be selected according to the actual situation. For example, the second preset time period can be selected as 20ms.

[0077] In one possible implementation, during a first low-level duration of a preset time period, the power timing signal PWR_GOOD is synchronously detected. If a level transition in the power timing signal PWR_GOOD that matches a restart scenario is detected, such as a transition from stable power supply to brief fluctuation and then back to stable, and the transition duration is a second preset time period (e.g., 20ms), it is ensured that the transition of the power timing signal is a related response triggered by a restart, rather than an unrelated power supply fluctuation. Finally, by combining the dual signals and time constraints, it is determined that the server system has actually restarted.

[0078] The restart control method provided in this application uses a global reset signal composed of a server system reset signal and a power timing signal. The logic controller detects that the server system reset signal transitions from a first high level to a first low level, and the first low level lasts for a first preset time period. Simultaneously, within the first preset time period, the power timing signal undergoes a signal transition for a second preset time period. The first preset time period is longer than the second preset time period, ensuring that power supply status verification is completed before reset determination, avoiding misjudgments due to unstable power supply, thus confirming that the server system has restarted. Therefore, this application, through a dual detection mechanism of server system reset signal triggering and power timing signal verification, effectively filters out false triggers caused by transient electromagnetic interference and power supply fluctuations, significantly improving the accuracy and reliability of restart determination. This provides a basis for the precise initiation of subsequent restart control procedures, avoiding abnormal power outages or control failures of target bus devices caused by misjudgments.

[0079] Optionally, before the logic controller detects whether the server system has restarted based on a global reset signal, the method further includes:

[0080] The baseboard controller sends configuration commands to the logic controller.

[0081] The configuration command is used to instruct the target bus device to perform a power-off operation when the server system restarts.

[0082] In one possible implementation, the baseboard controller sends a configuration command to the logic controller to enable the logic controller to set up a power-off operation on the target bus device when the server system restarts.

[0083] It should be noted that this configuration command only needs to be set once and is permanently effective. Once the baseboard controller sends and completes the configuration, the logic controller will store the configuration instruction in a non-volatile logic unit. Subsequently, the server system will automatically execute the power-off control of the target bus device each time it restarts, without needing to send the command again. Furthermore, this function is designed as a flexible on / off switch. That is, if it is necessary to cancel the automatic power-off of the target bus device during server system restart, the baseboard controller needs to send a separate cancellation command to the logic controller. Upon receiving the command, the logic controller will update its logic configuration and terminate the corresponding automatic power-off trigger mechanism, ensuring the flexibility and adaptability of the function control.

[0084] The restart control method provided in this application involves the baseboard controller sending a configuration command to the logic controller. This configuration command instructs the target bus device to perform a power-off operation when the server system restarts. Therefore, this application simplifies the control process by setting the configuration command once, eliminating the need to repeatedly issue commands before each restart.

[0085] Figure 5 A flowchart illustrating a restart control method provided in this application embodiment. Figure 3 .like Figure 5 As shown, in the above method, the baseboard controller sends configuration commands to the logic controller, including:

[0086] S510: The baseboard controller sends configuration command frames to the logic controller via a preset communication bus.

[0087] The configuration command frame is used to instruct whether to enable or disable the power-off operation on the target bus device when the server system restarts. The preset communication bus can be selected according to actual needs. For example, the preset communication bus can be I2C.

[0088] In one possible implementation, the baseboard controller and the logic controller interact with each other via a preset communication bus (such as I2C). It should be noted that the configuration command frame sent by the baseboard controller is a structured data packet. The configuration command frame includes at least the following fields: function identifier, target device information, enable or disable instruction, etc., rather than a single instruction. This structured design can ensure the accuracy of configuration command transmission, avoid information loss or misinterpretation, and provide a basis for subsequent function control.

[0089] S520: After the baseboard controller sends the configuration command frame, it waits for the logic controller to return the confirmation frame.

[0090] In one possible implementation, after the baseboard controller sends a configuration command frame, it does not immediately determine that the configuration is successful, but instead enters a waiting state to receive an acknowledgment frame from the logic controller.

[0091] The acknowledgment frame is a response signal returned by the logic controller through the same preset communication bus after receiving the configuration command frame. This response signal can verify that the configuration command has been correctly received by the logic controller and can also prevent the configuration command from being lost and undetected due to bus interference, transmission delay, etc.

[0092] S530. If the baseboard controller does not receive an acknowledgment frame from the logic controller, the baseboard controller will resend the configuration command frame after a preset time.

[0093] The preset duration can be selected according to the actual situation. For example, the preset duration can be selected as 50ms.

[0094] In one possible implementation, if the baseboard controller does not receive an acknowledgment frame within a preset time (e.g., 50ms), it is determined that the configuration command frame transmission has failed. In this case, the configuration command frame will be automatically retransmitted after the preset time (e.g., 50ms). This retransmission mechanism can effectively compensate for the unreliability of a single transmission, ensuring that the configuration command to enable or disable the power-off function is ultimately received by the logic controller, thus guaranteeing the achievability of the function configuration.

[0095] It should be noted that the number of times the above-mentioned configuration command frame is resent is generally set to a maximum of 3 times. If no acknowledgment frame is received after more than 3 times, it is determined that there is an abnormality in the communication link between the baseboard controller and the logic control device, and manual intervention is required for maintenance.

[0096] The restart control method provided in this application involves a baseboard controller sending a configuration command frame to a logic controller via a preset communication bus. After sending the configuration command frame, the baseboard controller waits for an acknowledgment frame from the logic controller. If it does not receive the acknowledgment frame from the logic controller within a preset time period, the baseboard controller retransmits the configuration command frame after the preset time period to ensure that the configuration command frame is effectively delivered and received and parsed by the logic controller, thus avoiding functional configuration failure due to a single transmission failure. At the same time, the configuration command frame supports bidirectional control of enabling and disabling functions, which not only adapts to the usage requirements in different scenarios but also ensures the accuracy of the configuration status through a reliable transmission mechanism, thus balancing functional flexibility and the reliability of command transmission.

[0097] Figure 6 A flowchart illustrating a restart control method provided in this application embodiment. Figure 4 .like Figure 6 As shown, in the above method, the baseboard controller stops accessing the target bus device, including:

[0098] S610. When the server system restarts, the platform controller drives the first reset signal to switch from the second high level to the second low level, and the second low level continues for a third preset time period.

[0099] The third preset time period can be selected according to the actual situation. For example, the third preset time period can be selected as 30ms.

[0100] In one possible implementation, when the server system restarts, the platform controller actively drives the first reset signal to complete a level switch, that is, from the second high level when the server system is running normally to the second low level that indicates that the reset is effective. This second low level will last for a third preset time period (such as 30ms) to avoid false triggering caused by transient noise, and ensure that the board controller, logic control devices and other components synchronously perceive the restart event, laying the signal foundation for subsequent collaborative operation.

[0101] S620: The baseboard controller detects the second low level of the first reset signal and triggers an interrupt mode for the access operation to the target bus device to stop the access operation to the target bus device.

[0102] In one possible implementation, the baseboard controller monitors the level of the first reset signal in real time. When the first reset signal is detected to be at a second low level, it immediately triggers its own interrupt mode for accessing the target bus device. This avoids communication conflicts or target bus device hangs caused by continued access during restart. It ensures that the timing of power-off and access stop actions of the baseboard controller and logic controller are coordinated, providing an interference-free environment for clearing anomalies when the target bus device is powered off, thus solving the problem of access stop delay in the prior art.

[0103] This interrupt mode allows the baseboard controller to instantly suspend all access behaviors to the target bus device (such as read / write commands, status queries, etc.), rather than gradually stopping them through software polling.

[0104] The restart control method provided in this application, when the server system restarts, drives the first reset signal to switch from a second high level to a second low level, and the second low level continues for a third preset time period to ensure that the first reset signal is effective and avoid false triggering; the baseboard controller detects the second low level of the first reset signal and immediately triggers the interrupt mode of the access operation to the target bus device to stop the access operation to the target bus device. By triggering the access interruption synchronously through the first reset signal, the delay problem of traditional software-level access stop is avoided, ensuring that the access operation has no timing conflict with subsequent power supply switching, abnormal clearing and other processes, providing an interference-free environment for power-off and abnormal clearing of the target bus device, further consolidating the reliability of restart control, and effectively avoiding target bus device reset failure due to access not stopping in time.

[0105] Optionally, the data on the bus includes at least: clock data SCL and corresponding link data SDA.

[0106] The clock data SCL is the time reference signal of the communication bus, carried by the bus's clock line. It generates high and low level transitions at a fixed frequency, clearly defining the start of transmission and sampling timing for each bit of data, ensuring complete synchronization of the operation timing between the sender and receiver, and avoiding data misalignment caused by transmission speed mismatch.

[0107] Link data SDA is the actual valid information data transmitted on the communication bus, carried by the data lines on the bus. This link data SDA includes at least: device address, read / write commands, configuration parameters, status feedback, and other specific service information, and must be transmitted in strict accordance with the timing rules defined by clock data SCL.

[0108] It should be noted that each bit of link data SDA on the bus is matched one-to-one with a specific time point of clock data SCL. Only by relying on the synchronization of clock data SCL can link data SDA be correctly identified and parsed.

[0109] Figure 7 A flowchart illustrating a restart control method provided in this application embodiment. Figure 5 .like Figure 7 As shown, in the above method, the logic controller captures data on the bus between the baseboard controller and the target bus device in real time, including:

[0110] The S710 logic controller monitors the level status of clock data and corresponding link data in real time.

[0111] In one possible implementation, the logic controller monitors the level of clock data SCL and the corresponding link data SDA in real time to provide a basis for accurately capturing valid data, ensuring that no key timing nodes on the communication bus are missed, and providing real-time data support for judging the communication status between the baseboard controller and the target bus device.

[0112] When the S720 logic controller detects that the clock data is at the third high level, the corresponding link data jumps from the fourth high level to the fourth low level, and the logic controller starts to capture data on the bus.

[0113] In one possible implementation, when the logic controller detects that the clock data SCL is at the third high level, it signifies that the data on the bus has entered a critical stage of stable data transmission. Simultaneously, it detects that the corresponding link data SDA transitions from the fourth high level to the fourth low level; this transition is a typical signal characteristic of a communication bus initiating effective communication (such as the start signal of an I2C bus). Once these two timing matching conditions are met, the logic controller immediately begins data capture. This avoids false captures caused by noise or invalid signals and accurately captures the actual communication data, providing a reliable initial basis for subsequently determining whether the board controller should stop accessing the target bus device.

[0114] The restart control method provided in this application includes at least clock data and corresponding link data on the bus. The logic controller monitors the level status of the clock data and the corresponding link data in real time. When the logic controller detects that the clock data is at the third high level, if the corresponding link data jumps from the fourth high level to the fourth low level, the logic controller starts capturing the data on the bus to effectively filter out bus noise and false captures caused by invalid signals. This ensures that only real and valid communication data is captured, providing a reliable source for subsequent accurate detection of whether the board controller has stopped accessing the target bus device. This ensures the accuracy of the status judgment in the restart control process from the data source.

[0115] Figure 8 A flowchart illustrating a restart control method provided in this application embodiment. Figure 6 .like Figure 8 As shown, the above method detects whether the board controller has stopped accessing the target bus device based on data on the bus, including:

[0116] The S810 logic controller parses the data on the bus to obtain link parsing data.

[0117] In one possible implementation, the logic controller performs timing decoding and format parsing on the previously captured bus data (such as clock data SCL and link data SDA) to ultimately obtain structured link parsing data.

[0118] The timing decoding and format parsing process must strictly follow the communication bus protocol, such as extracting key information like device address, read / write instruction identifier, and data frame type, and eliminating noise signals and invalid data to ensure that the link parsing data can truly reflect the core content of the communication bus and provide accurate data support for subsequent status judgment.

[0119] S820: Based on the link parsing data, determine whether the baseboard controller has stopped accessing the target bus device.

[0120] In one possible implementation, the logic controller determines whether the baseboard controller has stopped accessing the target bus device based on the parsed link resolution data. If no access command (such as a read / write command, status query frame, etc.) matching the target bus device address appears in the link resolution data, it is determined that the baseboard controller has stopped accessing the device; if an access command matching the target bus device address still appears in the link resolution data, it is determined that access has not stopped. This judgment method is directly based on the actual bus communication content, avoiding the delays and misjudgments of traditional software detection, providing a reliable basis for the subsequent accurate sending of power-on commands, and ensuring no communication timing conflicts when power is restored.

[0121] The restart control method provided in this application involves a logic controller parsing data on the bus to obtain link parsing data. Based on this link parsing data, it can be determined whether the baseboard controller has stopped accessing the target bus device, thereby effectively filtering out misjudgments caused by bus noise and invalid signals. This ensures more accurate judgment of the access status and provides a reliable basis for subsequent timing control of power-on after confirming that access has stopped, avoiding power supply and access conflicts caused by misjudgments and further improving the stability of restart control.

[0122] To facilitate understanding of the above-described restart control method, this application embodiment also provides an example of a restart control method, which will be further described below. This restart control method may include the following steps:

[0123] The baseboard controller sends a configuration command to the logic controller. This command instructs the target bus device to perform a power-off operation when the server system restarts. The logic controller detects whether the server system has restarted based on a global reset signal. When the logic controller detects a server system restart, it sends a power-off command to the target voltage regulator corresponding to the target bus device, controlling the target voltage regulator to cut off power to the target bus device. Simultaneously, the baseboard controller stops accessing the target bus device after detecting an LPC reset signal. The LPC reset signal instructs each device on the LPC bus to enter a reset state. After restarting, the server system initiates a power-on self-test and initializes the system. The logic controller captures data on the I2C bus between the baseboard controller and the target bus device in real time, detecting whether the baseboard controller has stopped accessing the target bus device based on the bus data. If no data is transmitted on the bus, it is determined that the baseboard controller has stopped accessing the target bus device. The logic controller sends a power-on command to the target voltage regulator, controlling it to restore power to the target bus device. When the baseboard controller detects that the power-on self-test has ended, it resumes access to and monitoring of the target bus device.

[0124] The restart control method provided in this application effectively solves the problem of abnormal hang-up of target bus devices during traditional restart processes through power supply timing intervention and state clearing mechanisms, ensuring that the target bus devices can be initialized normally after restarting and reducing the probability of server system startup failure. At the same time, it realizes an automated repair mechanism, which can complete the reset of the target bus devices without manual intervention, significantly shortening the average repair time and enhancing the automation capabilities of the server system. In addition, it reduces service interruptions caused by hardware failures, improves overall service continuity and user satisfaction, and is not only applicable to regular server system restarts, but also adaptable to special scenarios such as hot-swapping, enhancing the adaptability of the server system. All these advantages employ a self-healing scheme with BMC-CPLD-VR three-level collaborative control, enabling precise power-off and power-on control of target bus devices. The logic controller dynamically adjusts the power supply sequence of the target bus devices during the server system restart process, ensuring complete discharge before power-on and mitigating potential electrical and system software issues. An effective communication state residue clearing mechanism between the baseboard controller and the target bus devices ensures proper device initialization. A configuration command transmission and execution mechanism is designed for one-time setup and permanent effect; when the baseboard controller sends a restart command to the logic controller, the target bus device power-off command remains valid until a cancellation instruction is received. The logic controller monitors the system restart and executes the corresponding power-off and power-on operation. Simultaneously, the baseboard controller initiates monitoring of the target bus devices after power-on self-test, ensuring the safety and accuracy of the entire operation.

[0125] Optionally, embodiments of this application also provide a computer-readable storage medium storing a computer program. When the computer program is executed by a processor, the processor performs the steps of the removable storage medium restart control method described in the above embodiments. The specific implementation and technical effects are similar and will not be repeated here.

[0126] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0127] Embodiments of this application also provide a computer program product, which includes a computer program that, when executed by a processor, implements the steps in any of the above-described restart control method embodiments.

[0128] Embodiments of this application also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps in any of the above-described restart control method embodiments.

[0129] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0130] The restart control method and electronic device provided in this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only intended to help understand the method and core ideas of this application. It should be noted that those skilled in the art can make several improvements and modifications to this application without departing from the principles of this application, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A restart control method characterized by comprising: include: When the server system restarts, the logic controller sends a power-off command to the target voltage regulator corresponding to the target bus device to control the target voltage regulator to cut off the power supply to the target bus device; at the same time, the baseboard controller stops accessing the target bus device. During the server system restart process, the logic controller captures data on the bus between the baseboard controller and the target bus device in real time; Based on the data on the bus, detect whether the baseboard controller has stopped accessing the target bus device; If there is no data transmission on the bus, a power-on command is sent to the target voltage regulator to control the target voltage regulator to restore power supply to the target bus device; When the baseboard controller detects that the power-on self-test operation has ended, it resumes access to and monitoring of the target bus device; The data on the bus includes at least clock data and corresponding link data; the logic controller captures data on the bus between the baseboard controller and the target bus device in real time, including: The logic controller monitors the clock data and the corresponding link data level status in real time. When the logic controller detects that the clock data is at the third high level, the corresponding link data jumps from the fourth high level to the fourth low level, and the logic controller starts to capture data on the bus.

2. The method of claim 1, wherein, The method further includes: The logic controller detects whether the server system has restarted based on a global reset signal.

3. The method of claim 2, wherein, The global reset signal includes a server system reset signal; the logic controller detects whether the server system has restarted based on the global reset signal, including: If the logic controller detects that the server system reset signal changes from high level to low level and the low level lasts for a first preset time period, it determines that the server system has restarted.

4. The method of claim 2, wherein, The global reset signal includes: a server system reset signal and a power timing signal; the logic controller detects whether the server system has restarted based on the global reset signal, including: The logic controller detects that the server system reset signal changes from a first high level to a first low level, and the first low level lasts for a first preset time period; If the power timing signal undergoes a signal transition for a second preset time period during the first low-level duration, it is determined that the server system has restarted. Wherein, the first preset time period is longer than the second preset time period.

5. The method of claim 2, wherein, Before the logic controller detects whether the server system has restarted based on a global reset signal, the method further includes: The baseboard controller sends a configuration command to the logic controller; the configuration command is used to instruct the target bus device to perform a power-off operation when the server system restarts.

6. The method of claim 5, wherein, The baseboard controller sends configuration commands to the logic controller, including: The baseboard controller sends configuration command frames to the logic controller via a preset communication bus; After the baseboard controller sends the configuration command frame, it waits for the confirmation frame returned by the logic controller. If the baseboard controller does not receive the confirmation frame from the logic controller, the baseboard controller will resend the configuration command frame after a preset time. The configuration command frame is used to indicate whether to enable or disable the power-off operation of the target bus device when the server system restarts.

7. The method of claim 1, wherein, The baseboard controller stops access to the target bus device, including: When the server system restarts, the platform controller drives the first reset signal to switch from a second high level to a second low level, and the second low level lasts for a third preset time period; The baseboard controller detects a second low level of the first reset signal and triggers an interrupt mode for accessing the target bus device to stop the access operation to the target bus device.

8. The method of claim 1, wherein, The step of detecting whether the baseboard controller has stopped accessing the target bus device based on data on the bus includes: The logic controller parses the data on the bus to obtain link parsing data; Based on the link parsing data, determine whether the baseboard controller has stopped accessing the target bus device.

9. An electronic device, comprising: include: Memory, used to store computer programs; A processor for executing the computer program to implement the steps of the method as claimed in any one of claims 1 to 8.

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