Bus interface data processing method, system and equipment

Abstract

The embodiment of the invention discloses a bus interface data processing method, system and equipment, and the method comprises the steps that a programmable logic device obtains first bus data of a bus interface of a first bus protocol, and obtains the first bus data of the bus interface of the first bus protocol according to a preset mapping relation; the original bus data corresponding to each time slot is mapped to a transmission channel of a bus interface of a second bus protocol corresponding to the time slot, and each time slot carries voice data or original signaling data of the original bus data; the conversion module of the audio processor acquires original signaling data of the transmission channel, and performs data calibration on the original signaling data based on each bit of the original signaling data to obtain target signaling data; and the audio processor outputs the voice data and the target signaling data to a receiving end. According to the technical scheme provided by the invention, mutual mapping between bus protocols can be realized, the system hardware design is simplified, and the system flexibility is improved.

Description

Technical Field

[0001] This invention relates to the field of data processing, and in particular to a bus interface data processing method, system, and device. Background Technology

[0002] Currently, traditional digital signaling interfaces are still widely deployed in dedicated communication systems. When new communication equipment needs to interconnect with existing traditional equipment that uses such interfaces, corresponding data interoperability is usually required. Traditional digital signaling interface chips typically rely on a PCM (Pulse Code Modulation) bus for data interaction with the main processor in their hardware design, and their signaling channel's underlying protocol generally uses advanced data link control protocols for data frame encapsulation and parsing.

[0003] However, with the evolution of processor technology, many modern mainframe processors no longer natively integrate PCM bus controllers, nor do they provide dedicated hardware for high-level data link control protocols. This hardware-level technological gap leads to difficulties in interface implementation for new systems when connecting to traditional digital signaling networks, increasing the complexity of system design and the development threshold.

[0004] Currently, the conventional approach to address the aforementioned compatibility issues is to use an external dedicated HDLC controller chip to implement the PCM bus interface and HDLC (High-level Data Link Control) protocol processing functions at the hardware level. However, this approach involves complex hardware design, a long development cycle, and high costs. Summary of the Invention

[0005] This invention provides a bus interface data processing method, system, and device. The method of this invention can realize the conversion between audio data of different protocols, improve system compatibility, simplify system hardware design, and improve system flexibility.

[0006] In a first aspect, embodiments of the present invention provide a bus interface data processing method, including:

[0007] A programmable logic device acquires the first bus data of the bus interface of the first bus protocol, and maps the original bus data corresponding to each time slot to the transmission channel of the bus interface of the second bus protocol corresponding to the time slot according to a preset mapping relationship, wherein each time slot carries voice data or original signaling data of the original bus data.

[0008] The audio processor's conversion module acquires the raw signaling data of the transmission channel, performs data calibration on the raw signaling data based on each bit of the raw signaling data, and obtains the target signaling data; the audio processor outputs the voice data and the target signaling data to the receiving end.

[0009] Secondly, embodiments of the present invention provide an audio data processing system, comprising:

[0010] A programmable logic device is used to acquire the first bus data of the bus interface of the first bus protocol, and to map the original bus data corresponding to each time slot to the transmission channel of the bus interface of the second bus protocol corresponding to the time slot according to a preset mapping relationship, wherein each time slot carries voice data or original signaling data of the original bus data.

[0011] An audio processor is configured to acquire the raw signaling data of the transmission channel, perform data calibration on the raw signaling data based on each bit of the raw signaling data, and obtain target signaling data; the audio processor outputs the voice data and target signaling data to the receiving end.

[0012] Thirdly, embodiments of the present invention provide an electronic device, the electronic device comprising:

[0013] At least one processor; and,

[0014] A memory communicatively connected to the at least one processor; wherein,

[0015] The memory stores a computer program that can be executed by the at least one processor, the computer program being executed by the at least one processor to enable the at least one processor to perform a bus interface data processing method as described in any one of the embodiments of the present invention.

[0016] This invention provides a bus interface data processing method, system, and device. The method includes: a programmable logic device (PLD) acquiring first bus data of a bus interface of a first bus protocol; mapping the original bus data corresponding to each time slot to a transmission channel of a bus interface of a second bus protocol corresponding to the time slot according to a preset mapping relationship, wherein each time slot carries voice data or original signaling data of the original bus data; a conversion module of an audio processor acquiring the original signaling data of the transmission channel; performing data calibration on the original signaling data based on each bit of the original signaling data to obtain target signaling data; and the audio processor outputting the voice data and target signaling data to a receiving end. Specifically, the PLD can be used to map the communication process between data formats of the first bus protocol and the second bus protocol. Simultaneously, by performing data calibration on the original signaling data, target signaling data can be extracted from the original signaling data. By transmitting the target signaling data and voice data, conversion between audio data of different protocols can be achieved, improving system compatibility while simplifying system hardware design and increasing system flexibility. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 A flowchart of a bus interface data processing method provided in Embodiment 1 of the present invention;

[0019] Figure 2 This is a flowchart of a bus interface data processing method provided in Embodiment 2 of the present invention;

[0020] Figure 3 This is a flowchart of a bus interface data processing method provided in Embodiment 3 of the present invention;

[0021] Figure 4 This is a schematic diagram of the structure of the bus interface data processing method provided in an embodiment of the present invention;

[0022] Figure 5 This is a structural schematic diagram of a bus interface data processing system provided in Embodiment 4 of the present invention;

[0023] Figure 6 A schematic diagram of the structure of an electronic device is provided for embodiment five of the present invention. Detailed Implementation

[0024] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0025] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0026] It should be noted that the collection, storage, use, processing, transmission, provision, and disclosure of user personal information involved in the technical solution disclosed herein all comply with the provisions of relevant laws and regulations and do not violate public order and good morals.

[0027] Example 1

[0028] Figure 1 This is a flowchart illustrating a bus interface data processing method according to Embodiment 1 of the present invention. This method is specifically applicable to situations where audio data is transmitted between devices using different protocols, particularly when the data signaling interface chip and the processor have different interface protocols, and when the processor lacks a controller for data calibration or conversion. The method of this embodiment can be implemented using a bus interface data processing system.

[0029] It should be noted that the embodiments of the present invention are specifically applicable to the following technical scenarios:

[0030] In audio communication systems based on traditional digital signaling interfaces, voice data from both parties in a call needs to be processed and forwarded by an audio processor to enable transmission between different devices or interfaces. However, with the rapid iteration of audio processor technology, new processors have gradually abandoned some traditional hardware modules to optimize chip area and manufacturing costs. For example, they no longer integrate hardware controllers dedicated to processing High-Level Data Link Control (HDLC) protocols. As a key component in traditional communication architectures, the HDLC controller is responsible for enabling reliable signaling data transmission in addition to the voice stream. This includes channel establishment, maintenance, and the encapsulation and parsing of control information, thereby achieving coordinated transmission of voice and signaling on a single physical link.

[0031] Traditional equipment uses a PCM (Pulse Code Modulation)-based bus interface for audio and signaling data exchange. However, new-generation processors, to optimize integration and cost, generally adopt the I2S (Integrated Inter-Chip Sound) serial audio interface. The PCM and I2S interfaces differ fundamentally in timing, frame synchronization signals, and data width, making direct interconnection impossible and leading to physical layer data transmission failures. Furthermore, at the protocol level, traditional communication signaling transmission heavily relies on the HDLC (Higher Data Link Control) protocol for reliable data frame encapsulation and verification. New processors, while removing the PCM interface hardware, typically also no longer integrate a dedicated HDLC protocol controller. Therefore, even if physical layer connectivity is achieved through bridging, the system lacks the ability to process HDLC frames, making it unable to parse or generate compliant signaling messages, ultimately resulting in the failure to establish a communication link.

[0032] The method of this invention not only simulates the processing function of the HDLC protocol on the main processor through a configurable software module, replacing a dedicated hardware controller, but also realizes data format and timing conversion between PCM audio streams and I2S audio streams. Through the solution of this invention, the interoperability problem between new and old devices is effectively solved without increasing additional hardware costs, ensuring reliable and real-time transmission of audio and signaling data.

[0033] like Figure 1 As shown, it includes:

[0034] Step 110: The programmable logic device acquires the first bus data of the bus interface of the first bus protocol, and maps the original bus data corresponding to each time slot to the transmission channel of the bus interface of the second bus protocol corresponding to the time slot according to the preset mapping relationship. The original bus data or the original signaling data of the original bus data are carried in each time slot.

[0035] The first bus protocol can be the PCM protocol, and the second bus protocol can be the I2S protocol. The bus interface of the second bus protocol is a physical communication interface on the audio processor that conforms to the I2S protocol specification, while the bus interface of the first bus protocol is an interface that conforms to the PCM specification and is used in traditional communication equipment. The bus interfaces of the first and second bus protocols are connected through a programmable logic device.

[0036] The second bus protocol interface can be physically implemented as the actual transmission interface of the audio processor, while the first bus protocol interface can be implemented based on the physical interface of a 2M or 64k digital signaling interface chip. The programmable logic device includes physical interfaces conforming to the first and second bus protocols respectively, connecting to the digital signaling interface chip and the audio processor, thereby realizing the mapping and conversion between the two protocols. Furthermore, the programmable logic device is a hardware unit located between two different bus protocol interfaces, realizing the conversion of the first bus protocol data and the second bus protocol data in terms of timing and data format.

[0037] The first bus data is an audio frame transmitted through the bus interface of the first bus protocol. The first bus data is transmitted in multiple time slots. Each time slot represents voice data or raw signaling data within a time interval. For example, when using a sampling frequency of 8 kHz, the length of each time slot is 125 microseconds. An audio frame may contain multiple such time slots, such as 16 time slots forming a frame with a total duration of 2 milliseconds.

[0038] Among them, the preset mapping relationship is a configuration rule preset in the programmable logic device, which specifies the correspondence between each time slot in the original audio frame of the second bus protocol and the transmission channel of the second bus protocol.

[0039] The method for establishing the preset mapping relationship includes:

[0040] The programmable logic device acquires the bit size supported by the time slot and the bit size supported by the transmission channel; the programmable logic device determines the number of time slots supported by a single transmission channel based on the bit size supported by the time slot and the bit size supported by the transmission channel; the programmable logic device groups the time slots of the original audio frame sequentially according to the number of time slots to obtain each time slot group; for any time slot group, the programmable logic device establishes a mapping relationship between each time slot in the time slot group and a transmission channel.

[0041] For example, the original audio frame of the first bus protocol may include 32 time slots (0-31), each time slot having a bit size of 8 bits. Meanwhile, the transmission channel supports a bit size of 32 bits. Therefore, every 4 time slots (8 bits * 4) can be mapped to 1 transmission channel (32 bits).

[0042] PCM: Time slots 0~3 <-> I2S transmission channel 0;

[0043] PCM: Time slots 4-7 <-> I2S transmission channel 1;

[0044] PCM: Time slots 8-11 <-> I2S transmission channel 2;

[0045] PCM: Time slots 12-15 <-> I2S transmission channel 3;

[0046] PCM: Slots 16-19 <-> I2S transmission channel 4;

[0047] PCM: Time slots 20-23 <-> I2S transmission channel 5;

[0048] PCM: Time slots 24-27 <-> I2S transmission channel 6;

[0049] PCM: 28~31 time slots <-> I2S transmission channel 7.

[0050] Therefore, the data from 32 time slots can be mapped to 8 transmission channels through the above mapping relationship.

[0051] Step 120: The conversion module of the audio processor acquires the original signaling data of the transmission channel, and performs data calibration on the original signaling data based on each bit of the original signaling data to obtain the target signaling data.

[0052] Specifically, to ensure the normal processing and transmission of audio data, the system's signaling processing flow relies on the HDLC protocol. This process first requires calibrating each bit of the original signaling data, and then extracting the target signaling data that conforms to the HDLC protocol frame format requirements to complete reliable data encapsulation and verification.

[0053] Step 130: The audio processor outputs the voice data and target signaling data to the receiving end.

[0054] It should be noted that the essence of this embodiment of the invention is to realize voice communication between two parties. Therefore, steps 110-120 of this embodiment are the process of sending data from end A to end B (the receiving end). Simultaneously, end B can also send data to end A. The two sending methods are inverses of each other, and the preset mapping relationship can also map the data of the transmission channel to each time slot. Therefore, the concepts of receiving end and sending end are only relative. For example, end A only supports sending and receiving PCM type data, while end B only supports receiving and sending HDLC data. Here, end A and end B are the sending end and receiving end for each other, respectively.

[0055] This invention provides a bus interface data processing method, comprising: a programmable logic device (PLD) acquiring first bus data of a bus interface of a first bus protocol; mapping the original bus data corresponding to each time slot to a transmission channel of a bus interface of a second bus protocol corresponding to the time slot according to a preset mapping relationship, wherein each time slot carries voice data or original signaling data of the original bus data; a conversion module of an audio processor acquiring the original signaling data of the transmission channel; performing data calibration on the original signaling data based on each bit of the original signaling data to obtain target signaling data; and the audio processor outputting the voice data and the target signaling data to a receiving end. Specifically, the PLD can be used to map the communication process between the data formats of the first bus protocol and the second bus protocol, thereby realizing the conversion between audio data of different protocols, improving system compatibility, simplifying system hardware design, and increasing system flexibility.

[0056] Example 2

[0057] Figure 2 This is a flowchart of a bus interface data processing method provided in Embodiment 2 of the present invention. Based on the above embodiments, this embodiment further defines the specific method for calibrating the original signaling data to obtain the target signaling data.

[0058] like Figure 2 As shown, it includes:

[0059] Step 210: The programmable logic device acquires the first bus data of the bus interface of the first bus protocol, and maps the original bus data corresponding to each time slot to the transmission channel of the bus interface of the second bus protocol corresponding to the time slot according to the preset mapping relationship. The original bus data or the original signaling data of the original bus data are carried in each time slot.

[0060] Step 220: The conversion module of the audio processor obtains the raw signaling data of the transmission channel.

[0061] Step 230: The conversion module of the audio processor determines the target segment that matches the first preset bit segment from each bit, wherein the target segment is the start segment and the end segment of the original signaling data.

[0062] Step 240: The conversion module of the audio processor removes each target segment from the original signaling data to obtain the first candidate data.

[0063] Specifically, the original signaling data uses specific bit segments (first preset bit segments) as the data header (start segment) and data tail (end segment). Therefore, the boundary between the start segment and the end segment is the valid signaling data. Valid signaling data includes the core content of the signaling, such as address fields, control fields, information fields, and check fields. Therefore, it is necessary to remove each target segment from the original signaling data to obtain valid signaling data (first candidate data). In this way, interference from invalid data can be eliminated.

[0064] Optionally, the matching method is to match sequentially based on the high and low values ​​of each bit; the starting segment is the target segment that is matched successfully for the first time, and the ending segment is the target segment that is matched successfully for the second time.

[0065] For example, a bit stream buffer can be prepared. During the process of storing each bit of the original signaling data into the buffer sequentially, it is checked whether the target segment composed of the most recently stored preset number of bits is a first preset bit segment. If the first match is successful, the target segment is determined to be the starting segment, and the second successful match is the ending segment. For example, the first preset bit segment can be "01111110".

[0066] Step 250: The conversion module of the audio processor performs content calibration on the first candidate data to obtain the second candidate data.

[0067] Specifically, the conversion module of the audio processor obtains a second preset bit segment and a third preset bit segment, updates the second preset bit segment in the first candidate data with the third preset bit segment, and obtains the second candidate data.

[0068] The second preset bit segment can be 111110, and the third preset bit segment can be 11111.

[0069] Specifically, the HDLC protocol requires the sending end to execute bit insertion rules during data transmission:

[0070] When five consecutive "1"s appear in the original signaling data, the sending end automatically inserts a "0" to prevent the data segment from being misidentified as a frame header / tail marker (01111110). Therefore, this step needs to be reversed: delete the padding "0" bit and restore the original data stream. That is, replace 111110 with 11111.

[0071] Step 260: The conversion module of the audio processor performs format calibration on the second candidate data to obtain the target signaling data.

[0072] Specifically, if the bit length of the second candidate data meets the preset length requirement, then the second candidate data is determined as the target signaling data.

[0073] For example, check the number of bits in the second candidate data; if it is not a multiple of 8, it is considered invalid and discarded. Check the number of bits in the second candidate data; if it is less than 24 bits, it is considered invalid and discarded.

[0074] Optionally, the audio processor further includes a sound card, which determines a target transmission channel based on the type of data in the transmission channel, and transmits the raw signaling data in the target transmission channel to the conversion module.

[0075] Specifically, the original signaling data from the target transmission channel can be transmitted to the conversion module via the sound card driver. Voice data from the non-target transmission channel is then sent to the receiving end.

[0076] Optionally, format calibration may also include:

[0077] Perform a CRC16 checksum calculation on the bits of the second candidate data excluding the last two bytes, and compare it with the CRC16 calculation result of the last two bytes. If they are different, the data is considered invalid and discarded.

[0078] Step 270: The audio processor outputs the voice data and target signaling data to the receiving end.

[0079] This invention provides a bus interface data processing method. Through a conversion module, the original signaling data can be sequentially calibrated for data, content, and format to obtain target signaling data that conforms to the HDLC protocol frame format requirements. This reliably replaces the dedicated hardware controller at the software level, saving costs and improving the efficiency of protocol conversion.

[0080] Example 3

[0081] Figure 3This is a flowchart of a bus interface data processing method provided in Embodiment 3 of the present invention. The above embodiments specifically define the process of converting raw signaling data into target signaling data, that is, when communication party A transmits audio data to communication party B. Therefore, this embodiment will provide the process of converting target signaling data into raw signaling data, that is, the process of communication party B transmitting audio data to communication party A.

[0082] Specifically, for the voice data and target signaling data of the communication party B, the HDLC protocol data conversion is first performed through the conversion module, that is, the target signaling data is converted into the raw signaling data, and then the raw signaling data in each I2S transmission channel is allocated to each time slot of the PCM bus to complete the reverse transmission of audio data.

[0083] like Figure 3 As shown, it includes:

[0084] Step 310: The audio processor acquires the voice data and target signaling data sent by the receiving end, performs data calibration on the target signaling data according to each bit of the target signaling data to obtain the original signaling data, and outputs the original signaling data and voice data to the transmission channel of the bus interface of the second bus protocol.

[0085] Optionally, step 310 includes:

[0086] The target signaling data is subjected to CRC16 verification calculation to obtain the second candidate data corresponding to the target signaling data. Then, the third preset bit segment in the second candidate data is updated to the second preset bit segment, that is, the continuous "11111" is replaced with "111110" to obtain the first candidate data. Then, the first preset bit segment is added to the beginning and end of the first candidate data respectively, and the preset length requirement is judged. Then, if the judgment result represents the format accurately, the first candidate data is determined as the original signaling data.

[0087] Step 320: The programmable logic device determines, based on a preset mapping relationship, multiple time slots conforming to the first interface protocol to which the original signaling data or voice data of the transmission channel belongs, and the original signaling data and voice data of each time slot constitute the second bus data.

[0088] Specifically, through a preset mapping relationship, the raw signaling data and voice data in each transmission channel of the I2S bus (second bus) are accurately allocated to the corresponding time slots of the PCM bus (first bus). The raw signaling data and voice data in each time slot are then reassembled in time slot order to ultimately generate second bus data conforming to the first bus protocol format. It should be noted that the first bus data and second bus data are essentially the same; both are data supported and recognizable by the transmitting end. The different names are only to distinguish between the transmitting and receiving processes.

[0089] For example, Figure 4 This is a schematic diagram of the bus interface data processing method provided in an embodiment of the present invention. Specifically, in the direction from the interface chip to the general-purpose processor, the PCM bus interface sends voice data and raw signaling data in each time slot to the programmable logic device (PLD). The PLD determines the correspondence between the PCM time slots and the I2S transmission channels according to a preset mapping relationship, and then sends the voice data or raw signaling data in each PCM time slot through the corresponding I2S transmission channel. Subsequently, the sound card driver directly transmits the voice data to the upper-layer software; while the HDLC processing module, sensing the method provided in this embodiment, converts the raw signaling data into target signaling data before reporting it to the upper-layer software. In the direction from the general-purpose processor to the interface chip, after the voice data and signaling data sent by the upper-layer software arrive at the general-purpose processor, the voice data is processed by the sound card driver, while the target signaling data is encapsulated into raw signaling data by the HDLC processing module. The general-purpose processor sends the raw signaling data and voice data to the PLD via the I2S bus interface. The programmable logic device determines the corresponding PCM time slot for each I2S transmission channel according to a preset mapping relationship, and then maps the voice data and the original signaling data to the designated PCM time slots respectively. Finally, the complete PCM frame (i.e., the original audio frame) carrying the data of each time slot is sent to the interface chip via the PCM bus.

[0090] The method of this invention implements the mapping between PCM time slots and I2S channels using programmable logic devices and processes signaling data using an independent HDLC module (conversion module). This achieves efficient, parallel transmission of voice and signaling data, simplifying the system structure; simultaneously, the mutual conversion and mapping between different protocols improves compatibility between devices using different protocols.

[0091] Example 4

[0092] Figure 5 This is a schematic diagram of a bus interface data processing system provided in Embodiment 4 of the present invention. Figure 5 As shown, the system includes:

[0093] The programmable logic device 410 is used to acquire the first bus data of the bus interface of the first bus protocol, and map the original bus data corresponding to each time slot to the transmission channel of the bus interface of the second bus protocol corresponding to the time slot according to the preset mapping relationship, wherein each time slot carries the voice data or original signaling data of the original bus data.

[0094] The audio processor's conversion module 420 is used to acquire the original signaling data of the transmission channel, perform data calibration on the original signaling data based on each bit of the original signaling data, and obtain target signaling data; the audio processor outputs the voice data and target signaling data to the receiving end.

[0095] This invention provides a bus interface data processing system, comprising: a programmable logic device (PLD) for acquiring first bus data of a bus interface of a first bus protocol, and mapping the original bus data corresponding to each time slot to the transmission channel of a bus interface of a second bus protocol corresponding to the time slot according to a preset mapping relationship, wherein each time slot carries voice data or original signaling data of the original bus data; an audio processor for acquiring the original signaling data of the transmission channel, performing data calibration on the original signaling data based on each bit of the original signaling data to obtain target signaling data; and the audio processor outputting the voice data and the target signaling data to a receiving end. Specifically, the PLD can be used to map the communication process between the data formats of the first bus protocol and the second bus protocol, thereby realizing the conversion between audio data of different protocols, improving system compatibility, simplifying system hardware design, and increasing system flexibility.

[0096] Optionally, the programmable logic device 410 is specifically used for:

[0097] Obtain the bit size supported by the time slot and the bit size supported by the transmission channel; determine the number of time slots supported by a single transmission channel based on the bit size supported by the time slot and the bit size supported by the transmission channel; group the time slots of the original audio frame sequentially according to the number of time slots to obtain each time slot group; for any time slot group, establish a mapping relationship between each time slot in the time slot group and a transmission channel.

[0098] The audio processor specifically includes a conversion module 420, which is specifically used for:

[0099] The conversion module of the audio processor determines a target segment that matches the first preset bit segment from each bit, wherein the target segment is the start segment and the end segment of the original signaling data;

[0100] The conversion module of the audio processor is used to remove each target segment from the original signaling data to obtain the first candidate data;

[0101] The conversion module of the audio processor is used to perform content calibration on the first candidate data to obtain the second candidate data;

[0102] The conversion module of the audio processor is used to perform format calibration on the second candidate data to obtain the target signaling data.

[0103] Optionally, the matching method is to match sequentially based on the high and low values ​​of each bit; the starting segment is the target segment that is matched successfully for the first time, and the ending segment is the target segment that is matched successfully for the second time.

[0104] The conversion module of the audio processor is specifically used to: obtain a second preset bit segment and a third preset bit segment, update the second preset bit segment in the first candidate data to the third preset bit segment, and obtain the second candidate data.

[0105] Optionally, the audio processor also includes a sound card, which is used to determine a target transmission channel based on the type of data in the transmission channel, and transmit the raw signaling data in the target transmission channel to the conversion module.

[0106] Optionally, the conversion module 420 is further configured to acquire the voice data and target signaling data sent by the receiving end, perform data calibration on the target signaling data according to each bit of the target signaling data to obtain the original signaling data, and output the original signaling data and voice data to the transmission channel of the bus interface of the second bus protocol.

[0107] The programmable logic device 410 is further configured to determine, based on a preset mapping relationship, multiple time slots conforming to the first interface protocol to which the original signaling data or voice data of the transmission channel belongs, wherein the original signaling data and voice data of each time slot constitute the second bus data.

[0108] The bus interface data processing system provided in this embodiment of the invention can execute the bus interface data processing method provided in any embodiment of the invention, and has the corresponding functional modules and beneficial effects of the method execution.

[0109] Example 5

[0110] Figure 6A schematic diagram of an electronic device 10, which can be used to implement embodiments of the present invention, is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices (e.g., helmets, glasses, watches, etc.), and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the invention described and / or claimed herein.

[0111] like Figure 6 As shown, the electronic device 10 includes at least one processor 11 and a memory, such as a read-only memory (ROM) 12 or a random access memory (RAM) 13, communicatively connected to the at least one processor 11. The memory stores computer programs executable by the at least one processor. The processor 11 can perform various appropriate actions and processes based on the computer program stored in the ROM 12 or loaded from storage unit 18 into the RAM 13. The RAM 13 can also store various programs and data required for the operation of the electronic device 10. The processor 11, ROM 12, and RAM 13 are interconnected via a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.

[0112] Multiple components in electronic device 10 are connected to I / O interface 15, including: input unit 16, such as keyboard, mouse, etc.; output unit 17, such as various types of displays, speakers, etc.; storage unit 18, such as disk, optical disk, etc.; and communication unit 19, such as network card, modem, wireless transceiver, etc. Communication unit 19 allows electronic device 10 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0113] Processor 11 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. Processor 11 performs the various methods and processes described above, such as bus interface data processing methods.

[0114] In some embodiments, the bus interface data processing method may be implemented as a computer program tangibly contained in a computer-readable storage medium, such as storage unit 18. In some embodiments, part or all of the computer program may be loaded and / or installed on electronic device 10 via ROM 12 and / or communication unit 19. When the computer program is loaded into RAM 13 and executed by processor 11, one or more steps of the bus interface data processing method described above may be performed. Alternatively, in other embodiments, processor 11 may be configured to perform the bus interface data processing method by any other suitable means (e.g., by means of firmware).

[0115] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various implementations may include: implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0116] Computer programs used to implement the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when executed by the processor, the computer programs cause the functions / operations specified in the flowcharts and / or block diagrams to be performed. The computer programs may be executed entirely on a machine, partially on a machine, or as a standalone software package, partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0117] In the context of this invention, a computer-readable storage medium can be a tangible medium that may contain or store a computer program for use by or in conjunction with an instruction execution system, apparatus, or device. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination thereof. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0118] To provide interaction with a user, the systems and techniques described herein can be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the electronic device. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0119] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as data servers), or middleware components (e.g., application servers), or frontend components (e.g., user computers with graphical user interfaces or web browsers through which users can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., communication networks). Examples of communication networks include local area networks (LANs), wide area networks (WANs), blockchain networks, and the Internet.

[0120] A computing system can include clients and servers. Clients and servers are generally located far apart and typically interact through communication networks. The client-server relationship is created by computer programs running on the respective computers and having a client-server relationship with each other. The server can be a cloud server, also known as a cloud computing server or cloud host, which is a hosting product within the cloud computing service system to address the shortcomings of traditional physical hosts and VPS services, such as high management difficulty and weak business scalability.

[0121] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0122] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A bus interface data processing method, characterized in that, include: A programmable logic device acquires the first bus data of the bus interface of the first bus protocol, and maps the original bus data corresponding to each time slot to the transmission channel of the bus interface of the second bus protocol corresponding to the time slot according to a preset mapping relationship, wherein each time slot carries voice data or original signaling data of the original bus data. The audio processor's conversion module acquires the raw signaling data of the transmission channel, performs data calibration on the raw signaling data based on each bit of the raw signaling data, and obtains the target signaling data; the audio processor outputs the voice data and the target signaling data to the receiving end.

2. The method according to claim 1, characterized in that, The method for establishing the preset mapping relationship includes: The programmable logic device acquires the bit size supported by the time slot and the bit size supported by the transmission channel; The programmable logic device determines the number of time slots supported by a single transmission channel based on the bit size supported by the time slot and the bit size supported by the transmission channel. The programmable logic device groups the time slots of the original audio frame sequentially according to the number of time slots to obtain each time slot group; For any time slot group, the programmable logic device establishes a mapping relationship between each time slot in the time slot group and a transmission channel.

3. The method according to claim 1, characterized in that, The audio processor's conversion module performs data calibration on the original signaling data based on each bit of the original signaling data to obtain target signaling data, including: The conversion module of the audio processor determines a target segment that matches the first preset bit segment from each bit, wherein the target segment is the start segment and the end segment of the original signaling data; The audio processor's conversion module removes each target segment from the original signaling data to obtain the first candidate data; The audio processor's conversion module performs content calibration on the first candidate data to obtain the second candidate data; The audio processor's conversion module performs format calibration on the second candidate data to obtain the target signaling data.

4. The method according to claim 3, characterized in that, The matching method is to match sequentially based on the high and low values ​​of each bit; the starting segment is the target segment that is matched successfully for the first time, and the ending segment is the target segment that is matched successfully for the second time.

5. The method according to claim 3, characterized in that, The audio processor's conversion module performs content calibration on the first candidate data to obtain second candidate data, including: The audio processor's conversion module acquires a second preset bit segment and a third preset bit segment, updates the second preset bit segment in the first candidate data to the third preset bit segment, and obtains the second candidate data.

6. The method according to claim 3, characterized in that, The audio processor's conversion module performs format calibration on the second candidate data to obtain target signaling data, including: If the bit length of the second candidate data meets the preset length requirement, then the second candidate data is determined as the target signaling data.

7. The method according to claim 1, characterized in that, The audio processor also includes a sound card, which determines a target transmission channel based on the type of data in the transmission channel, and transmits the raw signaling data in the target transmission channel to the conversion module.

8. The method according to claim 1, characterized in that, Also includes: The audio processor acquires the voice data and target signaling data sent by the receiving end, performs data calibration on the target signaling data according to each bit of the target signaling data to obtain the original signaling data, and outputs the original signaling data and voice data to the transmission channel of the bus interface of the second bus protocol. The programmable logic device determines, based on a preset mapping relationship, multiple time slots conforming to the first interface protocol to which the original signaling data or voice data of the transmission channel belongs, and the original signaling data and voice data of each time slot constitute the second bus data.

9. An audio data processing system, characterized in that, include: A programmable logic device is used to acquire the first bus data of the bus interface of the first bus protocol, and to map the original bus data corresponding to each time slot to the transmission channel of the bus interface of the second bus protocol corresponding to the time slot according to a preset mapping relationship, wherein each time slot carries voice data or original signaling data of the original bus data. The audio processor's conversion module is used to acquire the raw signaling data of the transmission channel, perform data calibration on the raw signaling data based on each bit of the raw signaling data, and obtain target signaling data; the audio processor outputs the voice data and target signaling data to the receiving end.

10. An electronic device, characterized in that, The electronic device includes: At least one processor; and, A memory communicatively connected to the at least one processor; wherein, The memory stores a computer program that can be executed by the at least one processor, the computer program being executed by the at least one processor to enable the at least one processor to perform a bus interface data processing method according to any one of claims 1-8.

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