Intelligent and encryption integrated processing engine device

Abstract

The embodiment of the invention discloses an intelligent and encryption integrated processing engine device. According to one specific embodiment, the system comprises a core module which comprises a shared storage module used for data interaction storage of input data, output data, an intelligent computing array and a password computing array; the integrated control scheduler is used for controlling the operation core data reading and writing of the intelligent calculation module, the password calculation module and the shared storage module according to the received corresponding instruction and a preset control program; the input / output cache 1 is used for temporarily storing data when the intelligent computing module performs data interaction with the outside, and the input / output cache 2 is used for temporarily storing data when the password computing module performs data interaction with the outside. According to the implementation mode, password calculation and intelligent calculation are completed in one engine at the same time, data interaction is not transmitted through a bus any more, and the overall operation efficiency is greatly improved.

Description

Technical Field

[0001] The embodiments disclosed herein relate to the field of intelligent encryption integrated processing engines, and more specifically to intelligent encryption integrated processing engine devices. Background Technology

[0002] The current fusion of AI and cryptographic algorithms is mainly implemented using a board-level integration approach, which involves integrating two independent chips on the board. In some chips, such as Rockchip's RK3588, independent high-performance NPU processing units (for AI algorithm processing) and Cypto units (for cryptographic algorithm processing) are integrated. However, both units are directly interconnected to the bus without dedicated interconnection channels and shared data memory, resulting in low efficiency in the fusion of AI and cryptographic algorithms. Summary of the Invention

[0003] The summary portion of this disclosure is intended to provide a brief overview of the concepts, which will be described in detail in the detailed description portion. This summary portion is not intended to identify key or essential features of the claimed technical solutions, nor is it intended to limit the scope of the claimed technical solutions.

[0004] Some embodiments of this disclosure propose an integrated intelligent encryption processing engine device to address the technical problems mentioned in the background section above.

[0005] In a first aspect, some embodiments of this disclosure provide an integrated intelligent encryption processing engine device, which includes: an intelligent computing module, comprising: multiple intelligent computing arrays, wherein the multiple intelligent computing arrays are different or the same, and the connection method between the multiple intelligent computing arrays is: parallel connection method or cascaded serial method; a cryptographic computing module, comprising: multiple cryptographic computing arrays, wherein the multiple cryptographic computing arrays are different or the same, and the connection method between the multiple cryptographic computing arrays is: parallel connection method or cascaded serial method; a shared storage module for data interaction storage of input data, output data, and data of the intelligent computing arrays and the cryptographic computing arrays; an integrated control scheduler, according to receiving corresponding instructions and a pre-set control program, for controlling the core data read and write of the intelligent computing module, the cryptographic computing module, and the shared storage module, and controlling the data read and write of input / output buffer 1 and input / output buffer 2; an input / output buffer module, comprising: input / output buffer 1 and input / output buffer 2, wherein input / output buffer 1 is used for temporary data storage when the intelligent computing module interacts with external data, and input / output buffer 2 is used for temporary data storage when the cryptographic computing module interacts with external data.

[0006] Optionally, the aforementioned intelligent encryption integrated processing engine device further includes: an interface circuit, which is interconnected with an external bus; the interface circuit is interconnected with the intelligent computing module, the cryptographic computing module, the shared storage module, input / output buffer 1, input / output buffer 2, and the integrated control scheduler.

[0007] Optionally, the intelligent computing module is communicatively connected to input / output buffer 1, the integrated control scheduler, and the shared storage module, respectively; the cryptographic computing module is communicatively connected to input / output buffer 2, the integrated control scheduler, and the shared storage module, respectively; and the integrated control scheduler is communicatively connected to the shared storage module.

[0008] Optionally, in the working state, the program and key are written to the integrated control scheduler via an external processor; the integrated control scheduler parses the externally written program and dynamically configures the intelligent computing module and the cryptographic computing module; the cryptographic computing module reads AI algorithm model parameters from external memory through input / output buffer 2, decrypts the algorithm model parameters, temporarily stores the decrypted results in the shared storage module, and reports back to the integrated control scheduler that the decryption operation has started and the data storage address of the decrypted data; the intelligent computing module reads the temporarily decrypted data from the shared storage module according to the address, performs convolutional neural network calculations using the data, writes the calculation results into input / output buffer 1, and reports back to the integrated control scheduler that the calculation is complete and the storage address of the calculation results after the calculation is completed; the integrated control scheduler reports back to the external processor that the program calculation is complete and transmits the data in input / output buffer 1 to the external processor.

[0009] Secondly, some embodiments of this disclosure provide an electronic device, including: one or more processors; and a storage device having one or more programs stored thereon, wherein when the one or more programs are executed by the one or more processors, the one or more processors implement the apparatus described in any implementation of the first aspect above.

[0010] Thirdly, some embodiments of this disclosure provide a computer-readable medium having a computer program stored thereon, wherein the program, when executed by a processor, implements the apparatus described in any of the implementations of the first aspect above.

[0011] The above-described embodiments of this disclosure have the following beneficial effects: Through the intelligent encryption integrated processing engine device of some embodiments of this disclosure, cryptographic calculation and intelligent calculation are completed simultaneously within one engine. Data interaction is no longer transmitted through a bus, but through a high-efficiency shared storage module. At the same time, the integrated control scheduler is responsible for the overall scheduling and control, which greatly improves the overall computing efficiency. Attached Figure Description

[0012] The above and other features, advantages, and aspects of the embodiments of this disclosure will become more apparent from the accompanying drawings and the following detailed description. Throughout the drawings, the same or similar reference numerals denote the same or similar elements. It should be understood that the drawings are schematic, and elements are not necessarily drawn to scale.

[0013] Figure 1 This is a structural flowchart of a smart encryption integrated processing engine device according to some embodiments of the present disclosure; Figure 2 This is a schematic diagram of the structure of an electronic device suitable for implementing some embodiments of the present disclosure. Detailed Implementation

[0014] Embodiments of this disclosure will now be described in more detail with reference to the accompanying drawings. While some embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of this disclosure. It should be understood that the accompanying drawings and embodiments of this disclosure are for illustrative purposes only and are not intended to limit the scope of protection of this disclosure.

[0015] It should also be noted that, for ease of description, only the parts relevant to the invention are shown in the accompanying drawings. Unless otherwise specified, the embodiments and features described in this disclosure can be combined with each other.

[0016] It should be noted that the concepts of "first" and "second" mentioned in this disclosure are used only to distinguish different devices, modules or units, and are not used to limit the order of functions performed by these devices, modules or units or their interdependencies.

[0017] It should be noted that the terms "a" and "a plurality of" used in this disclosure are illustrative rather than restrictive, and those skilled in the art should understand that, unless otherwise expressly indicated in the context, they should be understood as "one or more".

[0018] The names of messages or information exchanged between multiple devices in the embodiments of this disclosure are for illustrative purposes only and are not intended to limit the scope of such messages or information.

[0019] This disclosure will now be described in detail with reference to the accompanying drawings and embodiments.

[0020] Figure 1This is a structural flowchart of some embodiments of the intelligent encryption integrated processing engine device disclosed herein. The intelligent encryption integrated processing engine device includes: an intelligent computing module, a cryptographic computing module, a shared storage module, an input / output buffer module, an integrated control scheduler and interface circuit, and the input / output buffer module includes: input / output buffer 1 and input / output buffer 2.

[0021] In some embodiments, the intelligent computing module includes: multiple intelligent computing arrays, wherein the multiple intelligent computing arrays are different or the same, and the connection between the multiple intelligent computing arrays is: parallel connection or cascaded serial connection.

[0022] Intelligent computing arrays can be either customized AI algorithm processors or reconfigurable AI algorithm processors. Customized AI algorithm processors can implement specific AI algorithms at high speed, but they are less flexible. If reconfigurable technology is used, the array can be flexibly and dynamically configured to implement different types of AI algorithms (including but not limited to MLP, CNN, DNN, Transformer, etc.) according to computing needs.

[0023] In some embodiments, the cryptographic computation module includes: multiple cryptographic computation arrays, wherein the multiple cryptographic computation arrays are different or the same, and the connection between the multiple cryptographic computation arrays is either a parallel connection or a cascaded serial connection.

[0024] Cryptographic computing arrays can be either custom-designed cryptographic algorithm processors or reconfigurable cryptographic algorithm processors. Custom-designed cryptographic algorithm processors can implement specific cryptographic algorithms at high speed, but they are less flexible. If reconfigurable technology is used, the array can be flexibly and dynamically configured to implement different types of cryptographic algorithms (including but not limited to block ciphers, stream ciphers, public-key cryptography, hash ciphers, etc.) according to computational needs.

[0025] In some embodiments, the shared storage module is used for data interaction storage of input data, output data, and intelligent computing arrays and cryptographic computing arrays.

[0026] In some embodiments, the integrated control scheduler, based on receiving corresponding instructions and a pre-set control program, controls the read and write of the core data of the intelligent computing module, the cryptographic computing module, and the shared storage module, as well as controls the read and write of data in input / output buffer 1 and input / output buffer 2.

[0027] In some embodiments, the input / output caching module includes: input / output caching 1 and input / output caching 2, wherein input / output caching 1 is used for temporary data storage when the intelligent computing module interacts with the outside world, and input / output caching 2 is used for temporary data storage when the cryptographic computing module interacts with the outside world.

[0028] Optionally, the aforementioned intelligent encryption integrated processing engine device further includes: an interface circuit, which communicates and interconnects with an external bus. The interface circuit is communicatively connected to the intelligent computing module, the cryptographic computing module, the shared storage module, input / output buffer 1, input / output buffer 2, and the integrated control scheduler.

[0029] Optionally, the intelligent computing module is communicatively connected to input / output buffer 1, the integrated control scheduler, and the shared storage module, respectively; the cryptographic computing module is communicatively connected to input / output buffer 2, the integrated control scheduler, and the shared storage module, respectively; and the integrated control scheduler is communicatively connected to the shared storage module.

[0030] In operation, the program and key are written to the integrated control scheduler via an external processor. The integrated control scheduler parses the externally written program and dynamically configures the intelligent computing module and the cryptographic computing module. The cryptographic computing module reads AI algorithm model parameters from external memory through input / output buffer 2, decrypts the algorithm model parameters, temporarily stores the decrypted results in the shared storage module, and reports back to the integrated control scheduler that the decryption operation has started and the data storage address of the decrypted data. The intelligent computing module reads the temporarily decrypted data from the shared storage module according to the address, performs convolutional neural network calculations using the data, writes the calculation results into input / output buffer 1, and reports the end of the calculation and the storage address of the calculation results to the integrated control scheduler after the calculation is completed. The integrated control scheduler reports the end of the program calculation to the external processor and transmits the data in input / output buffer 1 to the external processor.

[0031] The intelligent computing module comprises multiple intelligent computing arrays, each capable of implementing different types of AI algorithms (including but not limited to MLP, CNN, DNN, Transformer, and other types of neural networks). Multiple arrays can be processed in parallel through multiple channels, or cascaded sequentially to construct a long pipeline for data processing. The cryptographic computing module also comprises multiple cryptographic computing arrays, each capable of implementing different types of cryptographic algorithms (including but not limited to block ciphers, stream ciphers, public-key cryptography, hash ciphers, and other types of cryptographic algorithms). Multiple arrays can be processed in parallel through multiple channels, or cascaded sequentially to construct a long pipeline for data processing. The shared storage module is primarily used for data interaction and temporary storage between the intelligent computing and cryptographic computing arrays. An integrated control scheduler controls the operation and data read / write operations of the intelligent computing, cryptographic, and shared storage modules. Input / output buffers are used for temporary data storage during data interaction between the intelligent computing and cryptographic computing modules and external systems.

[0032] If the designed engine is integrated using the SoC approach, the entire intelligent integrated engine can be interconnected with an external bus through an interface circuit; at the same time, the engine can also form a separate chiplet, which can be interconnected with other chipslets through a chiplet interface circuit, thereby building the entire chip system.

[0033] The following is for reference. Figure 2 It illustrates a schematic diagram of the structure of an electronic device (such as a computing device) suitable for implementing some embodiments of the present disclosure. Figure 2 The electronic device shown is merely an example and should not be construed as limiting the functionality or scope of the embodiments of this disclosure. Figure 2 As shown, the computer device includes a processor, memory, and a network interface connected via a system bus. The memory may include non-volatile storage media and internal memory. The non-volatile storage media may store an operating system and a computer program. The computer program includes program instructions that, when executed, cause the processor to execute any intelligent encryption integrated processing engine. The processor provides computing and control capabilities to support the operation of the entire computer device. The internal memory provides an environment for the execution of the computer program in the non-volatile storage media; when executed by the processor, this program causes the processor to execute any intelligent encryption integrated processing engine. The network interface is used for network communication, such as sending assigned tasks. Those skilled in the art will understand that... Figure 2 The structure shown is merely a block diagram of a portion of the structure related to the present disclosure and does not constitute a limitation on the computer device to which the present disclosure is applied. A specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0034] It should be understood that the processor can be a Central Processing Unit (CPU), but it can also be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. Among these, a general-purpose processor can be a microprocessor or any conventional processor.

[0035] In one embodiment, the processor is used to run a computer program stored in a memory to achieve the following steps: an intelligent computing module, including multiple intelligent computing arrays, wherein the multiple intelligent computing arrays are different or the same, and the connection method between the multiple intelligent computing arrays is: parallel connection method or cascaded serial method; a cryptographic computing module, including multiple cryptographic computing arrays, wherein the multiple cryptographic computing arrays are different or the same, and the connection method between the multiple cryptographic computing arrays is: parallel connection method or cascaded serial method; a shared storage module is used for data interaction storage of input data, output data, and data of the intelligent computing arrays and the cryptographic computing arrays; an integrated control scheduler is used to control the read and write of core data of the intelligent computing module, the cryptographic computing module, and the shared storage module, and to control the read and write of data of input / output cache 1 and input / output cache 2, according to receiving corresponding instructions and a pre-set control program; an input / output cache module, including input / output cache 1 and input / output cache 2, wherein input / output cache 1 is used for temporary data storage when the intelligent computing module interacts with the outside world, and input / output cache 2 is used for temporary data storage when the cryptographic computing module interacts with the outside world.

[0036] This disclosure also provides a computer-readable storage medium storing a computer program, the computer program including program instructions, and the system implemented when the program instructions are executed can refer to various embodiments of the intelligent encryption integrated processing engine device of this disclosure.

[0037] The aforementioned computer-readable storage medium may be an internal storage unit of the computer device described in the foregoing embodiments, such as the hard disk or memory of the computer device. Alternatively, the aforementioned computer-readable storage medium may be an external storage device of the computer device, such as a plug-in hard disk, SmartMedia Card (SMC), Secure Digital (SD) card, or Flash Card equipped on the computer device.

[0038] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, system, article, or system that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, system, article, or system. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, system, article, or system that includes that element.

[0039] The above description is merely a selection of preferred embodiments of this disclosure and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of the invention involved in the embodiments of this disclosure is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the above-described inventive concept. For example, technical solutions formed by substituting the above-described features with (but not limited to) technical features with similar functions disclosed in the embodiments of this disclosure.

Claims

1. A smart encryption integrated processing engine device, characterized in that, include: The intelligent computing module includes: multiple intelligent computing arrays, wherein the multiple intelligent computing arrays are different or the same, and the connection between the multiple intelligent computing arrays is either a parallel connection or a cascaded serial connection. The cryptographic computation module includes: multiple cryptographic computation arrays, wherein the multiple cryptographic computation arrays are different or the same, and the connection between the multiple cryptographic computation arrays is either a parallel connection or a cascaded serial connection. The shared storage module is used for the interactive storage of input data, output data, and data from the intelligent computing array and the cryptographic computing array; The integrated control scheduler, based on the received instructions and pre-set control program, is used to control the read and write of the core data of the intelligent computing module, the cryptographic computing module, and the shared storage module, as well as to control the read and write of data in input / output buffer 1 and input / output buffer 2. The input / output buffer module includes: input / output buffer 1 and input / output buffer 2, wherein input / output buffer 1 is used for temporary data storage when the intelligent computing module interacts with the outside world, and input / output buffer 2 is used for temporary data storage when the cryptographic computing module interacts with the outside world.

2. The intelligent encryption integrated processing engine device according to claim 1, characterized in that, The intelligent encryption integrated processing engine device also includes: an interface circuit, which communicates and interconnects with an external bus. The interface circuits are connected to the intelligent computing module, the cryptographic computing module, the shared storage module, input / output buffer 1, input / output buffer 2, and the integrated control scheduler.

3. The intelligent encryption integrated processing engine device according to claim 2, characterized in that, The intelligent computing module is communicatively connected to input / output buffer 1, integrated control scheduler, and shared storage module, respectively. The cryptographic calculation module is communicatively connected to input / output buffer 2, integrated control scheduler, and shared storage module, respectively. The integrated control scheduler communicates with the shared storage module.

4. The intelligent encryption integrated processing engine device according to claim 3, characterized in that, In operation, the program and key are written to the integrated control scheduler via an external processor; The integrated control scheduler parses externally written programs and dynamically configures the intelligent computing module and the cryptographic computing module; The cryptographic calculation module reads AI algorithm model parameters from external memory through input / output buffer 2, decrypts the algorithm model parameters, temporarily stores the decrypted results in the shared storage module, and feeds back to the integrated control scheduler that the decryption operation has started and the data storage address of the decrypted data. The intelligent computing module reads the temporarily stored decrypted data from the shared storage module according to the address, uses the data to perform convolutional neural network calculations, and writes the calculation results into input / output buffer 1. After the operation is completed, it sends the end of the calculation and the storage address of the calculation results back to the integrated control scheduler. The integrated control scheduler reports the completion of the program calculation to the external processor and transmits the data in input / output buffer 1 to the external processor.

5. An electronic device, characterized in that, include: One or more processors; A storage device on which one or more programs are stored; When the one or more programs are executed by the one or more processors, the one or more processors implement the intelligent encryption integrated processing engine device as described in claims 1-4.

6. A computer-readable medium, characterized in that, It stores a computer program, wherein the computer program, when executed by a processor, implements the intelligent encryption integrated processing engine device as described in claims 1-4.

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