Method and device for generating internal scan chain of integrated chip in 2.5 D / 3D circuit, storage medium and equipment

Abstract

The invention discloses an internal scan chain generation method and device for an integrated chip in a 2.5 D / 3D circuit, a storage medium and equipment. The integrated chip comprises a plurality of cores, and each core is connected to each test bus through a controllable unit; the method comprises the following steps: receiving scan chain demand information; based on the received test demand information, by taking minimization of the overall test duration of the integrated chip as a target, utilizing a preset scan chain configuration model to obtain scan chain configuration information; and based on the obtained scan chain configuration information, controlling a corresponding controllable unit to generate a corresponding scan chain. By adopting the scheme, the configuration flexibility of the scan chain in the integrated chip can be improved so as to meet a dynamically changing integrated environment in a 2.5 D / 3D circuit.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and specifically to a method, apparatus, storage medium, and device for generating internal scan chains of integrated chips in 2.5D / 3D circuits. Background Technology

[0002] An integrated chip is a unit chip that can perform certain functions and contains interconnection interfaces. Multiple integrated chips can be packaged into a chip group using 2.5D, 3D and other packaging technologies. Interconnection and communication between integrated chips can be achieved based on interconnection interfaces, thereby forming a chip with the expected functions.

[0003] Integrated chips typically consist of several cores and a scan chain for testing the cores. During the manufacturing, stacking, and packaging of 2.5D / 3D circuits, operations such as thinning, alignment, and bonding can introduce faults and defects into the integrated chip. Therefore, to reduce yield losses and manufacturing costs, each of these processes requires testing the cores of the integrated chip using the scan chain within the integrated chip.

[0004] However, the scan chain path in existing integrated chips is fixed, resulting in poor flexibility in scan chain configuration during testing and making it difficult to adapt to dynamically changing integrated environments. Summary of the Invention

[0005] The problem this invention aims to solve is: how to improve the configuration flexibility of the scan chain within an integrated chip to meet the needs of dynamically changing integration environments.

[0006] To address the aforementioned problems, embodiments of the present invention provide a method for generating an internal scan chain of an integrated chip. The integrated chip includes several cores, each core being connected to a test bus via a controllable unit. The method includes:

[0007] Receive scan chain requirement information;

[0008] Based on the received test requirement information, with the goal of minimizing the overall test time of the integrated chip, the scan chain configuration information is obtained using a preset scan chain configuration model;

[0009] Based on the obtained scan chain configuration information, the corresponding controllable unit is controlled to generate the corresponding scan chain.

[0010] In one possible embodiment, the scan chain requirement information includes: test duration information, location information, and scan chain quantity information for each core within the integrated chip.

[0011] In one possible embodiment, the scan chain requirement information further includes: test bandwidth information of each core within the integrated chip and total available bandwidth information of the test bus.

[0012] In one possible embodiment, the preset scan chain configuration model is implemented using a mixed integer programming solver.

[0013] In one possible embodiment, the preset scan chain configuration model is implemented using the CP-SAT solver.

[0014] In one possible embodiment, the preset scan chain configuration model is adapted to obtain scan chain constraint information based on the received scan chain requirement information, and obtain the values ​​of each decision variable through constraint propagation based on the scan chain constraint information, and filter the values ​​of each decision variable to obtain the scan chain configuration information.

[0015] In one possible embodiment, the scan chain constraint information includes:

[0016] The allocation constraint information is suitable for constraining each core within the integrated chip to be assigned to only one scan chain, as well as constraining the start and end points of each scan chain;

[0017] Chain structure constraint information is suitable for constraining the start and end positions of each scan chain, the connection relationship between non-terminal cores, and the test timing of each core within each scan chain;

[0018] Time constraint information is suitable for constraining the start and end times of each core test;

[0019] Test bus resource constraint information, suitable for globally constraining the test time and test bandwidth of each core on any scan chain in each scan chain;

[0020] The target constraint information is suitable for constraining the overall test duration of all cores.

[0021] This invention also provides an apparatus for generating an internal scan chain of an integrated chip, wherein the integrated chip includes several cores, each core being connected to a test bus via a controllable unit; the apparatus includes:

[0022] A receiving unit, adapted to receive scan chain requirement information;

[0023] The configuration unit is adapted to obtain scan chain configuration information based on the received test requirement information, with the goal of minimizing the overall test time of the integrated chip, using a preset scan chain configuration model;

[0024] The generation unit is adapted to control the corresponding controllable unit based on the obtained scan chain configuration information to generate the corresponding scan chain.

[0025] This invention also provides a computer-readable storage medium having a computer program stored thereon, the computer program being executed by a processor to implement the steps of any of the methods described above.

[0026] This invention also provides an electronic device, including a memory and a processor, wherein the memory stores a computer program that can run on the processor, and the processor executes the steps of any of the methods described above when running the computer program.

[0027] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0028] By applying the solution of this invention, since each core within the integrated chip is connected to each test bus via a controllable unit, upon receiving scan chain requirement information, scan chain configuration information can be obtained based on the received test requirement information. Furthermore, based on the obtained scan chain configuration information, the corresponding controllable unit can be controlled to generate the corresponding scan chain. This allows the scan chain within the integrated chip to change with the scan chain requirement information, realizing the reconfiguration of the scan chain within the integrated chip and better meeting the needs of adapting to various integration environments. In addition, using a preset scan chain configuration model to generate scan chain configuration information can improve scan chain configuration efficiency. Moreover, this preset scan chain configuration model outputs scan chain configuration information with the goal of minimizing the overall test time of the integrated chip, thereby minimizing the overall test time of the integrated chip.

[0029] Furthermore, since the scan chain requirement information also includes the test bandwidth information of each core within the integrated chip and the total available bandwidth information of the test bus, the scan chain can be automatically configured based on test resources. This allows the final generated scan chain to be automatically and adaptively adjusted based on changes in test resources. Thus, while minimizing the overall test time of the integrated chip, changes in test resources can be fully considered, further improving the configuration flexibility of the scan chain within the integrated chip. Attached Figure Description

[0030] Figure 1 This is a schematic diagram of the connection between the core and the test bus in an embodiment of the present invention;

[0031] Figure 2 This is a schematic diagram of an integrated chip layout structure in an embodiment of the present invention;

[0032] Figure 3 This is a flowchart of a scan chain generation method according to an embodiment of the present invention;

[0033] Figures 4 to 6 These are schematic diagrams of different scan chains in the same integrated chip in the embodiments of the present invention;

[0034] Figures 7 to 9 These are schematic diagrams showing the time and bandwidth usage of cores on different scan chains in the same integrated chip in the embodiments of the present invention.

[0035] Figure 10 This is a schematic diagram of the structure of an integrated chip internal scan chain generation device according to an embodiment of the present invention. Detailed Implementation

[0036] A scan chain is a series of flip-flops within an integrated circuit (IC) connected in series to form one or more shiftable "long lines," constituting a long shift register in test mode. An IC may have only one scan chain, or it may have two or more scan chains. Each scan chain has its own input and output ports. The on-chip test controller inputs test data into the IC through the input ports of the scan chain, thereby testing the flip-flops along the path of the scan chain and obtaining the corresponding test response data through the output ports of the scan chain. The flip-flops within the IC used to form a particular scan chain and the timing relationships between them constitute the path of that scan chain.

[0037] Within existing integrated chips, the path of each scan chain is fixed. During testing, only triggers that are part of the scan chain path can selectively connect to the scan chain, while triggers that are not part of the scan chain path cannot connect to the scan chain. This results in poor flexibility in scan chain configuration, making it difficult to adapt to dynamically changing integrated environments.

[0038] To address this issue, this invention provides a method for generating internal scan chains within an integrated chip. This method generates corresponding scan chains based on obtained scan chain configuration information, allowing the internal scan chains of the integrated chip to adapt to changes in scan chain requirements. This enables reconfiguration of the internal scan chains and better meets the needs of various integration environments. Furthermore, using a preset scan chain configuration model to generate scan chain configuration information improves scan chain configuration efficiency and shortens the overall testing time of the integrated chip.

[0039] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0040] To facilitate understanding and implementation of the integrated chip internal scan chain generation method in this embodiment of the invention, the connection method between each core of the integrated chip and the Test Access Mechanism (TAM) bus (hereinafter referred to as "test bus") in this embodiment of the invention will first be described. An integrated chip may include multiple cores. A core is typically a relatively complete, independently operable processor or accelerator that is physically block-shaped and located within the integrated chip.

[0041] In an embodiment of the present invention, in order to enable the scan chain generated inside the integrated chip to change according to the actual needs, that is, to configure the scan chain generated inside the integrated chip according to the actual needs, each core can be set to be connected to each test bus through a controllable unit.

[0042] For example, refer to Figure 1 Taking core C1 in an integrated chip as an example, assuming there are M test buses in the current layout of the integrated chip, core C1 can be connected to each of the M test buses. Each test bus connection path between core C1 and the test C1 can have a controllable unit, such as controllable units q1, q2, q3, and q4. Each controllable unit can be opened or closed under the control of an external control signal. When a controllable unit is closed, core C1 is connected to the test bus connected to that controllable unit; conversely, the connection between core C1 and the test bus connected to that controllable unit is closed. This allows for the custom selection of which test buses to use for transmitting test data to the core, and further, the controllable units can control whether core C1 is connected to the corresponding scan chain. The scan chain can be understood as a movable "long line" formed by the cores connected to the test bus, allowing for the testing of each core connected to the test bus.

[0043] To ensure that controllable units can be configured on each connection path between core C1 and each test bus, the cores within the integrated chip can be laid out in a grid structure. When the integrated chip layout can be a grid structure, each core of the integrated chip is a grid cell, and each grid cell is distributed along the row and column directions to form a regular shape. Typically, this regular shape is as close to a square as possible to minimize aspect ratio deviation.

[0044] In practical implementation, the controllable unit can be implemented using several multiplexers. For example, refer to... Figure 2 Assuming the integrated chip includes 16 cores, designated C1 to C16, a mesh layout of cores C1 to C16 can be obtained. Figure 2 The mesh structure shown. Figure 2 In this configuration, 16 cores are arranged in a 4x4 grid. S1, S2, ..., S16 are multiplexers, and N is the bit width of the test bus. Each core is connected to each test bus L1 to L6 via a corresponding multiplexer. Several multiplexers between each core and a test bus serve as controllable units between that core and the test bus, and are controlled by external control signals.

[0045] For example, core C1 is connected to test bus L1 via multiplexer S1, to test bus L2 via multiplexers S1 and S5, to test bus L3 via multiplexers S1, S5, and S9, and to test bus L4 via multiplexers S1, S5, S9, and S13. Multiplexers S1 and S5 are controllable units between core C1 and test bus L2, multiplexers S1, S5, and S9 are controllable units between core C1 and test bus L3, and multiplexers S1, S5, S9, and S13 are controllable units between core C1 and test bus L4.

[0046] Within this mesh structure, due to the limited number of test ports, the core located at the edge of the mesh structure can be used as the input and output ports for testing. Figure 2 The core components C1, C5, C9, C13, C14, C15, C4, C8, C12, C16, C2, and C3 serve as the input / output ports TI / O1 to TI / O12 for this mesh structure. These input / output ports TI / O1 to TI / O12 can subsequently be used as input and output ports for scan chains. Each scan chain has independent input and output ports, allowing for parallel testing.

[0047] Reference Figure 3 This invention provides a method for generating an internal scan chain of an integrated chip, the method including the following steps:

[0048] Step 31: Receive scan chain requirement information.

[0049] In specific implementation, before generating the scan chain, the device for generating the scan chain inside the integrated chip in this embodiment of the invention has prior knowledge of the integrated chip itself, including the number of cores and the total number of cores, layout structure, set B of boundary cores (i.e., cores located at the edge of the mesh structure), set A of effective cores (i.e., non-empty cores), and set BA of boundary effective cores (located at the edge of the mesh structure and are not empty).

[0050] In one embodiment of the present invention, the scan chain requirement information may include: test duration information, location information, and scan chain quantity information for each core within the integrated chip. Assuming the integrated chip contains 16 cores, the corresponding scan chain requirement information may include: the test duration for each of the 16 cores, the location coordinates of each of the 16 cores, and the required number of scan chains. The integrated chip may generate only one scan chain, or it may generate two or more scan chains, depending on actual needs.

[0051] Integrated chips may be integrated into various system architectures with different test bandwidth availability in the future. Therefore, designing scan chain paths based on the total available bandwidth of the test bus is crucial for maximizing the reusability and market competitiveness of integrated chip designs. However, most existing technologies use static test bandwidth, which is fixed after allocation and cannot be changed, making it difficult to adapt to dynamically changing integration environments.

[0052] Therefore, in one embodiment of the present invention, the scan chain requirement information may further include: the test bandwidth information of each core within the integrated chip and the total available bandwidth information of the test bus. Assuming the integrated chip includes 16 cores, the corresponding scan chain requirement information may further include: the test bandwidth required by each of the 16 cores, and the total available bandwidth of the test bus. This allows the final generated scan chain to not only minimize the overall test time but also meet dynamically changing test bandwidth requirements, offering better configuration flexibility and adaptability to dynamically changing integrated environments.

[0053] Step 32: Based on the received test requirement information, with the goal of minimizing the overall test time of the integrated chip, the scan chain configuration information is obtained using a preset scan chain configuration model.

[0054] In specific implementation, the preset scan chain configuration model is adapted to obtain scan chain constraint information based on the received scan chain requirement information, and obtain the values ​​of each decision variable through constraint propagation based on the scan chain constraint information, and filter the values ​​of each decision variable to obtain the scan chain configuration information.

[0055] Specifically, upon receiving test requirement information, the received information is input into a preset scan chain configuration model. This model first obtains scan chain constraint information based on the received scan chain requirement information, then compiles this constraint information into an integrated chip internal constraint network. A search tree is then used to explore and assign values ​​to decision variables one by one. After each assignment, constraint propagation is immediately performed to deduce the necessary values ​​of other variables. Simultaneously, the objective function T, representing the overall test duration of the integrated chip, is maintained. max The upper and lower bounds are defined, and pruning occurs when the lower bound of a branch exceeds the current optimal upper bound. In this way, multiple worker threads explore different search strategies in parallel, share the optimal solution and learning clauses, and finally return the optimal or feasible solution found within the time limit, thus obtaining the scan chain configuration information with the shortest overall test time for the integrated chip.

[0056] In one embodiment, when the scan chain requirement information only includes the test duration information, location information, and scan chain quantity information of each core within the integrated chip, the scan chain constraint information may only include: allocation constraint information, chain structure constraint information, time constraint information, and target constraint information. Specifically, the allocation constraint information is suitable for constraining each core within the integrated chip to be assigned to only one scan chain, and constraining the start and end points of each scan chain. The chain structure constraint information is suitable for constraining the start and end points of each scan chain, the connection relationships between non-terminal cores, and the test timing of each core within each scan chain. The time constraint information is suitable for constraining the test start and end times of each core.

[0057] Specifically, regarding the allocation constraint information, let core i represent any core within the integrated chip. For each core, the following method can be used to allocate constraints: a binary allocation variable x can be used. i,k Indicates whether core i belongs to scan chain k, where, , Let A be the set of all valid cores within the integrated chip, and K be the total number of scan chains. When x i,k =1 indicates that core i belongs to scan chain k, when x i,k =0 indicates that core i does not belong to scan chain k. Each core i must be assigned to only one scan chain k for testing; other scan chains can only pass through it, and cannot test core i repeatedly. For any scan chain, there is a start point and an end point. To indicate whether core i is the start or end point of scan chain k, we can set two variables for each core, namely... and , , This indicates that core i is the starting point of scan chain k. This indicates that core i is the end point of scan chain k, and the variables corresponding to other cores on scan chain k, excluding the start and end points. and All values ​​are 0. Alternatively, variables can be set. This indicates whether core j immediately follows core i, representing the successor relationship and also the test order. , This means that core j immediately follows core i, otherwise .

[0058] Regarding chain structure constraints, these constraints require that the start and end points of each scan chain must be located at the edge of the mesh structure and belong to that chain. Taking core i as an example, when core i is the start point of the scan chain, the following conditions must be met: and When core i is the end point of the scan chain, it needs to satisfy the following condition: and Additionally, the flow conservation constraint requires that each intermediate core (cores on the scan chain excluding the start and end points) has exactly one predecessor and one successor, forming a continuous path. For example, when core i is the start point of the scan chain, it also needs to satisfy... When core i is the end point of the scan chain, it is also necessary to satisfy... To avoid the formation of sub-loops within the same scan chain, the testing order between cores can be constrained by forcing a specific order. For example, the Miller-Tucker-Zemlin (MTZ) constraint can be used to constrain the testing order between cores, which can be specifically represented as follows: ,Right now This represents the test sequence number of the j-th core on scan chain k. This represents the test sequence number of the i-th core on scan chain k.

[0059] Regarding time constraints, a test start time and a test end time can be defined for each core. Taking core i as an example, let's assume the test start time for core i is S. i S i ∈[0, T_sum], where T_sum represents the sum of the durations of all core tests, then the end time F of core test i is... i =S i +T i T i This represents the test duration for core i. From this, we can obtain the start and end times of the test for each core i.

[0060] Regarding the target constraint information, the overall test duration T of all cores can be... max Defined as the latest end time of all cores, assuming core i is the core tested latest in each scan chain, the target constraint information can be expressed as: T max ≥F i .

[0061] In another embodiment of the present invention, when the scan chain requirement information further includes the test bandwidth information of each core within the integrated chip and the total available bandwidth information of the test bus, the scan chain constraint information may further include: test bus resource constraint information. The test bus resource constraint information is suitable for globally constraining the test time and test bandwidth of each core on any scan chain in each scan chain.

[0062] Specifically, regarding test bus resource constraints, the test bandwidth allocated to each core can be set to not exceed the total available bandwidth of the test bus, for example, the test width w allocated to core i on the k-th scan chain. i,k For example, the global constraint of core i can be specifically expressed as: w i,k +(W) i-1) ≤ WIDTH, where WIDTH is the total available bandwidth of the test bus, W i This represents the test bandwidth allocated to core i, from which the test bus resource constraint information for each core can be obtained. Simultaneously, it ensures that cores allocated to the same chain do not conflict in either time or test bandwidth dimensions. When time overlap exists, efficient parallel testing can be achieved. Taking the two-dimensional non-overlapping constraint NoOverlap2D on core i in both time and test bandwidth dimensions as an example, it can be specifically expressed as: NoOverlap2D ( , ).

[0063] In practical implementation, the pre-defined scan chain configuration model can compile the scan chain constraint information into an integrated chip internal constraint network. Through a search tree exploration, values ​​are assigned to decision variables one by one. For example, assigning core i to scan chain k1, i.e., setting x... i,k1 =1. After each assignment, constraint propagation is immediately performed to deduce the necessary values ​​of other variables. For example, when x... i,k1 When x = 1, then the x of other scan chains k2 i,k2 The value must be 0. Simultaneously, maintain the objective function T representing the overall test duration of the integrated chip. max By identifying the upper and lower bounds, finding the optimal or feasible solution, we obtain the scan chain configuration information that minimizes the overall test time of the integrated chip.

[0064] In practical implementation, the preset scan chain configuration model can be implemented using a mixed-integer programming solver. For example, this mixed-integer programming solver can be the CP-SAT solver. The mixed-integer programming solver can efficiently handle combinations of linear constraints, global constraints, and discrete optimization, thereby quickly obtaining scan chain configuration information.

[0065] Step 33: Based on the obtained scan chain configuration information, control the corresponding controllable unit to generate the corresponding scan chain.

[0066] In practice, once the scan chain configuration information is obtained, the corresponding controllable units within the integrated chip layout structure can be opened or closed, and the corresponding scan chain can be produced within the integrated chip.

[0067] Taking an integrated chip comprising nine cores, designated cores 0 to 8, as an example, with cores 0 to 8 arranged in a 3x3 array, the method for generating the internal scan chain of the integrated chip in this embodiment of the invention can be used to obtain... Figures 4 to 6 The three scan chains are shown. Among them, Figure 4 The diagram shows the path of scan chain 1, which starts at core 6 and proceeds through core 0 and core 3 to core 5 (i.e., the end point). Figure 5The diagram shows the path of scan chain 2, which starts at core 1 and ends at core 4 (i.e., the endpoint). Figure 6 The diagram shows the path of scan chain 4, which starts at core 2, passes through core 6, and reaches core 7 (the endpoint). Figures 4 to 6 In the middle, the blue solid line represents the test path.

[0068] Figure 7 The diagram shows the time and bandwidth usage of each core on scan chain 1. Figure 8 The diagram shows the time and bandwidth usage of each core on scan chain 2. Figure 9 This diagram illustrates the time and bandwidth usage of each core on scan chain 3. Figures 7 to 9 In the diagram, the horizontal axis represents time, the vertical axis represents bandwidth, and the numbers within the coordinate area are the core identifiers.

[0069] from Figure 7 It can be seen that in scan chain 1, cores 0, 6, and 3 can start testing simultaneously. After core 3 finishes testing, core 5 is tested, and the test completion time for core 5 is earlier than that for core 0. From Figure 8 It can be seen that in scan chain 2, core 1 and core 4 were tested sequentially. From Figure 9 As can be seen, in scan chain 3, core 2 and core 7 are tested sequentially. Scan chains 1 through 3 can be tested in parallel.

[0070] As can be seen from the above, the solution of the present invention generates multiple scan chains based on multiple constraints, comprehensively considers test bandwidth allocation, time scheduling constraints, and time conflict constraints of intra-chain and cross-chain routing, and realizes scan chain routing through a mixed integer programming solver. While minimizing the overall test time of the integrated chip, it can also take into account the dynamic changes of test bandwidth and better adapt to various heterogeneous environments.

[0071] To enable those skilled in the art to better understand and implement the present invention, the apparatus, testing system, electronic device, and computer-readable storage medium corresponding to the above method are described in detail below.

[0072] Reference Figure 10 This invention also provides an apparatus for generating an internal scan chain of an integrated chip, the apparatus including: a receiving unit 101, a configuration unit 102, and a generation unit 103. Wherein:

[0073] The receiving unit 101 is adapted to receive scan chain requirement information;

[0074] The configuration unit 102, based on the received test requirement information, aims to minimize the overall test time of the integrated chip and uses a preset scan chain configuration model to obtain scan chain configuration information.

[0075] The generation unit 103 is adapted to control the corresponding controllable unit based on the obtained scan chain configuration information to generate the corresponding scan chain.

[0076] The receiving unit 101, the configuration unit 102, and the generating unit 103 can be implemented with reference to the above description of steps 11 to 13, and will not be repeated here.

[0077] This invention also provides a computer-readable storage medium having a computer program stored thereon, the computer program being executed by a processor to implement the steps of any of the above methods.

[0078] In specific implementations, the computer-readable storage medium may include ROM, RAM, disk, or optical disk, etc.

[0079] This invention also provides an electronic device, which includes a memory and a processor. The memory stores a computer program that can run on the processor, and the processor executes the steps of any of the methods described above when running the computer program.

[0080] Regarding the modules / units included in the various devices and products described in the above embodiments, they can be software modules / units, hardware modules / units, or a combination of both. For example, for various devices and products applied to or integrated into a chip, all of their modules / units can be implemented using hardware methods such as circuits, or at least some modules / units can be implemented using software programs that run on a processor integrated within the chip, while the remaining (if any) modules / units can be implemented using hardware methods such as circuits; for various devices and products applied to or integrated into a chip module, all of their modules / units can be implemented using hardware methods such as circuits, and different modules / units can be located in the same component (e.g., chip, circuit module, etc.) or different components of the chip module, or at least some modules / units can be implemented using hardware methods such as circuits. The components can be implemented using software programs that run on the processor integrated within the chip module. The remaining (if any) modules / units can be implemented using hardware methods such as circuits. For various devices and products applied to or integrated into the terminal, each of its components / units can be implemented using hardware methods such as circuits. Different modules / units can be located in the same component (e.g., chip, circuit module, etc.) or in different components within the terminal. Alternatively, at least some modules / units can be implemented using software programs that run on the processor integrated within the terminal, while the remaining (if any) modules / units can be implemented using hardware methods such as circuits.

[0081] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for generating an internal scan chain of an integrated chip in a 2.5D / 3D circuit, characterized in that, The integrated chip includes several cores, each core being connected to a test bus via a controllable unit; the method includes: Receive scan chain requirement information; Based on the received test requirement information, with the goal of minimizing the overall test time of the integrated chip, the scan chain configuration information is obtained using a preset scan chain configuration model; Based on the obtained scan chain configuration information, the corresponding controllable unit is controlled to generate the corresponding scan chain.

2. The method for generating an internal scan chain of an integrated chip as described in claim 1, characterized in that, The scan chain requirement information includes: test duration information, location information, and scan chain quantity information for each core within the integrated chip.

3. The method for generating an internal scan chain of an integrated chip as described in claim 2, characterized in that, The scan chain requirement information also includes: the test bandwidth information of each core within the integrated chip and the total available bandwidth information of the test bus.

4. The method for generating an internal scan chain of an integrated chip as described in claim 1, characterized in that, The preset scan chain configuration model is implemented using a mixed integer programming solver.

5. The method for generating an internal scan chain of an integrated chip as described in claim 1, characterized in that, The preset scan chain configuration model is implemented using the CP-SAT solver.

6. The method for generating an internal scan chain of an integrated chip as described in claim 4 or 5, characterized in that, The preset scan chain configuration model is adapted to obtain scan chain constraint information based on the received scan chain requirement information, obtain the values ​​of each decision variable through constraint propagation based on the scan chain constraint information, and filter the values ​​of each decision variable to obtain the scan chain configuration information.

7. The method for generating an internal scan chain of an integrated chip as described in claim 6, characterized in that, The scan chain constraint information includes: The allocation constraint information is suitable for constraining each core within the integrated chip to be assigned to only one scan chain, as well as constraining the start and end points of each scan chain; Chain structure constraint information is suitable for constraining the start and end positions of each scan chain, the connection relationship between non-terminal cores, and the test timing of each core within each scan chain; Time constraint information is suitable for constraining the start and end times of each core test; Test bus resource constraint information, suitable for globally constraining the test time and test bandwidth of each core on any scan chain in each scan chain; The target constraint information is suitable for constraining the overall test duration of all cores.

8. An apparatus for generating an internal scan chain of an integrated chip, characterized in that, The integrated chip includes several cores, each core being connected to a test bus via a controllable unit; the device includes: A receiving unit, adapted to receive scan chain requirement information; The configuration unit is adapted to obtain scan chain configuration information based on the received test requirement information, with the goal of minimizing the overall test time of the integrated chip, using a preset scan chain configuration model; The generation unit is adapted to control the corresponding controllable unit based on the obtained scan chain configuration information to generate the corresponding scan chain.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that, The computer program is executed by a processor to implement the steps of the method according to any one of claims 1 to 7.

10. An electronic device comprising a memory and a processor, wherein the memory stores a computer program capable of running on the processor, characterized in that, When the processor runs the computer program, it performs the steps of the method according to any one of claims 1 to 7.

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