Driving method and driving circuit of display panel and display device

Abstract

The invention provides a driving method of a display panel, a driving circuit and a display device, and the driving method comprises the steps: outputting a data voltage with unchanged polarity to each data line at an effective display stage of a current frame picture; respectively outputting corresponding first data voltages to the a target data lines in at least part of the time period of the vertical blanking stage of the current frame of picture, so as to apply a bias voltage to the adjacent pixel electrodes of the target data lines through the coupling effect of the corresponding first coupling capacitors; the polarity of the first data voltage corresponding to each target data line is the same as the polarity of the data voltage received by the data line in the effective display stage of the current frame of picture; the gray scale number of the first data voltage corresponding to each target data line is higher than or equal to the highest gray scale number of the data voltage received by the data line in the current frame picture. According to the driving method, the problems of brightness change and flicker of the display panel in a variable refresh rate mode can be improved.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a driving method, driving circuit, and display device for a display panel. Background Technology

[0002] In traditional display systems, the monitor's refresh rate is fixed (e.g., 60Hz), while the frame output rate of the graphics processing unit (GPU) fluctuates depending on the complexity of the scene. This mismatch can lead to screen tearing (when multiple frames of content are displayed on the same screen simultaneously) and stuttering.

[0003] To address these issues, the industry introduced FreeSync technology (variable refresh rate technology, also known as a screen adaptive synchronization technology). This technology dynamically adjusts the monitor's refresh rate to match the GPU's frame rate output in real time, effectively reducing screen tearing and stuttering without strictly limiting GPU performance. FreeSync adjusts the refresh rate by changing the number of rows in the vertical blanking phase (VBlank area). Specifically, while keeping the pixel clock constant, the refresh rate is dynamically changed by increasing or decreasing the duration of the VBLank area (i.e., changing the total number of rows (VTotal) in a frame). For example, when a lower refresh rate is needed, the system appropriately increases the number of rows in the VBLank area.

[0004] However, in liquid crystal displays (LCDs), due to the physical characteristics of liquid crystal materials, the charge in the liquid crystal capacitors leaks slowly. When using Freesync technology, when the dynamic refresh rate changes significantly, the duration of the vertical blanking phase between different frames varies considerably. This leads to significant differences in the leakage time of the liquid crystal capacitors, resulting in large differences in brightness between different frames, causing noticeable changes in brightness and flickering on the display. Summary of the Invention

[0005] In view of this, the main purpose of this application is to propose a driving method, driving circuit and display device for a display panel, which aims to solve the problem that when existing displays use Freesync technology for display, significant changes in brightness and flickering can easily occur when the dynamic refresh rate changes drastically.

[0006] To achieve the above objectives, a first aspect of this application provides a driving method for a display panel, the display panel comprising x data lines and x columns of sub-pixels, wherein the x data lines extend along the column direction, the x data lines and the x columns of sub-pixels are electrically connected in a one-to-one correspondence, each sub-pixel includes a pixel electrode, and the pixel electrode forms a first coupling capacitor with an adjacent data line, x>1; the driving method includes: during the effective display phase of the current frame, outputting a data voltage with constant polarity to each of the data lines; and during at least a portion of the vertical blanking phase of the current frame, outputting a data voltage to each of the x data lines. According to the a target data lines in the data line, the corresponding first data voltage is output respectively, so as to apply a bias voltage to the pixel electrode in the sub-pixel of each target data line through the coupling effect of the corresponding first coupling capacitor; wherein, a≤x, and a≥1; wherein, the polarity of the first data voltage corresponding to each target data line is the same as the polarity of the data voltage received by this data line in the effective display stage of the current frame, and the gray level of the first data voltage corresponding to each target data line is higher than or equal to the highest gray level of the data voltage received by this data line in the effective display stage of the current frame.

[0007] The driving method provided in this application outputs corresponding first data voltages to a target data lines among the x data lines during at least a portion of the vertical blanking phase of the current frame. Through the coupling effect of the corresponding first coupling capacitor, a bias voltage is applied to the pixel electrodes in the adjacent sub-pixels of each target data line. This can compensate for the voltage loss caused by leakage current in the pixel electrodes of at least a portion of the sub-pixels during the vertical blanking phase. The brightness increase brought by the bias voltage can at least partially offset the brightness decay caused by leakage current, thereby improving the brightness variation and flickering problems of the display panel in Freesync mode.

[0008] In some embodiments of this application, the display panel is a column-reversed display panel, x=3×b; the sub-pixels located in the same column have the same color, the x-column sub-pixels include b-column red sub-pixels, b-column green sub-pixels and b-column blue sub-pixels, the a-target data lines include at least one of the b-column green data lines, wherein the green data lines are data lines electrically connected to the green sub-pixels, and a≤b.

[0009] In some embodiments of this application, the display panel is a column-inverted display panel, x = 3 × b; the sub-pixels located in the same column have the same color, the x-column sub-pixels include b-column red sub-pixels, b-column green sub-pixels and b-column blue sub-pixels, the a-target data lines include e-column red data lines and f-column green data lines; wherein, the red data lines are data lines electrically connected to the red sub-pixels, the green data lines are data lines electrically connected to the green sub-pixels, 1 ≤ e ≤ b, 1 ≤ f ≤ b.

[0010] In some embodiments of this application, the display panel is a surface-reversible display panel, where a=x.

[0011] In some embodiments of this application, before outputting corresponding first data voltages to a target data lines among the x data lines respectively during at least a portion of the vertical blanking phase of the current frame, the driving method further includes: determining whether the display panel is currently in a variable refresh rate mode; outputting corresponding first data voltages to a target data lines among the x data lines respectively during at least a portion of the vertical blanking phase of the current frame, including: if the display panel is currently in a variable refresh rate mode, then outputting corresponding first data voltages to a target data lines among the x data lines respectively during at least a portion of the vertical blanking phase of the current frame.

[0012] In some embodiments of this application, the step of outputting corresponding first data voltages to a target data lines among the x data lines includes: outputting the highest positive grayscale voltage of the display panel to the positive polarity data lines among the a target data lines; wherein, the positive polarity data lines are the data lines among the a target data lines whose data voltage polarity is positive during the effective display phase of the current frame; and outputting the highest negative grayscale voltage of the display panel to the negative polarity data lines among the a target data lines; wherein, the negative polarity data lines are the data lines among the a target data lines whose data voltage polarity is negative during the effective display phase of the current frame.

[0013] In some embodiments of this application, the step of outputting corresponding first data voltages to a target data lines among the x data lines during at least a portion of the vertical blanking phase of the current frame includes: outputting corresponding first data voltages to a target data lines among the x data lines at the start of the vertical blanking phase of the current frame; and stopping the output of corresponding first data voltages to a target data lines among the x data lines before the effective display phase of the next frame.

[0014] In some embodiments of this application, the step of outputting corresponding first data voltages to a target data lines among the x data lines during at least a portion of the vertical blanking phase of the current frame includes: outputting corresponding zero-grayscale voltages to the x data lines at the start of the vertical blanking phase of the current frame; and outputting corresponding first data voltages to a target data lines among the x data lines when the duration of the vertical blanking phase of the current frame reaches a preset duration.

[0015] A second aspect of this application also provides a driving circuit for controlling the execution of steps in the driving method for a display panel as described in the first aspect above, so as to drive the display panel to display.

[0016] A third aspect of this application also provides a display device, the display device including a display panel and a driving circuit as described in the first aspect above, the driving circuit being electrically connected to the display panel and used to drive the display panel to perform display.

[0017] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the structure of the display device provided in the embodiments of this application; Figure 2 for Figure 1 The equivalent circuit diagram of a sub-pixel; Figure 3 A flowchart illustrating the driving method for a display panel provided in an embodiment of this application; Figure 4 for Figure 1 The timing diagram of the first type of data signal for the display device shown is as follows; Figure 5 for Figure 1 The second type of data signal timing diagram of the display device is shown; Figure 6 for Figure 1 The image shown is a measured diagram of the first type of brightness change during refresh rate switching of the display device. Figure 7 for Figure 1 The image shown is a measured diagram of the second type of brightness change during refresh rate switching of the display device.

[0019] The annotations in the attached figures are explained as follows:

[0020] The following detailed description, in conjunction with the accompanying drawings, will further illustrate this application. Detailed Implementation

[0021] In the description of the embodiments of this application, the terminology used in the following embodiments is for the purpose of describing specific embodiments only and is not intended to be a limitation of this application. As used in the specification and appended claims of this application, the singular expressions "a," "the," "the," "the," and "this" are intended to also include expressions such as "one or more," unless the context clearly indicates otherwise. It should also be understood that in the following embodiments of this application, "at least one" and "one or more" refer to one or more (including two). The term "and / or" is used to describe the relationship between related objects, indicating that three relationships can exist; for example, A and / or B can indicate: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship.

[0022] References to "one embodiment" or "some embodiments" in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized. The term "connection" includes direct connections and indirect connections, unless otherwise stated. "First" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated.

[0023] In the embodiments of this application, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design that is described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design. Specifically, the use of the terms "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0024] The various embodiments of this application can be combined arbitrarily to achieve different technical effects.

[0025] In recent years, with the booming development of the e-sports industry and high-quality video content, users have placed higher demands on the smoothness, stability, and response speed of monitors. Against this backdrop, adaptive synchronous display technology has emerged as a key solution to the refresh rate mismatch between graphics rendering devices (such as GPUs) and display devices.

[0026] Screen tearing, stuttering, and input lag are persistent problems in traditional fixed refresh rate display technologies for dynamic video displays. The root cause lies in the fact that the frame output rate of the graphics processor (GPU) changes dynamically, while the monitor's refresh rate is fixed. When the GPU's output frame rate exceeds the monitor's refresh rate, the buffer data is overwritten by new frames during the monitor's scan, causing parts of multiple frames to appear on the screen simultaneously—this is screen tearing. To solve this problem, Vertical Sync (V-Sync) technology was commonly used, which eliminates tearing by having the GPU wait for the monitor to complete the refresh of the current frame before outputting the next. However, this "waiting" mechanism inevitably introduces additional input lag and easily leads to severe stuttering when the frame rate fluctuates, thus seriously affecting the gaming experience.

[0027] To overcome the drawbacks of V-Sync, the industry introduced FreeSync technology. Its core principle is to make the monitor's refresh rate no longer a fixed value, but a dynamically changing variable that matches the GPU's instantaneous frame rate in real time. Specifically, FreeSync technology achieves continuous refresh rate changes by dynamically adjusting the duration of the vertical blanking phase (VBlank area) in the display timing. With a constant pixel clock, by increasing or decreasing the line scan time included in the VBLank area (i.e., changing the total number of lines in a frame, VTotal), the duration of each frame is altered, ultimately achieving dynamic adjustment of the refresh rate. This method allows the monitor to "wait" for the GPU to fully render one frame before starting the scan of the next, fundamentally eliminating tearing and significantly reducing input latency and stuttering. Specifically, the display cycle of a frame is divided into an effective display phase (Active area) and a vertical blanking phase before entering the next frame. Taking an FHD (48Hz-240Hz) display as an example, its display resolution is 1920*1080, meaning that a frame needs to scan and charge 1080 lines. This 1080-line charging time is the Active area. Then, there is a 45-line pause before entering the next frame. This 45-line pause time is the VBLank area. Freesync technology changes the refresh rate by changing the number of lines in the VBLank area. For a 240Hz screen, the number of lines in a frame, or VTotal, is 1125. If the VBLank area increases by 1125 lines, the number of lines in a frame, or VTotal, becomes 2250. Since the time for each line is the same, the refresh rate changes from 240Hz to 120Hz.

[0028] While FreeSync technology has achieved significant results in improving image smoothness, its dynamic refresh rate adjustment mechanism presents new challenges to the brightness stability of liquid crystal displays (LCDs). LCDs rely on charging the liquid crystal capacitors of each sub-pixel P to maintain the required voltage difference (voltage differential) across the liquid crystal to control light transmission and thus display grayscale. However, the charge stored in the liquid crystal capacitors inevitably leaks between frames (i.e., leakage current).

[0029] Specifically, for example Figures 1-2 As shown, Figure 1 This is a schematic diagram of the structure of the display panel 10 provided in an embodiment of this application; Figure 2 for Figure 1 The equivalent circuit diagram of a sub-pixel is shown. The sub-pixel P located in the m-th row and n-th column includes a scanning transistor T1 and a pixel electrode 111, where m ≥ 1 and n ≥ 1. The gate of the scanning transistor T1 is electrically connected to the m-th scan line Gm, the drain of the scanning transistor T1 is electrically connected to the n-th data line Dn, and the source of the scanning transistor T1 is electrically connected to the pixel electrode 111. A coupling capacitor Cpg is formed between the m-th scan line Gm and the pixel electrode 111, a coupling capacitor Cpg' is formed between the (m+1)-th scan line Gm+1 and the pixel electrode 111, a coupling capacitor Cpd is formed between the pixel electrode 111 and the n-th data line Dn, a coupling capacitor Cpd' is formed between the pixel electrode 111 and the common electrode COM, a storage capacitor Cst and a liquid crystal capacitor Clc are formed between the pixel electrode 111 and the common electrode COM, and a parasitic capacitance Cgs is formed between the gate and the source of the scanning transistor T1. When the sub-pixel P finishes charging, the charge stored in its pixel electrode 111 will slowly leak out through these capacitors.

[0030] At a fixed refresh rate, this leakage is regular and predictable, and can be compensated for through circuit design. However, in Freesync mode, when the refresh rate fluctuates drastically over a wide range (e.g., from 48Hz to 240Hz), the duration of each frame at a low refresh rate (e.g., approximately 20.83ms at 48Hz) is much longer than the frame duration at a high refresh rate (e.g., approximately 4.17ms at 240Hz). This means that the time the liquid crystal cell needs to maintain the voltage difference at low refresh rates increases exponentially, resulting in significantly greater charge leakage than at high refresh rates. The difference in the degree to which the voltage difference is maintained directly leads to different actual brightness levels for the same target grayscale at different refresh rates. When the refresh rate changes drastically, the human eye will perceive fluctuations in screen brightness or even flickering. This problem has become one of the bottlenecks restricting the further application of Freesync technology in high-quality LCD display devices.

[0031] Currently, industry efforts to address this issue are mainly focused on two directions: First, fundamentally improving the properties of liquid crystal materials or optimizing the manufacturing process of thin-film transistors (TFTs) (e.g., using materials with higher mobility and lower off-state current, such as IGZO) to reduce leakage current. However, such solutions involve complex materials science and process adjustments, resulting in high costs and long development cycles. Second, compensation is implemented at the driving level, such as attempting to adjust the Gamma voltage in the VBLANK region to improve display brightness at low refresh rates. However, achieving a dynamic compensation scheme that can accurately and smoothly adapt to wide, high-frequency variable refresh rates still presents many technical challenges that need to be overcome.

[0032] Therefore, there is an urgent need for an innovative driving method that can effectively solve the problem of noticeable brightness changes and flickering when existing displays use Freesync technology and the dynamic refresh rate changes significantly. This would allow users to enjoy the smooth picture advantages brought by variable refresh rate technology while ensuring a high degree of consistency in visual brightness.

[0033] In view of this, embodiments of this application provide a method for driving a display panel. Please refer to the following: Figure 1 and Figure 3 , Figure 3 A flowchart illustrating the driving method for a display panel provided in an embodiment of this application.

[0034] like Figure 1 As shown, the display panel 10 is an LCD display panel. The display panel 10 includes x data lines and x columns of sub-pixels P. The x data lines extend along the column direction, and each of the x data lines and the x columns of sub-pixels P is electrically connected in a one-to-one correspondence (i.e., each data line corresponds to one column of sub-pixels P and is electrically connected to each sub-pixel P in the corresponding column of sub-pixels P). Each data line is adjacent to the corresponding column of sub-pixels P. The x data lines and the x columns of sub-pixels P are arranged alternately along the row direction, i.e., one data line is arranged between any two adjacent columns of sub-pixels P, and one column of sub-pixels P is arranged between any two adjacent data lines. Each sub-pixel P includes a pixel electrode 111, and a first coupling capacitor (e.g., ...) is formed between the pixel electrode 111 and the data line adjacent to the sub-pixel P. Figure 2 The coupling capacitors Cpd and Cpd' in the figure are x>1.

[0035] like Figure 3 As shown, the driving method includes: Step S1: During the effective display phase of the current frame, output a data voltage with constant polarity to each of the data lines; Step S2, during at least a part of the vertical blanking period of the current frame image, output corresponding first data voltages to a target data lines among the x data lines respectively, so as to apply a bias voltage to the pixel electrodes 111 in the sub-pixels P adjacent to each target data line through the coupling effect of the corresponding first coupling capacitors.

[0036] Among them, a ≤ x and a ≥ 1.

[0037] Among them, outputting data voltages with unchanged polarities to each data line means that the polarities of the data voltages received by each data line during the effective display period of the current frame image are either all positive polarities or all negative polarities, while the polarities of the data voltages received by different data lines can be different. Among them, the polarity of the data voltage is defined relative to the common voltage (Vcom). When the data voltage > Vcom, it is a positive polarity (+), and the higher the data voltage, the higher the gray scale number; when the data voltage < Vcom, it is a negative polarity (-), and the lower the data voltage, the higher the gray scale number.

[0038] Among them, the polarity of the first data voltage corresponding to each target data line is the same as the polarity of the data voltage received by this data line during the effective display period of the current frame image, and the gray scale number of the first data voltage corresponding to each target data line is higher than or equal to the highest gray scale number of the data voltage received by this data line during the effective display period of the current frame image.

[0039] That is to say, the polarity of the bias voltage applied by each target data line to the pixel electrode 111 in the adjacent sub-pixel P through the corresponding first coupling capacitor is the same as the polarity of the data voltage received by this target data line during the effective display period of the current frame image. Thus, this bias voltage will increase the brightness of at least some sub-pixels P.

[0040] Exemplarily, if the polarity of the data voltage received by a certain target data line during the effective display period of the current frame image is a positive polarity, and the highest gray scale number of the received data voltage is 200 gray scales of positive polarity, then the first data voltage corresponding to this target data line is higher than or equal to the data voltage corresponding to 200 gray scales of positive polarity (for example, a positive polarity 210 gray scale voltage). Thus, this target data line applies a positive polarity bias voltage to the pixel electrode 111 in the adjacent sub-pixel P, that is, raises the voltage of the corresponding pixel electrode 111. Therefore, when the polarity of the data voltage received by the pixel electrode 111 in the sub-pixel P adjacent to this target data line during the effective display period of the current frame image is also a positive polarity, this bias voltage can compensate for the voltage loss caused by leakage of the pixel electrode 111 in the vertical blanking period, and further, the brightness increase brought by this bias voltage will at least partially offset the brightness attenuation caused by leakage.

[0041] Similarly, if the polarity of the data voltage received by a target data line during the effective display phase of the current frame is negative, and the highest gray level of the received data voltage is negative 150 gray level, then the first data voltage corresponding to the target data line is lower than or equal to the data voltage corresponding to negative 150 gray level (e.g., negative 160 gray level voltage). Thus, the target data line applies a negative bias voltage to the pixel electrode 111 in the adjacent sub-pixel P, i.e., pulls down the voltage of the corresponding pixel electrode 111. Therefore, when the polarity of the data voltage received by the pixel electrode 111 in the sub-pixel P adjacent to the target data line during the effective display phase of the current frame is also negative, this bias voltage can compensate for the voltage loss caused by leakage current in the pixel electrode 111 of the sub-pixel P during the vertical blanking phase. Consequently, the brightness increase brought about by this bias voltage will at least partially offset the brightness decay caused by leakage current.

[0042] The driving method provided in this application outputs corresponding first data voltages to a target data lines among the x data lines during at least a portion of the vertical blanking phase of the current frame. Through the coupling effect of the corresponding first coupling capacitor, a bias voltage is applied to the pixel electrodes 111 in the adjacent sub-pixels P of each target data line. This can compensate for the voltage loss caused by leakage current in the pixel electrodes 111 of at least a portion of the sub-pixels P during the vertical blanking phase. The brightness increase brought by the bias voltage can at least partially offset the brightness decay caused by leakage current, thereby improving the brightness variation and flickering problems of the display panel 10 in Freesync mode.

[0043] In some embodiments of this application, the polarity of the data voltage received by each data line during the effective display phase of the current frame is opposite to the polarity of the data voltage received during the effective display phase of the previous frame. That is, if the polarity of the data voltage received by a data line during the effective display phase of the previous frame is positive, then the polarity of the data voltage received by that data line during the effective display phase of the current frame is negative; if the polarity of the data voltage received by a data line during the effective display phase of the previous frame is negative, then the polarity of the data voltage received by that data line during the effective display phase of the current frame is positive.

[0044] In some embodiments of this application, before outputting corresponding first data voltages to a target data lines among the x data lines respectively during at least a portion of the vertical blanking phase of the current frame, the driving method further includes: Determine whether the display panel 10 is currently in variable refresh rate mode.

[0045] The step of outputting corresponding first data voltages to a target data lines among the x data lines during at least a portion of the vertical blanking phase of the current frame includes: If the display panel 10 is currently in variable refresh rate mode, then during at least a portion of the vertical blanking phase of the current frame, the corresponding first data voltage is output to a target data line among the x data lines, and zero grayscale voltage is output to the other data lines besides the a target data lines.

[0046] The driving method further includes: If the display panel 10 is not currently in variable refresh rate mode, then during the vertical blanking phase of the current frame, the corresponding zero grayscale voltage is output to the x data lines.

[0047] Specifically, outputting a corresponding zero-grayscale voltage to a certain data line includes: when the polarity of the data voltage received by the data line in the current frame is positive, outputting a positive zero-grayscale voltage to the data line; when the polarity of the data voltage received by the data line in the current frame is negative, outputting a negative zero-grayscale voltage to the data line.

[0048] It is easy to understand that when the display panel 10 is not in variable refresh rate mode, brightness compensation is not required. Thus, brightness compensation is only performed by outputting the first data voltage to the target data line when the display panel 10 is currently in variable refresh rate mode, and not when the display panel 10 is not in variable refresh rate mode, thereby reducing power consumption.

[0049] In some embodiments of this application, the step of outputting a corresponding first data voltage to a target data lines among the x data lines includes: The highest positive grayscale voltage of the display panel 10 is output to the positive polarity data line among the a target data lines; wherein, the positive polarity data line is the data line among the a target data lines whose data voltage polarity is positive during the effective display phase of the current frame. The highest negative grayscale voltage of the display panel 10 is output to the negative polarity data line among the a target data lines; wherein, the negative polarity data line is the data line among the a target data lines whose data voltage polarity is negative during the effective display phase of the current frame.

[0050] For example, when the highest gray level of the display panel 10 is 255 gray levels, the data voltage corresponding to the positive polarity 255 gray level is the highest gray level voltage of the positive polarity, and the data voltage corresponding to the negative polarity 255 gray level is the highest gray level voltage of the negative polarity.

[0051] Thus, in the target data lines a, the first data voltage received by all positive data lines is the same, which is the highest positive grayscale voltage of the display panel 10, and the first data voltage received by all negative data lines is the same, which is the highest negative grayscale voltage of the display panel 10. The control logic is simple.

[0052] In some embodiments of this application, before outputting corresponding first data voltages to a target data lines among the x data lines respectively during at least a portion of the vertical blanking phase of the current frame, so as to apply a bias voltage to the pixel electrode 111 in the adjacent sub-pixel P of each of the target data lines through the coupling effect of the corresponding first coupling capacitor, the driving method further includes: The first data voltage corresponding to each target data line is determined based on the data voltage received by each target data line in the current frame.

[0053] For example, when a target data line is a positive polarity data line, the first data voltage corresponding to each target data line can be calculated according to the following formula: Vs=max{α1×V1max+, Vtmax+}; Wherein, α1≥1, for example 1.1, Vs is the first data voltage corresponding to the target data line, V1max+ is the maximum value of the data voltage received by the target data line in the current frame, and Vtmax+ is the highest positive grayscale voltage of the display panel 10.

[0054] When a target data line is a negative polarity data line, the first data voltage corresponding to each target data line can be calculated using the following formula: Vs=min{α2×V1min-, Vtmax-}; Where α2≤1, for example 0.9, Vs is the first data voltage corresponding to the target data line, V1min is the minimum value of the data voltage received by the target data line in the current frame, and Vtmax is the highest negative grayscale voltage of the display panel 10.

[0055] In this way, by selecting an appropriate first data voltage based on the data voltage received by each target data line in the current frame, the compensation accuracy is higher compared to using a uniform first data voltage for compensation.

[0056] In some embodiments of this application, the step of outputting corresponding first data voltages to a target data lines among the x data lines respectively during at least a portion of the vertical blanking phase of the current frame includes: At the start of the vertical blanking phase of the current frame, the corresponding first data voltage is output to a target data lines among the x data lines respectively; Before the effective display phase of the next frame, the output of the corresponding first data voltage to each of the x data lines is stopped.

[0057] In some embodiments of this application, the display panel 10 is a surface-inverted display panel 10, where a=x. That is, each data line in the display panel 10 is the target data line, meaning all sub-pixels P in the display panel 10 are compensation targets, resulting in better compensation effects. Of course, in other embodiments, some data lines in the display panel 10 can also be designated as the target data lines.

[0058] In some embodiments of this application, the display panel 10 is a column-reversed display panel 10, x=3×a; the sub-pixels P located in the same column have the same color, the x columns of sub-pixels P include b columns of red sub-pixels P1, b columns of green sub-pixels P2 and b columns of blue sub-pixels P3, the a target data lines include at least one of the b green data lines, wherein the green data lines are data lines electrically connected to the green sub-pixels, and a≤b.

[0059] For example, please refer to the following: Figure 1 and Figure 4 , Figure 4 for Figure 1 The diagram shows the timing of the first type of data signal for the display device. (See diagram for example.) Figure 1 As shown, in the display panel 10, the i-th data line is located on the first side of the row direction of the i-th column sub-pixel P and is electrically connected to the i-th column sub-pixel P, where 1≤i≤x. Each row of sub-pixels P is arranged cyclically in the order of red sub-pixel P1, green sub-pixel P2, and blue sub-pixel P3. Specifically, the 3×c+1-th column sub-pixel is red sub-pixel P1, the 3×c+2-th column sub-pixel is green sub-pixel P2, and the 3×c+3-th column sub-pixel is blue sub-pixel P3. Correspondingly, the 3×c+1-th data line is electrically connected to the red sub-pixel P1 (referred to as the red data line), the 3×c+2-th data line is electrically connected to the green sub-pixel P2 (referred to as the green data line), and the 3×c+3-th data line is electrically connected to the blue sub-pixel P3 (referred to as the blue data line), where 0≤c≤b-1. In this embodiment, a=b, that is, b green data lines are the a-th target data line. In other embodiments, the number of target data lines may also be only a portion of the b green data lines, i.e., a may be less than b.

[0060] like Figure 4As shown, during operation, in the vertical blanking phase of each frame, zero grayscale voltage is output to the first data line D1 (i.e., the red data line) and the third data line D3 (i.e., the blue data line); in the vertical blanking phase of the first frame, the highest negative grayscale voltage, such as a negative 255 grayscale voltage, is output to the second data line D2 (i.e., the green data line). During the vertical blanking phase of the second frame, the highest positive grayscale voltage, such as a positive 255 grayscale voltage, is output to the second data line D2; during the vertical blanking phase of the third frame, the highest negative grayscale voltage is output to the second data line D2, and so on.

[0061] It should be noted that in the display panel 10, adjacent red sub-pixels P1, green sub-pixels P2, and blue sub-pixels P3 in the row direction form a pixel unit. Since the human eye is most sensitive to green light (wavelength approximately 550 nanometers), with a sensitivity far exceeding that of red and blue, and the lowest sensitivity to blue, the green sub-pixel P2 is typically used as the "primary brightness" carrier within a pixel unit.

[0062] Since the polarity of the first data voltage received by the green data line is the same as the polarity of the data voltage received by the green sub-pixel P2, which is electrically connected to this data line, during the effective display phase, under the coupling effect of the first coupling capacitor, the first data voltage will apply a bias voltage of the same polarity to the pixel electrode 111 in the corresponding green sub-pixel P2, which will positively pull the voltage of the pixel electrode 111 in the green sub-pixel P2, thereby increasing the brightness of the green sub-pixel P2.

[0063] Similarly, since the polarity of the first data voltage received by the green data line is opposite to the polarity of the data voltage received by the red sub-pixel P1, which is electrically connected to this data line, during the effective display phase, under the coupling effect of the first coupling capacitor, the first data voltage will apply a bias voltage of opposite polarity to the pixel electrode 111 in the corresponding red sub-pixel P1, which will pull the voltage of the pixel electrode 111 in the red sub-pixel P1 in the opposite direction, thereby reducing the brightness of the red sub-pixel P1.

[0064] Since the pixel electrode 111 in the blue sub-pixel P3 is not coupled by the first data voltage, the brightness of the blue sub-pixel P3 is not affected.

[0065] In summary, when the display panel 10 displays using the driving method that compensates for the green data line, compared to existing driving methods, it can increase the brightness of the green sub-pixel P2 and decrease the brightness of the red sub-pixel P1. As mentioned earlier, since the green sub-pixel P2 is the "main brightness" carrier in the pixel unit, the overall brightness of the display panel 10 is increased. At high refresh rates, due to the short duration of the vertical blanking phase, this brightness increase has virtually no impact on the brightness of the display panel 10. As the refresh rate decreases, the vertical blanking phase becomes longer, and the duration of this brightness increase is longer. The increased brightness can at least partially offset the brightness decay caused by leakage. Furthermore, in Freesync or VRR modes, the brightness decay at low refresh rates is reduced, which can improve the problems of brightness changes and flickering that occur during refresh rate switching.

[0066] In some embodiments of this application, the display panel 10 is a column-reversed display panel 10, where x = 3 × b. Sub-pixels P located in the same column have the same color. The x columns of sub-pixels P include b columns of red sub-pixels P1, b columns of green sub-pixels P2, and b columns of blue sub-pixels P3. The a target data lines include e red data lines and f green data lines, wherein the red data lines are data lines electrically connected to the red sub-pixels, and the green data lines are data lines electrically connected to the green sub-pixels, where 1 ≤ e ≤ b and 1 ≤ f ≤ b.

[0067] For example, please refer to the following: Figure 1 , Figures 5-7 , Figure 5 for Figure 1 The second data signal timing diagram of the display device shown is as follows: Figure 6 for Figure 1 The image shown is a measured diagram of the first type of brightness change during refresh rate switching of the display device. Figure 1 The image shown is a measured diagram of the brightness change of the display device during refresh rate switching under the control of the existing driving method. Figure 7 for Figure 1 The image shown is a measured diagram of the second type of brightness change during refresh rate switching of the display device. Figure 1 The diagram shown illustrates the measured brightness change of the display device during refresh rate switching under the control of the driving method provided in this embodiment.

[0068] like Figure 1As shown, in the display panel 10, the i-th data line is located on the first side of the row direction of the i-th column sub-pixel P and is electrically connected to the i-th column sub-pixel P, where 1≤i≤x. Each row of sub-pixels P is arranged cyclically in the order of red sub-pixel P1, green sub-pixel P2, and blue sub-pixel P3. Specifically, the 3×c+1-th column sub-pixel is red sub-pixel P1, the 3×c+2-th column sub-pixel is green sub-pixel P2, and the 3×c+3-th column sub-pixel is blue sub-pixel P3. Correspondingly, the 3×c+1-th data line is electrically connected to the red sub-pixel P1 and is referred to as the red data line; the 3×c+2-th data line is electrically connected to the green sub-pixel P2 and is referred to as the green data line; and the 3×c+3-th data line is electrically connected to the blue sub-pixel P3 and is referred to as the blue data line, where 0≤c≤b-1. In this embodiment, e=f=b, a=2×b, that is, the target data lines a include b green data lines and b red data lines.

[0069] like Figure 5 As shown, during operation, in the vertical blanking phase of the first frame, the highest positive grayscale voltage, such as a positive 255 grayscale voltage, is output to the first data line D1 (i.e., the red data line); in the vertical blanking phase of the second frame, the highest negative grayscale voltage, such as a negative 255 grayscale voltage, is output to the first data line D1; in the vertical blanking phase of the third frame, the highest positive grayscale voltage is output to the first data line D1, and so on.

[0070] During the vertical blanking phase of the first frame, the highest negative grayscale voltage is output to the second data line D2 (i.e., the green data line); during the vertical blanking phase of the second frame, the highest positive grayscale voltage is output to the second data line D2; during the vertical blanking phase of the third frame, the highest negative grayscale voltage is output to the second data line D2, and so on.

[0071] During the vertical blanking phase of each frame, a zero-grayscale voltage is output to the third data line D3 (i.e., the blue data line).

[0072] Since the polarity of the first data voltage received by the green data line is the same as the polarity of the data voltage received by the green sub-pixel P2, which is electrically connected to this data line, during the effective display phase, under the coupling effect of the first coupling capacitor, the first data voltage received by the green data line will apply a bias voltage of the same polarity to the pixel electrode 111 in the corresponding green sub-pixel P2, which will positively pull the voltage of the pixel electrode 111 in the green sub-pixel P2, thereby increasing the brightness of the green sub-pixel P2.

[0073] Similarly, since the polarity of the first data voltage received by the green data line is opposite to the polarity of the data voltage received by the red sub-pixel P1 electrically connected to this data line during the effective display phase, while the polarity of the first data voltage received by the red data line is the same as the polarity of the data voltage received by the red sub-pixel P1 electrically connected to this data line during the effective display phase, under the coupling effect of the first coupling capacitor, the first data voltage received by the green data line will apply a bias voltage of opposite polarity to the pixel electrode 111 in the corresponding red sub-pixel P1, and the first data voltage received by the red data line will apply a bias voltage of the same polarity to the pixel electrode 111 in the corresponding red sub-pixel P1. Thus, the bias voltage of opposite polarity and the bias voltage of the same polarity received by the red sub-pixel P1 will cancel each other out, and thus, the brightness of the red sub-pixel P1 will remain unchanged.

[0074] Similarly, since the polarity of the first data voltage received by the red data line is opposite to the polarity of the data voltage received by the blue sub-pixel P3, which is electrically connected to this data line, during the effective display phase, under the coupling effect of the first coupling capacitor, the first data voltage received by the red data line will apply a bias voltage of opposite polarity to the pixel electrode 111 in the corresponding blue sub-pixel P3, thereby reducing the brightness of the blue sub-pixel P3.

[0075] In summary, when the display panel 10 is displayed using a driving method that compensates for the green and red data lines, compared to a driving method that only compensates for the green data lines, the brightness of the green sub-pixel P2 can be increased, the brightness of the red sub-pixel P1 can be increased, and the brightness of the blue sub-pixel P3 can be decreased. As mentioned above, since the blue sub-pixel P3 contributes the least to the brightness of the display panel, the overall brightness of the display panel 10 will be increased, resulting in a better brightness compensation effect.

[0076] according to Figure 6 It is known that when the display panel 10 is driven using the existing driving method, when the display panel 10 switches refresh rates in Freesync mode, the maximum brightness value and the minimum brightness value are 50.747 nit and 46.458 nit, respectively, and the brightness difference reaches 4.289 nit.

[0077] according to Figure 7 As can be seen, when the display panel 10 is driven using the driving method of this embodiment (i.e., the driving method for compensating the green data line and the red data line), when the display panel 10 switches refresh rates in Freesync mode, the maximum brightness value and the minimum brightness value are 55.080 nit and 52.165 nit, respectively, and the brightness difference is only 2.915 nit < 4.289 nit.

[0078] The comparison shows that when the display panel 10 displays using the driving method that compensates for the green and red data lines, compared with the existing driving method, the brightness difference and flicker value during the refresh rate switching process can be reduced, and the display effect of the display panel 10 in Freesync mode can be improved.

[0079] In some embodiments of this application, the step of outputting corresponding first data voltages to a target data lines among the x data lines respectively during at least a portion of the vertical blanking phase of the current frame includes: At the start of the vertical blanking phase of the current frame, the corresponding zero grayscale voltage is output to each of the x data lines. When the duration of the vertical blanking phase of the current frame reaches the preset duration, the corresponding first data voltage is output to a target data lines among the x data lines, and the corresponding zero grayscale voltage is maintained to the other data lines other than the a target data lines until the vertical blanking phase of the current frame ends.

[0080] Specifically, outputting a corresponding zero-grayscale voltage to a data line includes: when the polarity of the data voltage received by the data line in the current frame is positive, outputting a positive zero-grayscale voltage to the data line; and when the polarity of the data voltage received by the data line in the current frame is negative, outputting a negative zero-grayscale voltage to the data line.

[0081] The preset duration can be the duration of the vertical blanking phase corresponding to a preset refresh rate (e.g., 120Hz).

[0082] As mentioned earlier, in Freesync mode, the higher the refresh rate, the shorter the vertical blanking phase. In other words, there is a one-to-one correspondence between the refresh rate and the duration of the vertical blanking phase. Only when the refresh rate is low will noticeable changes in brightness occur.

[0083] Thus, when the duration of the vertical blanking phase of the current frame is less than or equal to a preset duration, a corresponding zero-grayscale voltage is output to each of the x data lines. When the duration of the vertical blanking phase of the current frame is greater than the preset duration, a corresponding first data voltage is output to each of the a target data lines among the x data lines. This allows the compensation function provided in this application to be enabled only when the refresh rate is low, while the existing driving method (i.e., outputting zero-grayscale voltage to the data lines during the vertical blanking phase) is used when the refresh rate is high, thereby reducing the power consumption of the driving circuit.

[0084] In some embodiments of this application, the process of outputting a zero grayscale voltage to the target data line and then outputting the corresponding first data voltage is performed in a step manner or a gradual manner. The gradual manner causes the voltage output to the target data line to change from a zero grayscale voltage to the corresponding first data voltage within a preset time period.

[0085] The step transition method, also known as the jump transition method, involves the voltage output to the target data line instantly changing from zero grayscale voltage to the corresponding first data voltage. The gradient transition method includes one of the following: step-like gradient, linear gradient, or non-linear gradient.

[0086] Please refer to it again. Figure 1 Based on the same inventive concept, this application provides a driving circuit 20, which is used to control the execution of the steps in the driving method as described in any of the preceding embodiments, so as to drive the display panel 10 to display.

[0087] The driving circuit 20 includes a scan driving circuit 21, a data driving circuit 22, and a timing controller 23.

[0088] The scanning drive circuit 21 and the scanning lines in the display panel 10 (including Figure 1 The scan lines G1, G2, G3, G4, etc. are electrically connected.

[0089] The data driving circuit 22 and the data lines in the display panel (including) Figure 1 The data cables D1, D2, D3, D4, D5, D6, etc. are electrically connected.

[0090] The timing controller 23 is electrically connected to the scan driving circuit 21 and the data driving circuit 22, respectively. The timing controller 23 is used to control the scan driving circuit 21 to output corresponding scan signals to each scan line, so as to perform line-by-line scanning of the sub-pixels P in the display panel 10. The timing controller 23 is also used to control the data driving circuit 22 to perform the steps in the driving method as described in any of the embodiments above.

[0091] Based on the same inventive concept, this application also provides a display device 100, which includes a display panel 10 and a driving circuit 20 mentioned above. The driving circuit 20 is electrically connected to the display panel 10 and is used to drive the display panel 10 to perform display.

[0092] It should be noted that the driving circuit 20, the display device 100 and the driving method of the display panel mentioned above correspond to each other. For a more detailed description, please refer to the contents of the various embodiments of the driving method of the display panel mentioned above, which will not be repeated here.

[0093] Although embodiments of this application have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of this application, the scope of which is defined by the claims and their equivalents.

Claims

1. A driving method for a display panel, characterized in that, The display panel includes x data lines and x columns of sub-pixels. The x data lines all extend along the column direction. The x data lines and the x columns of sub-pixels are electrically connected in a one-to-one correspondence, and each data line is adjacent to the corresponding column of sub-pixels. Each sub-pixel includes a pixel electrode, and a first coupling capacitor is formed between the pixel electrode and the adjacent data line, where x>1. The driving method includes: During the effective display phase of the current frame, a data voltage with constant polarity is output to each of the data lines; and During at least a portion of the vertical blanking phase of the current frame, a corresponding first data voltage is output to a target data lines among the x data lines, so as to apply a bias voltage to the pixel electrode in the adjacent sub-pixel of each target data line through the coupling effect of the corresponding first coupling capacitor; wherein, a≤x and a≥1; The polarity of the first data voltage corresponding to each target data line is the same as the polarity of the data voltage received by the data line during the effective display phase of the current frame, and the grayscale number of the first data voltage corresponding to each target data line is higher than or equal to the highest grayscale number of the data voltage received by the data line during the effective display phase of the current frame.

2. The driving method for the display panel as described in claim 1, characterized in that, The display panel is a column-reversed display panel, x=3×b; the sub-pixels located in the same column have the same color, the x-column sub-pixels include b-column red sub-pixels, b-column green sub-pixels and b-column blue sub-pixels, the a-target data lines include at least one of the b-column green data lines, wherein the green data lines are data lines electrically connected to the green sub-pixels, and a≤b.

3. The driving method for the display panel as described in claim 1, characterized in that, The display panel is a column-reversed display panel, x=3×b; sub-pixels located in the same column have the same color, the x-column sub-pixels include b-column red sub-pixels, b-column green sub-pixels and b-column blue sub-pixels, the a-target data lines include e-column red data lines and f-column green data lines; wherein, the red data lines are data lines electrically connected to the red sub-pixels, the green data lines are data lines electrically connected to the green sub-pixels, 1≤e≤b, 1≤f≤b.

4. The driving method for the display panel as described in claim 1, characterized in that, The display panel is a surface-inverted display panel, where a=x.

5. The driving method for a display panel as described in claim 1, characterized in that, Before outputting corresponding first data voltages to a target data lines among the x data lines respectively during at least a portion of the vertical blanking phase of the current frame, the driving method further includes: Determine whether the display panel is currently in variable refresh rate mode; The step of outputting corresponding first data voltages to a target data lines among the x data lines during at least a portion of the vertical blanking phase of the current frame includes: If the display panel is currently in variable refresh rate mode, then during at least a portion of the vertical blanking phase of the current frame, the corresponding first data voltage is output to a target data lines among the x data lines.

6. The driving method for a display panel as described in claim 1, characterized in that, The step of outputting the corresponding first data voltage to a target data lines out of the x data lines includes: Output the highest positive grayscale voltage of the display panel to the positive data line among the a target data lines; wherein, the positive data line is the data line among the a target data lines whose data voltage polarity is positive during the effective display phase of the current frame; and Output the highest negative grayscale voltage of the display panel to the negative polarity data line among the a target data lines; wherein, the negative polarity data line is the data line among the a target data lines whose data voltage polarity is negative during the effective display phase of the current frame.

7. The driving method for a display panel as described in claim 1, characterized in that, The step of outputting corresponding first data voltages to a target data lines among the x data lines during at least a portion of the vertical blanking phase of the current frame includes: At the start of the vertical blanking phase of the current frame, the corresponding first data voltage is output to a target data lines out of the x data lines; and Before the effective display phase of the next frame, the output of the corresponding first data voltage to each of the x data lines is stopped.

8. The driving method for a display panel as described in claim 1, characterized in that, The step of outputting corresponding first data voltages to a target data lines among the x data lines during at least a portion of the vertical blanking phase of the current frame includes: At the start of the vertical blanking phase of the current frame, corresponding zero-grayscale voltages are output to the x data lines respectively; and When the duration of the vertical blanking phase of the current frame reaches a preset duration, the corresponding first data voltage is output to a target data lines among the x data lines.

9. A driving circuit, characterized in that, The driving circuit is used to control the execution of the steps in the driving method of the display panel as described in any one of claims 1 to 8, so as to drive the display panel to display.

10. A display device, characterized in that, The display device includes: Display panel; and The driving circuit as described in claim 9 is electrically connected to the display panel, and the driving circuit is used to drive the display panel to perform display.

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