Display device

Abstract

A display device includes a display panel including: a data line extending in a first direction; a gate line extending in a second direction different from the first direction; and unit pixels connected to the data lines and the gate lines, in which each of the unit pixels includes white pixels and a plurality of color pixels, an n-th white pixel disposed at an n-th position among the white pixels disposed in the first direction is connected to an odd-number white data line, where n is an odd number, and n is an integer greater than or equal to 2. And an (n + 1)-th white pixel disposed at an (n + 1)-th position among the white pixels disposed in the first direction is connected to the even white data line.

Description

[0001] This application is a divisional application of the original invention patent application with application number 202211361326.8 (application date: November 2, 2022, invention title: display device). Technical Field

[0002] This disclosure relates to a display device. Background Technology

[0003] To improve the quality of display devices, the driving frequency of display devices has been gradually increased.

[0004] However, although display devices are manufactured for high-frequency driving, there is a need to drive them at low frequencies depending on the circumstances.

[0005] In particular, in both cases where the display device is driven at low and high frequencies, the quality of the display device can be improved by driving the pixels included in the display device independently. However, in the prior art, no display device driven in this manner is provided. Summary of the Invention

[0006] Therefore, this disclosure aims to provide a display device that substantially eliminates one or more problems caused by the limitations and disadvantages of the prior art.

[0007] One aspect of this disclosure aims to provide a display device in which, when the display device is driven at a high frequency, the same data voltage can be provided to two color pixels adjacent to each other along the data line, and when the display device is driven at a low frequency, different data voltages can be provided to two color pixels adjacent to each other along the data line.

[0008] Further advantages and features of this disclosure will be set forth in part in the description which follows, and in part will be apparent to those skilled in the art upon examination of the description, or may be learned by practice of this disclosure. The objects and other advantages of this disclosure may be realized and obtained by means of the structures particularly pointed out in the written description and claims and the accompanying drawings.

[0009] To achieve these and other advantages and in accordance with the purposes of this disclosure, as embodied and broadly described herein, a display device is provided, the display device comprising a display panel including: a data line extending along a first direction; a gate line extending in a second direction different from the first direction; and unit pixels connected to the data line and the gate line, wherein each unit pixel includes a white pixel and a plurality of color pixels, an nth white pixel disposed at an nth position among the white pixels disposed along the first direction is connected to an odd number of white data lines, wherein n is an odd number, and a (n+1)th white pixel disposed at an (n+1)th position among the white pixels disposed along the first direction is connected to an even number of white data lines.

[0010] It should be understood that the above overview and the following detailed description of this disclosure are illustrative and explanatory, and are intended to provide further explanation of the claimed disclosure. Attached Figure Description

[0011] The accompanying drawings are included to provide a further understanding of this disclosure, and are incorporated in and constitute a part of this application. The drawings illustrate embodiments of the disclosure and, together with the description, serve to explain the principles of the disclosure. In the drawings:

[0012] Figure 1 This is an exemplary diagram illustrating the configuration of a display device according to the present disclosure;

[0013] Figure 2 This is an exemplary diagram illustrating the structure of pixels applied to a display device according to the present disclosure;

[0014] Figure 3 This is an exemplary diagram illustrating the configuration of a data driver applied to a display device according to the present disclosure;

[0015] Figure 4 This is an exemplary diagram illustrating the configuration of a controller applied to a display device according to the present disclosure;

[0016] Figure 5 This is an exemplary diagram illustrating the configuration of a gating driver applied to a display device according to the present disclosure;

[0017] Figure 6 This is an exemplary diagram showing a display panel applied to a display device according to the present disclosure;

[0018] Figure 7 This is an exemplary diagram illustrating the waveforms applied to the present disclosure when a display device according to the present disclosure is driven at a low frequency;

[0019] Figure 8This is an exemplary diagram illustrating the waveforms applied to the present disclosure when a display device according to the present disclosure is driven at a high frequency; and

[0020] Figure 9 This is an exemplary diagram illustrating the format of input image data that can be input to a display device according to the present disclosure driven at a high frequency. Detailed Implementation

[0021] Reference will now be made in detail to exemplary embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Where possible, the same reference numerals will be used throughout the drawings to refer to the same or similar parts.

[0022] The advantages and features of this disclosure and its implementation methods will be illustrated by the following embodiments described with reference to the accompanying drawings. However, this disclosure may be implemented in different forms and should not be construed as limited to the described embodiments. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of this disclosure to those skilled in the art. Furthermore, this disclosure is limited only by the scope of the claims.

[0023] The shapes, sizes, ratios, angles, and quantities disclosed in the accompanying drawings used to describe embodiments of this disclosure are merely examples, and therefore, this disclosure is not limited to the details shown. The same reference numerals denote the same elements throughout the specification. In the following description, detailed descriptions that would unnecessarily obscure the focus of this disclosure will be omitted where such descriptions would unnecessarily obscure the main points. When using terms such as “comprising,” “having,” and “including” as described in this specification, additional parts may be added unless “only” is used. Unless otherwise stated, singular terms may include plural forms.

[0024] When interpreting a component, it is interpreted as including a range of errors or tolerances, even though there is no explicit description of that range of errors or tolerances.

[0025] When describing positional relationships, for example, when the positional relationship between two parts is described as, for example, "above," "on top," "below," and "nearby," one or more other parts may be placed between the two parts unless more restrictive terms such as "only" or "directly" are used.

[0026] When describing temporal relationships, such as when time sequence is described as "after," "following," "next," and "before," discontinuous situations may be included unless more restrictive terms such as "only," "immediately," or "directly" are used.

[0027] It should be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0028] In describing the elements of this disclosure, the terms “first,” “second,” “A,” “B,” “(a),” “(b),” etc., may be used. These terms are intended to distinguish corresponding elements from other elements, and the basis, order, or number of corresponding elements shall not be limited by these terms. Unless otherwise stated, the expression that an element is “connected,” “linked,” or “attached” to another element or layer indicates that the element or layer may be directly connected or attached to another element or layer, or indirectly connected or attached to another element or layer, and that one or more intermediate elements or layers are “disposed” between the elements or layers.

[0029] The term "at least one" should be understood to include any and all combinations of one or more associated listed items. For example, "at least one of the first, second, and third items" means a combination of all items derived from two or more of the first, second, and third items, as well as the first, second, or third item.

[0030] Features of the various embodiments of this disclosure may be linked or combined with each other in part or in whole, and may interoperate with each other and be technically driven in various ways, as will be fully understood by those skilled in the art. Embodiments of this disclosure may be performed independently of each other, or may be performed together in an interdependent relationship.

[0031] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0032] Figure 1 This is an exemplary diagram illustrating the configuration of a display device according to the present disclosure. Figure 2 This is an exemplary diagram illustrating the structure of pixels applied to a display device according to the present disclosure. Figure 3 This is an exemplary diagram illustrating the configuration of a data driver applied to a display device according to the present disclosure. Figure 4 This is an exemplary diagram illustrating the configuration of a controller applied to a display device according to the present disclosure. Figure 5 This is an exemplary diagram illustrating the configuration of a gating driver applied to a display device according to the present disclosure.

[0033] The display device according to this disclosure can be configured with various electronic devices. These electronic devices may include, for example, smartphones, tablet PCs, televisions (TVs), and monitors.

[0034] like Figure 1 As shown, the display device according to this disclosure may include a display panel 100, which includes: a display area 120 for displaying images and a non-display area 130 disposed outside the display area 120; a gating driver 200 that provides gating signals to a plurality of gating lines GL1 to GLg disposed in the display area 120 of the display panel 100; a data driver 300 that provides data voltage to a plurality of data lines DL1 to DLd disposed in the display panel 100; a controller 400 that controls the driving of the gating driver 200 and the data driver 300; and a power supply 500 that supplies power to the controller 400, the gating driver 200, the data driver 300, and the display panel 100.

[0035] First, the display panel 100 may include a display area 120 and a non-display area 130. Gate lines GL1 to GLG, data lines DL1 to DLd, and pixels 110 may be disposed within the display area 120. Therefore, the display area 120 can display an image. Here, g and d can each be a natural number. The non-display area 130 may surround the outside of the display area 120.

[0036] like Figure 2 As shown, the pixel 110 included in the display panel 100 may include a light-emitting area, which includes a pixel driving circuit PDC and a light-emitting device ED. The pixel driving circuit PDC includes a switching transistor Tsw1, a storage capacitor Cst, a driving transistor Tdr, and a sensing transistor Tsw2.

[0037] The first terminal of the driving transistor Tdr can be connected to the high-voltage power line PLA that provides high voltage EVDD, and the second terminal of the driving transistor Tdr can be connected to the light-emitting device ED.

[0038] The first terminal of the switching transistor Tsw1 can be connected to the data line DL, the second terminal of the switching transistor Tsw1 can be connected to the gate of the driving transistor Tdr, and the gate of the switching transistor Tsw1 can be connected to the gate line GL.

[0039] It can provide a data voltage Vdata to the data line DL and a gating signal GS to the gating line GL.

[0040] A sensing transistor Tsw2 can be configured to measure the threshold voltage or mobility of the driving transistor. The first terminal of the sensing transistor Tsw2 can be connected to the second terminal of the driving transistor Tdr and the light-emitting device ED. The second terminal of the sensing transistor Tsw2 can be connected to the sensing line SL that provides the reference voltage Vref, and the gate of the sensing transistor Tsw2 can be connected to the sensing control line that provides the sensing control signal.

[0041] The sensing line SL can be connected to the data driver 300, and can also be connected to the power supply 500 through the data driver 300. That is, the reference voltage Vref provided from the power supply 500 can be provided to the pixel through the sensing line SL, and the sensing signal transmitted from the pixel can be processed by the data driver 300.

[0042] In this case, the gate line GL can perform the function of a sensing control line. That is, as... Figure 2 As shown, the gate of sensing transistor Tsw2 and the gate of switching transistor Tsw1 can be connected together to the gating line GL. Therefore, the gating signal GS can be used as a sensing control signal.

[0043] However, the sensing control line can be a separate line independent of the gate line GL, and the sensing control signal can be provided by a separately supplied sensing control line.

[0044] The structure of pixel 110 applied in this disclosure is not limited to Figure 2 The structure shown. Therefore, the structure of pixel 110 can be changed to various types.

[0045] In addition to including Figure 2 In addition to the light-emitting display devices illustrated, this disclosure can also be applied to liquid crystal display devices that include liquid crystal display panels. That is, this disclosure can be applied to various types of display devices currently in use. However, in the following description, light-emitting display devices will be described as examples of this disclosure for ease of description.

[0046] The data driver 300 can be mounted on a chip-on-film (COF) attached to the display panel 100, or it can be directly mounted in the display panel 100.

[0047] Data driver 300 can provide data voltage Vdata to data lines DL1 to DLd.

[0048] The data driver 300 can convert the sensing signal received through the sensing line SL into a digital signal and can transmit the digital signal to the controller 400.

[0049] The data driver 300 can shift the source start pulse transmitted from the controller 400 based on the source shift clock to generate a sampling signal. Furthermore, the data driver 300 can latch image data based on the sampling signal, convert the image data into a data voltage, and provide a data voltage corresponding to the gating line unit to the data lines in response to a source output enable signal.

[0050] Therefore, such as Figure 3 As shown, the data driver 300 may include a shift register unit 310, a latch unit 320, a digital-to-analog converter (DAC) 330, and an output buffer 340.

[0051] The shift register unit 310 can output a sampled signal using the data control signal DCS received from the controller 400.

[0052] The latch unit 320 can latch multiple image data Data received sequentially from the controller 400, and then output the multiple image data Data to the DAC 330 simultaneously based on the sampling signal.

[0053] DAC 330 can simultaneously convert multiple image data Data transmitted from latch unit 320 into data voltages Vdata1 to Vdata(d).

[0054] The output buffer 340 can simultaneously output the data voltages Vdata1 to Vdata(d) transmitted from the DAC 330 to the data lines DL1 to DLd of the display panel based on the source output enable signal transmitted from the controller 400.

[0055] The controller 400 can re-align the input video data transmitted from the external system using a timing synchronization signal transmitted from the external system, and can generate a data control signal DCS to be provided to the data driver 300 and a gating control signal GCS to be provided to the gating driver 200.

[0056] For this purpose, the controller 400 may include: a data aligner 430, which realigns the input video data to generate image data Data and provides the image data Data to the data driver 300; a control signal generator 420, which generates a gating control signal GCS and a data control signal DCS using a timing synchronization signal; an input unit 410, which receives the timing synchronization signal and the input video data transmitted from an external system and transmits the timing synchronization signal and the input video data to the data aligner and the control signal generator, respectively; and an output unit, which provides the image data Data generated by the data aligner and the data control signal DCS generated by the control signal generator to the data driver 300, and provides the gating control signal GCS generated by the control signal generator to the gating driver 200.

[0057] The controller 400 may include a storage unit 450 for storing various information.

[0058] An external system can perform the functions of the drive controller 400 and the electronic device. For example, when the electronic device is a TV, the external system can receive various audio, video, and audio information via a communication network and can transmit the received video information to the controller 400. In this case, the image information may include input video data.

[0059] The power supply 500 can generate various types of electricity and can supply the generated electricity to the controller 400, the strobe driver 200, the data driver 300 and the display panel 100.

[0060] Finally, the gate driver 200 can be configured as an integrated circuit (IC) and mounted in the non-display area 130. Alternatively, the gate driver 200 can be directly embedded in the non-display area 130 using a gate-in-panel (GIP) type. When using the GIP type, the transistors configuring the gate driver 200 can be placed in the non-display area using the same process as the transistors included in each pixel 110.

[0061] The gating driver 200 can provide gating pulses GP1 to GPg to gating lines GL1 to GLg. When the gating pulse generated by the gating driver 200 is provided to the gate of the switching transistor Tsw1 included in the pixel 110, the switching transistor Tsw1 can be turned on. When the switching transistor Tsw1 is turned on, the data voltage supplied through the data line can be provided to the pixel 110. When the gating cutoff signal generated by the gating driver 200 is provided to the switching transistor Tsw1, the switching transistor Tsw1 can be turned off. When the switching transistor Tsw1 is turned off, the data voltage can no longer be supplied to the pixel 110. The gating signal GS provided to the gating line GL can include the gating pulse GP and the gating cutoff signal.

[0062] Therefore, such as Figure 5 As shown, the strobe driver 200 may include multiple stages 201.

[0063] Each stage 201 can be connected to at least one strobe line GL. Each stage 201 can be driven by a start signal transmitted from the controller 400, or by a start signal transmitted from the previous or next stage.

[0064] Each stage 201 may include at least two transistors and can be configured in various ways.

[0065] Figure 6 This is an exemplary diagram illustrating a display panel applied to a display device according to the present disclosure. Specifically, Figure 6 This is an exemplary diagram showing two unit pixels 110a connected to the nth gating line GLn and two unit pixels 110a connected to the (n+1)th gating line GLn+1. That is, in Figure 6 In the middle, it is shown that the connection is... Figure 1 The diagram shows four unit pixels of the nth gate line GLn and the (n+1)th gate line GLn+1 in the illuminated display panel. Here, n can be an odd number less than an even number. Referencing the diagram below... Figure 6 The structure of the display panel applied in this disclosure is described.

[0066] like Figure 1 and Figure 6 As shown, the display device according to this disclosure may include a display panel 100, which includes a data line DL and a gate line GL.

[0067] The display panel 100 may include data lines DL1 to DLd extending in a first direction and gate lines GL1 to GLg extending in a second direction different from the first direction.

[0068] The first direction could be, for example, Figure 1 and Figure 6 The length direction of the display panel 100 shown, and the second direction, for example, could be... Figure 1 and Figure 6 The display panel 100 shown is in its width direction. That is, in Figure 1 and Figure 6 In this context, the first direction can be the direction in which the data line DL extends, and the second direction can be the direction in which the gating line GL extends.

[0069] The display panel 100 may include unit pixels 110a connected to the data line DL and the gate line GL.

[0070] Each unit pixel 110a may include a white pixel W, a red pixel R, a green pixel G, and a blue pixel B. However, the combination of pixels constituting unit pixel 110a is not limited to white pixel W, red pixel R, green pixel G, and blue pixel B. Therefore, unit pixel 110a can be configured with various combinations of colors.

[0071] In the following description, for ease of description, a display panel 100 comprising a unit pixel 110a including a white pixel W, a red pixel R, a green pixel G, and a blue pixel B will be described as an example of this disclosure. In this case, each of the red pixel R, the green pixel G, and the blue pixel B can be described as a color pixel. That is, each of the pixels other than the white pixel can be a color pixel. Therefore, in the following description, a unit pixel may include a white pixel and three color pixels.

[0072] To provide additional descriptions, Figure 6 The image shows two unit pixels 110a connected to the nth gating line GLn and two unit pixels 110a connected to the (n+1)th gating line GLn+1.

[0073] In this case, the nth white pixel Wn located at the nth position in the white pixel W set along the first direction can be connected to the odd-numbered white data line DL1W, and the (n+1)th white pixel Wn+1 located at the (n+1)th position in the white pixel W set along the first direction can be connected to the even-numbered white data line DL2W.

[0074] Furthermore, the red pixel R, which is set along the first direction, can be connected to the red data line DLR, the green pixel G, which is set along the first direction, can be connected to the green data line DLG, and the blue pixel B, which is set along the first direction, can be connected to the blue data line DLB.

[0075] For example, in Figure 6 In the display panel 100 shown, the nth white pixel Wn, which is connected to the nth gating line GLn, can be connected to the mth odd-numbered white data line DL1W_m, and the (n+1)th white pixel Wn+1, which is connected to the (n+1)th gating line GLn+1, can be connected to the mth even-numbered white data line DL2W_m. Here, m can be a natural number less than d. That is, m represents the order of the data lines. Therefore, in the following description, when the order is not required, m or n can be omitted in the reference numerals.

[0076] That is, in this disclosure, the nth white pixel Wn connected to the nth gating line GLn and the (n+1)th white pixel Wn+1 connected to the (n+1)th gating line GLn+1, which are adjacent to each other along the data line DL, can be connected to different data lines.

[0077] In this case, the red pixel R set along the first direction can be connected to the m-th red data line DLR_m, the green pixel G set along the first direction can be connected to the m-th green data line DLG_m, and the blue pixel B set along the first direction can be connected to the m-th blue data line DLB_m.

[0078] That is, in this disclosure, red pixels R that are adjacent to each other along data line DL can be connected to a red data line DLR, green pixels G can be connected to a green data line DLG, and blue pixels B can be connected to a blue data line DLB.

[0079] Figure 7 This is an exemplary diagram illustrating the waveforms applied to the present disclosure when the display device according to the present disclosure is driven at a low frequency. In the following, reference will be made to... Figure 6 and Figure 7 This describes a method for driving a display device according to the present disclosure at a low frequency. Here, low frequency can mean a frequency higher than that described below. Figure 8 The frequency described is high or low, and can be, for example, 120Hz or 60Hz. Therefore, the following references... Figure 8 The high frequency described could be, for example, 240 Hz.

[0080] In the above text, as referenced above Figure 6 In the display panel applied to this disclosure, the nth white pixel Wn at position n of the white pixels W arranged along the first direction can be connected to the odd-numbered white data line DL1W, and the (n+1)th white pixel Wn+1 at position (n+1) of the white pixels W arranged along the first direction can be connected to the even-numbered white data line DL2W, where n is an odd number. In this case, the red pixel R arranged along the first direction can be connected to the red data line DLR, the green pixel G arranged along the first direction can be connected to the green data line DLG, and the blue pixel B arranged along the first direction can be connected to the blue data line DLB.

[0081] In this case, when the display panel 100 is driven at the first frequency, such as Figure 6 and Figure 7As shown, the data voltage Vdata1W provided to the odd-numbered white data line DL1W can have a width of two horizontal periods of 2H, the data voltage Vdata2W provided to the even-numbered white data line DL2W can have a width of two horizontal periods of 2H, the data voltages VdataR, VdataG and VdataB provided to the red pixel R, green pixel G and blue pixel B respectively can have a width of one horizontal period of 1H, and the selection pulses GPn, GPn+1, GPn+2 and GPn+3 provided to the selection lines respectively can have a width of two horizontal periods of 2H.

[0082] Here, as mentioned above, the first frequency can be represented by a frequency that is less than the frequency referred to below. Figure 8 The high-frequency description refers to a low-frequency range, for example, 120Hz or 60Hz. In the following text, reference will be made to... Figure 7 A display device driven at a frequency of 120Hz is described as an example of this disclosure.

[0083] In the following text, such as Figure 7 As shown, this disclosure will be described with reference to the nth gating pulse GPn to the (n+3)th gating pulse GPn+3 provided to the nth gating line GLn to the (n+3)th gating line GLn+3.

[0084] In the following text, such as Figure 7 As shown, this disclosure will be described with reference to the m-th odd white data voltage Vdata1W_m provided to the m-th odd white data line DL1W_m, the m-th even white data voltage Vdata2W_m provided to the m-th even white data line DL2W_m, and the m-th red data voltage VdataR_m, the m-th green data line DLG_m, and the m-th blue data line DLB_m, respectively.

[0085] In this case, Figure 7In each data voltage Vdata1W_m, Vdata2W_m, VdataR_m, VdataG_m, and VdataB_m, 'n' can represent the data voltage corresponding to the nth gate line GLn, (n+1) can represent the data voltage corresponding to the (n+1)th gate line GLn+1, (n+2) can represent the data voltage corresponding to the (n+2)th gate line GLn+2, and (n+3) can represent the data voltage corresponding to the (n+3)th gate line GLn+3. Similarly, (n-1) can represent the data voltage corresponding to the (n-1)th gate line GLn-1, (n-2) can represent the data voltage corresponding to the (n-2)th gate line GLn-2, ​​and (n-3) can represent the data voltage corresponding to the (n-3)th gate line GLn-3.

[0086] For example, when the display panel 100 is driven at a first frequency (120Hz), such as Figure 7 As shown, the m-th odd-numbered white data voltage Vdata1W_m provided to the m-th odd-numbered white data line DL1W_m can have a width of two horizontal periods of 2H. The m-th even-numbered white data voltage Vdata2W_m provided to the m-th even-numbered white data line DL2W_m can also have a width of two horizontal periods of 2H. The m-th red data voltage VdataR_m, m-th green data voltage VdataG_m, and m-th blue data voltage VdataB_m provided to the red pixel R, green pixel G, and blue pixel B respectively through the m-th red data line DLR_m, the m-th green data line DLG_m, and the m-th blue data line DLB_m can have a width of one horizontal period. The gating pulses GPn, GPn+1, GPn+2, and GPn+3 provided to the gating lines can have a width of two horizontal periods of 2H.

[0087] In this case, two consecutively output gating pulses can each overlap by one horizontal period 1H. For example, in Figure 7 In the process, the nth gating pulse GPn and the (n+1)th gating pulse GPn+1 can overlap by a horizontal period 1H, the (n+1)th gating pulse GPn+1 and the (n+2)th gating pulse GPn+2 can overlap by a horizontal period 1H, and the (n+2)th gating pulse GPn+2 and the (n+3)th gating pulse GPn+3 can overlap by a horizontal period 1H.

[0088] The width and overlap of each of the above-mentioned gating pulses can vary based on the width and overlap of each gating clock provided to the gating driver 200.

[0089] The width and overlap width of each strobe clock provided to the strobe driver 200 can be changed by the controller 400.

[0090] That is, when the display device is configured to be driven at a first frequency, which is a low frequency, the controller 400 can generate a gating clock of the form described above, and can transmit the gating clock to the gating driver 200. The configuration information that enables the display device to be driven at the first frequency can be stored in the storage unit 450.

[0091] Therefore, when the display device is turned on, the controller 400 can check the configuration information stored in the storage unit 450, and then, by using the timing synchronization signal transmitted from the external system, the controller 400 can generate a gating clock of the form described above, and can transmit the gating clock to the gating driver 200.

[0092] In this case, when the nth gating pulse GPn is provided to the nth gating line GLn and the odd white data voltage Vdata1W is provided to the nth white pixel Wn connected to the nth gating line GLn through the odd white data line DL1W, where n is odd, the data voltage can be provided to the red pixel R, green pixel G and blue pixel B connected to the nth gating line GLn through the red data line DLR, the green data line DLG and the blue data line DLB.

[0093] For example, such as Figure 6 and Figure 7 As shown, when the nth gating pulse GPn is provided to the nth gating line GLn and the mth odd-numbered white data voltage Vdata1W_m is provided to the nth white pixel Wn connected to the nth gating line GLn through the mth odd-numbered white data line DL1W_m, where n is odd, the mth red data voltage VdataR_m, the mth green data voltage VdataG_m, and the mth blue data voltage VdataB_m can be provided to the nth red pixel Rn, the nth green pixel Gn, and the nth blue pixel Bn connected to the nth gating line GLn through the mth red data line DLR_m, the mth green data line DLG_m, and the mth blue data line DLB_m, respectively.

[0094] To provide additional description, via Figure 7 A in the diagram shows that the nth gating pulse GPn is provided to the nth gating line GLn and the mth odd white data voltage Vdata1W_m is provided to the timing of the nth white pixel Wn connected to the nth gating line GLn through the mth odd white data line DL1W_m.

[0095] That is, at time A, the m-th odd-numbered white data voltage Vdata1W_m(n) can be provided to the n-th white pixel Wn. Here, (n) can represent the data voltage provided to the n-th white pixel Wn from the m-th odd-numbered white data voltage Vdata1W_m.

[0096] In this case, the m-th red data voltage VdataR_m(n), the m-th green data voltage VdataG_m(n), and the m-th blue data voltage VdataB_m(n) can be provided to the n-th red pixel Rn, the n-th green pixel Gn, and the n-th blue pixel Bn. Here, (n) can represent the data voltages provided to the n-th red pixel Rn, the n-th green pixel Gn, and the n-th blue pixel Bn from the m-th red data voltage VdataR_m(n), the m-th green data voltage VdataG_m(n), and the m-th blue data voltage VdataB_m(n).

[0097] For additional description, data voltages can be simultaneously supplied at time A to the nth white pixel Wn, the nth red pixel Rn, the nth green pixel Gn, and the nth blue pixel Bn connected to the nth gating line GLn.

[0098] However, at time A, it is not necessary to provide the m-th even-numbered white data voltage Vdata2W_m(n+1) to the (n+1)-th white pixel Wn+1.

[0099] When the (n+1)th gating pulse GPn+1 is provided to the (n+1)th gating line GLn+1, the even-numbered white data voltage Vdata2W can be provided to the (n+1)th white pixel Wn+1 connected to the (n+1)th gating line GLn+1 through the even-numbered white data line DL2W.

[0100] For example, such as Figure 6 and Figure 7 As shown, when the (n+1)th gating pulse GPn+1 is provided to the (n+1)th gating line GLn+1, the m-th even-numbered white data voltage Vdata2W_m can be provided to the (n+1)th white pixel Wn+1 connected to the (n+1)th gating line GLn+1 through the m-th even-numbered white data line DL2W_m.

[0101] To provide additional description, via Figure 7 B in the diagram shows the timing of the (n+1)th gating pulse GPn+1 being provided to the (n+1)th gating line GLn+1 and the m-th even white data voltage Vdata2W_m being provided to the (n+1)th white pixel Wn+1 connected to the (n+1)th gating line GLn+1 via the m-th even white data line DL2W_m.

[0102] That is, at time B, the m-th even-numbered white data voltage Vdata2W_m(n+1) can be provided to the (n+1)-th white pixel Wn+1. Here, (n+1) can represent the data voltage provided to the (n+1)-th white pixel Wn+1 in the m-th even-numbered white data voltage Vdata2W_m.

[0103] At time B, data voltage can be supplied to the red pixel R, green pixel G, and blue pixel B connected to the (n+1)th strobe line GLn+1 via the red data line DLR, green data line DLG, and blue data line DLB.

[0104] In other words, at time B, the m-th red data voltage VdataR_m(n+1), the m-th green data voltage VdataG_m(n+1), and the m-th blue data voltage VdataB_m(n+1) can be provided to the (n+1)-th red pixel Rn+1, the (n+1)-th green pixel Gn+1, and the (n+1)-th blue pixel Bn+1. Here, (n+1) can represent the data voltage provided to the (n+1)-th red pixel Rn+1, the (n+1)-th green pixel Gn+1, and the (n+1)-th blue pixel Bn+1 from the m-th red data voltage VdataR_m, the m-th green data voltage VdataG_m, and the m-th blue data voltage VdataB_m.

[0105] For additional description, data voltages can be simultaneously supplied at time B to the (n+1)th white pixel Wn+1, the (n+1)th red pixel Rn+1, the (n+1)th green pixel Gn+1, and the (n+1)th blue pixel Bn+1 connected to the (n+1)th strobe line GLn+1.

[0106] As described above, when the display device is driven at a first frequency that is a low frequency, the data voltage can be simultaneously provided to the nth white pixel Wn, the nth red pixel Rn, the nth green pixel Gn and the nth blue pixel Bn connected to the nth gating line GLn at time A, and the data voltage can be simultaneously provided to the (n+1)th white pixel Wn+1, the (n+1)th red pixel Rn+1, the (n+1)th green pixel Gn+1 and the (n+1)th blue pixel Bn+1 connected to the (n+1)th gating line GLn+1 at time B.

[0107] In this case, at different timings, data voltages can be provided to the nth white pixel Wn and the (n+1)th white pixel Wn+1, and different data voltages can be provided to them.

[0108] Similar to the white pixels, data voltages can be provided to the nth red pixel Rn and the (n+1)th red pixel Rn+1 at different timings, and different data voltages can be provided to them. Furthermore, data voltages can be provided to the nth green pixel Gn and the (n+1)th green pixel Gn+1 at different timings, and different data voltages can be provided to them. Additionally, data voltages can be provided to the nth blue pixel Bn and the (n+1)th blue pixel Bn+1 at different timings, and different data voltages can be provided to them.

[0109] Therefore, the data voltage corresponding to each pixel can be provided to the corresponding pixel of the pixel.

[0110] Therefore, when driving the display device at a first frequency that is low, a compensation voltage can be applied to each pixel. Here, the compensation voltage can refer to the voltage used to compensate for the change in the threshold voltage of the driving transistor Tdr due to degradation.

[0111] That is, according to this disclosure, pixels can be driven individually, and therefore, the threshold voltage compensation method can be applied to each pixel. Thus, pixels can display images correctly, thereby improving the quality of the display device.

[0112] Figure 8 This is an exemplary diagram illustrating the waveforms applied to the present disclosure when a display device according to the present disclosure is driven at a high frequency. In the following, reference will be made to... Figure 6 and Figure 8 This describes a method of driving a display device according to the present disclosure at a high frequency. Here, high frequency can mean higher than that described above. Figure 7 The described low-frequency to high-frequency range can be, for example, 240Hz. Therefore, in the following description, frequencies may be omitted or briefly given. Figure 7 The description is the same as or similar to the description.

[0113] In the above text, as referenced above Figure 6 In the display panel applied to this disclosure, the nth white pixel Wn at the nth position of the white pixels W arranged along the first direction can be connected to the odd-numbered white data line DL1W, and the (n+1)th white pixel Wn+1 at the (n+1)th position of the white pixels W arranged along the first direction can be connected to the even-numbered white data line DL2W. In this case, the red pixel R arranged along the first direction can be connected to the red data line DLR, the green pixel G arranged along the first direction can be connected to the green data line DLG, and the blue pixel B arranged along the first direction can be connected to the blue data line DLB.

[0114] In this case, when the display panel 100 is driven at a second frequency, which is the first frequency, such as Figure 6 and Figure 8 As shown, the data voltage provided to the odd-numbered white data line DL1W can have a width of two horizontal periods 2H, the data voltage provided to the even-numbered white data line DL2W can have a width of two horizontal periods 2H, the data voltages provided to the red pixel R, green pixel G and blue pixel B can have a width of two horizontal periods 2H, and the gating pulses GPn, GPn+1, GPn+2 and GPn+3 provided to the gating lines can have a width of four horizontal periods 4H.

[0115] Here, as mentioned above, the second frequency can be represented as compared to the previous reference. Figure 7 The described low-frequency to high-frequency range could be, for example, 240Hz. In the following text, reference will be made to... Figure 8 A display device driven at a frequency of 240 Hz is described as an example of this disclosure.

[0116] For example, when the display panel 100 is driven at a second frequency (240Hz), such as Figure 8 As shown, the m-th odd-numbered white data voltage Vdata1W_m provided to the m-th odd-numbered white data line DL1W_m can have a width of two horizontal periods of 2H. The m-th even-numbered white data voltage Vdata2W_m provided to the m-th even-numbered white data line DL2W_m can also have a width of two horizontal periods of 2H. The m-th red data voltage VdataR_m, m-th green data voltage VdataG_m, and m-th blue data voltage VdataB_m provided to the red pixel R, green pixel G, and blue pixel B respectively through the m-th red data line DLR_m, the m-th green data line DLG_m, and the m-th blue data line DLB_m can have a width of two horizontal periods of 2H. The gating pulses GPn, GPn+1, GPn+2, and GPn+3 provided to the gating lines can have a width of four horizontal periods of 4H.

[0117] In this case, two consecutively output gating pulses can have the same phase, and each gating pulse can overlap by two horizontal periods. For example, in Figure 8 In the process, the nth gating pulse GPn and the (n+1)th gating pulse GPn+1 can have the same phase, the (n+1)th gating pulse GPn+1 and the (n+2)th gating pulse GPn+2 can overlap two horizontal periods, and the (n+2)th gating pulse GPn+2 and the (n+3)th gating pulse GPn+3 can have the same phase.

[0118] That is, the nth gating pulse GPn output to the nth gating line GLn and the (n+1)th gating pulse GPn+1 output to the (n+1)th gating line GLn+1 can have the same phase, the (n+2)th gating pulse GPn+2 output to the (n+2)th gating line GLn+2 and the (n+3)th gating pulse GPn+3 output to the (n+3)th gating line GLn+3 can have the same phase, and the nth gating pulse GPn and the (n+2)th gating pulse GPn+2 can overlap during two horizontal periods 2H.

[0119] The width and overlap of each of the above-mentioned gating pulses can vary based on the width and overlap of each gating clock provided to the gating driver 200.

[0120] The width and overlap width of each strobe clock provided to the strobe driver 200 can be changed by the controller 400.

[0121] That is, when the display device is configured to be driven at a second frequency as a high frequency, the controller 400 can generate a gating clock of the form described above, and can transmit the gating clock to the gating driver 200. The configuration information enabling the display device to be driven at the second frequency can be stored in the storage unit 450.

[0122] Therefore, when the display device is turned on, the controller 400 can check the configuration information stored in the storage unit 450, and then, by using the timing synchronization signal transmitted from the external system, the controller 400 can generate a gating clock of the form described above, and can transmit the gating clock to the gating driver 200.

[0123] In this scenario, when the nth gating pulse GPn is provided to the nth gating line GLn and the (n+1)th gating pulse GPn+1 is provided to the (n+1)th gating line GLn+1, where n is an odd number, the odd-numbered white data voltage Vdata1W can be provided to the nth white pixel Wn connected to the nth gating line GLn, and the even-numbered white data voltage Vdata2W can be provided to the (n+1)th white pixel Wn+1 connected to the (n+1)th gating line GLn+1. The data voltage can be provided to the red pixel R, green pixel G, and blue pixel B connected to the nth gating line GLn via the red data line DLR, green data line DLG, and blue data line DLB, and the data voltage can be provided to the red pixel R, green pixel G, and blue pixel B connected to the (n+1)th gating line GLn+1 via the red data line DLR, green data line DLG, and blue data line DLB.

[0124] For example, such as Figure 6 and Figure 8As shown, when the nth gating pulse GPn is provided to the nth gating line GLn and the (n+1)th gating pulse GPn+1 is provided to the (n+1)th gating line GLn+1, where n is an odd number, the mth odd-numbered white data voltage Vdata1W_m can be provided to the nth white pixel Wn connected to the nth gating line GLn through the mth odd-numbered white data line DL1W_m, and the mth even-numbered white data voltage Vdata2W_m can be provided to the (n+1)th white pixel Wn+1 connected to the (n+1)th gating line GLn+1 through the mth even-numbered white data line DL2W_m. The data voltages VdataR_m, VdataG_m, and V... dataB_m can be supplied to the nth red pixel Rn, the nth green pixel Gn, and the nth blue pixel Bn connected to the nth gating line GLn through the mth red data line DLR_m, the mth green data line DLG_m, and the mth blue data line DLB_m, respectively. And the data voltages VdataR_m, VdataG_m, and VdataB_m can be supplied to the (n+1)th red pixel Rn+1, the (n+1)th green pixel Bn+1, and the (n+1)th blue pixel connected to the (n+1)th gating line GLn+1, respectively, through the mth red data line DLR_m, the mth green data line DLG_m, and the mth blue data line DLB_m.

[0125] To provide additional description, via Figure 8 C in the figure shows the timing for providing the nth gating pulse GPn to the nth gating line GLn and providing the (n+1)th gating pulse GPn+1 to the (n+1)th gating line GLn+1.

[0126] That is, at timing A, the m-th odd-numbered white data voltage Vdata1W_m(n) can be provided to the n-th white pixel Wn, and the m-th even-numbered white data voltage Vdata2W_m(n+1) can be provided to the (n+1)-th white pixel Wn+1. In the m-th odd-numbered white data voltage Vdata1W_m(n), (n) can represent the data voltage provided to the n-th white pixel Wn in the m-th odd-numbered white data voltage Vdata1W_m. In the m-th even-numbered white data voltage Vdata2W_m(n+1), (n+1) can represent the data voltage provided to the (n+1)-th white pixel Wn+1 in the m-th even-numbered white data voltage Vdata2W_m.

[0127] In this scenario, the m-th red data voltage VdataR_m(n) can be provided to the n-th red pixel Rn and the (n+1)-th red pixel Rn+1, the m-th green data voltage VdataG_m(n) can be provided to the n-th green pixel Gn and the (n+1)-th green pixel Gn+1, and the m-th blue data voltage VdataB_m(n) can be provided to the n-th blue pixel Bn and the (n+1)-th blue pixel Bn+1. Here, (n) can represent the data voltages provided to the n-th red pixel Rn, the n-th green pixel Gn, and the n-th blue pixel Bn from the m-th red data voltage VdataR_m(n), the m-th green data voltage VdataG_m(n), and the m-th blue data voltage VdataB_m(n).

[0128] In this case, such as Figure 8 As shown, when the nth gating pulse GPn is provided to the nth gating line GLn, the (n+1)th gating pulse GPn+1 can be provided to the (n+1)th gating line GLn+1. Therefore, the data voltage provided to the nth red pixel Rn can be provided to the (n+1)th red pixel Rn+1, the data voltage provided to the nth green pixel Gn can be provided to the (n+1)th green pixel Gn+1, and the data voltage provided to the nth blue pixel Bn can be provided to the (n+1)th blue pixel Bn+1.

[0129] Therefore, although Figure 8 The diagram shows the m-th red data voltage VdataR_m(n+1), the m-th green data voltage VdataG_m(n+1), and the m-th blue data voltage VdataB_m(n+1). The m-th red data voltage VdataR_m(n+1), the m-th green data voltage VdataG_m(n+1), and the m-th blue data voltage VdataB_m(n+1) can be the data voltages provided to the (n+1)-th red pixel Rn+1, the (n+1)-th green pixel Gn+1, and the (n+1)-th blue pixel Bn+1.

[0130] For additional description, at timing C, the m-th odd-numbered white data voltage Vdata1W_m can be provided to the n-th white pixel Wn, the m-th even-numbered white data voltage Vdata2W_m can be provided to the (n+1)-th white pixel Wn+1, the m-th red data voltage VdataR_m(n) can be provided to the n-th red pixel Rn and the (n+1)-th red pixel Rn+1, the m-th green data voltage VdataG_m(n) can be provided to the n-th green pixel Gn and the (n+1)-th green pixel Gn+1, and the m-th blue data voltage VdataB_m(n) can be provided to the n-th blue pixel Bn and the (n+1)-th blue pixel Bn+1.

[0131] That is, at time C, different data voltages can be provided to the nth white pixel Wn and the (n+1)th white pixel Wn+1.

[0132] However, at timing C, the same data voltage as that provided to the red pixel R connected to the (n+1)th gating line GLn+1 can be provided.

[0133] Furthermore, at timing C, the same data voltage as that provided to the green pixel G connected to the (n+1)th gating line GLn+1 can be provided to the green pixel G.

[0134] Furthermore, at timing C, the same data voltage as that provided to the blue pixel B connected to the (n+1)th gating line GLn+1 can be provided to the blue pixel B connected to the (n+1)th gating line GLn+1.

[0135] In this case, as mentioned above, the period for charging the pixel with data voltage can be 2H.

[0136] Therefore, in passing Figure 8 In the display device driven by the method shown, data voltage is charged into the red pixels Rn and Rn+1, green pixels Gn and Gn+1, and blue pixels Bn and Bn+1 for a period of 2H, which can be compared to the period 2H when the data voltage is charged into the red pixels Rn and Rn+1, green pixels Gn and Gn+1, and blue pixels Bn and Bn+1. Figure 7 In the display device driven by the method shown, data voltage is charged into the red pixels Rn and Rn+1, the green pixels Gn and Gn+1, and the blue pixels Bn and Bn+1 for a period of 1H.

[0137] Therefore, when Figure 8 When the method shown is applied to a display device driven at a high frequency, the period during which the data voltage is charged into the pixel can be increased, thereby improving the quality of the display device.

[0138] In the following text, reference will be made to Figure 9 Detailed examples of display devices that apply embodiments of this disclosure are described.

[0139] Figure 9 This is an exemplary diagram illustrating the format of input image data that can be input to a display device according to the present disclosure, driven at a high frequency.

[0140] The input image data to the display device can be RGB image data, including red data R, green data G, and blue data B.

[0141] Furthermore, the input image data to the display device can be YCbCr image data, which includes luminance data Y and chrominance data Cb and Cr. Here, Cb data can represent the difference YB between luminance data Y and blue data B, and Cr data can represent the difference YR between luminance data Y and red data R.

[0142] When the display device is configured with unit pixels 110a including white pixels W, red pixels R, green pixels G and blue pixels B, the display device can convert input RGB image data or YCbCr image data into WRGB format.

[0143] RGB image data can be used in a 4:4:4 format where all color components have the same sampling rate, and as... Figure 9 As shown, YCbCr image data can be used in one of the following formats based on the sampling rate of the chromaticity components: 4:4:4, 4:2:2, and 4:2:0. The 4:4:4, 4:2:2, and 4:2:0 formats are currently commonly used, so their descriptions are omitted.

[0144] When driving the display device according to this disclosure at a low frequency, at least one of the 4:4:4, 4:2:2, and 4:2:0 formats can be used. That is, as referred to above... Figure 7 In a display device driven at a low frequency, all pixels can be driven independently. Therefore, at least one of the 4:4:4, 4:2:2, and 4:2:0 formats can be used.

[0145] Recently, in order to improve the quality of display devices, the driving frequency of display devices can be gradually increased. When driving display devices at high frequencies, in order to increase the pixel charge ratio, a 4:2:0 format can be used, in which the same data voltage is provided to two adjacent unit pixels along the data line.

[0146] That is, when using the 4:2:0 format, as referred to above... Figure 8 The same data voltage should be provided to the nth red pixel Rn and the (n+1)th red pixel Rn+1 that are adjacent to each other along the data line, the same data voltage should be provided to the nth green pixel Gn and the (n+1)th green pixel Gn+1 that are adjacent to each other along the data line, and the same data voltage should be provided to the nth blue pixel Bn and the (n+1)th blue pixel Bn+1 that are adjacent to each other along the data line.

[0147] For the purpose of providing additional description, the display device according to this disclosure can be driven at all frequencies, both low and high. In particular, when the display device is driven at a low frequency, the display device can use at least one of the following formats: 4:4:4, 4:2:2, and 4:2:0, and when the display device is driven at a high frequency, the display device can use the 4:2:0 format.

[0148] Therefore, the display device according to the present disclosure can be driven at various frequencies, and the display device according to the present disclosure can be driven by using various formats.

[0149] According to this disclosure, when a display device is driven at a high frequency, the same data voltage can be provided to two adjacent color pixels along the data lines. Therefore, in a display device driven at a high frequency, the duration for which the data voltage is charged into the pixel can be increased, thereby improving the quality of the display device.

[0150] According to this disclosure, a display device that is driven at a high frequency can be driven at a low frequency. That is, according to this disclosure, a display device can be driven at various frequencies based on user selection.

[0151] In particular, when driving a display device at a low frequency, different data voltages can be provided to two adjacent color pixels along the data lines. Therefore, the quality of the display device driven at a low frequency can be improved.

[0152] Furthermore, according to this disclosure, when the display device is driven at a low frequency, different data voltages can be provided to two adjacent color pixels along the data lines. Therefore, the compensation methods used in the prior art can be fully applied to this disclosure. Consequently, a separate compensation method may be needed for the display device according to this disclosure, thus reducing the manufacturing cost of the display device.

[0153] The features, structures, and effects described above in this disclosure are included in at least one embodiment of this disclosure, but are not limited to only one embodiment. Furthermore, the features, structures, and effects described in at least one embodiment of this disclosure can be implemented by those skilled in the art through combinations or modifications of other embodiments. Therefore, anything associated with combinations and modifications should be interpreted as being within the scope of this disclosure.

[0154] It will be apparent to those skilled in the art that various modifications and variations can be made to this disclosure without departing from the technical concept or scope thereof. Therefore, this disclosure is intended to cover modifications and variations that fall within the scope of the appended claims and their equivalents.

[0155] Cross-reference to related applications

[0156] This patent application claims the benefit of Korean Patent Application No. 10-2021-0189821, filed on December 28, 2021, which is incorporated herein by reference as if fully set forth herein.

Claims

1. A display device, the display device comprising: Multiple data lines, wherein the multiple data lines extend along a first direction; Multiple gate lines, the multiple gate lines extending along a second direction; as well as Multiple unit pixels, wherein the multiple unit pixels are connected to the multiple data lines and the multiple gating lines, Each unit pixel comprises multiple pixels. When the display device is driven at a first frequency, the data voltages supplied to two adjacent color pixels arranged along the data lines are different from each other. When the display device is driven at a second frequency higher than the first frequency, the data voltage supplied to the two adjacent color pixels arranged along the data line is the same, and Wherein, the two adjacent colored pixels have the same color.

2. The display device according to claim 1, wherein, When the display device is driven at the first frequency, data voltages are provided to the nth white pixel and the (n+1)th white pixel via different data lines, where n is an odd number, and When the display device is driven at a second frequency higher than the first frequency, data voltage is provided to the nth white pixel and the (n+1)th white pixel through the different data lines.

3. The display device according to claim 1, wherein, Each pixel unit consists of a white pixel and multiple colored pixels.

4. The display device according to claim 3, wherein, The nth white pixel among a plurality of white pixels arranged in the first direction is connected to an odd-numbered white data line, where n is an odd number, and The (n+1)th white pixel among the plurality of white pixels arranged in the first direction is connected to an even-numbered white data line.

5. The display device according to claim 3, wherein, The plurality of colored pixels includes red pixels, green pixels, and blue pixels. The red pixel positioned in the first direction is connected to the red data line. The green pixel positioned in the first direction is connected to the green data line, and The blue pixel positioned in the first direction is connected to the blue data line.

6. The display device according to claim 4, wherein, Drive the display device at a first frequency. The data voltage supplied to the odd-numbered white data lines and the even-numbered white data lines has a width of two horizontal cycles. The data voltage provided to the plurality of color pixels has a horizontal period width, and The gating pulses provided to the multiple gating lines have a width of two horizontal cycles.

7. The display device according to claim 6, wherein, The two gating pulses in the gating pulse are output continuously and overlap each other by one horizontal cycle.

8. The display device according to claim 7, wherein, The plurality of colored pixels includes red pixels, green pixels, and blue pixels. The red pixel positioned in the first direction is connected to the red data line. The green pixel positioned in the first direction is connected to the green data line. The blue pixel positioned in the first direction is connected to the blue data line, and The data voltages supplied to the red, green, and blue data lines have a horizontal cycle width.

9. The display device according to claim 8, wherein, When the nth gating pulse is provided to the nth gating line The nth white data voltage is provided to the nth white pixel connected to the nth gating line via the odd-numbered white data lines, and The nth data voltage is provided to the red pixel, the green pixel, and the blue pixel connected to the nth gate line through the red data line, the green data line, and the blue data line, respectively.

10. The display device according to claim 9, wherein, When the (n+1)th gating pulse is provided to the (n+1)th gating line, The (n+1)th white data voltage is provided to the (n+1)th white pixel connected to the (n+1)th gate line via the even-numbered white data lines, and The (n+1)th data voltage is provided to the red pixel, the green pixel, and the blue pixel connected to the (n+1)th gate line through the red data line, the green data line, and the blue data line, respectively.

11. The display device according to claim 6, wherein, Different data voltages are provided to the nth white pixel and the (n+1)th white pixel.

12. The display device according to claim 4, wherein, Drive the display device at a second frequency. The data voltage supplied to the odd-numbered white data lines and the even-numbered white data lines has a width of two horizontal cycles. The data voltage supplied to the plurality of color pixels has a width of two horizontal periods, and The gating pulses provided to the multiple gating lines have a width of four horizontal cycles.

13. The display device according to claim 12, wherein, The gating pulses include the nth gating pulse transmitted to the nth gating line, the (n+1)th gating pulse transmitted to the (n+1)th gating line, the (n+2)th gating pulse transmitted to the (n+2)th gating line, and the (n+3)th gating pulse transmitted to the (n+3)th gating line. The nth gating pulse and the (n+1)th gating pulse have the same phase. The (n+2)th gating pulse and the (n+3)th gating pulse have the same phase, and The nth gating pulse overlaps with the (n+1)th gating pulse during two horizontal cycles.

14. The display device according to claim 13, wherein, The plurality of colored pixels includes red pixels, green pixels, and blue pixels. The red pixel positioned in the first direction is connected to the red data line. The green pixel positioned in the first direction is connected to the green data line. The blue pixel positioned in the first direction is connected to the blue data line, and The data voltages supplied to the red, green, and blue data lines have a width of two horizontal cycles.

15. The display device according to claim 14, wherein, The nth gating pulse is provided to the nth gating line and the (n+1)th gating pulse is provided to the (n+1)th gating line. The nth white data voltage is provided to the nth white pixel connected to the nth gating line through the odd-numbered white data lines. The (n+1)th white data voltage is provided to the (n+1)th white pixel connected to the (n+1)th gating line via the even-numbered white data line. Data voltages are provided to the red, blue, and green pixels connected to the nth gate line via the red, green, and blue data lines. Data voltages are provided to the red pixel, the blue pixel, and the green pixel connected to the (n+1)th gating line via the red data line, the green data line, and the blue data line.

16. The display device according to claim 12, wherein, Different data voltages are provided to the nth white pixel and the (n+1)th white pixel.

17. The display device according to claim 12, wherein, The plurality of colored pixels includes red pixels, green pixels, and blue pixels. The same data voltage is provided to the red pixel connected to the nth gating line and the red pixel connected to the (n+1)th gating line. The same data voltage is provided to the green pixels connected to the nth gating line and the green pixels connected to the (n+1)th gating line, and The same data voltage is provided to the blue pixels connected to the nth gating line and the blue pixels connected to the (n+1)th gating line.

Images