Staggered parallel active static var generator

Abstract

The invention provides an active static var generator in an interleaved parallel form, and relates to the technical field of integrated circuits, and the active static var generator comprises a first three-level topology module which comprises a first three-level topology circuit and a second three-level topology circuit which are connected in parallel between a bus positive electrode and a bus negative electrode, the midpoint of a first switching tube bridge arm of the first three-level topological circuit is coupled with the second end of the first inductor, and the midpoint of a second switching tube bridge arm of the second three-level topological circuit is coupled with the second end of the second inductor. The midpoint of a first diode bridge arm of the first three-level topological circuit and the midpoint of a second diode bridge arm of the second three-level topological circuit are both coupled with the null line connecting end, and the first capacitor is coupled between the first live line connecting end and the second end coupled with the null line connecting end. The first end of the first inductor and the first end of the second inductor are both coupled with the first live wire connecting end, and the problem that the performance is poor in the scene of ultrahigh frequency response, extreme ripple suppression or multi-module flexible expansion is solved.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit technology, specifically to an active static var generator in an interleaved parallel configuration. Background Technology

[0002] An SVG (Static Var Generator) is a device used in power systems to regulate voltage, current, and reactive power, thereby dynamically compensating for reactive power in the power grid and improving power quality. SVG stabilizes voltage by rapidly adjusting current and is widely used in industrial power grids. A three-level topology is a circuit structure design in power electronic converters. Compared to the traditional two-level design, it can reduce the harmonic content of the output voltage and improve efficiency, but its design and control are more complex. Among related technologies, SVGs based on the "three-level topology" perform poorly in scenarios requiring ultra-high frequency response, extreme ripple suppression, or flexible expansion with multiple modules. Summary of the Invention

[0003] The main purpose of this disclosure is to provide an active static var generator in an interleaved parallel configuration to improve the poor performance of SVG in scenarios requiring ultra-high frequency response, extreme ripple suppression, or flexible expansion with multiple modules.

[0004] To achieve the above objectives, a first aspect of this disclosure provides an active static var generator in an interleaved parallel configuration, the active static var generator comprising: The first live wire connection terminal is used to couple to the first live wire in the power grid; The load-side busbar includes the positive and negative terminals of the busbar. Neutral wire connection terminal, used to couple to the neutral wire in the power grid; The first capacitor has a first terminal coupled to the first live wire connection terminal and a second terminal coupled to the neutral wire connection terminal. The first inductor and the second inductor are both coupled to the first live wire connection terminal. A first three-level topology module is coupled between the positive and negative terminals of the busbar. The first three-level topology module includes a first three-level topology circuit and a second three-level topology circuit connected in parallel between the positive and negative terminals of the busbar. The midpoint of the first switching transistor bridge arm of the first three-level topology circuit is coupled to the second terminal of the first inductor. The midpoint of the second switching transistor bridge arm of the second three-level topology circuit is coupled to the second terminal of the second inductor. The midpoints of the first diode bridge arm of the first three-level topology circuit and the midpoints of the second diode bridge arm of the second three-level topology circuit are both coupled to the neutral connection terminal.

[0005] In some embodiments of this disclosure, the active static var generator further includes: A first driving component includes a first driver and a second driver, wherein the first driver is configured to drive the switching transistor in a first three-level topology circuit to turn off and turn on, and the second driver is configured to drive the switching transistor in a second three-level topology circuit to turn off and turn on.

[0006] In some embodiments of this disclosure, the first three-level topology circuit includes: The first switch transistor, the second switch transistor, the third switch transistor, and the fourth switch transistor are provided. The first end of the first switch transistor is coupled to the positive terminal of the busbar, the second end of the first switch transistor is coupled to the first end of the second switch transistor, the second end of the second switch transistor is coupled to the first end of the third switch transistor through the midpoint of the bridge arm of the first switch transistor, the second end of the third switch transistor is coupled to the first end of the fourth switch transistor, and the second end of the fourth switch transistor is coupled to the negative terminal of the busbar. The first diode and the second diode are provided, wherein the positive terminal of the first diode is coupled to the negative terminal of the second diode through the midpoint of the first diode bridge arm, the negative terminal of the first diode is coupled to the second terminal of the first switch and the first terminal of the second switch, and the positive terminal of the second diode is coupled to the second terminal of the third switch and the first terminal of the fourth switch. The first driver is configured to drive the first switch, the second switch, the third switch and the fourth switch to turn off and on.

[0007] In some embodiments of this disclosure, the second three-level topology circuit includes: The fifth, sixth, seventh, and eighth switch transistors are provided. The first end of the fifth switch transistor is coupled to the positive terminal of the busbar, the second end of the fifth switch transistor is coupled to the first end of the sixth switch transistor, the second end of the sixth switch transistor is coupled to the first end of the seventh switch transistor through the midpoint of the second switch transistor bridge arm, the second end of the seventh switch transistor is coupled to the first end of the eighth switch transistor, and the second end of the eighth switch transistor is coupled to the negative terminal of the busbar. The third diode and the fourth diode, wherein the positive terminal of the third diode is coupled to the negative terminal of the fourth diode through the midpoint of the second diode bridge arm, the negative terminal of the third diode is coupled to the second terminal of the fifth switch and the first terminal of the sixth switch, and the positive terminal of the fourth diode is coupled to the second terminal of the seventh switch and the first terminal of the eighth switch. The second driver is configured to turn the fifth, sixth, seventh and eighth switching transistors on and off.

[0008] In some embodiments of this disclosure, the active static var generator further includes: The second live wire connection terminal is used to couple to the second live wire in the power grid; The second capacitor has its first end coupled to the second live wire connection terminal and its second end coupled to the neutral wire connection terminal. The third inductor and the fourth inductor, the first end of the third inductor and the first end of the fourth inductor are both coupled to the second live wire connection terminal; A second three-level topology module is coupled between the positive and negative terminals of the busbar. The second three-level topology module includes a third three-level topology circuit and a fourth three-level topology circuit connected in parallel between the positive and negative terminals of the busbar. The midpoint of the third switching bridge arm of the third three-level topology circuit is coupled to the second terminal of the third inductor, and the midpoint of the fourth switching bridge arm of the fourth three-level topology circuit is coupled to the second terminal of the fourth inductor. The midpoints of the third diode bridge arm of the third three-level topology circuit and the midpoints of the fourth diode bridge arm of the fourth three-level topology circuit are both coupled to the neutral connection terminal.

[0009] In some embodiments of this disclosure, the active static var generator further includes: The second driving component includes a third driver and a fourth driver, wherein the third driver is configured to drive the switching transistor in the third three-level topology circuit to turn off and turn on, and the fourth driver is configured to drive the switching transistor in the fourth three-level topology circuit to turn off and turn on.

[0010] In some embodiments of this disclosure, the active static var generator further includes: The third live wire connection terminal is used to couple to the third live wire in the power grid; The third capacitor has its first end coupled to the third live wire connection terminal and its second end coupled to the neutral wire connection terminal. The fifth inductor and the sixth inductor, the first end of the fifth inductor and the first end of the sixth inductor are both coupled to the third live wire connection terminal; A third three-level topology module is coupled between the positive and negative terminals of the busbar. The third three-level topology module includes a fifth three-level topology circuit and a sixth three-level topology circuit connected in parallel between the positive and negative terminals of the busbar. The midpoint of the fifth switching bridge arm of the fifth three-level topology circuit is coupled to the second terminal of the fifth inductor, and the midpoint of the sixth switching bridge arm of the sixth three-level topology circuit is coupled to the second terminal of the sixth inductor. The midpoints of the fifth diode bridge arm of the fifth three-level topology circuit and the sixth diode bridge arm of the sixth three-level topology circuit are both coupled to the neutral connection terminal.

[0011] In some embodiments of this disclosure, the switching transistors in the first three-level topology circuit to the sixth three-level topology circuit are all high-frequency switching transistors with a switching frequency of not less than 40kHz.

[0012] In some embodiments of this disclosure, the active static var generator further includes: The third driving component includes a fifth driver and a sixth driver, wherein the fifth driver is configured to drive the switching transistor in the fifth three-level topology circuit to turn off and turn on, and the sixth driver is configured to drive the switching transistor in the sixth three-level topology circuit to turn off and turn on.

[0013] In some embodiments of this disclosure, the third three-level topology circuit includes: a ninth switch, a tenth switch, an eleventh switch, a twelfth switch, a fifth diode, and a sixth diode. The first terminal of the ninth switch is coupled to the positive terminal of the bus; the second terminal of the ninth switch is coupled to the first terminal of the tenth switch; the second terminal of the tenth switch is coupled to the first terminal of the eleventh switch via the midpoint of a third switch bridge arm; the second terminal of the eleventh switch is coupled to the first terminal of the twelfth switch; and the second terminal of the twelfth switch is coupled to the negative terminal of the bus. The anode of the fifth diode is coupled to the cathode of the sixth diode via the midpoint of a third diode bridge arm; the cathode of the fifth diode is coupled to the second terminal of the ninth switch and the first terminal of the tenth switch; and the anode of the sixth diode is coupled to the second terminal of the eleventh switch and the first terminal of the twelfth switch. A third driver is configured to drive the ninth, tenth, eleventh, and twelfth switches to turn off and on; and / or, The fourth three-level topology circuit includes: a thirteenth switch, a fourteenth switch, a fifteenth switch, a sixteenth switch, a seventh diode, and an eighth diode. The first terminal of the thirteenth switch is coupled to the positive terminal of the bus; the second terminal of the thirteenth switch is coupled to the first terminal of the fourteenth switch; the second terminal of the fourteenth switch is coupled to the first terminal of the fifteenth switch through the midpoint of the fourth switch bridge arm; the second terminal of the fifteenth switch is coupled to the first terminal of the sixteenth switch; and the second terminal of the sixteenth switch is coupled to the negative terminal of the bus. The anode of the seventh diode is coupled to the cathode of the eighth diode through the midpoint of the fourth diode bridge arm; the cathode of the seventh diode is coupled to the second terminal of the thirteenth switch and the first terminal of the fourteenth switch; and the anode of the eighth diode is coupled to the second terminal of the fifteenth switch and the first terminal of the sixteenth switch. The fourth driver is configured to drive the thirteenth, fourteenth, fifteenth, and sixteenth switches to turn off and on; and / or, The fifth three-level topology circuit includes: a seventeenth switch, an eighteenth switch, a nineteenth switch, a twentieth switch, a ninth diode, and a tenth diode. The first terminal of the seventeenth switch is coupled to the positive terminal of the bus; the second terminal of the seventeenth switch is coupled to the first terminal of the eighteenth switch; the second terminal of the eighteenth switch is coupled to the first terminal of the nineteenth switch via the midpoint of the fifth switch bridge arm; the second terminal of the nineteenth switch is coupled to the first terminal of the twentieth switch; and the second terminal of the twentieth switch is coupled to the negative terminal of the bus. The anode of the ninth diode is coupled to the cathode of the tenth diode via the midpoint of the fifth diode bridge arm; the cathode of the ninth diode is coupled to the second terminal of the seventeenth switch and the first terminal of the eighteenth switch; and the anode of the tenth diode is coupled to the second terminal of the nineteenth switch and the first terminal of the twentieth switch. The fifth driver is configured to drive the seventeenth, eighteenth, nineteenth, and twentieth switches to turn off and on; and / or, The sixth three-level topology circuit includes: a twenty-first switch, a twenty-second switch, a twenty-third switch, a twenty-fourth switch, an eleventh diode, and a twelfth diode. The first terminal of the twenty-first switch is coupled to the positive terminal of the bus, the second terminal of the twenty-first switch is coupled to the first terminal of the twenty-second switch, the second terminal of the twenty-second switch is coupled to the first terminal of the twenty-third switch through the midpoint of the sixth switch bridge arm, the second terminal of the twenty-third switch is coupled to the first terminal of the twenty-fourth switch, and the second terminal of the twenty-fourth switch is coupled to the negative terminal of the bus. The positive terminal of the eleventh diode is coupled to the negative terminal of the twelfth diode through the midpoint of the sixth diode bridge arm, the negative terminal of the eleventh diode is coupled to the second terminal of the twenty-first switch and the first terminal of the twenty-second switch, and the positive terminal of the twelfth diode is coupled to the second terminal of the twenty-third switch and the first terminal of the twenty-fourth switch. The sixth driver is configured to drive the twenty-first, twenty-second, twenty-third, and twenty-fourth switches to turn off and on.

[0014] A second aspect of this disclosure provides a chip that includes an active static var generator in an interleaved parallel configuration according to a first aspect of this disclosure.

[0015] A third aspect of this disclosure provides an electronic device that includes a chip according to a second aspect of this disclosure.

[0016] The interleaved parallel configuration of the active static var generator (SVG) provided in this embodiment employs a first three-level topology circuit and a second three-level topology circuit connected in parallel between the positive and negative terminals of the bus as the first three-level topology module. The midpoint of the first switching arm of the first three-level topology circuit is coupled to the second terminal of the first inductor, and the midpoint of the second switching arm of the second three-level topology circuit is coupled to the second terminal of the second inductor. The midpoints of the first diode arms of both the first and second three-level topology circuits are coupled to the neutral wire connection. The first terminal of the first capacitor is coupled to the first live wire connection, and the second terminal of the first capacitor is coupled to the neutral wire connection. The first and second inductors are both coupled to the first live wire connection. This interleaved parallel configuration technology leverages its advantages of improved ripple suppression, reduced stress on main power devices, and optimized filter element size to improve the poor performance of SVG in scenarios requiring ultra-high frequency response, extreme ripple suppression, or flexible multi-module expansion. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the specific embodiments or related technologies of this disclosure, the accompanying drawings used in the description of the specific embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of the circuit topology of an active static var generator with an interleaved parallel configuration provided in an embodiment of this disclosure; Figure 2 This is a schematic diagram of the circuit topology of another interleaved parallel configuration of an active static var generator provided in this embodiment of the present disclosure; Figure 3 This is a partial circuit topology diagram of another interleaved parallel configuration of an active static var generator provided in this embodiment.

[0019] It should be noted that the elements in the attached diagram are schematic and not drawn to scale. Detailed Implementation

[0020] To enable those skilled in the art to better understand the present disclosure, the technical solutions of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present disclosure, and not all embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present disclosure.

[0021] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this disclosure described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0022] In this disclosure, the terms "upper," "middle," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. These terms are primarily used to better describe this disclosure and its embodiments, and are not intended to limit the indicated devices, elements, or components to having a particular orientation, or to be constructed and operated in a particular orientation.

[0023] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this subject matter pertains. It will be further understood that terms such as those defined in commonly used dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the specification and in the relevant art, and shall not be interpreted in an idealized or overly formal form unless otherwise explicitly defined herein. As used herein, the statement of “connecting” or “coupling” two or more parts together shall mean that these parts are directly joined together or joined through one or more intermediate components.

[0024] In all embodiments of this disclosure, the controlled intermediate terminal of the switching transistor is referred to as the control electrode, and the other two ends of the switching transistor and other switching devices are referred to as the first electrode and the second electrode, respectively.

[0025] It should be noted that, unless otherwise specified, the embodiments and features described in this disclosure can be combined with each other. This disclosure will now be described in detail with reference to the accompanying drawings and embodiments.

[0026] The inventors of this disclosure have discovered that using an SVG with a conventional three-level topology and a switching frequency of 20kHz presents several challenges. These challenges primarily focus on three aspects: performance adaptability, cost control, and engineering implementation difficulty. For instance, when using a conventional three-level topology and a 20kHz switching frequency for an SVG, the main drawbacks revolve around performance adaptability (the ability of the device to meet actual needs in specific application scenarios; for SVG, poor performance adaptability may mean an inability to adapt well to grid fluctuations or load changes), cost control (achieving target performance at the lowest cost is a crucial consideration in engineering design; high switching frequencies and complex topologies may lead to higher material and manufacturing costs), and engineering implementation difficulty (the ease with which theoretical designs are translated into actual products or systems; complex topologies and high-frequency switching may require more sophisticated processes and technical support, increasing implementation complexity). These are detailed below: (1) The high-frequency performance is weaker than the higher switching frequency scheme: Compared with the 40kHz interleaved parallel (equivalent to 80K) scheme, the current ripple at the 20kHz frequency is larger (under the same inductance, the ripple amplitude is about 4 times that of the 80K scheme), requiring a larger capacity LCL filter to achieve the same ripple suppression effect, resulting in a slightly larger filter size and weight, and a slightly slower dynamic response speed, making it difficult to cope with ultra-fast changing loads (such as high-frequency pulse loads).

[0027] (2) The flexibility of multi-module parallel control is low: If the power needs to be expanded by using multi-module parallel connection, the 20kHz single frequency scheme cannot cancel the ripple through phase shift like the interleaved parallel connection. An additional current sharing control strategy needs to be designed. Otherwise, uneven current distribution between modules is likely to occur, increasing the risk of system instability. Moreover, the overall harmonic suppression capability is only slightly improved after expansion.

[0028] (3) Insufficient adaptability to high-frequency scenarios: In scenarios with extremely high requirements for power quality (such as high-frequency harmonic control in precision electronic manufacturing and new energy grid connection), high-frequency harmonics at a switching frequency of 20kHz (such as around 20kHz) may not be sufficiently suppressed, requiring additional high-frequency filtering links, which leads to increased system complexity and cost.

[0029] In summary, the SVG solution consisting of a conventional three-level topology and a 20kHz switching frequency is a balanced choice in terms of performance, cost, and reliability. It is suitable for conventional reactive power compensation scenarios with moderate dynamic response requirements and cost sensitivity (such as low-voltage side compensation in industrial plants, distribution networks, and wind farms / photovoltaic power plants). However, in scenarios requiring ultra-high frequency response, extreme ripple suppression, or flexible expansion with multiple modules, its performance is inferior to the high-frequency interleaved parallel solution provided in this application's embodiments. Furthermore, when this "three-level topology" design is combined with a specific higher switching frequency, it leads to technical challenges, such as difficulty in meeting practical needs, higher costs, or complex construction.

[0030] Example 1: To solve the above problems, refer to Figure 1 This disclosure provides an active static var generator in an interleaved parallel configuration, which aims to improve the poor performance of SVG in scenarios requiring ultra-high frequency response, extreme ripple suppression, or flexible expansion of multiple modules. Figure 1 A schematic block diagram of an active static var generator in an interleaved parallel configuration according to an embodiment of the present disclosure is shown. Figure 1 As shown, the interleaved parallel active static var generator includes: a first live wire connection terminal UA, a load-side bus, a neutral wire connection terminal N, a first capacitor C1, a first inductor L1, a second inductor L2, and a first three-level topology module. The first live wire connection terminal UA is used to couple to the first live wire in the power grid; the load-side bus includes a positive terminal Bus+ and a negative terminal Bus-; the neutral wire connection terminal N is used to couple to the neutral wire in the power grid; the first terminal of the first capacitor C1 is coupled to the first live wire connection terminal UA, and the second terminal of the first capacitor C1 is coupled to the neutral wire connection terminal N; the first terminals of the first inductor L1 and the second inductor L2 are both coupled to the first live wire connection terminal UA; the first three-level topology module is coupled between the positive terminal Bus+ and the negative terminal Bus- of the bus. The topology module includes a first three-level topology circuit 11 and a second three-level topology circuit 12 connected in parallel between the positive terminal Bus+ and the negative terminal Bus- of the bus. The midpoint Z1 of the first switching bridge arm of the first three-level topology circuit 11 is coupled to the second terminal of the first inductor L1. The midpoint Z2 of the second switching bridge arm of the second three-level topology circuit 12 is coupled to the second terminal of the second inductor L2. The midpoint Y1 of the first diode bridge arm of the first three-level topology circuit 11 and the midpoint Y2 of the second diode bridge arm of the second three-level topology circuit 12 are both coupled to the neutral connection terminal N.

[0031] In the above scheme, a first three-level topology circuit 11 and a second three-level topology circuit 12 connected in parallel between the positive terminal Bus+ and the negative terminal Bus- are used as the first three-level topology module. The midpoint Z1 of the first switching bridge arm of the first three-level topology circuit 11 is coupled to the second end of the first inductor L1. The midpoint Z2 of the second switching bridge arm of the second three-level topology circuit 12 is coupled to the second end of the second inductor L2. The midpoint Y1 of the first diode bridge arm of the first three-level topology circuit 11 and the midpoint Y2 of the second diode bridge arm of the second three-level topology circuit 12 are both coupled to the neutral connection terminal N. The first end of the first capacitor C1 is coupled to the first live connection terminal UA. The second end of the first capacitor C1 is coupled to the neutral connection terminal N. The first inductor L1 and the second inductor L2 are both coupled to the first live connection terminal UA.

[0032] By employing the aforementioned interleaved parallel technology, the advantages of this technology—enhanced ripple suppression, reduced stress on main power devices, and optimized filter component size—can be leveraged to improve the poor performance of SVG in scenarios requiring ultra-high frequency response, extreme ripple suppression, or flexible multi-module expansion. Specifically, in the interleaved parallel topology, the ripple of the output current from the first three-level topology circuit 11 and the second three-level topology circuit 12 cancels each other out. This eliminates the need for large-volume filter components, effectively suppressing grid-connected current ripple to an extremely low level, significantly reducing the burden on subsequent filters and simplifying the design of the filtering system. Interleaved parallel connection allows multiple switching devices, including but not limited to power devices (such as IGBTs), to share the total current, reducing the current stress on individual switching devices, improving the overall efficiency of the SVG, and extending device lifespan, making it particularly suitable for medium-to-high power SVG scenarios. Furthermore, this approach optimizes the overall size and dynamic response, enhances high-frequency response and ripple suppression, and significantly reduces the capacitance requirements of components such as filter inductors and capacitors, thereby drastically reducing the overall size and weight of the SVG. This reduces the capacitance requirement of the first capacitor C1, eliminating the need for a large capacitor as the first capacitor C1 and thus reducing its size. Similarly, this method reduces the inductance requirements of the first inductor L1 and the second inductor L2, eliminating the need for large inductance values ​​for each, and thus reducing their size as well.

[0033] The following is a detailed description of the interleaved parallel configuration of the active static var generator (VSG). It should be understood that the accompanying drawings are for illustrative purposes only and do not constitute a limitation on the protection scope of the interleaved parallel configuration of the VSG.

[0034] For example, refer to Figure 2The active static var generator further includes a first drive assembly, comprising a first driver M1 and a second driver M2. The first driver M1 is configured to drive the switching transistors in the first three-level topology circuit 11 to turn off and on, and the second driver M2 is configured to drive the switching transistors in the second three-level topology circuit 12 to turn off and on. By employing two independent first drivers M1 and second drivers M2 to drive the switching transistors in the first three-level topology circuit 11 and the second three-level topology circuit 12 to turn off and on respectively, compared to the related technology's "conventional three-level topology" which can only use one driver to drive the switching transistors to turn on and off, the method disclosed herein can control the switching transistors in the first three-level topology circuit 11 and the second three-level topology circuit 12 to turn off and on separately, thereby reducing the synchronization accuracy requirement. Furthermore, it allows for independent adjustment feedback loops, achieving diversified and refined adjustment methods, thus more accurately adjusting the electrical output parameters of the load bus.

[0035] For example, refer to Figure 1 and Figure 2 The first three-level topology circuit 11 includes: a first switch Q1, a second switch Q2, a third switch Q3, a fourth switch Q4, a first diode D1, and a second diode D2. The first terminal of the first switch Q1 is coupled to the positive terminal Bus+, the second terminal of the first switch Q1 is coupled to the first terminal of the second switch Q2, the second terminal of the second switch Q2 is coupled to the first terminal of the third switch Q3 through the midpoint Z1 of the first switch bridge arm, and the second terminal of the third switch Q3 is coupled to the first terminal of the fourth switch Q4. The second terminal of switch Q4 is coupled to the negative terminal of bus Bus-; the positive terminal of the first diode D1 is coupled to the negative terminal of the second diode D2 through the midpoint Y1 of the first diode bridge arm. The negative terminal of the first diode D1 is coupled to the second terminal of the first switch Q1 and the first terminal of the second switch Q2. The positive terminal of the second diode D2 is coupled to the second terminal of the third switch Q3 and the first terminal of the fourth switch Q4. The first driver M1 is configured to drive the first switch Q1, the second switch Q2, the third switch Q3, and the fourth switch Q4 to turn off and on. By using the above method to form the first three-level topology circuit 11, the harmonic components of the output waveform of the first three-level topology circuit 11 can be reduced, the loss can be reduced, thereby increasing the switching frequency of the switches in the first three-level topology circuit 11 and reducing the system cost. Moreover, the above method can improve the reliability of the first three-level topology circuit 11 and improve electromagnetic interference (EMI).

[0036] For example, refer to Figure 1 and Figure 2The second three-level topology circuit 12 includes: a fifth switch Q5, a sixth switch Q6, a seventh switch Q7, an eighth switch Q8, a third diode D3, and a fourth diode D4. The first terminal of the fifth switch Q5 is coupled to the positive terminal Bus+, the second terminal of the fifth switch Q5 is coupled to the first terminal of the sixth switch Q6, the second terminal of the sixth switch Q6 is coupled to the first terminal of the seventh switch Q7 through the midpoint Z2 of the second switch bridge arm, and the second terminal of the seventh switch Q7 is coupled to the first terminal of the eighth switch Q8. The second terminal of switch Q8 is coupled to the negative terminal of the bus (Bus-). The positive terminal of the third diode D3 is coupled to the negative terminal of the fourth diode D4 through the midpoint Y2 of the second diode bridge arm. The negative terminal of the third diode D3 is coupled to the second terminal of the fifth switch Q5 and the first terminal of the sixth switch Q6. The positive terminal of the fourth diode D4 is coupled to the second terminal of the seventh switch Q7 and the first terminal of the eighth switch Q8. The second driver M2 is configured to drive the fifth switch Q5, the sixth switch Q6, the seventh switch Q7, and the eighth switch Q8 to turn off and on. By using the above method to form the second three-level topology circuit 12, the harmonic components of the output waveform of the second three-level topology circuit 12 can be reduced, the loss can be reduced, thereby increasing the switching frequency of the switches in the second three-level topology circuit 12 and reducing the system cost. Moreover, the above method can improve the reliability of the second three-level topology circuit 12 and improve electromagnetic interference (EMI).

[0037] For example, refer to Figure 1 and Figure 2 The active static var generator also includes: a second live wire connection terminal UB, a second capacitor C2, a third inductor L3, a fourth inductor L4, and a second three-level topology module. The second live wire connection terminal UB is used to couple to the second live wire in the power grid; the first end of the second capacitor C2 is coupled to the second live wire connection terminal UB, and the second end of the second capacitor C2 is coupled to the neutral wire connection terminal N; the first end of the third inductor L3 and the first end of the fourth inductor L4 are both coupled to the second live wire connection terminal UB; the second three-level topology module is coupled between the positive terminal Bus+ and the negative terminal Bus- of the bus. The second three-level topology module includes a third three-level topology circuit 13 and a fourth three-level topology circuit 14 connected in parallel between the positive terminal Bus+ and the negative terminal Bus- of the bus. The midpoint Z3 of the third switch bridge arm of the third three-level topology circuit 13 is coupled to the second end of the third inductor L3, the midpoint Z4 of the fourth switch bridge arm of the fourth three-level topology circuit 14 is coupled to the second end of the fourth inductor L4, and the midpoint Y3 of the third diode bridge arm of the third three-level topology circuit 13 and the midpoint Y4 of the fourth diode bridge arm of the fourth three-level topology circuit 14 are both coupled to the neutral wire connection terminal N.

[0038] By employing the aforementioned interleaved parallel topology, the output current ripple of the third three-level topology circuit 13 and the fourth three-level topology circuit 14 cancel each other out. This eliminates the need for bulky filter components, suppressing grid-connected current ripple to an extremely low level, significantly reducing the burden on subsequent filters and simplifying the design of the filtering system. Interleaved parallel connection allows multiple switching devices, including but not limited to power devices (such as IGBTs), to share the total current, reducing the current stress on individual switching devices, improving the overall efficiency of the SVG, and extending device lifespan. This is particularly suitable for medium-to-high power SVG applications. Furthermore, this approach optimizes the overall size and dynamic response, enhances high-frequency operation and ripple suppression, and significantly reduces the capacitance requirements of components such as filter inductors and capacitors, resulting in a substantial reduction in the overall size and weight of the SVG. This reduces the capacitance requirement of the second capacitor C2, eliminating the need for a large capacitor as the second capacitor C2 and thus reducing its size. The above method can also reduce the inductance value requirements of the third inductor L3 and the fourth inductor L4, so that inductors with large inductance values ​​can be used as the third inductor L3 and the fourth inductor L4 respectively, thereby reducing the size of the third inductor L3 and the fourth inductor L4.

[0039] For example, refer to Figure 2 The active static var generator further includes a second drive assembly, which comprises a third driver M3 and a fourth driver M4. The third driver M3 is configured to drive the switching transistors in the third three-level topology circuit 13 to turn off and on, and the fourth driver M4 is configured to drive the switching transistors in the fourth three-level topology circuit 14 to turn off and on. By employing two independent third drivers M3 and fourth drivers M4 to drive the switching transistors in the third three-level topology circuit 13 and the fourth three-level topology circuit 14 to turn off and on respectively, compared to the "conventional three-level topology" in related technologies which can only use one driver to drive the switching transistors to turn on and off, the method disclosed herein can control the switching transistors in the third three-level topology circuit 13 and the fourth three-level topology circuit 14 to turn off and on separately, thereby reducing the synchronization accuracy requirement. Furthermore, it allows for independent adjustment feedback loops, enabling diversified and refined adjustment methods, thus more accurately adjusting the electrical output parameters of the load bus.

[0040] For example, refer to Figure 1 and Figure 2The third three-level topology circuit 13 includes: a ninth switch Q9, a tenth switch Q10, an eleventh switch Q11, a twelfth switch Q12, a fifth diode D5, and a sixth diode D6. The first terminal of the ninth switch Q9 is coupled to the positive terminal Bus+, and the second terminal of the ninth switch Q9 is coupled to the first terminal of the tenth switch Q10. The second terminal of the tenth switch Q10 is coupled to the first terminal of the eleventh switch Q11 through the midpoint Z3 of the third switch bridge arm. The second terminal of the eleventh switch Q11 is coupled to the first terminal of the twelfth switch Q12. The second terminal of the second switching transistor Q12 is coupled to the negative terminal of the bus (Bus-). The positive terminal of the fifth diode D5 is coupled to the negative terminal of the sixth diode D6 through the midpoint Y3 of the third diode bridge arm. The negative terminal of the fifth diode D5 is coupled to the second terminal of the ninth switching transistor Q9 and the first terminal of the tenth switching transistor Q10. The positive terminal of the sixth diode D6 is coupled to the second terminal of the eleventh switching transistor Q11 and the first terminal of the twelfth switching transistor Q12. The third driver M3 is configured to drive the turn-off and turn-on of the ninth switching transistor Q9, the tenth switching transistor Q10, the eleventh switching transistor Q11, and the twelfth switching transistor Q12. By using the above method to form the third three-level topology circuit 13, the harmonic components of the output waveform of the third three-level topology circuit 13 can be reduced, the loss can be reduced, thereby increasing the switching frequency of the switching transistors in the third three-level topology circuit 13 and reducing the system cost. Moreover, the above method can improve the reliability of the third three-level topology circuit 13 and improve electromagnetic interference (EMI).

[0041] For example, refer to Figure 1 and Figure 2The fourth three-level topology circuit 14 includes: a thirteenth switch Q13, a fourteenth switch Q14, a fifteenth switch Q15, a sixteenth switch Q16, a seventh diode D7, and an eighth diode D8. The first terminal of the thirteenth switch Q13 is coupled to the positive terminal Bus+, and the second terminal of the thirteenth switch Q13 is coupled to the first terminal of the fourteenth switch Q14. The second terminal of the fourteenth switch Q14 is coupled to the first terminal of the fifteenth switch Q15 through the midpoint Z4 of the fourth switch bridge arm, and the second terminal of the fifteenth switch Q15 is coupled to the first terminal of the sixteenth switch Q16. The second terminal of the sixteenth switch Q16 is coupled to the negative terminal of the bus (Bus-); the positive terminal of the seventh diode D7 is coupled to the negative terminal of the eighth diode D8 through the midpoint Y4 of the fourth diode bridge arm; the negative terminal of the seventh diode D7 is coupled to the second terminal of the thirteenth switch Q13 and the first terminal of the fourteenth switch Q14; the positive terminal of the eighth diode D8 is coupled to the second terminal of the fifteenth switch Q15 and the first terminal of the sixteenth switch Q16; the fourth driver M4 is configured to drive the turn-off and turn-on of the thirteenth switch Q13, the fourteenth switch Q14, the fifteenth switch Q15, and the sixteenth switch Q16. By using the above method to form the fourth three-level topology circuit 14, the harmonic components of the output waveform of the fourth three-level topology circuit 14 can be reduced, the loss can be reduced, thereby increasing the switching frequency of the switches in the fourth three-level topology circuit 14 and reducing the system cost. Furthermore, the above method can improve the reliability of the fourth three-level topology circuit 14 and improve electromagnetic interference (EMI).

[0042] For example, refer to Figure 1 and Figure 2 The active static var generator also includes: the third live wire connection terminal UC, the third capacitor C3, the fifth inductor L5, the sixth inductor L6, and the third three-level topology module. The third live wire connection terminal UC is used to couple to the third live wire in the power grid; the first end of the third capacitor C3 is coupled to the third live wire connection terminal UC, and the second end of the third capacitor C3 is coupled to the neutral wire connection terminal N; the first end of the fifth inductor L5 and the first end of the sixth inductor L6 are both coupled to the third live wire connection terminal UC; the third three-level topology module is coupled between the positive terminal Bus+ and the negative terminal Bus- of the bus. The third three-level topology module includes a fifth three-level topology circuit 15 and a sixth three-level topology circuit 16 connected in parallel between the positive terminal Bus+ and the negative terminal Bus- of the bus. The midpoint Z5 of the fifth switching bridge arm of the fifth three-level topology circuit 15 is coupled to the second end of the fifth inductor L5, and the midpoint Z6 of the sixth switching bridge arm of the sixth three-level topology circuit 16 is coupled to the second end of the sixth inductor L6. The midpoint Y5 of the fifth diode bridge arm of the fifth three-level topology circuit 15 and the midpoint Y6 of the sixth diode bridge arm of the sixth three-level topology circuit 16 are both coupled to the neutral wire connection terminal N.

[0043] By employing the aforementioned interleaved parallel topology, the output current ripple of the fifth three-level topology circuit 15 and the sixth three-level topology circuit 16 cancel each other out. This eliminates the need for bulky filter components, suppressing grid-connected current ripple to an extremely low level, significantly reducing the burden on subsequent filters and lowering the design complexity of the filtering system. Interleaved parallel connection allows multiple switching devices, such as but not limited to power devices (e.g., IGBTs), to share the total current, reducing the current stress on individual switching devices, improving the overall efficiency of the SVG, and extending device lifespan, making it particularly suitable for medium-to-high power SVG applications. Furthermore, this approach optimizes the overall size and dynamic response, enhances high-frequency operation and ripple suppression, and significantly reduces the capacitance requirements of filter inductors, capacitors, and other components, resulting in a substantial reduction in the overall size and weight of the SVG. This allows for a reduction in the capacitance requirement of the third capacitor C3, eliminating the need for a large capacitor as the third capacitor C3 and thus reducing its size. The above method can also reduce the inductance value requirements of the fifth inductor L5 and the sixth inductor L6, so that inductors with large inductance values ​​can be used as the fifth inductor L5 and the sixth inductor L6 respectively, thereby reducing the size of the fifth inductor L5 and the sixth inductor L6.

[0044] For example, refer to Figure 2 The active static var generator further includes a third drive assembly, which comprises a fifth driver M5 and a sixth driver M6. The fifth driver M5 is configured to drive the switching transistors in the fifth three-level topology circuit 15 to turn off and on, and the sixth driver M6 is configured to drive the switching transistors in the sixth three-level topology circuit 16 to turn off and on. By employing two independent fifth drivers M5 and sixth drivers M6 to drive the switching transistors in the fifth three-level topology circuit 15 and the sixth three-level topology circuit 16 to turn off and on respectively, compared to the "conventional three-level topology" in related technologies which can only use one driver to drive the switching transistors to turn on and off, the method disclosed herein can control the switching transistors in the fifth three-level topology circuit 15 and the sixth three-level topology circuit 16 to turn off and on separately, thereby reducing the synchronization accuracy requirement. Furthermore, it allows for independent adjustment feedback loops for adjustment, achieving diversified and refined adjustment methods, thus more accurately adjusting the electrical output parameters of the load bus.

[0045] For example, refer to Figure 1 and Figure 2The fifth three-level topology circuit 15 includes: a seventeenth switch Q17, an eighteenth switch Q18, a nineteenth switch Q19, a twentieth switch Q20, a ninth diode D9, and a tenth diode D10. The first terminal of the seventeenth switch Q17 is coupled to the positive terminal Bus+, and the second terminal of the seventeenth switch Q17 is coupled to the first terminal of the eighteenth switch Q18. The second terminal of the eighteenth switch Q18 is coupled to the first terminal of the nineteenth switch Q19 through the midpoint Z5 of the fifth switch bridge arm. The second terminal of the nineteenth switch Q19 is coupled to the first terminal of the twentieth switch Q20. The second terminal of the 20th switch Q20 is coupled to the negative terminal of the bus (Bus-); the positive terminal of the 9th diode D9 is coupled to the negative terminal of the 10th diode D10 through the midpoint Y5 of the 5th diode bridge arm. The negative terminal of the 9th diode D9 is coupled to the second terminal of the 17th switch Q17 and the first terminal of the 18th switch Q18. The positive terminal of the 10th diode D10 is coupled to the second terminal of the 19th switch Q19 and the first terminal of the 20th switch Q20. The 5th driver M5 is configured to drive the 17th switch Q17, the 18th switch Q18, the 19th switch Q19, and the 20th switch Q20 to turn off and on. By using the above method to form the 5th three-level topology circuit 15, the harmonic components of the output waveform of the 5th three-level topology circuit 15 can be reduced, the loss can be reduced, thereby increasing the switching frequency of the switches in the 5th three-level topology circuit 15 and reducing the system cost. Moreover, the above method can improve the reliability of the 5th three-level topology circuit 15 and improve electromagnetic interference (EMI).

[0046] For example, refer to Figure 1 and Figure 2The sixth three-level topology circuit 16 includes: a twenty-first switch Q21, a twenty-second switch Q22, a twenty-third switch Q23, a twenty-fourth switch Q24, an eleventh diode D11, and a twelfth diode D12. The first terminal of the twenty-first switch Q21 is coupled to the positive terminal Bus+, and the second terminal of the twenty-first switch Q21 is coupled to the first terminal of the twenty-second switch Q22. The second terminal of the twenty-second switch Q22 is coupled to the first terminal of the twenty-third switch Q23 through the midpoint Z6 of the sixth switch bridge arm. The second terminal of the twenty-third switch Q23 is coupled to the first terminal of the twenty-fourth switch Q24. The second terminal of the 24th switching transistor Q24 is coupled to the negative terminal of the bus (Bus-). The positive terminal of the 11th diode D11 is coupled to the negative terminal of the 12th diode D12 through the midpoint Y6 of the 6th diode bridge arm. The negative terminal of the 11th diode D11 is coupled to the second terminal of the 21st switching transistor Q21 and the first terminal of the 22nd switching transistor Q22. The positive terminal of the 12th diode D12 is coupled to the second terminal of the 23rd switching transistor Q23 and the first terminal of the 24th switching transistor Q24. The sixth driver M6 is configured to drive the 21st switching transistor Q21, the 22nd switching transistor Q22, the 23rd switching transistor Q23, and the 24th switching transistor Q24 to turn off and on. By using the above method to form the sixth three-level topology circuit 16, the harmonic components of the output waveform of the sixth three-level topology circuit 16 can be reduced, the loss can be reduced, thereby increasing the switching frequency of the switching transistors in the sixth three-level topology circuit 16 and reducing the system cost. Moreover, the above method can improve the reliability of the sixth three-level topology circuit 16 and improve electromagnetic interference (EMI).

[0047] For example, refer to Figure 1 and Figure 2 In the first three-level topology circuit 11 to the sixth three-level topology circuit 16, the switching transistors are all high-frequency switching transistors with a switching frequency of not less than 40kHz. It should be noted that the switching frequency refers to the number of times a power electronic device (such as an IGBT) switches per second. This disclosure reduces output waveform distortion and thus significantly reduces current ripple by using a higher switching frequency. Simultaneously, the 40kHz high-frequency switching reduces device switching losses, but it also increases losses and the performance requirements of the device. Furthermore, the 40kHz high-frequency switching, combined with interleaved control, can improve the SVG's response speed to changes in reactive power in the power grid, more quickly compensate for grid fluctuations, and ensure stable power quality.

[0048] For example, refer to Figure 3The active static var generator may also include a switching power supply control circuit, which includes a digital signal control circuit (not shown in the figure) composed of a low-voltage control chip, an analog signal control circuit, and a modulator 20. The modulator 20 includes a digital signal modulation region 23, an analog signal modulation region 21, and an isolation region 22 that electrically isolates the digital signal modulation region 23 and the analog signal modulation region 21. The digital signal control circuit is coupled to the digital signal modulation region 23, and the analog signal control circuit is coupled to the analog signal modulation region 21. The analog signal control circuit includes a sampling resistor R. shunt The analog signal modulation region 21 includes a differential amplifier circuit, which has a non-inverting input pin AINP (receiving the voltage signal from the active electrode) and an inverting input pin AINN (receiving the voltage signal from the reference electrode). A sampling resistor R... shunt The first terminal is used to couple the load, and the sampling resistor R shunt The second terminal is coupled to the positive busbar Bus+ of the load-side busbar; the non-inverting input pin AINP of the differential amplifier circuit is coupled to the sampling resistor R. shunt The second terminal, the inverting input pin AINN of the differential amplifier circuit, is coupled to the sampling resistor R. shunt The first terminal is used to enable the modulator 20 to determine the value based on the differential amplified signal output by the differential amplifier circuit, using the sampling resistor R. shunt The measured sampling current value.

[0049] By employing a modulator 20 with isolation region 22, the low-voltage digital signal control circuit and the high-voltage analog signal control circuit are electrically isolated, thereby mitigating the risks to downstream low-voltage circuits and personnel safety. Furthermore, by incorporating a differential amplifier circuit in the analog signal modulation region 21, the non-inverting input pin AINP of the differential amplifier circuit is coupled to the sampling resistor R. shunt The second terminal, the inverting input pin AINN of the differential amplifier circuit, is coupled to the sampling resistor R. shunt The first terminal is used to enable the modulator 20 to determine the value based on the differential amplified signal output by the differential amplifier circuit, using the sampling resistor R. shunt The measured sampling current value can improve the accuracy of the measured sampling current, thereby solving the problems of low measurement accuracy and the risks to downstream low-voltage circuits and personnel safety.

[0050] For example, refer to Figure 3 The analog signal control circuit may include a bridge arm switch coupled between the positive terminal Bus+ and the negative terminal Bus- of the load-side bus, and the bridge arm switch includes a high-side switch Q. H and low-side switching transistor Q L high-side switch Q H The first pole is coupled to the positive pole of the bus (Bus+), and the high-side switch Q is connected to it. HThe second electrode is coupled to the low-side switch Q. L The first pole, the low-side switch Q L The second pole is coupled to the negative terminal of the bus (Bus-); sampling resistor R shunt The second terminal is coupled to the high-side switch transistor Q. H The second electrode and the low-side switch Q L The first pole. By adopting the above method, through the high-side switching transistor Q... H and low-side switching transistor Q L The power supply current and other parameters of the load can be adjusted by changing the on and off time, making it easy to adjust the power supply parameters of the load.

[0051] For example, refer to Figure 3 The analog signal control circuit may further include a first resistor R1, a second resistor R2, and a fourth capacitor C4; wherein, the first end of the first resistor R1 is coupled to the sampling resistor R. shunt The second terminal of the first resistor R1 is coupled to the non-inverting input pin AINP of the differential amplifier circuit; the first terminal of the second resistor R2 is coupled to the sampling resistor R. shunt The first terminal of the first capacitor C1 and the second terminal of the second resistor R2 are coupled to the inverting input pin AINN of the differential amplifier circuit. The first terminal of the fourth capacitor C4 is coupled to the second terminal of the first resistor R1 and the non-inverting input pin AINP of the differential amplifier circuit, and the second terminal of the fourth capacitor C4 is coupled to the second terminal of the second resistor R2 and the inverting input pin AINN of the differential amplifier circuit. By using a filter composed of the first resistor R1, the second resistor R2, and the fourth capacitor C4, the sampling signals of the non-inverting input pin AINP and the inverting input pin AINN are filtered, thereby improving the measurement accuracy of current sampling.

[0052] refer to Figure 3 The first terminal of the load is coupled to the sampling resistor R. shunt The first end of the load is coupled to the second end of the bus negative terminal Bus-, thus forming a loop.

[0053] In summary, the active static var generators provided in the above embodiments of this disclosure have the following beneficial effects compared with related technologies: The active static var generators (SVG) shown in some embodiments of this disclosure adopt 40kHz interleaved parallel technology. The core advantages are to improve ripple suppression capability, reduce the stress of main power devices and optimize the size of filter components. Specifically, they can be divided into the following three points: (1) Significantly reduce current ripple: With 40kHz high-frequency switching combined with interleaved parallel topology, the ripple of the output current of each module will cancel each other out. Without relying on large-volume filter components, the grid-connected current ripple can be suppressed to an extremely low level, greatly reducing the burden on subsequent filters and reducing the design difficulty of the filter system. (2) Reduce device losses and stress: Interleaved parallel connection allows multiple power devices (such as IGBTs) to share the total current, reducing the current stress of individual devices; at the same time, 40kHz high-frequency switching can reduce device switching losses, improve the overall efficiency of SVG, and extend the service life of devices, which is especially suitable for medium and high power SVG scenarios. (3) Optimize overall size and dynamic response: The high frequency and ripple suppression effect significantly reduce the capacity requirements of components such as filter inductors and capacitors, which can greatly reduce the overall size and weight of SVG; in addition, the 40kHz high frequency switch combined with interleaved control can improve the response speed of SVG to changes in grid reactive power, compensate grid fluctuations more quickly, and ensure stable power quality.

[0054] It should be understood that the interleaved parallel active static var generator of this disclosure may include other elements in addition to the elements shown above, and these schemes are all within the protection scope of the interleaved parallel active static var generator of this disclosure.

[0055] Example 2: This disclosure provides a chip that includes an active static var generator in an interleaved parallel configuration as shown in Embodiment 1 or Embodiment 2. This chip is, for example, a power rectifier control chip.

[0056] Example 3: This disclosure provides an electronic device that includes a chip as shown in Embodiment 2. This electronic device may be, for example, an industrial control device, a motor drive device, or an automotive electronic device.

[0057] Unless otherwise expressly indicated by the context, the singular form of words used herein and in the appended claims includes the plural form, and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the terms “comprising” and “including” shall be interpreted as including rather than exclusively. Likewise, the terms “including” and “or” shall be interpreted as including unless such interpretation is expressly prohibited herein. Where the term “example” is used herein, particularly when it follows a set of terms, “example” is merely exemplary and illustrative and should not be considered exclusive or extensive.

[0058] Further aspects and scope of adaptation become apparent from the description provided herein. It should be understood that various aspects of this disclosure may be implemented individually or in combination with one or more other aspects. It should also be understood that the descriptions and specific embodiments herein are for illustrative purposes only and are not intended to limit the scope of this disclosure.

[0059] Several embodiments of this disclosure have been described in detail above. However, it is obvious that those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of this disclosure. The scope of protection of this disclosure is defined by the appended claims. Although embodiments of this disclosure have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of this disclosure, and all such modifications and variations fall within the scope defined by the appended claims.

Claims

1. An active static var generator with an interleaved parallel configuration, characterized in that, include: The first live wire connection terminal is used to couple to the first live wire in the power grid; The load-side busbar includes the positive and negative terminals of the busbar. Neutral wire connection terminal, used to couple to the neutral wire in the power grid; A first capacitor, wherein a first end of the first capacitor is coupled to the first live wire connection terminal, and a second end of the first capacitor is coupled to the neutral wire connection terminal; A first inductor and a second inductor, wherein the first end of the first inductor and the first end of the second inductor are both coupled to the first live wire connection terminal. A first three-level topology module is coupled between the positive and negative terminals of the busbar. The first three-level topology module includes a first three-level topology circuit and a second three-level topology circuit connected in parallel between the positive and negative terminals of the busbar. The midpoint of the first switching bridge arm of the first three-level topology circuit is coupled to the second terminal of the first inductor, and the midpoint of the second switching bridge arm of the second three-level topology circuit is coupled to the second terminal of the second inductor. The midpoints of the first diode bridge arm of the first three-level topology circuit and the midpoints of the second diode bridge arm of the second three-level topology circuit are both coupled to the neutral connection terminal.

2. The active static var generator as described in claim 1, characterized in that, Also includes: A first driving component, comprising a first driver and a second driver, wherein the first driver is configured to drive the switching transistor in the first three-level topology circuit to turn off and turn on, and the second driver is configured to drive the switching transistor in the second three-level topology circuit to turn off and turn on.

3. The active static var generator as described in claim 2, characterized in that, The first three-level topology circuit includes: A first switch, a second switch, a third switch, and a fourth switch, wherein the first end of the first switch is coupled to the positive terminal of the busbar, the second end of the first switch is coupled to the first end of the second switch, the second end of the second switch is coupled to the first end of the third switch through the midpoint of the bridge arm of the first switch, the second end of the third switch is coupled to the first end of the fourth switch, and the second end of the fourth switch is coupled to the negative terminal of the busbar. A first diode and a second diode, wherein the anode of the first diode is coupled to the cathode of the second diode through the midpoint of the first diode bridge arm, the cathode of the first diode is coupled to the second terminal of the first switch and the first terminal of the second switch, and the anode of the second diode is coupled to the second terminal of the third switch and the first terminal of the fourth switch. The first driver is configured to drive the first switch, the second switch, the third switch, and the fourth switch to turn off and on.

4. The active static var generator as described in claim 2, characterized in that, The second three-level topology circuit includes: The fifth, sixth, seventh, and eighth switching transistors are provided, wherein the first end of the fifth switching transistor is coupled to the positive terminal of the busbar, the second end of the fifth switching transistor is coupled to the first end of the sixth switching transistor, the second end of the sixth switching transistor is coupled to the first end of the seventh switching transistor through the midpoint of the second switching transistor bridge arm, the second end of the seventh switching transistor is coupled to the first end of the eighth switching transistor, and the second end of the eighth switching transistor is coupled to the negative terminal of the busbar. The third diode and the fourth diode, wherein the positive terminal of the third diode is coupled to the negative terminal of the fourth diode through the midpoint of the second diode bridge arm, the negative terminal of the third diode is coupled to the second terminal of the fifth switch and the first terminal of the sixth switch, and the positive terminal of the fourth diode is coupled to the second terminal of the seventh switch and the first terminal of the eighth switch. The second driver is configured to turn the fifth, sixth, seventh, and eighth switches on and off.

5. The active static var generator as described in claim 1, characterized in that, Also includes: The second live wire connection terminal is used to couple to the second live wire in the power grid; The second capacitor has a first end coupled to the second live wire connection terminal and a second end coupled to the neutral wire connection terminal. The third inductor and the fourth inductor, the first end of the third inductor and the first end of the fourth inductor are both coupled to the second live wire connection terminal; A second three-level topology module is coupled between the positive and negative terminals of the busbar. The second three-level topology module includes a third three-level topology circuit and a fourth three-level topology circuit connected in parallel between the positive and negative terminals of the busbar. The midpoint of the third switching bridge arm of the third three-level topology circuit is coupled to the second terminal of the third inductor. The midpoint of the fourth switching bridge arm of the fourth three-level topology circuit is coupled to the second terminal of the fourth inductor. The midpoints of the third diode bridge arm of the third three-level topology circuit and the midpoints of the fourth diode bridge arm of the fourth three-level topology circuit are both coupled to the neutral connection terminal.

6. The active static var generator as described in claim 5, characterized in that, Also includes: The second driving component includes a third driver and a fourth driver, wherein the third driver is configured to drive the switching transistor in the third three-level topology circuit to turn off and on, and the fourth driver is configured to drive the switching transistor in the fourth three-level topology circuit to turn off and on.

7. The active static var generator as described in claim 5, characterized in that, Also includes: The third live wire connection terminal is used to couple to the third live wire in the power grid; A third capacitor, wherein a first end of the third capacitor is coupled to the third live wire connection terminal, and a second end of the third capacitor is coupled to the neutral wire connection terminal; The fifth inductor and the sixth inductor, the first end of the fifth inductor and the first end of the sixth inductor are both coupled to the third live wire connection terminal; A third three-level topology module is coupled between the positive and negative terminals of the busbar. The third three-level topology module includes a fifth three-level topology circuit and a sixth three-level topology circuit connected in parallel between the positive and negative terminals of the busbar. The midpoint of the fifth switching bridge arm of the fifth three-level topology circuit is coupled to the second terminal of the fifth inductor. The midpoint of the sixth switching bridge arm of the sixth three-level topology circuit is coupled to the second terminal of the sixth inductor. The midpoints of the fifth diode bridge arm of the fifth three-level topology circuit and the sixth diode bridge arm of the sixth three-level topology circuit are both coupled to the neutral connection terminal.

8. The active static var generator as described in claim 7, characterized in that, The switching transistors in the first three-level topology circuit to the sixth three-level topology circuit are all high-frequency switching transistors with a switching frequency of not less than 40kHz.

9. The active static var generator as described in claim 7, characterized in that, Also includes: A third driving component, comprising a fifth driver and a sixth driver, wherein the fifth driver is configured to drive the switching transistor in the fifth three-level topology circuit to turn off and on, and the sixth driver is configured to drive the switching transistor in the sixth three-level topology circuit to turn off and on.

10. The active static var generator as described in claim 9, characterized in that, The third three-level topology circuit includes: a ninth switch, a tenth switch, an eleventh switch, a twelfth switch, a fifth diode, and a sixth diode. The first terminal of the ninth switch is coupled to the positive terminal of the bus. The second terminal of the ninth switch is coupled to the first terminal of the tenth switch. The second terminal of the tenth switch is coupled to the first terminal of the eleventh switch through the midpoint of the third switch bridge arm. The second terminal of the eleventh switch is coupled to the first terminal of the twelfth switch. The second terminal of the twelfth switch is coupled to the negative terminal of the bus. The anode of the fifth diode is coupled to the cathode of the sixth diode through the midpoint of the third diode bridge arm. The cathode of the fifth diode is coupled to the second terminal of the ninth switch and the first terminal of the tenth switch. The anode of the sixth diode is coupled to the second terminal of the eleventh switch and the first terminal of the twelfth switch. The third driver is configured to drive the ninth, tenth, eleventh, and twelfth switches to turn off and on; and / or, The fourth three-level topology circuit includes: a thirteenth switch, a fourteenth switch, a fifteenth switch, a sixteenth switch, a seventh diode, and an eighth diode. The first terminal of the thirteenth switch is coupled to the positive terminal of the bus; the second terminal of the thirteenth switch is coupled to the first terminal of the fourteenth switch; the second terminal of the fourteenth switch is coupled to the first terminal of the fifteenth switch through the midpoint of the fourth switch bridge arm; the second terminal of the fifteenth switch is coupled to the first terminal of the sixteenth switch; and the second terminal of the sixteenth switch is coupled to the negative terminal of the bus. The anode of the seventh diode is coupled to the cathode of the eighth diode through the midpoint of the fourth diode bridge arm; the cathode of the seventh diode is coupled to the second terminal of the thirteenth switch and the first terminal of the fourteenth switch; and the anode of the eighth diode is coupled to the second terminal of the fifteenth switch and the first terminal of the sixteenth switch. The fourth driver is configured to drive the thirteenth, fourteenth, fifteenth, and sixteenth switches to turn off and on; and / or, The fifth three-level topology circuit includes: a seventeenth switch, an eighteenth switch, a nineteenth switch, a twentieth switch, a ninth diode, and a tenth diode. The first terminal of the seventeenth switch is coupled to the positive terminal of the bus; the second terminal of the seventeenth switch is coupled to the first terminal of the eighteenth switch; the second terminal of the eighteenth switch is coupled to the first terminal of the nineteenth switch through the midpoint of the fifth switch bridge arm; the second terminal of the nineteenth switch is coupled to the first terminal of the twentieth switch; and the second terminal of the twentieth switch is coupled to the negative terminal of the bus. The anode of the ninth diode is coupled to the cathode of the tenth diode through the midpoint of the fifth diode bridge arm; the cathode of the ninth diode is coupled to the second terminal of the seventeenth switch and the first terminal of the eighteenth switch; and the anode of the tenth diode is coupled to the second terminal of the nineteenth switch and the first terminal of the twentieth switch. The fifth driver is configured to drive the seventeenth switch, the eighteenth switch, the nineteenth switch, and the twentieth switch to turn off and on; and / or, The sixth three-level topology circuit includes: a twenty-first switch, a twenty-second switch, a twenty-third switch, a twenty-fourth switch, an eleventh diode, and a twelfth diode. The first terminal of the twenty-first switch is coupled to the positive terminal of the bus. The second terminal of the twenty-first switch is coupled to the first terminal of the twenty-second switch. The second terminal of the twenty-second switch is coupled to the first terminal of the twenty-third switch through the midpoint of the sixth switch bridge arm. The second terminal of the twenty-third switch is coupled to the first terminal of the twenty-fourth switch. The second terminal of the twenty-fourth switch is coupled to the negative terminal of the bus. The positive terminal of the eleventh diode is coupled to the negative terminal of the twelfth diode through the midpoint of the sixth diode bridge arm. The negative terminal of the eleventh diode is coupled to the second terminal of the twenty-first switch and the first terminal of the twenty-second switch. The positive terminal of the twelfth diode is coupled to the second terminal of the twenty-third switch and the first terminal of the twenty-fourth switch. The sixth driver is configured to drive the twenty-first, twenty-second, twenty-third, and twenty-fourth switches to turn off and on.

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