Wide-backoff load modulation balanced power amplifier based on full-automatic analog amplitude regulation and control

Abstract

The invention discloses a wide-backoff load modulation balanced power amplifier based on full-automatic analog amplitude regulation and control, which is characterized in that a full-automatic analog power division ratio regulation and control power divider in the wide-backoff load modulation balanced power amplifier based on full-automatic analog amplitude regulation and control has a first power distribution characteristic; the power division ratio of the two output ends can be automatically adjusted along with power changes, under the low power level, namely before a power amplifier rollback point, only the carrier amplifier works, at the moment, most of power is distributed to the carrier amplifier, under the high power level, namely in a power amplifier rollback area, the carrier amplifier is saturated, and the balance amplifier is not saturated, so that the balance amplifier is not saturated. At the moment, most of the power is distributed to the balance amplifier, the overdrive problem of the carrier amplifier is relieved, the overdrive problem of the carrier amplifier is relieved by reasonably regulating and controlling the power input to the two amplifiers and adopting an asymmetric drain electrode bias mode, and the rollback range of the power amplifier is widened. The method is widely applied to the technical field of wireless communication.

Description

Technical Field

[0001] This invention relates to the field of wireless communication technology, and in particular to a wide backoff load modulation balanced power amplifier based on fully automatic analog amplitude control. Background Technology

[0002] Power amplifiers are core functional components in wireless communication systems. Their main function is to amplify the input radio frequency (RF) signal using DC power, providing sufficiently high RF power for the antenna to transmit the signal. As the final stage unit circuit of the transmitter, the performance of the power amplifier plays a crucial role in the quality of the transmitted signal and greatly affects the performance of the entire communication system.

[0003] To improve spectrum utilization, complex high-order modulation techniques such as orthogonal frequency division multiplexing (OFDM) are applied to 5G communication systems, resulting in a high peak-to-average power ratio (PS-A ratio) for the modulated signal. This high P-A ratio forces the RF power amplifier to operate over a very wide output power back-off region. However, the efficiency of traditional Class A and Class AB power amplifiers drops sharply at low power, leading to low back-off efficiency. Since the power amplifier primarily operates near the back-off point, low back-off efficiency severely impacts communication quality, increases system power consumption, and causes a series of problems such as heat dissipation difficulties and soaring costs, making it difficult to meet the demands of modern wireless communication systems. Summary of the Invention

[0004] To address at least one of the aforementioned technical problems, the present invention aims to provide a wide backoff load modulation balanced power amplifier based on fully automatic analog amplitude control.

[0005] Embodiments of the present invention include a wide back-off load modulation balanced power amplifier based on fully automatic analog amplitude control, wherein the wide back-off load modulation balanced power amplifier based on fully automatic analog amplitude control comprises: A fully automatic analog power ratio control power divider 101; the fully automatic analog power ratio control power divider 101 includes a first output terminal and a second output terminal, and the fully automatic analog power ratio control power divider 101 adjusts the output power of the first output terminal and the second output terminal through a first power distribution characteristic; Carrier amplifier 102; the input terminal of the carrier amplifier 102 is connected to the first output terminal. Phase offset line 103; Balanced amplifier 104; the input terminal of the balanced amplifier 104 is connected to the second output terminal through the phase offset line 103.

[0006] Furthermore, the first power distribution characteristic includes: the power division ratio between the second output terminal and the first output terminal is positively correlated with the input power obtained by the fully automatic analog power division ratio control power divider 101; when the input power obtained by the fully automatic analog power division ratio control power divider 101 is lower than the power threshold, the power division ratio between the second output terminal and the first output terminal is negative; when the input power obtained by the fully automatic analog power division ratio control power divider 101 is higher than the power threshold, the power division ratio between the second output terminal and the first output terminal is positive.

[0007] Furthermore, the fully automatic analog power divider 101 includes a coupled-line coupler 201, a rectifier circuit 202, and a power divider with adjustable power ratio 203; One output terminal of the coupling line coupler 201 is connected to the input terminal of the power divider 203 with adjustable power ratio, and the other output terminal is connected to the RF input terminal of the rectifier circuit 202. The input terminal of the rectifier circuit 202 is connected to the coupling terminal of the coupling line coupler 201; The output terminal of the rectifier circuit 202 is connected to the DC bias terminal of the power divider 203 with adjustable power ratio; the rectifier circuit 202 is used to provide a bias voltage to the power divider 203 with adjustable power ratio, so that the power divider 203 has a second power distribution characteristic.

[0008] Furthermore, the second power distribution characteristic includes: the power division ratio between the second output terminal and the first output terminal is positively correlated with the bias voltage obtained by the power division ratio adjustable power divider 203; when the bias voltage obtained by the power division ratio adjustable power divider 203 is lower than the voltage threshold, the power division ratio between the second output terminal and the first output terminal is negative; when the bias voltage obtained by the power division ratio adjustable power divider 203 is higher than the voltage threshold, the power division ratio between the second output terminal and the first output terminal is positive.

[0009] Furthermore, the carrier amplifier 102 includes a carrier amplifier input matching network 204, a carrier amplifier gate bias stabilization network 205, a carrier amplifier chip 206, and a carrier amplifier output matching network 207. One end of the carrier amplifier gate bias stabilization network 205 is connected to a stabilizing resistor R6 and a capacitor C. 10 One end is connected to the carrier amplifier input matching network 204, and the other end is connected to the carrier amplifier output matching network 207 through the carrier amplifier chip 206.

[0010] Furthermore, the balanced amplifier 104 includes an input 3dB directional coupler 209, a first peak amplifier input matching network 210, a first peak amplifier gate bias stabilization network 211, a first peak amplifier chip 212, a first peak amplifier output matching network 213, a second peak amplifier input matching network 214, a second peak amplifier gate bias stabilization network 215, a second peak amplifier chip 216, a second peak amplifier output matching network 217, and an output 3dB directional coupler 218; The input terminal of the 3dB directional coupler 209 is connected to the phase offset line 103, and the output terminal is connected to the input terminal of the first peak amplifier input matching network 210 and the input terminal of the second peak amplifier input matching network 214, respectively. One end of the first peak amplifier gate bias stabilization network 211 is connected to a stabilizing resistor R9 and a capacitor C. 13 One end is connected to the input matching network 210 of the first peak amplifier, and the other end is connected to the output matching network 213 of the first peak amplifier through the first peak amplifier chip 212. One end of the second peak amplifier gate bias stabilization network 215 is connected to a stabilizing resistor R. 11 and capacitor C 16 One end is connected to the input matching network 214 of the second peak amplifier, and the other end is connected to the output matching network 217 of the second peak amplifier through the second peak amplifier chip 216. The 3dB output directional coupler 218 is connected to the carrier amplifier output matching network 207, the first peak amplifier output matching network 213, the second peak amplifier output matching network 217, and the load, respectively.

[0011] Furthermore, the input terminal of the coupling line coupler 201 is connected to a radio frequency source; The power divider 203 with adjustable power ratio includes a first output terminal and a second output terminal. The first output terminal is connected to the input terminal of the carrier amplifier input matching network 204, and the second output terminal is connected to the input terminal of the phase offset line 103. The output terminal of the phase offset line 103 is connected to the input terminal of the input 3dB directional coupler 209; The output of the 3dB directional coupler 209 is connected to the first peak amplifier input matching network 210 and the second peak amplifier input matching network 214, respectively.

[0012] Furthermore, the phase offset line 103 is a transmission line with a characteristic impedance of 50 Ω.

[0013] Furthermore, the wide back-off load modulation balanced power amplifier based on fully automatic analog amplitude control also includes: The dielectric substrate; the fully automatic analog power divider 101, the carrier amplifier 102, the phase offset line 103 and the balanced amplifier 104 are fixed on one side of the dielectric substrate using microstrip technology.

[0014] Furthermore, one side of the dielectric substrate is provided with a signal shielding unit 219, and the other side is provided with a metal ground. The dielectric substrate is provided with metallized vias, and the signal shielding unit 219 is connected to the metal ground through the metallized vias.

[0015] The beneficial effects of the embodiments of the present invention are as follows: The fully automatic analog amplitude control-based wide back-off load modulation balanced power amplifier in the embodiments has a first power distribution characteristic in its fully automatic analog power ratio control power divider 101, which can automatically adjust the power ratio of the two output terminals according to the power change. At the low power level, that is, before the power amplifier back-off point, only the carrier amplifier 102 is working. At this time, most of the power is distributed to the carrier amplifier 102. At the high power level, that is, in the power amplifier back-off region, the carrier amplifier 102 has reached saturation while the balanced amplifier 104 has not yet saturated. At this time, most of the power is distributed to the balanced amplifier 104 through the phase offset line 103, which greatly alleviates the overdrive problem of the carrier amplifier 102. By reasonably controlling the power input to the two amplifiers and adopting an asymmetric drain bias method, the overdrive problem of the carrier amplifier 102 is alleviated and the back-off range is widened. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the load modulation balanced power amplifier in the embodiment; Figure 2 The circuit layout diagram of the load-modulated balanced power amplifier in the embodiment is shown. Figure 3 The figure shows the simulation results of the power division ratio of the fully automatic analog power division ratio control power divider in the embodiment changing with the output power of the load-modulated balanced power amplifier; Figure 4 The figure shows the simulation results of the carrier amplifier gain changing with the output power of the load-modulated balanced power amplifier in the embodiment. Figure 5 The figure shows the simulation results of the drain efficiency and gain of the load-modulated balanced power amplifier as a function of output power in the embodiment. Figure 6 The figure shows the measured results of the drain efficiency and gain of the load-modulated balanced power amplifier as a function of output power in the example. Detailed Implementation

[0017] To broaden the output power back-off range of power amplifiers, power supply modulation and load modulation techniques can be considered. Compared to the complex power supply modulation technique, load modulation is simpler to implement and offers superior overall performance. Among load modulation techniques, load-modulated balanced power amplifiers offer a wider load modulation range than Doherty power amplifiers. Furthermore, by directly utilizing a 3 dB directional coupler for load modulation, they more easily achieve a wide back-off range and large bandwidth, perfectly meeting the needs of current wireless communication systems.

[0018] In load-modulated balanced power amplifiers, time-sequential load-modulated balanced power amplifiers (TMPs) exhibit excellent performance characteristics, including simple structure, wide back-off range, and high back-off efficiency. However, TMPs suffer from severe carrier amplifier overdrive, leading to potential reliability issues. Current research on mitigating this problem primarily focuses on improving the load modulation method, without considering amplitude control. Furthermore, current research on amplitude control mainly employs automatic control by microcontrollers and manual control of the bias voltage. The former requires additional computer algorithms, resulting in high complexity and cost, while the latter necessitates manual adjustment, significantly limiting its application in practical communication systems.

[0019] I. Circuit Structure Based on the above principles, this embodiment provides a wide back-off load modulation balanced power amplifier based on fully automatic analog amplitude control. The structure of the wide back-off load modulation balanced power amplifier based on fully automatic analog amplitude control is as follows: Figure 1 As shown.

[0020] Reference Figure 1 The wide back-off load modulation balanced power amplifier based on fully automatic analog amplitude control includes a fully automatic analog power divider 101, a carrier amplifier 102, a phase offset line 103, and a balanced amplifier 104. A dielectric substrate made of Rogers RO4003C material with a dielectric constant of 3.38 and a thickness of 0.813 mm can be used. The components, including the fully automatic analog power divider 101, carrier amplifier 102, phase offset line 103, and balanced amplifier 104, are fabricated on one side of the dielectric substrate using microstrip line technology. In this embodiment, the circuit layout of the fabricated wide back-off load modulation balanced power amplifier based on fully automatic analog amplitude control is shown below. Figure 2 As shown.

[0021] Reference Figure 1 and Figure 2The fully automatic analog power divider 101 includes internal components such as a coupled-line coupler 201, a rectifier circuit 202, and a power divider with adjustable power ratio 203. The input of the fully automatic analog power divider 101 is connected to an RF source, and one end of its output port is connected to a carrier amplifier 102, while the other end is connected to a balanced amplifier 104 via a phase offset line 103. The output of the carrier amplifier 102 is connected to the output 3dB directional coupler 218 of the balanced amplifier 104. The output 3dB directional coupler 218 also serves as the output port of the entire wide back-off load modulation balanced power amplifier based on fully automatic analog amplitude control (i.e.,...). Figure 1 (The port that connects to the load).

[0022] Reference Figure 1 and Figure 2 The carrier amplifier 102 includes internal components connected in sequence, such as a carrier amplifier input matching network 204, a carrier amplifier gate bias stabilization network 205, a carrier amplifier chip 206, and a carrier amplifier output matching network 207. The carrier amplifier output matching network 207 is used to meet the impedance matching requirements of the carrier amplifier chip 206 at the saturation point. The input terminal of the carrier amplifier input matching network 204 serves as the input terminal of the carrier amplifier 102, and the output terminal of the carrier amplifier output matching network 207 serves as the output terminal of the carrier amplifier 102.

[0023] Reference Figure 1 and Figure 2 The balanced amplifier 104 includes an input 3 dB directional coupler 209, a peak amplifier, and an output 3 dB directional coupler 218 connected in sequence. The input terminal of the input 3 dB directional coupler 209 serves as the input terminal of the balanced amplifier 104, and the output terminal of the output 3 dB directional coupler 218 serves as the output terminal of the balanced amplifier 104.

[0024] Among them, reference Figure 1 The peak amplifier comprises two identical parallel branches: a first peak amplifier and a second peak amplifier. The first peak amplifier includes, in sequence, a first peak amplifier input matching network 210, a first peak amplifier gate bias stabilization network 211, a first peak amplifier chip 212, and a first peak amplifier output matching network 213. The first peak amplifier output matching network 213 is used to meet the impedance matching requirements of the first peak amplifier chip 212 at the saturation point. Similarly, the second peak amplifier includes, in sequence, a second peak amplifier input matching network 214, a second peak amplifier gate bias stabilization network 215, a second peak amplifier chip 216, and a second peak amplifier output matching network 217. The second peak amplifier output matching network 217 is used to meet the impedance matching requirements of the second peak amplifier chip 216 at the saturation point.

[0025] In this embodiment, the load-modulated balanced power amplifier adopts an asymmetric drain bias method, that is, reducing the drain bias voltage of the carrier amplifier 102, thereby increasing the saturation power ratio of the balanced amplifier 104 and the carrier amplifier 102, and thus widening the output power back-off range of the load-modulated balanced power amplifier.

[0026] In this embodiment, a load-modulated balanced power amplifier circuit can be manufactured using microstrip technology. Microstrip circuit units are fabricated on one side of the dielectric substrate, i.e., the first surface. These microstrip circuit units refer to a fully automatic analog power divider 101, a carrier amplifier 102, a phase offset line 103, and a balanced amplifier 104, all manufactured using microstrip technology. A metal ground layer is provided on the other side of the dielectric substrate, i.e., the second surface. The ground terminals of the fully automatic analog power divider 101, the carrier amplifier 102, and the balanced amplifier 104 are connected to the metal ground layer through metallized vias passing through the dielectric substrate. The dielectric substrate is mounted on an aluminum profile heat sink with screws, and the second surface of the dielectric substrate faces the aluminum profile heat sink. In this embodiment, the dielectric substrate used is Rogers RO4003C material with a dielectric constant of 3.38 and a thickness of 0.813 mm. The microstrip circuit units and the metal ground layer both use 0.035 mm thick copper foil.

[0027] In this embodiment, the structural layout of the wide back-off load modulation balanced power amplifier based on fully automatic analog amplitude control is as follows: Figure 2 As shown. Figure 2 and Figure 1 It corresponds. Figure 2 Equivalent to having Figure 1 The physical circuit topology shown. Figure 2 In the middle, the gray part represents the copper-clad or microstrip circuit structure, which includes components such as the fully automatic analog power divider 101, carrier amplifier 102, phase offset line 103 and balanced amplifier 104, which are manufactured by microstrip technology.

[0028] The circuit structures corresponding to each part are indicated by dashed boxes. Specifically, 201 represents the coupling line coupler, 202 represents the rectifier circuit, 203 represents the power divider with adjustable power ratio, 204 represents the carrier amplifier input matching network, 205 represents the carrier amplifier gate bias stabilization network, 206 represents the carrier amplifier chip, 207 represents the carrier amplifier output matching network, and 208 represents the phase offset line (corresponding to...). Figure 1In the diagram, phase offset lines 103 and 209 represent the input 3 dB directional coupler, 210 represents the first peak amplifier input matching network, 211 represents the first peak amplifier gate bias stabilization network, 212 represents the first peak amplifier chip, 213 represents the first peak amplifier output matching network, 214 represents the second peak amplifier input matching network, 215 represents the second peak amplifier gate bias stabilization network, 216 represents the second peak amplifier chip, 217 represents the second peak amplifier output matching network, and 218 represents the output 3 dB directional coupler. 201, 202, and 203 are three components of the fully automatic analog power ratio control power divider 101, 204, 205, 206, and 207 are four components of the carrier amplifier 102, and 209 to 218 are ten components of the balanced amplifier 104. One output terminal of the fully automatic analog power ratio control power divider 101 is connected to the input terminal of the carrier amplifier 102, and the other output terminal is connected to the input terminal of the balanced amplifier 104 via phase offset line 103. In addition, the signal shielding unit 219 is a copper pour around the periphery of other microstrip circuits and is connected to the metal ground plane through metallized vias. The signal shielding unit can improve signal shielding performance and thermal conductivity.

[0029] In this embodiment, as Figure 2 As shown, the coupled-line coupler 201 includes a microstrip coupled line and a DC blocking capacitor. C 1 and isolation resistor R 1. Coupled-line coupler via DC blocking capacitor C 1. Connect to the RF input terminal.

[0030] In this embodiment, as Figure 2 As shown, the rectifier circuit 202 includes multiple matching microstrip lines, two fan-shaped stubs, a Schottky diode D, and a DC blocking capacitor. C 3 and load resistor R 13 The rectifier circuit 202 uses a DC blocking capacitor. C 3. Coupler 203 is connected to the coupling line.

[0031] In this embodiment, as Figure 2 As shown, the power divider 203 with adjustable power ratio includes an equal-division Wilkinson power divider, three 3 dB directional couplers, multiple microstrip lines, and four sets of varactor diodes. C p1 arrive C p4 Fixed capacitors C 5 and C 6. DC blocking capacitor C 2. C 7 and C 8. Isolation resistor R 5. Bias resistorR 3. R 4. The adjustable power divider 203 uses a DC blocking capacitor. C 2. Connected to the coupling line coupler, the rectifier circuit 202 is connected through a bias resistor. R 3 and R 4 is a varactor diode. C p1 arrive C p4 It provides bias voltage while avoiding high-frequency leakage. The power divider 203 with adjustable power ratio forms a first output terminal and a second output terminal. The first output terminal of the power divider 203 also serves as the first output terminal of the fully automatic analog power divider 101, and the second output terminal of the power divider 203 also serves as the second output terminal of the fully automatic analog power divider 101.

[0032] By changing the bias voltage, the power divider 203 with adjustable power ratio can exhibit a specific power ratio characteristic, namely the second power distribution characteristic.

[0033] In this embodiment, as Figure 2 As shown, the carrier amplifier input matching network 204 includes multiple microstrip transmission lines for achieving matching, through a stabilizing capacitor. C 10 It is connected to the carrier amplifier gate bias stabilization network 205. The gate bias portion of the carrier amplifier gate bias stabilization network 205 includes a quarter-wavelength microstrip transmission line to prevent RF leakage, multiple filter capacitors for power supply filtering and RF grounding, and power line pads. The stabilization network portion consists of stabilizing resistors. R 6. Stabilizing capacitor C 10 The carrier amplifier chip 206 is composed of a carrier amplifier chip gate pad. The carrier amplifier chip 206 connects the carrier amplifier gate bias stabilization network 205 to the carrier amplifier output matching network 207. The carrier amplifier output matching network 207 includes multiple microstrip transmission lines and drain bias circuits for matching. The drain bias section includes a quarter-wavelength microstrip transmission line to prevent RF leakage, multiple filter capacitors and power line pads for power filtering and RF grounding, and a DC blocking capacitor. C 11 Connect the carrier amplifier output matching network 207 to the output 3 dB directional coupler 218.

[0034] In this embodiment, as Figure 2 As shown, the phase offset line 208 includes a transmission line with a characteristic impedance of 50 Ω, the length of which meets the output phase requirements of the two amplifiers.

[0035] In this embodiment, as Figure 2As shown, the balanced amplifier includes an input 3 dB directional coupler 209, a peak amplifier, and an output 3 dB directional coupler 218. The peak amplifier comprises two identical parallel branches: a first peak amplifier and a second peak amplifier.

[0036] The first peak amplifier input matching network 210 includes multiple microstrip transmission lines for matching, via stabilizing capacitors. C 13 It is connected to the first peak amplifier gate bias stabilization network 211. The gate bias portion of the first peak amplifier gate bias stabilization network 211 includes a quarter-wavelength microstrip transmission line to prevent RF leakage, multiple filter capacitors for power supply filtering and RF grounding, and power line pads. The stabilization network portion consists of stabilizing resistors. R 9. Stabilizing capacitor C 13 The first peak amplifier chip 212 is composed of a gate pad and a first peak amplifier chip. The first peak amplifier chip 212 connects the first peak amplifier gate bias stabilization network 211 to the first peak amplifier output matching network 213. The first peak amplifier output matching network 213 includes multiple microstrip transmission lines and drain bias circuits for matching. The drain bias section includes a quarter-wavelength microstrip transmission line to prevent RF leakage, multiple filter capacitors and power line pads for power filtering and RF grounding, and a DC blocking capacitor. C 14 Connect the first peak amplifier output matching network 213 to the output 3 dB directional coupler 218.

[0037] Similarly, the second peak amplifier input matching network 214 includes multiple microstrip transmission lines for achieving matching, via a stabilizing capacitor. C 16 It is connected to the second peak amplifier gate bias stabilization network 215. The gate bias portion of the second peak amplifier gate bias stabilization network 215 includes a quarter-wavelength microstrip transmission line to prevent RF leakage, multiple filter capacitors for power supply filtering and RF grounding, and power line pads. The stabilization network portion consists of stabilizing resistors. R 11 Stabilizing capacitor C 16 The second peak amplifier chip 216 is composed of a gate pad and a second peak amplifier chip. The second peak amplifier chip 216 connects the second peak amplifier gate bias stabilization network 215 to the second peak amplifier output matching network 217. The second peak amplifier output matching network 217 includes multiple microstrip transmission lines and drain bias circuits for matching. The drain bias section includes a quarter-wavelength microstrip transmission line to prevent RF leakage, multiple filter capacitors for power supply filtering and RF grounding, power line pads, and DC blocking capacitors.C 17 Connect the second peak amplifier output matching network 217 to the output 3dB directional coupler 218.

[0038] In this embodiment, as Figure 2 As shown, the diode in the rectifier circuit 202 can be a Schottky diode, and more specifically, a Schottky diode of model HSMS-2822.

[0039] In this embodiment, as Figure 2 As shown, the four sets of varactor diodes in the power divider 203 with adjustable power ratio C p1 , C p2 , C p3 and C p4 It can be achieved by using three SMV2019 varactor diodes connected in parallel. The reverse bias voltage range of a single varactor diode is 0 V to 20 V, and the corresponding adjustable capacitance value is approximately 0.3 pF to 2.22 pF.

[0040] In this embodiment, the adjustable capacitance range of the varactor diode decreases under high power conditions, while the power divider 203 corresponds to the low power state in both simulation and measured S-parameters. Therefore, to ensure that the power division ratio corresponding to the saturation of the load-modulated balanced power amplifier is approximately consistent with that of the power divider 203 in both simulation and measured S-parameters, the load-modulated balanced power amplifier has a fixed capacitance. C 5 and C The capacitance value of 6 should be slightly larger than that of the adjustable power divider 203 when simulating and measuring the S-parameters separately. C 5 and C The capacitance value is 6.

[0041] In this embodiment, as Figure 2 As shown, the carrier amplifier chip 206 can be a CREE CGH40006P chip, and the first peak amplifier chip 212 and the second peak amplifier chip 216 can both be CREE CG2H40010F chips. The drain bias voltage of the carrier amplifier is 16 V, and the gate bias voltage is... 2.77V, resulting in a quiescent current of 99 mA for carrier amplifier chip 206; the drain bias voltage of both the first peak amplifier chip 212 and the second peak amplifier chip 216 is 28V, and the gate bias voltage is... 5V, which enables both the first peak amplifier chip 212 and the second peak amplifier chip 216 to operate in Class C mode.

[0042] In this embodiment, the dielectric substrate can be fixed to the metal heat sink with M3 screws, and the first peak amplifier chip 212 and the second peak amplifier chip 216 can be fixed to the metal heat sink with M2 screws.

[0043] II. Working Principle In this embodiment, due to the varactor diode in the power divider 203 with adjustable power ratio... C p1 - C p4 The bias voltage is provided by the rectifier circuit 202. The rectifier circuit 202 can adjust the bias voltage of the varactor diode, so that the power divider 203 with adjustable power ratio exhibits specific power distribution characteristics. Specifically, in this embodiment, the adjustable power divider 203 exhibits a second power distribution characteristic, which means that the adjustable power divider 203 is affected by the bias voltage provided by the rectifier circuit 202. The second power distribution characteristic includes: the power division ratio between the second output terminal and the first output terminal is positively correlated with the bias voltage obtained by the adjustable power divider 203. That is, the larger the bias voltage, the larger the power division ratio between the second output terminal and the first output terminal. For example, when the bias voltage obtained by the adjustable power divider 203 is small (below the voltage threshold), the power division ratio between the second output terminal and the first output terminal is negative. When the bias voltage obtained by the adjustable power divider 203 is large (above the voltage threshold), the power division ratio between the second output terminal and the first output terminal is positive. Here, the power division ratio between the second output terminal and the first output terminal refers to the ratio of the output power of the second output terminal to the output power of the first output terminal.

[0044] Because the power divider 203 with adjustable power ratio has a second power distribution characteristic, under low bias voltage, the total capacitance of the varactor diodes is greater than the fixed capacitance, and the power division ratio is negative, meaning that most of the power is distributed to the carrier amplifier 102; under high bias voltage, the total capacitance of the varactor diodes is less than the fixed capacitance, and the power division ratio is positive, meaning that most of the power is distributed to the balanced amplifier 104 via the phase offset line 103.

[0045] In this embodiment, refer to Figure 1The power ratio adjustable power divider 203 is an internal component of the fully automatic analog power ratio control power divider 101. Because the power ratio adjustable power divider 203 has the aforementioned second power distribution characteristics, the fully automatic analog power ratio control power divider 101 exhibits the first power distribution characteristics corresponding to the second power distribution characteristics. In this embodiment, the first power distribution characteristic includes: the power division ratio between the second output terminal and the first output terminal is positively correlated with the input power obtained by the fully automatic analog power division ratio control power divider 101. That is, the greater the input power of the RF source, the greater the power division ratio between the second output terminal and the first output terminal. For example, when the input power obtained by the fully automatic analog power division ratio control power divider 101 is low (below the power threshold), the output bias voltage of the rectifier circuit 202 will be small, resulting in a negative power division ratio between the second output terminal and the first output terminal. When the input power obtained by the fully automatic analog power division ratio control power divider 101 is high (above the power threshold), the output bias voltage of the rectifier circuit 202 will be large, resulting in a positive power division ratio between the second output terminal and the first output terminal.

[0046] Because the fully automatic analog power divider 101 has a first power distribution characteristic, at low input power levels, the output bias voltage of the rectifier circuit 202 is small, and the power division ratio is negative, meaning that most of the power is distributed to the carrier amplifier 102; at high input power levels, the output bias voltage of the rectifier circuit 202 is large, and the power division ratio is positive, meaning that most of the power is distributed to the balanced amplifier 104 via the phase offset line 103.

[0047] In this embodiment, the fully automatic analog power divider 101 with first power distribution characteristics can automatically adjust the power distribution of the two sub-amplifiers according to the input power level. By using the fully automatic analog power divider 101 with first power distribution characteristics, the wide backoff load modulation balanced power amplifier based on fully automatic analog amplitude control achieves the following: before the backoff point, only the carrier amplifier 103 is working, and most of the input power is distributed to the carrier amplifier 103; in the backoff region, the carrier amplifier 103 has reached saturation, while the balanced amplifier 104 is not yet saturated, and at this time, most of the power is distributed to the balanced amplifier 104 through the phase offset line 103. Through the above power divider control method, the input power can be more rationally distributed according to the different operating states of the two sub-amplifiers, greatly alleviating the inherent overdrive problem of the carrier amplifier 103 while maintaining wide backoff, thereby improving the reliability of the load modulation balanced power amplifier.

[0048] In this embodiment, the carrier amplifier 102 can be configured to operate in Class AB mode, and the balanced amplifier 104 can be configured to operate in Class C mode. Before the back-off point, only the carrier amplifier 102 is turned on. When the back-off point is reached, the carrier amplifier 102 reaches saturation. In the back-off region, the balanced amplifier 104 gradually turns on and load modulation is achieved through the output 3 dB directional coupler 218, which can obtain a high back-off efficiency.

[0049] Based on the above working principle, the overall working principle of the wide back-off load modulation balanced power amplifier based on fully automatic analog amplitude control is as follows: the coupling line coupler 201 allocates a very small portion of the RF energy to the rectifier circuit 202. The output of the rectifier circuit 202 provides a bias voltage to the varactor diode in the power divider 203, thereby achieving fully automatic analog amplitude control. In the low-power state, i.e., when only the carrier amplifier 102 is operating, the output voltage of the rectifier circuit 202 is relatively small, and the power divider 203 allocates most of the power to the carrier amplifier 102. In the high-power state, i.e., when the carrier amplifier 102 is overdriven, the output voltage of the rectifier circuit 202 is relatively large, and the power divider 203 allocates most of the power to the balanced amplifier 104, greatly alleviating the overdrive problem of the carrier amplifier 102. Simultaneously, by reducing the drain bias of the carrier amplifier 102, the back-off range of the load modulation balanced power amplifier is widened.

[0050] III. Simulation and Actual Measurement In this embodiment, as Figure 2 As shown, the values ​​of each discrete component in a microstrip circuit can be: C 1= C 2= C 7= C 8= C 9= C 11 = C 12 = C 14 = C 15 = C 17 =39pF, C 3= C 4 = 27 pF C 5= C 6 = 1.3 pF C 10 =2pF, C 13 = C 16 =2.4pF, R 1= R 8 = 50Ω R2 = 0Ω R 3= R 4 = 120000Ω R 5 = 100Ω R 6= R 9= R 11 =75Ω, R 7= R 10 = R 12 =75Ω, R 13 =1300Ω.

[0051] In this embodiment, as Figure 2 As shown, the values ​​of each parameter in a microstrip circuit can be: L 1 = 10mm L 2 = 19.4 mm L 3=66mm, L 4 = 39.9 mm, L 5 = 9.9mm, L 6 = 66mm L 7 = 21.8mm, L 8 = 13.5mm L 9 = 2.4mm L 10 =20mm, L 11 =3.3mm, L 12 =12.8mm, L 13 =7.9mm, L 14 =1mm, L 15 =1.6mm, L 16 =8.2mm, L 17 =4.8mm, L 18 =8mm, L 19 =1.6mm, L 20 =18.9mm, L 21 =6mm, L 22 =10mm, L 23 =5.9mm, L 24 =7.9mm, L 25=7.9mm, L 26 =1.3mm, L 27 =1.4mm, L 28 =3.4mm, L 29 =3.4mm, L 30 =1.4mm, L 31 =1.3mm, L 32 =5.6mm, L 33 =5.6mm, L 34 =2mm, L 35 =14.8mm, L 36 =14.8mm, L 37 =40.2mm, L 38 =21mm, L 39 =17.7mm, L 40 =17.7mm, L 41 =21mm, L 42 =18.4mm, L 43 =40.2mm, L 44 =21mm, L 45 =17.7mm, L 46 =17.7mm, L 47 =21mm, L 48 =6.3mm, L 49 =1.3mm, L 50 =1.8mm, L 51 =6.3mm, L 52 =1.3mm, L 53 =1.8mm, L 54 =6.9mm, L 55 =6.9mm,L 56 =17.7mm, L 57 =21mm, L 58 =21mm, L 59 =17.7mm, L 60 =3mm, L 61 =3mm, L 62 =54.6mm, L 63 =3.4mm, L 64 =0.4mm, L 65 =9.2mm, L 66 =3.4mm, L 67 =4mm, L 68 =5mm, L 69 =17.3mm, L 70 =3mm, L 71 =17.3mm, L 72 =3.1mm, L 73 =2.7mm, L 74 =6.7mm, L 75 =1.8mm, L 76 =7.8mm, L 77 =61.8mm, L 78 =124.6mm, L 79 =6mm, L 80 =17.3mm, L 81 =21.8mm, L 82 =21.8mm, L 83 =17.3mm, L 84 =17.8mm, L 85 =17.8mm, L86 =2mm, L 87 =1.2mm, L 88 =4.5mm, L 89 =1.4mm, L 90 =1.3mm, L 91 =5mm, L 92 =17.3mm, L 93 =3mm, L 94 =17.3mm, L 95 =1.2mm, L 96 =1.9mm, L 97 =8.4mm, L 98 =10.5mm, L 99 =2mm, L 100 =1.2mm, L 101 =4.5mm, L 102 =1.4mm, L 103 =1.3mm, L 104 =5mm, L 105 =17.3mm, L 106 =3mm, L 107 =17.3mm, L 108 =1.2mm, L 109 =1.9mm, L 110 =8.4mm, L 111 =10.5mm, L 112 =17.8mm, L 113 =17.8mm, L 114 =17.3mm, L 115 =21.8mm, L 116=17.3mm, L 117 =21.8mm, L 118 =16mm, W 1=1.8mm, W 2=1.8mm, W 3=1.8mm, W 4=1.8mm, W 5=1.8mm, W 6=1.8mm, W 7=1.8mm, W 8=2mm, W 9=5.1mm, W 10 =2.8mm, W 11 =3.7mm, W 12 =2.1mm, W 13 =1mm, W 14 =1.2mm, W 15 =1.2mm, W 16 =2.2mm, W 17 =2.2mm, W 18 =2.2mm, W 19 =1.2mm, W 20 =0.1mm, W 21 =1.8mm, W 22 =1.2mm, W 23 =1.2mm, W 24 =1.2mm, W 25 =1.2mm, W 26 =2.7mm, W 27 =2.7mm, W 28 =2.7mm, W 29 =2.7mm, W 30 =2.7mm, W 31 =2.7mm, W32 =0.1mm, W 33 =0.1mm, W 34 =1.8mm, W 35 =0.9mm, W 36 =0.9mm, W 37 =1.8mm, W 38 =1.9mm, W 39 =3mm, W 40 =3mm, W 41 =1.9mm, W 42 =0.1mm, W 43 =1.8mm, W 44 =1.9mm, W 45 =3mm, W 46 =3mm, W 47 =1.9mm, W 48 =0.1mm, W 49 =1.2mm, W 50 =1.2mm, W 51 =0.1mm, W 52 =1.2mm, W 53 =1.2mm, W 54 =1.8mm, W 55 =1.8mm, W 56 =3mm, W 57 =1.9mm, W 58 =1.9mm, W 59 =3mm, W 60 =1.8mm, W 61 =1.8mm, W 62 =1.8mm,W 63 =3.3mm, W 64 =24.3mm, W 65 =3.3mm, W 66 =19.1mm, W 67 =3.2mm, W 68 =9mm, W 69 =1mm, W 70 =3mm, W 71 =1mm, W 72 =3.1mm, W 73 =14.5mm, W 74 =3.1mm, W 75 =9.1mm, W 76 =3.1mm, W 77 =1.8mm, W 78 =1.8mm, W 79 =1.8mm, W 80 =3mm, W 81 =1.8mm, W 82 =1.8mm, W 83 =3mm, W 84 =1.8mm, W 85 =1.8mm, W 86 =1.4mm, W 87 =22.4mm, W 88 =1.4mm, W 89 =29.2mm, W 90 =1.5mm, W 91 =9mm, W 92 =1mm, W 93=3mm, W 94 =1mm, W 95 =2.8mm, W 96 =4.2mm, W 97 =2.8mm, W 98 =1.3mm, W 99 =1.4mm, W 100 =22.4mm, W 101 =1.4mm, W 102 =29.2mm, W 103 =1.5mm, W 104 =9mm, W 105 =1mm, W 106 =3mm, W 107 =1mm, W 108 =2.8mm, W 109 =4.2mm, W 110 =2.8mm, W 111 =1.3mm, W 112 =1.8mm, W 113 =1.8mm, W 114 =3mm, W 115 =1.8mm, W 116 =3mm, W 117 =1.8mm, W 118 =1.8mm, S =1mm, r 1 = 15.9 mm r 2 = 5.4 mm θ 1 = 100° θ 2 = 130°.

[0052] In this embodiment, as Figure 2 As shown, the values ​​of each bias voltage in the microstrip circuit can be: V 1= 2.77V, V 3= V 5= 5V V 2 = 16V, V 4= V 6 = 28V.

[0053] Based on the above conditions, the load-modulated balanced power amplifier in this embodiment was simulated and measured, and the results are as follows. Figure 3 – Figure 6 As shown.

[0054] Figure 3 This is a simulation result diagram showing the power division ratio of the fully automatic analog power division ratio control power divider 101 in this embodiment as a function of the load-modulated balanced power amplifier output power. (Refer to...) Figure 3 Within the target frequency band of 2.4–2.8 GHz, the power division ratio of the fully automatic analog power divider 101 increases with the increase of output power, changing from a negative value to a positive value. That is, from distributing most of the power to the carrier amplifier 102, most of the power is distributed to the balanced amplifier 104 via the phase offset line 103. (Refer to...) Figure 3 Within the target frequency band, the fully automatic analog power ratio control power divider 101 has a power ratio of 6.3–9.6 dB at the saturation point of the load-modulated balanced power amplifier. Compared with the Wilkinson power divider with a power ratio of 0 in the traditional structure, the fully automatic analog power ratio control power divider 101 can significantly reduce the power input to the carrier amplifier 102 at the saturation point, thereby greatly alleviating the overdrive problem and improving reliability while maintaining a wide back-off.

[0055] Figure 4 This is a simulation result diagram showing the change in gain of carrier amplifier 102 with load modulation balanced power amplifier output power in this embodiment. (Refer to...) Figure 4 Within the target frequency band of 2.4–2.8 GHz, the gain of the carrier amplifier 102 at the saturation point of the load-modulated balanced power amplifier is 6.6–11 dB, while the gain of the carrier amplifier 102 at the saturation point of the power amplifier is 1.3–2.7 dB when the power division ratio is fixed. That is, after amplitude regulation, the gain compression phenomenon of the carrier power amplifier 102 at the saturation point of the load-modulated balanced power amplifier is greatly alleviated, which greatly alleviates its inherent overdrive problem and improves reliability.

[0056] Figure 5 This is a simulation result graph showing the changes in drain efficiency and gain of the load-modulated balanced power amplifier as a function of output power in this embodiment. (Refer to...) Figure 5The load-modulated balanced power amplifier operates in the 2.4–2.8 GHz band, with a saturation power of 44.6–45.6 dBm, a saturation efficiency of 64.5%–72.4%, an output power back-off range of 12 dB, and a back-off efficiency of 39.6%–50.3%. While significantly mitigating the overdrive problem of the carrier amplifier 102, the load-modulated balanced power amplifier still maintains a wide output power back-off range and high efficiency.

[0057] Figure 6 This is a graph showing the measured results of the drain efficiency and gain of the load-modulated balanced power amplifier as a function of output power in this embodiment. (Refer to...) Figure 6 The load-modulated balanced power amplifier operates in the 2.4–2.8 GHz band, with a saturation power of 44.1–44.9 dBm and a saturation efficiency of 66.1%–75.2%. The output power back-off range is 12 dB, with a back-off efficiency of 40%–49%, which is in good agreement with the simulation results. Even with the overdrive problem of carrier amplifier 102 significantly mitigated and reliability improved, the load-modulated balanced power amplifier still maintains superior overall performance.

[0058] pass Figure 3 – Figure 6 The simulation and experimental results show that the load-modulated balanced power amplifier in this embodiment allocates a small portion of the RF energy to the rectifier circuit via a coupling line connector connected to the input terminal. This provides a bias voltage to the varactor diode of the adjustable power divider. The bias voltage increases with increasing power, and the power division ratio of the adjustable power divider also increases accordingly, thus achieving fully automatic analog amplitude control and greatly alleviating the inherent overdrive problem of timing-based load-modulated balanced power amplifiers. Simultaneously, by using asymmetric drain bias, i.e., reducing the drain bias voltage of the carrier amplifier, the output power back-off range is widened. The load-modulated balanced power amplifier in this embodiment features overdrive mitigation, a large back-off range, and high efficiency, and has a simple structure and repeatability. Therefore, the load-modulated balanced power amplifier in this embodiment can automatically adjust the power division ratio according to the input power, making the input power more rationally distributed to the two sub-amplifiers, significantly alleviating the overdrive problem of the carrier amplifier, improving reliability, while maintaining a wide back-off range and high operating efficiency.

[0059] It should be noted that, unless otherwise specified, when a feature is referred to as "fixed" or "connected" to another feature, it can be directly fixed or connected to the other feature, or indirectly fixed or connected to the other feature. Furthermore, the descriptions of "upper," "lower," "left," and "right" used in this disclosure are only relative to the relative positional relationships of the components of this disclosure in the accompanying drawings. The singular forms "a" and "the" used in this disclosure are also intended to include the plural forms, unless the context clearly indicates otherwise. Moreover, unless otherwise defined, all technical and scientific terms used in this embodiment have the same meaning as commonly understood by one of ordinary skill in the art. The terminology used in this embodiment specification is only for describing specific embodiments and is not intended to limit the embodiments of the invention. The term "and / or" as used in this embodiment includes any combination of one or more of the associated listed items.

[0060] It should be understood that although the terms first, second, third, etc., may be used to describe various elements in this disclosure, these elements should not be limited to these terms. These terms are only used to distinguish elements of the same type from each other. For example, a first element may also be referred to as a second element without departing from the scope of this disclosure, and similarly, a second element may also be referred to as a first element. The use of any and all instances or exemplary language (“e.g.,” “such as,” etc.) provided in this embodiment is intended only to better illustrate embodiments of the invention and, unless otherwise required, does not impose a limitation on the scope of embodiments of the invention.

[0061] It should be recognized that embodiments of the present invention can be implemented or carried out by computer hardware, a combination of hardware and software, or by computer instructions stored in a non-transitory computer-readable storage medium. The method can be implemented using standard programming techniques—including a non-transitory computer-readable storage medium configured with a computer program, wherein such a storage medium causes the computer to operate in a specific and predefined manner—according to the methods and drawings described in the specific embodiments. Each program can be implemented in a high-level procedural or object-oriented programming language to communicate with the computer system. However, if desired, the program can be implemented in assembly or machine language. In any case, the language can be a compiled or interpreted language. Furthermore, for this purpose, the program can run on a programmed application-specific integrated circuit (ASIC).

[0062] Furthermore, the procedures described in this embodiment can be performed in any suitable order unless otherwise indicated by this embodiment or otherwise obviously contradict the context. The procedures (or variations and / or combinations thereof) described in this embodiment can be executed under the control of one or more computer systems configured with executable instructions, and can be implemented by hardware or a combination thereof as code (e.g., executable instructions, one or more computer programs, or one or more applications) that commonly executes on one or more processors. A computer program includes a plurality of instructions executable by one or more processors.

[0063] Furthermore, the method can be implemented in any suitable type of computing platform, including but not limited to personal computers, minicomputers, mainframes, workstations, networked or distributed computing environments, standalone or integrated computer platforms, or in communication with charged particle tools or other imaging devices, etc. Aspects of embodiments of the invention can be implemented as machine-readable code stored on a non-transitory storage medium or device, whether removable or integrated into a computing platform, such as a hard disk, optical read and / or write storage medium, RAM, ROM, etc., such that it is readable by a programmable computer, and when the storage medium or device is read by the computer, it can be used to configure and operate the computer to perform the processes described herein. Furthermore, the machine-readable code, or portions thereof, can be transmitted via wired or wireless networks. The invention of this embodiment includes these and other different types of non-transitory computer-readable storage media when such media comprises instructions or programs that implement the steps above in conjunction with a microprocessor or other data processor. Embodiments of the invention also include the computer itself when programmed according to the methods and techniques of embodiments of the invention.

[0064] A computer program can be applied to input data to perform the functions of this embodiment, thereby transforming the input data to generate output data stored in non-volatile memory. The output information can also be applied to one or more output devices, such as a display. In a preferred embodiment of the invention, the transformed data represents physical and tangible objects, including a specific visual depiction of physical and tangible objects generated on the display.

[0065] The above are merely preferred embodiments of the present invention. The embodiments of the present invention are not limited to the above-described implementations. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the embodiments of the present invention, as long as they achieve the same technical effects, should be included within the scope of protection of the embodiments of the present invention. Within the scope of protection of the embodiments of the present invention, the technical solutions and / or implementation methods can have various modifications and variations.

Claims

1. A wide backoff load modulation balanced power amplifier based on fully automatic analog amplitude control, characterized in that, The wide back-off load modulation balanced power amplifier based on fully automatic analog amplitude control includes: A fully automatic analog power ratio control power divider 101; the fully automatic analog power ratio control power divider 101 includes a first output terminal and a second output terminal, and the fully automatic analog power ratio control power divider 101 adjusts the output power of the first output terminal and the second output terminal through a first power distribution characteristic; Carrier amplifier 102; the input terminal of the carrier amplifier 102 is connected to the first output terminal. Phase offset line 103; Balanced amplifier 104; the input terminal of the balanced amplifier 104 is connected to the second output terminal through the phase offset line 103.

2. The wide back-off load modulation balanced power amplifier based on fully automatic analog amplitude control according to claim 1, characterized in that: The first power distribution characteristic includes: the power division ratio between the second output terminal and the first output terminal is positively correlated with the input power obtained by the fully automatic analog power division ratio control power divider 101; when the input power obtained by the fully automatic analog power division ratio control power divider 101 is lower than the power threshold, the power division ratio between the second output terminal and the first output terminal is negative; when the input power obtained by the fully automatic analog power division ratio control power divider 101 is higher than the power threshold, the power division ratio between the second output terminal and the first output terminal is positive.

3. The wide back-off load modulation balanced power amplifier based on fully automatic analog amplitude control according to claim 1, characterized in that: The fully automatic analog power divider 101 includes a coupled-line coupler 201, a rectifier circuit 202, and a power divider 203 with adjustable power ratio. One output terminal of the coupling line coupler 201 is connected to the input terminal of the power divider 203 with adjustable power ratio, and the other output terminal is connected to the RF input terminal of the rectifier circuit 202. The input terminal of the rectifier circuit 202 is connected to the coupling terminal of the coupling line coupler 201; The output terminal of the rectifier circuit 202 is connected to the DC bias terminal of the power divider 203 with adjustable power ratio; the rectifier circuit 202 is used to provide a bias voltage to the power divider 203 with adjustable power ratio, so that the power divider 203 has a second power distribution characteristic.

4. The wide back-off load modulation balanced power amplifier based on fully automatic analog amplitude control according to claim 3, characterized in that: The second power distribution characteristic includes: the power division ratio between the second output terminal and the first output terminal is positively correlated with the bias voltage obtained by the power division ratio adjustable power divider 203. When the bias voltage obtained by the power division ratio adjustable power divider 203 is lower than the voltage threshold, the power division ratio between the second output terminal and the first output terminal is negative. When the bias voltage obtained by the power division ratio adjustable power divider 203 is higher than the voltage threshold, the power division ratio between the second output terminal and the first output terminal is positive.

5. The wide back-off load modulation balanced power amplifier based on fully automatic analog amplitude control according to claim 1, characterized in that: The carrier amplifier 102 includes a carrier amplifier input matching network 204, a carrier amplifier gate bias stabilization network 205, a carrier amplifier chip 206, and a carrier amplifier output matching network 207. One end of the carrier amplifier gate bias stabilization network 205 is connected to a stabilizing resistor R6 and a capacitor C. 10 One end is connected to the carrier amplifier input matching network 204, and the other end is connected to the carrier amplifier output matching network 207 through the carrier amplifier chip 206.

6. The wide back-off load modulation balanced power amplifier based on fully automatic analog amplitude control according to claim 5, characterized in that: The balanced amplifier 104 includes an input 3dB directional coupler 209, a first peak amplifier input matching network 210, a first peak amplifier gate bias stabilization network 211, a first peak amplifier chip 212, a first peak amplifier output matching network 213, a second peak amplifier input matching network 214, a second peak amplifier gate bias stabilization network 215, a second peak amplifier chip 216, a second peak amplifier output matching network 217, and an output 3dB directional coupler 218. The input terminal of the 3dB directional coupler 209 is connected to the phase offset line 103, and the output terminal is connected to the input terminal of the first peak amplifier input matching network 210 and the input terminal of the second peak amplifier input matching network 214, respectively. One end of the first peak amplifier gate bias stabilization network 211 is connected to a stabilizing resistor R9 and a capacitor C. 13 One end is connected to the input matching network 210 of the first peak amplifier, and the other end is connected to the output matching network 213 of the first peak amplifier through the first peak amplifier chip 212. One end of the second peak amplifier gate bias stabilization network 215 is connected to a stabilizing resistor R. 11 and capacitor C 16 One end is connected to the input matching network 214 of the second peak amplifier, and the other end is connected to the output matching network 217 of the second peak amplifier through the second peak amplifier chip 216. The 3dB output directional coupler 218 is connected to the carrier amplifier output matching network 207, the first peak amplifier output matching network 213, the second peak amplifier output matching network 217, and the load, respectively.

7. The wide back-off load modulation balanced power amplifier based on fully automatic analog amplitude control according to claim 5, characterized in that: The input terminal of the coupling line coupler 201 is connected to the radio frequency source; The power divider 203 with adjustable power ratio includes a first output terminal and a second output terminal. The first output terminal is connected to the input terminal of the carrier amplifier input matching network 204, and the second output terminal is connected to the input terminal of the phase offset line 103. The output terminal of the phase offset line 103 is connected to the input terminal of the input 3dB directional coupler 209; The output of the 3dB directional coupler 209 is connected to the first peak amplifier input matching network 210 and the second peak amplifier input matching network 214, respectively.

8. The wide back-off load modulation balanced power amplifier based on fully automatic analog amplitude control according to claim 1, characterized in that: The phase offset line 103 is a transmission line with a characteristic impedance of 50 Ω.

9. The wide back-off load modulation balanced power amplifier based on fully automatic analog amplitude control according to any one of claims 1-8, characterized in that, The wide back-off load modulation balanced power amplifier based on fully automatic analog amplitude control also includes: The dielectric substrate; the fully automatic analog power divider 101, the carrier amplifier 102, the phase offset line 103 and the balanced amplifier 104 are fixed on one side of the dielectric substrate using microstrip technology.

10. The wide back-off load modulation balanced power amplifier based on fully automatic analog amplitude control according to claim 9, characterized in that: The dielectric substrate has a signal shielding unit 219 on one side and a metal ground on the other side. The dielectric substrate has metallized vias, and the signal shielding unit 219 is connected to the metal ground through the metallized vias.

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