Automatic gain control circuit applied to inductance encoder chip

Abstract

The invention provides an automatic gain control circuit applied to an inductance encoder chip. The circuit is characterized in that the circuit is composed of a quadratic sum circuit (1), a sampling comparison circuit (2), a controlled current source (3), a comparator CMP1 (4), a comparator CMP2 (5), an AGC control logic unit (6) and a controlled voltage source (7). The automatic gain control method can be used for automatic gain control of the output signal of the inductance encoder chip, and can be widely applied to the fields of industrial automation, robots, automobiles, transportation, aerospace and the like.

Description

(I) Technical Field

[0001] This invention relates to an automatic gain control circuit for inductive encoder chips. It can be used for automatic gain control of the output signal of inductive encoder chips and is widely applied in industrial automation, robotics, automotive and transportation, aerospace, and other fields, belonging to the field of precision measurement and sensing technology. (II) Background Technology

[0002] Inductive encoders are position and speed sensors that utilize the principle of electromagnetic induction. Due to their extremely high reliability, ultra-long service life, and excellent environmental adaptability, they demonstrate unique technological value in modern industry and high-end equipment. Compared to photoelectric encoders, they do not have fragile optical components or limited LED lifespan, and are naturally immune to oil, dust, and condensation. Compared to magnetoelectric encoders, they do not rely on permanent magnets, thus exhibiting strong resistance to external stray magnetic fields, resulting in higher accuracy and stability. This robust and durable characteristic allows them to operate stably under harsh conditions such as vibration, shock, and a wide temperature range from -40℃ to 125℃. Furthermore, through precise internal coil design and advanced interpolation algorithms, they can achieve resolutions of up to 20 bits or more and absolute accuracy better than ±0.01°, meeting the pursuit of ultimate performance in high-precision motion control.

[0003] However, during the operation of an inductive encoder, the air gap between the rotor and stator can change due to mechanical tolerances, thermal expansion, or long-term wear. Even minute changes in the air gap can lead to significant variations in the strength of the coupled magnetic field, causing fluctuations in the amplitude of the signal induced by the receiving coil. Subsequent angle calculations are highly dependent on the amplitudes of the sin and cosine signals. Unstable amplitudes will directly result in incorrect angle calculations. Therefore, inductive encoders utilize automatic gain control (AGC) technology, which has become a crucial element in angle calculation and high-precision measurement for inductive encoders.

[0004] Currently, the main automatic gain control technologies applied to inductive encoders include: analog closed-loop automatic gain control, digital closed-loop automatic gain control, and reference channel technology. Analog closed-loop automatic gain control is the most classic and direct automatic gain control technology for inductive encoders. It first amplifies and filters the signal output from the receiving coil, then uses a peak detection circuit to detect the signal amplitude. The detected amplitude is then compared with an internally stable reference voltage to generate an error signal. This error signal is used to control the gain of a variable gain amplifier. If the detected amplitude is too low, the gain of the variable gain amplifier is increased; if the detected amplitude is too high, the gain is decreased, ultimately stabilizing the output. The advantages of analog closed-loop automatic gain control are its fast response speed and its use of pure hardware, without consuming digital processing resources. However, it requires additional analog circuitry, may introduce temperature drift and noise, and has relatively lower accuracy and stability. Digital closed-loop automatic gain control uses an ADC to simultaneously sample the signal in real time, digitizing the input analog signal. Then, in the digital domain, the amplitude of the signal is calculated by taking the vector sum of the sine and cosine signals. The calculated signal amplitude is compared with a preset digital reference value to obtain the error value. This error value is smoothed by a digital PID controller or low-pass filter to maintain system stability. The processed error value is converted into control commands and sent to the digitally controlled programmable gain amplifier to adjust its gain, ultimately stabilizing the output amplitude to the preset value. With the development and popularization of ADCs and digital processors, digital closed-loop automatic gain control technology has become the mainstream calculation for automatic gain control of inductive encoders due to its high accuracy and flexibility. However, it requires digital processing, has a certain algorithm delay, and consumes a large amount of digital resources. The reference channel technology involves designing a reference coil on the stator in addition to the receiving coil. This reference coil is designed to be independent of the rotor position and only related to the air gap size, providing a stable amplitude reference. Changes in the air gap cause synchronous changes in the amplitude of the output signals of the receiving coil and the reference coil. The system detects the amplitude changes of the reference coil's output signal and synchronously adjusts the gain of the variable gain amplifier in the receiving coil's signal channel to eliminate the influence of air gap changes on the output signal amplitude, ultimately stabilizing the output signal. This technology is direct and efficient, requiring no complex circuitry to detect signal amplitude, and has a fast response speed. However, it requires additional coils and analog channels, which increases the difficulty of sensor design and manufacturing.

[0005] This invention proposes an automatic gain control circuit for inductive encoder chips. By detecting the amplitude of the input sine and cosine signals and comparing and quantizing them with a threshold amplitude, the output current is adjusted to control the amplitude of the excitation coil, thereby indirectly regulating the amplitude of the input sine and cosine signals and ultimately stabilizing them at a preset amplitude. Compared to digital closed-loop automatic gain control technology and reference channel technology, this method significantly reduces circuit complexity, eliminating the need for complex ADCs and digital signal processors (DSPs), as well as additional coils and analog channels, thus greatly reducing the cost of the inductive encoder. Compared to traditional analog closed-loop automatic gain control technology, which adjusts the output signal amplitude by controlling the gain of the output signal, this invention directly controls the amplitude of the excitation coil by adjusting the current, thereby adjusting the signal amplitude and resulting in a faster response speed. Furthermore, this invention performs interval processing on the detected amplitude signal, with different rates of current change in different intervals, further shortening the adjustment time of the automatic gain control system and improving the chip's response speed. (III) Summary of the Invention

[0006] The purpose of this invention is to provide an automatic gain control circuit for use in inductive encoder chips.

[0007] The objective of this invention is achieved as follows:

[0008] (Claim 1) The automatic gain control circuit applied to an inductive encoder chip consists of a sum-of-squares circuit (1), a sampling and comparison circuit (2), a controlled current source (3), comparators CMP1 (4) and CMP2 (5), an AGC control logic unit (6), and a controlled voltage source (7). In this circuit, the sum-of-squares circuit (1) receives a sinusoidal voltage signal V. sin Cosine voltage signal V cos and input common-mode voltage V CM The sum of squares circuit (1) will V sin and V cos With common-mode voltage V respectively CM After subtraction, the voltage is converted into a current signal, and the squares of the results are summed to generate the current signal I. R It can detect the magnitude of the input signal amplitude in real time. Current signal I R The signal is fed into the sampling comparison circuit (2) and compared with the internal threshold current. After the sampling capacitor is charged and discharged, the output voltage signal V is generated. C Voltage signal V C The positive input signals of comparators CMP1(4) and CMP2(5) are respectively compared with the threshold voltage V generated by the controlled voltage source (3). O1 and V O2 A comparison is made to generate a control signal V. CMP1 and VCMP2 The AGC control logic unit (6) receives the control signal V. CMP1 and V CMP2 Then, a control signal D<2:0> is generated to control the threshold voltage V output by the controlled voltage source (3). O1 and V O2 Simultaneously, it generates a coarse current control signal GR<3:0> and a fine current control signal GF<9:0>, adjusting the output current signal I of the controlled current source. LC This indirectly controls the input signal V. sin and V cos The amplitude is adjusted to achieve automatic gain control.

[0009] like Figure 6 The diagram shows an example of an inductive encoder, consisting of a rotor (60), a stator (61), and an inductive encoder chip (62). The outer ring of the stator has an excitation coil printed on it, and the inner ring has a receiving coil printed on it. The inductive encoder chip outputs a drive signal to drive the excitation coil and receives the induced voltage output by the receiving coil. When the rotor rotates, due to the eddy current effect, the receiving coil generates an alternating voltage signal with an envelope, which can be expressed as:

[0010] In the formula V is the carrier angular frequency, i.e., the excitation frequency of the excitation coil, which is mainly determined by the inductance of the excitation coil and the external capacitor; where w is the signal angular frequency, i.e., the frequency of the envelope signal generated by the receiving coil, which is related to the rotor's rotational speed and the number of pole pairs of the code disk; where V m The signal amplitude is positively correlated with the strength of the alternating magnetic field, the coupling coefficient between the excitation line and the receiving coil, and the size of the air gap between the code disk and the inductor coil, and can be expressed as: V m ∝H·k·l (2)

[0011] In the formula, H represents the intensity of the alternating magnetic field, k represents the coupling coefficient between the excitation coil and the receiving coil, and l represents the air gap size between the code disk and the inductor coil. The intensity of the alternating magnetic field is positively correlated with the oscillation amplitude of the LC oscillation drive excitation coil in the inductor encoder chip (62), and the oscillation amplitude can be expressed as:

[0012] In the formula R S Let V represent the parasitic resistance of the excitation coil, Q represent the quality factor of the excitation coil, and I represent the bias current of the LC oscillator. From equations (2) and (3) above, the signal amplitude V m The relationship influenced by other factors can be further expressed as: V m ∝k·l·RS ·Q 2 ·I (4)

[0013] In the formula, the coupling coefficient k and the parasitic resistance R S The quality factor Q is determined by the physical characteristics of the coil itself. Therefore, with the same coil and a fixed air gap size, the signal amplitude V... m The amplitude of the signal is directly proportional to the bias current of the LC oscillator. A larger bias current results in a larger received signal amplitude, while a smaller bias current results in a smaller received signal amplitude. The automatic gain control circuit described in this patent adjusts the signal amplitude by detecting the input signal amplitude and outputting the bias current of the LC oscillator.

[0014] like Figure 2 The diagram shown is the block diagram of the sum of squares circuit (1), with input signal V. sin and common-mode voltage V CM After passing through the voltage conversion circuit (8), a current signal I containing the square term of the signal is obtained. out1 I out2 Similarly, signal V cos and signal common-mode voltage V CM After passing through the voltage conversion circuit (9), a current signal I containing the square term of the signal is obtained. out3 I out4 The four current signals are summed in the current summing circuit (10) to obtain the current signal I. R .

[0015] like Figure 3 The diagram shows the voltage conversion circuit (9, 10) in the sum-of-squares circuit (1). The circuit is divided into two stages: In the first stage, switches K1 (14), K2 (23), K3 (24), K4 (22), and K5 (25) are closed, while switches K6 (16), K7 (19), K8 (28), and K9 (29) are open. Assume that the voltage signal V at this moment is... sin It is the negative half-cycle, less than V. CM Then the current flowing through transistor M3 (311) is equal to the current flowing through transistor M4 (28) plus the current flowing through resistor R1, i.e., I M3 =I M4 +I R1 In the second stage, switches K1(14), K2(23), K3(24), K4(22), and K5(25) are turned on, while switches K6(16), K7(19), K8(28), and K9(29) are closed. The current stored in capacitors C1(21) and C2(26) is then calculated as the difference I. M3 -I M4The output current I is obtained. sin , can be represented as: I sin =I R1 =(V sin -V CM ) / R1 (6)

[0016] Current signal I sin As the input to the square circuit (12), the circuit is divided into three stages: the first stage is the switching transistor K 10 (32) Switching transistor K 11 (33) Switching transistor K 12 (37) Closed, switch K 13 (43) Switching transistor K 15 (40) Switching transistor K 14 (39) Switching transistor K 16 (45) Open, at this time the voltage V on capacitor C5(34) C5 It can be represented as:

[0017] In the formula, β5 and β6 represent the products of the transconductance coefficient and the width-to-length ratio of MOSFETs M5 (35) and M6 (44), respectively; the second-stage switching transistor K 10 (32) Switching transistor K 11 (33) Switching transistor K 14 (39) Turn on the switch K. 12 (37) Switching transistor K 13 (43) Switching transistor K 15 (40) Switching transistor K 16 (45) Closed. During this stage, transistor M7 (44) is connected as a diode, and current I2 (42) flows into transistor M7 (44), storing energy in capacitor C4 (41). At the same time, the voltage-to-current circuit (12) outputs current signal I during this stage. sin When MOSFET M5 is injected, the gate voltage V of MOSFET M6 (38) will be... M6 It can be represented as:

[0018] In the formula I M5 and I M6 The currents of MOSFETs M5 (35) and M6 (44) are represented respectively. Since capacitor C5 has no discharge path, the gate voltage remains constant. C5 =V M6 Furthermore, since the width-to-length ratios of M5 tube (35) and M6 tube (44) are relatively equal, then β5 = β6. Equations (7) and (8) can be simplified to obtain:

[0019] Let the output current I3 = I during this stage OUT1 The output current can then be expressed as:

[0020] Third stage switching transistor K 10 (32) Switching transistor K 11 (33) Switching transistor K 13 (43) Switching transistor K 15 (40) Turn on the switch K 12 (37) Switching transistor K 14 (39) Switching transistor K 16 (45) Closed. In this stage, the switching transistor K9 (30) in the voltage-to-current conversion circuit (12) is open, and the current signal I... sin Removed, and due to the voltage holding effect of capacitors C3 (36) and C4 (41), the current flowing through MOSFETs M5 (35) and M7 (44) is the same as in the second stage. Let the output current I3 = I in this stage. OUT2 The output current is:

[0021] If the bias current I2 is twice the magnitude of I1, then equation (11) can be expressed as:

[0022] Similarly, voltage signal V cos The output current I can be obtained through another voltage conversion circuit (10). OUT3 and I OUT4 , can be represented as:

[0023] The output current I of the two voltage conversion circuits (8, 9) OUT1 I OUT2 I OUT3 I OUT4 The output current I can be obtained by summing the currents through the current summing circuit (10). R Substituting equation (6) into the equation, we get:

[0024] make The above formula can be simplified to: I R =k*V m *[sin 2 (wt)+cos 2 (wt)] (16)

[0025] Since the sum of the squares of the orthogonal signals sin and cos is 1, the output current signal I of the sum of squares circuit (1) is... R It is positively correlated with the amplitude of the signal. The sum of squares circuit (1) realizes real-time detection of the signal amplitude by summing the squares of the two-phase signals.

[0026] The circuit schematic of the sampling comparison circuit (2) is as follows: Figure 4 As shown. This circuit is mainly used to generate a set threshold current I. S and the current signal I R With the set threshold current I S To make a comparison, due to the current signal I R It is positively correlated with the amplitude of the signal, therefore when the current signal I... R With our set threshold current I S When they are equal, the signal amplitude is the signal amplitude we want to set. Initially, the switching transistor K... 20 (56) Closed, switch K 17 (53), K 18 (54), K 19 (55) Turn on the sampling capacitor C6(46) and check the voltage V. C6 Charged to V CM After capacitor C6(46) has finished charging, switch K... 20 (56) Turn on the switch K. 17 (53), K 18 (54), K 19 (55) The output current I of the closed, sum of squares circuit (1) R The set threshold current I generated by the sampling comparison circuit (2) S After the difference is calculated, the sampling capacitor C6(46) is charged and discharged. Switch K 17 (53), K 18 (54), K 19 (55) Periodic opening and closing of the sampling capacitor C6(46) charges and discharges the capacitor, and the voltage on the sampling capacitor C6(46) can reflect the change in the amplitude of the two-phase signal in real time. When the voltage on the sampling capacitor C6(46) is stable within a certain range, and the input current I... R With the set threshold current I S When they are equal, the signal amplitude is the voltage amplitude I want to preset. The threshold current I is set within this. S Composed of operational amplifier (47), MOSFET M8 (50), MOSFET M9 (51), MOSFET M 10 (52) The negative feedback network and current mirror circuit formed by resistor R5 (48) and adjustable resistor R4 (49) generate the current. The threshold current I can be obtained by setting the value of the adjustable resistor R4 (49).S , which satisfy the following relationship: I S =V REF / R4 (17)

[0027] In the formula V REF As a reference voltage signal, a threshold current I is set. S By adjusting the value of the signal, you can set the desired amplitude of the two-phase signal and also adjust the deviation between the final stable signal amplitude and the preset amplitude caused by factors such as temperature, process, and voltage.

[0028] like Figure 1 As shown, the sampling voltage V output by the sampling comparison circuit (2) C The input signals, which are the positive terminals of comparators CMP1(4) and CMP2(5), are respectively compared with the threshold voltage V generated by the controlled voltage source (3). O1 and V O2 A comparison is made to generate a control signal V. CMP1 and V CMP2 The AGC control logic unit (6) receives the control signal V. CMP1 and V CMP2 The changes generate control signals D<2:0>, coarse current control signal GR<3:0>, and fine current control signal GF<9:0>. The controlled voltage source (3) is controlled by the output control signal D<2:0> of the AGC control logic unit (6), which outputs the threshold voltage V. O1 and V O2 It has 5 gears: when D<2:0>=000, V O1 =V CM +7V a V O2 =V CM +3V a When D<2:0>=001, V O1 =V CM +3V a V O2 =V CM +V a When D<2:0>=010, V O1 =V CM +V a V O2 =V CM -V a When D<2:0>=100, V O1 =V CM -V a V O2 =V CM -3V aWhen D<2:0>=101, V O1 =V CM -3V a V O2 =V CM -7V a When the AGC control logic unit (6) receives the control signal V CMP1 and V CMP2 When the value is "00", the output control signal D<2:0> lowers the threshold voltage by one level, and simultaneously controls GR<3:0> or GF<9:0> to reduce the current I. LC When the AGC control logic unit (6) receives a control signal of "01", the output control signal D<2:0> remains unchanged, and the control signal GR<3:0> or GF<9:0> is controlled to increase the current I. LC When the AGC control logic unit (6) receives a control signal of "10", the output control signal D<2:0> remains unchanged, and controls GR<3:0> or GF<9:0> to reduce the current I. LC When the AGC control logic unit (6) receives a control signal of "11", it outputs a control signal D<2:0> that is increased by one level, controlling GR<3:0> or GF<9:0> to increase the current I. LC The change of GR<3:0> or GF<9:0> depends on the gear position of D<2:0> in the previous cycle and the sampling voltage Vc: when D<2:0> = 000 and the sampling voltage Vc is above the interval, the AGC control logic unit (6) controls GR<3:0> to change; when D<2:0> = 000 and the sampling voltage Vc is within the interval, the AGC control logic unit (6) controls GF<9:0> to change in a step of 4 bits; when D<2:0> = 001 and the sampling voltage Vc is within the interval, the AGC control logic unit (6) controls GF<9:0> to change in a step of 1 bit; when D<2:0> = 010 and the sampling voltage Vc is within the interval, GR<3:0> and GF<9:0> remain unchanged. When D<2:0>=101 and the sampled voltage Vc is below the interval, the AGC control logic unit (6) controls GR<3:0> to change; when D<2:0>=100 and the sampled voltage Vc is within the interval, the AGC control logic unit (6) controls GF<9:0> to change in a step of 4 bits; when D<2:0>=011 and the sampled voltage Vc is within the interval, the AGC control logic unit (6) controls GF<9:0> to change in a step of 1 bit.

[0029] like Figure 5 The figure shows the current I in the automatic gain control circuit. R With sampling voltage V CThe curve of the change. Assuming that at time t0, the signal amplitude is abnormally increased due to external factors, the sum of squares circuit (7) detects the increase in amplitude and outputs current I. R Increase; at time t1, the CLK signal is high, and the switching transistor K... 17 (53), K 18 (54), K 19 (55) Closed, I R >I S Sampling capacitor C6 discharges, V C The signal decreases and continues until time t2, at which point the CLK signal transitions to a low level, and the switching transistor K... 17 (53), K 18 (54), K 19 (55) Open, V C The sampling voltage V remains unchanged; during the time interval t2-t3, the sampling voltage V C Less than V CM -V a At this time, D<2:0> is “010”, so the comparator CMP1(4) and comparator CMP2(5) output control signals are “00”. After the AGC control logic unit (6) detects the control signal “00” output by the comparator, it controls the fine-tuning current control signal GF<9:0> in small increments of 1 bit to reduce the output current I of the controlled current source (61). LC This refers to the bias current of the LC oscillator, which reduces the amplitude of the output signal. Simultaneously, the output control signal D<2:0> is changed to "100", and the comparison thresholds of comparators CMP1(4) and CMP2(5) are changed to V. O1 =V CM -V a V O2 =V CM -3V a At time t3, the CLK signal is high, and the switching transistor K... 17 (53), K 18 (54), K 19 (55) Closed, I R >I S The sampling capacitor C6 continues to discharge, V C The signal decreases and continues until time t4, when the CLK signal jumps to a low level, and the switching transistor K... 17 (53), K 18 (54), K 19 (55) Closed, V C The sampling voltage V remains unchanged; during the time interval t4-t5, the sampling voltage V C Less than V CM -3V aIf the comparator CMP1(4) and comparator CMP2(5) output control signals "00", the AGC control logic unit (6) detects the control signal "00" output by the comparator and reduces the output current I of the controlled current source (61) according to the fine-tuning current control signal GF<9:0> with a step size of 4 bits. LC This reduces the amplitude of the output signal. Simultaneously, the output control signal D<2:0> is changed to "101", and the comparison thresholds of comparators CMP1(4) and CMP2(5) are changed to V. O1 =V CM -3V a V O2 =V CM -7V a At time t5, the CLK signal is high, and the switching transistor K... 17 (53), K 18 (54), K 19 (55) Closed, I R >I S The sampling capacitor C6 continues to discharge, V C The signal decreases and continues until time t6, when the CLK signal jumps to a low level, and the switching transistor K... 17 (53), K 18 (54), K 19 (55) Turn on, VC remains unchanged; during t6-t7, sampled voltage V C Less than V CM -7V a If the comparator CMP1(4) and comparator CMP2(5) output control signals "00", the AGC control logic unit (6) detects the control signal "00" output by the comparator and controls the coarse adjustment current control signal GR<3:0> to significantly reduce the output current I of the controlled current source (61). LC This reduces the amplitude of the output signal. The output control signal D<2:0> remains unchanged; at time t7, the CLK signal is high, and the switching transistor K... 17 (53), K 18 (54), K 19 (55) Closed, I R S Sampling capacitor C6 is charging, V C The signal rises and continues until time t8, at which point the CLK signal transitions to a low level, and the switching transistor K... 17 (53), K 18 (54), K 19 (55) Open, V C The sampling voltage V remains unchanged during t8-t9. C Less than V CM -7V a ​If the comparator CMP1(4) and comparator CMP2(5) output control signals "00", the AGC control logic unit (6) will detect the comparator output control signal "00" and continue to control the coarse adjustment current control signal GR<3:0> to significantly reduce the output current I of the controlled current source (61). LC This reduces the amplitude of the output signal while keeping the output control signal D<2:0> unchanged; at time t9, the CLK signal is high, and the switching transistor K... 17 (53), K 18 (54), K 19 (55) Closed, I R S Sampling capacitor C6 is charging, V C The rise continued until t 10 At that moment, the CLK signal transitions to a low level, and the switching transistor K... 17 (53), K 18 (54), K 19 (55) Open, V C Remain unchanged; at t 10 -t 11 At that time, the sampling voltage V C Greater than V CM -7V a Less than V CM -3V a If the comparator CMP1(4) and comparator CMP2(5) output control signals "01", the AGC control logic unit (6) detects the control signal "01" output by the comparator and controls the fine-tuning current control signal GF<9:0> to increase according to a step size of 4 bits, and the output current I of the controlled current source (61) increases. LC This increases the amplitude of the output signal. The output control signal D<2:0> remains unchanged; similarly, at t 11 -t 16 At time, switch K 17 (53), K 18 (54), K 19 (55) Periodically open and close, the AGC control logic unit (6) controls the fine-tuning current control signal GF<9:0> in 4-bit increments to gradually increase the amplitude of the output signal, and the sampling voltage V C Increase; at t 16 -t 17 At that time, the sampling voltage V C Greater than V CM -3V a Less than V CM -V a ​Then, the comparator CMP1(4) and comparator CMP2(5) output control signals "11". After the AGC control logic unit (6) detects the control signal "11" output by the comparator, it controls the fine-tuning current control signal GF<9:0> to increase the output current I of the controlled current source (61) according to a step size of 1 bit. LC This increases the amplitude of the output signal. Simultaneously, the output control signal D<2:0> is changed to "100", and the comparison thresholds of comparators CMP1(4) and CMP2(5) are changed to V. O1 =V CM -V a V O2 =V CM -3V a ; in t 17 -t 26 At that time, the switching transistor K 17 (53), K 18 (54), K 19 (55) Periodically opening and closing, the AGC control logic unit (6) controls the fine-tuning current control signal GF<9:0> in 1-bit increments to gradually increase the amplitude of the output signal, and the current I R It rises little by little; at t 26 -t 27 At that time, the sampling voltage V C Greater than V CM -V a Less than V CM +V a If the comparator CMP1(4) and comparator CMP2(5) output control signals "11", the AGC control logic unit (6) detects the comparator output control signal "11" and changes the output control signal D<2:0> to "010", while keeping the fine-tuning current control signal GF<9:0> unchanged; at this time, the current I R Approximately equal to the set threshold current I S That is, the output signal amplitude eventually stabilizes at the preset value. After several cycles, V C The voltage on is greater than V CM +V a Or less than V CM -V a At that time, the AGC control logic unit (6) detects the change in the comparator's control signal, adjusts the current control signal GF<9:0>, repeats the above steps, and finally makes the output current I... R Stabilized at the threshold current I S Near the preset value, meaning the output signal amplitude stabilizes at the preset value. (iv) Description of the attached drawings

[0030] Figure 1This is a block diagram of an automatic gain control circuit applied to an inductive encoder chip. The circuit consists of a sum-of-squares circuit (1), a sampling and comparison circuit (2), a controlled current source (3), comparators CMP1 (4) and CMP2 (5), an AGC control logic unit (6), and a controlled voltage source (7).

[0031] Figure 2 This is the circuit block diagram of the sum of squares circuit. The circuit consists of two voltage conversion circuits (8, 9) and one current summing circuit (10).

[0032] Figure 3 This is the circuit diagram of a voltage conversion circuit. The circuit consists of a voltage-to-current conversion circuit (11) and a current-to-square circuit (12).

[0033] Figure 4 The circuit diagram of the sampling comparator circuit consists of an operational amplifier (47), resistor R5 (48), adjustable resistor R4 (49), MOSFET M8 (50), MOSFET M9 (51), and MOSFET M... 10 (52) Switching transistor K 17 (53) Switching transistor K 18 (55) Switching transistor K 19 (54) and switching transistor K 20 (56) Composition.

[0034] Figure 5 It is the input current I of the automatic gain control circuit. R With sampling voltage V C Example graph of the variation curve. Curve 1 (57) is the sampled voltage V. C The curves showing the change over time, curve 2(58) represents the input current I. R The curves showing the change over time, curve 3(59) is the timing diagram of clock CLK.

[0035] Figure 6 This is an example diagram of an inductive encoder. It consists of a rotor (60), a stator (61), and an inductive encoder chip (62).

[0036] Figure 7 This is a system schematic diagram of an embodiment. The example diagram consists of an encoder (63), an excitation coil (64), a receiving coil (65), a synchronous detection circuit (66), an LC oscillator (70), a comparator (69), a Clarke transform circuit (67), and an automatic gain control circuit (68). The excitation coil (64) and the receiving coil (65) are etched on the PCB board as the stator of the motor, and the encoder (63) is mounted on the concentric shaft of the motor as the rotor of the motor. (V) Detailed Implementation

[0037] Figure 7 This is an example of an automatic gain control circuit applied to an inductive encoder chip. It consists of a code disk (63), an excitation coil (64), a receiving coil (65), a synchronous detection circuit (66), an LC oscillator (70), a comparator (69), a Clarke transform circuit (67), and an automatic gain control circuit (68). The excitation coil (64) and the receiving coil (64) are etched onto a PCB board to serve as the stator of the motor, while the code disk is mounted on the concentric shaft of the motor to serve as the rotor.

[0038] In this embodiment, pins TX1 and TX2 of the LC oscillator (70) are connected to the two ends of the excitation coil (64), driving the excitation coil (64) to establish a high-frequency alternating magnetic field in the air gap between the stator and rotor of the motor. When the motor rotates, the metal object on the code disk periodically modulates the coupling strength between the excitation coil (64) and the receiving coil (65), generating a high-frequency modulated signal with an envelope whose shape strictly corresponds to the angular position of the rotor. After amplification, demodulation, and filtering by the synchronous detection circuit (66), three-phase voltage signals Va, Vb, and Vc with a phase difference of 120° are generated. Among them, the demodulation clock V CLK The three-phase voltage signals Va, Vb, and Vc are generated by comparison by the comparator (69) of the LC oscillator (70). After conversion by the Clarke converter circuit (67), the two-phase voltage signal V is obtained. sin and V cos and the common-mode voltage V of the signal CM The input is fed into the automatic gain control circuit (68) to generate the bias current I of the LC oscillator (70). LC This controls the oscillation amplitude of the excitation coil, thereby adjusting the signal amplitude output by the receiving coil.

[0039] When the motor rotates, the air gap between the rotor and stator changes due to mechanical tolerances, thermal expansion, or long-term wear, causing fluctuations in the amplitude of the signal sensed by the receiving coil (65). At this time, the sum of squares circuit (1) in the automatic gain control circuit (68) receives the two-phase voltage signal V. sin and V cos The current signal I is generated by squaring and summing the squares. R Current signal I R It reflects changes in the amplitude of the input signal in real time. Current signal I R The signal is fed into the sampling comparison circuit (2) and compared with the internal threshold current. After the sampling capacitor is charged and discharged, the output voltage signal V is generated. C Voltage signal V C The positive input signals of comparators CMP1(4) and CMP2(5) are respectively compared with the threshold voltage V generated by the controlled voltage source (3). O1 and VO2 A comparison is made to generate a control signal V. CMP1 and V CMP2 The AGC control logic unit (6) receives the control signal V. CMP1 and V CMP2 Then, a control signal D<2:0> is generated to control the threshold voltage V output by the controlled voltage source (3). O1 and V O2 Simultaneously, it generates a coarse current control signal GR<3:0> and a fine current control signal GF<9:0>, adjusting the output current signal I of the controlled current source. LC Current signal I LC As the bias current of the LC oscillator (70), it drives and adjusts the magnetic field strength of the excitation coil (64), thereby adjusting the amplitude of the alternating voltage signal output by the receiving coil (65). After passing through the synchronous detection circuit (66) and the Clarke transform circuit (6), the two-phase voltage signal V is finally adjusted. sin and V cos The output amplitude is stable, eliminating the influence of external environmental changes on the signal amplitude.

Claims

1. An automatic gain control circuit applied to an inductive encoder chip. Its characteristics are: It consists of a sum-of-squares circuit (1), a sampling and comparison circuit (2), a controlled current source (3), comparators CMP1 (4) and CMP2 (5), an AGC control logic unit (6), and a controlled voltage source (7). The sum-of-squares circuit (1) receives a sinusoidal voltage signal V. sin Cosine voltage signal V cos and input common-mode voltage V CM The sum of squares circuit (1) will V sin and V cos With common-mode voltage V respectively CM After subtraction, the voltage is converted into a current signal, and the squares of the results are summed to generate the current signal I. R It can detect the magnitude of the input signal amplitude in real time. Current signal I R The signal is fed into the sampling comparison circuit (2) and compared with the internal threshold current. After the sampling capacitor is charged and discharged, the output voltage signal V is generated. C Voltage signal V C The positive input signals of comparators CMP1(4) and CMP2(5) are respectively compared with the threshold voltage V generated by the controlled voltage source (3). O1 and V O2 A comparison is made to generate a control signal V. CMP1 and V CMP2 The AGC control logic unit (6) receives the control signal V. CMP1 and V CMP2 Then, a control signal D<2:0> is generated to control the threshold voltage V output by the controlled voltage source (3). O1 and V O2 Simultaneously, it generates a coarse current control signal GR<3:0> and a fine current control signal GF<9:0>, adjusting the output current signal I of the controlled current source. LC This indirectly controls the input signal V. sin and V cos The amplitude is adjusted to achieve automatic gain control.

2. The sum-of-squares circuit (1) applied to the automatic gain control circuit of an inductive encoder chip according to claim 1, characterized in that: The circuit consists of two voltage conversion circuits (8, 9) and one current summing circuit (10). One of the voltage conversion circuits (8) converts the input voltage signal V... sin With common-mode voltage V CM After subtraction, it is converted into a current signal I with the square component of the signal. out1 and I out2 Similarly, another voltage conversion circuit (9) converts the input voltage signal V... cos With common-mode voltage V CM After subtraction, it is converted into a current signal I with the square component of the signal. out3 and I out4 These four current signals serve as inputs to the current summing circuit (10), and are summed in the current summing circuit (10) to obtain the current signal I. R .

3. The voltage conversion circuit (8, 9) in the sum-of-squares circuit (1) according to claim 2, characterized in that: The circuit consists of a voltage-to-current converter (11) and a current-square circuit (12). The voltage-to-current converter (11) receives the input voltage signal V. sin Or V cos and common-mode voltage signal V CM After subtraction, it is converted into a current signal I. sin Or I cos The output is sent to the current squaring circuit (12). The current squaring circuit (12) converts the received current signal into a current signal with a signal square term.

4. The voltage-to-current circuit (11) in the voltage conversion circuit (8, 9) according to claim 3 is characterized in that: It consists of switching transistors K1(14), K2(23), K3(24), K4(22), K5(25), K6(16), K7(19), K8(28), K9(29), resistors R1(13), R2(17), R3(18), capacitors C1(21), C2(26), MOSFETs M1(15), M2(20), M3(30), and M4(27). One end of switching transistor K1(14) is connected to R1(13), and the other end serves as the input. The other end of resistor R1(13) is connected to the input common-mode voltage signal V. CM Resistors R2 (17) and R3 (18). The source of MOSFET M2 (20) is grounded, and its drain and gate are shorted and connected to one end of switch K7 (19). The other end of switch K7 (19) is connected to resistor R3 (18) and switch K3 (24). The other end of switch K3 (24) is connected to switch K8 (28), switch K9 (29), switch K5 (25) and MOSFET M4 (27). One end of resistor R3(18) is connected to switching transistors K3(24) and K7(19), and the other end is connected to resistors R2(17) and R1(13). The other end of resistor R2(17) is connected to switching transistors K2(23) and K6(16). The other end of switching transistor K2(23) is connected to the drain of switching transistors K4(22), K8(28), and MOSFET M3(30). The other end of switching transistor K6(16) is connected to the gate of MOSFET M1(15). The drain and gate of MOSFET M1(15) are shorted and connected to switching transistor K6(16), and the source is grounded. The gate of MOSFET M3(30) is connected to capacitor C1(21) and switch K4(22), the source is connected to the power supply, and the drain is connected to switches K2(23), K4(22), and K8(28). The other end of capacitor C1(21) is grounded. Switch K4(22) is connected across the gate and drain of MOSFET M3(30). One end of switch K8(28) is connected to the drain of switches K2(23), K4(22), and MOSFET M3(30), and the other end is connected to the drain of switches K3(24), K5(25), and MOSFET M4(27). The source of MOSFET M4(27) is grounded, the gate is connected to capacitor C2(26) and one end of switch K5(25), and the drain is connected to the other end of switch K5(25), switch K3(24), switch K8(28), and switch K9(29). One end of switch K9 (29) is connected to the drains of switch K3 (24), switch K8 (28), and MOSFET M4 (27), while the other end serves as the output. This circuit converts the input two-phase voltage signal V... sin Or V cos With the input common-mode voltage signal V CM After subtraction, it is converted into a current signal and input to the current squaring circuit.

5. The current squaring circuit (12) in the voltage conversion circuit (8, 9) according to claim 3. Its characteristic is: The circuit consists of a switching transistor K 10 (32) Switching transistor K 11 (33) Switching transistor K 12 (37) Switching transistor K 13 (43) Switching transistor K 14 (39), switch K 15 (40) Switching transistor K 16 The circuit consists of (45), capacitor C3 (36), capacitor C4 (41), capacitor C5 (34), MOSFET M5 (35), MOSFET M6 (38), MOSFET M7 (44), current source I1 (31), and current source I2 (42). One end of current source I1 (31) is grounded, and the other end is connected to the switching transistor K. 10 (32), switch K 10 (32) The other end is connected to capacitor C5 (34), the gate of MOSFET M6 (38), and switch K. 11 (33) The other end of capacitor C5 (34) is grounded. The source of MOSFET M5 (35) is grounded, the gate is connected to capacitor C3 (36), and the drain is connected to switch K. 12 (37) and the source of MOSFET M6 (38), the other end of capacitor C3 (36) is grounded, and the switching transistor K 12 (37) Connected across the gate and source of MOSFET M5 (35). The source of MOSFET M6 (38) is connected to the source of MOSFET M5 (35) and the switch K. 12 (37) The gate is connected to the switch transistor K. 11 (33) Switching transistor K 10 (33) and capacitor C5 (34), missing switch transistor K 11 (33) Switching transistor K 14 (39) and switching transistor K 16 (45), switch K 11 (33) Connected across the gate and drain of MOSFET M6(38), switch K 16 (45) The other end of the circuit is the output, and the switching transistor K is the output of the circuit. 14 (39) The other end is connected to the switching transistor K. 13 (43) Switching transistor K 15 (40) and the source of MOSFET M7(44), switch K 13 (43) The other end is connected to current source I2 (42), and the other end of current source I2 (42) is grounded. The drain of MOSFET M7 (44) is connected to switch K. 13 (43) Switching transistor K 14 (39) and switching transistor K 15 (40), gate connected to switch K 13 The other end of (43) and capacitor C4 (41) are grounded, with the source of C4 (41) grounded. This circuit converts the received current signal into a current signal with a squared term.

6. The sampling comparison circuit (2) applied to the automatic gain control circuit of the inductive encoder chip according to claim 1, characterized in that: The circuit consists of an operational amplifier (47), resistor R5 (48), adjustable resistor R4 (49), MOSFET M8 (50), MOSFET M9 (51), and MOSFET M... 10 (52) Switching transistor K 17 (53) Switching transistor K 18 (55) Switching transistor K 19 (54) and switching transistor K 20 (56) Composition. The positive input terminal of the operational amplifier (47) is connected to the reference voltage V. REF The negative input terminal is connected to one end of the adjustable resistor R4 (49) and resistor R5 (48), and the output is connected to the gate of MOSFET M8 (50). One end of the adjustable resistor R4 (49) is connected to the negative input terminal of operational amplifier (47) and resistor R5 (48), and the other end is grounded. One end of resistor R5 (48) is connected to the adjustable resistor R4 (49) and the negative input terminal of operational amplifier (47), and the other end is connected to the source of MOSFET M9 (51). The drain of MOSFET M8 (50) is connected to the drain of MOSFET M9 (51), the source is connected to resistor R5 (48), and the gate is connected to the output of operational amplifier (47). The gate and drain of MOSFET M9 (51) are shorted and connected to MOSFET M8 (50). 10 (52) The gate and source are connected to the power supply voltage V. DD MOSFET M 10 (52) has its gate connected to the gate of MOSFET M9 (51), and its source connected to the power supply voltage V. DD Drain connected to switch K 17 (53), switch K 17 (53) The other end is connected to the switch transistor K. 19 (54) and switching transistor K 18 (55), switch K 19 (54) The other end is connected to the switching transistor K. 20 (56), switch K 18 (54) The other end is connected to the current signal I generated by the sum of squares circuit (7). R Switching transistor K 20 (56) One end is connected to the switching transistor K 19 (54) The other end is connected to the input common-mode voltage V. CM The sampling comparison circuit (2) is used to compare the sum of squares of the current I. R With setting the threshold current I S Perform the difference.

Images