Digital decimation filter bank based on multiplexing structure

Abstract

The invention provides a digital decimation filter bank based on a multiplexing structure. The digital decimation filter bank is formed by connecting a plurality of digital decimation filters in series; the digital decimation filter comprises a control module, a tap coefficient output module and a convolution operation module. The control module is used for acquiring configuration information of a user and generating a clock and a control signal in a corresponding working mode; the tap coefficient output module is used for generating tap coefficients of the multi-stage filter and periodically and alternately outputting the tap coefficients to the convolution operation module; the convolution operation module is used for carrying out convolution operation on a preceding-stage output signal and a tap coefficient and carrying out digital filtering; according to the digital decimation filter bank, on the premise that hardware resources consumed by the circuit are not greatly increased, the filtering effect and the anti-interference capacity of the circuit are improved, and meanwhile the highest working frequency capable of being borne by the circuit is improved.

Description

Technical Field

[0001] This invention belongs to the field of communication technology, and specifically relates to a digital decimation filter bank based on a multiplexing structure. Background Technology

[0002] The Sigma-Delta ADC is a commonly used, slow but high-precision ADC. Like other types of ADCs, it consists of analog and digital circuits. In its overall structure, the analog circuit implements the Sigma-Delta structure, converting the input floating-point voltage into a noisy multi-bit digital signal. The subsequent digital circuit can be broken down into multiple stages according to its function, working together to filter out the noise signal introduced during analog circuit transmission. Due to the limitations of the overall structure of the Sigma-Delta ADC, it can only completely separate low-frequency floating-point voltages from noise signals. Therefore, the clock frequency corresponding to the output sampling result of the digital circuit cannot be too fast, generally controlled at about twice the input signal frequency.

[0003] Based on the above design requirements, the data rate should be reduced while preserving the signal's data information. This reduction is typically achieved in circuits through decimation, specifically using a decimation filter to meet the design requirements. The CIC filter primarily performs decimation, during which passband loss occurs, requiring compensation from a subsequent CIC compensation filter. The subsequent decimation filter further performs decimation filtering, ultimately ensuring that the output sampling frequency is approximately twice the highest frequency of the signal.

[0004] In circuit design, carrying excessively high clock frequencies will exponentially increase the order of digital decimation filters and the bit width of the tap coefficients. However, the higher the filter order and the wider the tap coefficients, the more complex the corresponding hardware circuit structure becomes, increasing the number of registers, multipliers, and adders. Excessive hardware resource consumption inevitably reduces the circuit's operating speed and increases power consumption. Therefore, in high-speed, low-power design scenarios, traditional design structures cannot simultaneously meet the requirements of high speed and low power consumption, thus introducing certain limitations to the design work. Summary of the Invention

[0005] To address the problems existing in the prior art, this invention proposes a digital decimation filter bank based on a multiplexing structure. This device comprises multiple digital decimation filters connected in series to form a digital decimation filter bank. The digital decimation filter includes a control module, a tap coefficient output module, and a convolution operation module. The control module acquires user configuration information and generates clock and control signals for the corresponding operating mode. The tap coefficient output module generates tap coefficients for multiple filter stages and periodically outputs them alternately to the convolution operation module. The convolution operation module performs convolution operations on the previous stage output signal and the tap coefficients, and performs digital filtering.

[0006] The beneficial effects of this invention are:

[0007] This invention designs a digital decimation filter bank implemented with a multiplexing structure, which achieves a more streamlined structure. The digital decimation filter bank designed according to this structure improves the filtering effect and anti-interference capability of the circuit without significantly increasing the hardware resources consumed by the circuit, while also increasing the highest operating frequency that the circuit can support. Attached Figure Description

[0008] Figure 1 This is a schematic diagram of the overall structure of the Sigma-Delta ADC of the present invention;

[0009] Figure 2 This is a schematic diagram of the overall structure of the digital decimation filter bank based on the multiplexing structure of the present invention.

[0010] Figure 3 This is a diagram showing the overall structure of a cascaded digital decimation filter bank designed based on a traditional structure.

[0011] Figure 4 This is a data flow graph for cascaded convolution operations.

[0012] Figure 5 Here is a structural diagram of the coefficient output module;

[0013] Figure 6 This is a structural diagram of the convolution module of the present invention;

[0014] Figure 7 This is the core control circuit diagram of the present invention;

[0015] Figure 8 This is a power management circuit diagram of the present invention;

[0016] Figure 9 This is the input interface circuit diagram of the present invention;

[0017] Figure 10 This is the output interface circuit diagram of the present invention;

[0018] Figure 11 This is a circuit diagram of the communication interface of the present invention. Detailed Implementation

[0019] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0020] A digital decimation filter bank based on a multiplexing structure, such as Figure 2 As shown, a digital decimation filter bank is formed by cascading multiple digital decimation filters. The digital decimation filter includes a control module, a tap coefficient output module, and a convolution operation module. The control module is used to acquire user configuration information and generate clock and control signals for the corresponding working mode. The tap coefficient output module is used to generate tap coefficients for multiple filter stages and periodically output them alternately to the convolution operation module. The convolution operation module is used to perform convolution operations on the previous stage output signal and the tap coefficients, and to perform digital filtering.

[0021] In this embodiment, a Sigma-Delta ADC structure based on a digital decimation filter is disclosed, such as... Figure 1 As shown, the structure includes analog and digital sections. The module section adopts a Sigma-Delta structure, which converts the input floating-point voltage into a noisy multi-bit digital signal. The digital section includes a CIC filter, a CIC compensation filter, and a half-band filter. The IC filter mainly performs decimation, during which passband loss occurs, which needs to be compensated by the subsequent CIC compensation filter. The subsequent decimation filter further performs decimation filtering, ultimately ensuring that the sampling frequency at the output is approximately twice the highest frequency of the signal.

[0022] In this embodiment, the digital decimation filter bank contains n digital decimation filters, where n is an integer greater than or equal to 2.

[0023] User configuration information is dynamically written to the configuration information storage module via SPI, and a configuration list is generated.

[0024] In this embodiment, the control module is the core unit of the electronic system responsible for logical decision-making, timing control, and signal interaction. Its structure and circuit design need to be determined based on the application scenario to determine its complexity.

[0025] Specifically, the control module includes: a main controller, a power management unit, an input interface circuit, an output interface circuit, a clock and reset circuit, and a communication interface circuit. The communication interface circuit connects the various circuits, enabling their electrical conduction. The power management unit provides a stable voltage to each module. The input interface acquires input signals and inputs them to the main controller. The clock and reset circuit provides a stable clock signal and reset function to the main controller. The main controller processes the input signals and inputs the processed signals to the output interface circuit, which then outputs the clock and control signals corresponding to the operating mode.

[0026] like Figure 5 As shown, the tap coefficient output module includes a control module, a counter, an address decoding module, and a coefficient register module. A control signal is input to the control module, which generates an instruction signal and inputs it to the counter. The counter counts, sends the count result to the address decoding module, and feeds it back to the control module. The address decoding module performs address decoding based on the count result. The coefficient register module addresses the input based on the decoding result from the address decoding module and periodically outputs the corresponding coefficient values ​​alternately.

[0027] like Figure 6 As shown, the convolution operation module includes: a selection module, a multiplier, and a multiplexer. The input signal is input to the selection module for signal selection, the selected signal is delayed, and the delayed selected signal is input to the multiplier. At the same time, the output signal of the coefficient output module is delayed and then input to the multiplier. The multiplier multiplies the delayed selected signal and the delayed output signal. The output signal of the multiplier, the selected signal, the delayed selected signal, and the delayed signal of the multiplier are input to the multiplexer for selection to obtain the output signal. The output signal is delayed and then fed back to the selection module.

[0028] Taking an STM32-based embedded control module as an example, its circuit diagram can be divided into the following sub-circuits:

[0029] 1. Core control circuit

[0030] The main controller is an STM32F103C8T6 (ARM Cortex-M3 core, which is sufficient to meet the needs of small and medium-sized control). The circuit must include basic connections for power supply pins, clock pins, and reset pins.

[0031] In this embodiment, the structure of the core control circuit is as follows: Figure 7As shown, the circuit includes a resistor R1, four capacitors C1~C4, an HSE circuit, a switch K, and an STM32F103C8T6 chip. One end of the resistor R1 is connected to the input power supply, and the other end of the resistor R1 is connected to one end of the switch K, one end of the capacitor C1, and the NRST terminal of the STM32F103C8T6 chip. The other ends of the switch K and the capacitor C1 are grounded. The VDD terminal of the STM32F103C8T6 chip is connected to the input power supply and one end of the capacitor C2. The VSS terminal of the STM32F103C8T6 chip is connected to the other end of the capacitor C2 and then grounded. The PA8 terminal of the STM32F103C8T6 chip is connected to one end of the HSE circuit and one end of the capacitor C3. The PA9 terminal of the STM32F103C8T6 chip is connected to the other end of the HSE circuit and one end of the capacitor C4. The other end of the capacitor C4 is connected to the other end of the capacitor C3 and then grounded.

[0032] Capacitors C1 and C2 have the same capacitance value of 100nF. Capacitors C3 and C4 have the same capacitance value of 10pF.

[0033] Power connection: Connect the STM32's VDD (3.3V) to the power management unit output, connect VSS (ground) to system ground (GND), and connect a 100nF ceramic capacitor in parallel next to the power pin (for filtering and reducing power supply noise).

[0034] Clock circuit: The external high-speed crystal oscillator (HSE) is selected at 8MHz, and its two ends are connected to the OSC_IN (PA8) and OSC_OUT (PA9) of STM32 respectively, and each is connected in series with a 10pF capacitor to ground (for stable oscillation); the internal low-speed crystal oscillator (LSE) can be selected at 32.768kHz (for RTC real-time clock).

[0035] Reset circuit: The NRST pin of STM32 is connected to 3.3V through a 10kΩ resistor (pull-up, default high level), and is also connected to GND through a tactile button (reset when pressed), with a 100nF capacitor in parallel (to eliminate button bounce).

[0036] 2. Power Management Circuit

[0037] The external input is 12V DC (such as a lithium battery or adapter), which needs to be converted to 3.3V (for STM32 and logic circuits) and 5V (for sensors or relays).

[0038] like Figure 8As shown, the power management circuit specifically includes a DC-DC converter, a linear regulator, a transient voltage suppressor diode SMBJ1, four capacitors C5~C8, a resistor, and an inductor. One end of the resistor is connected to the external input power supply, and the other end is connected to one end of the transient voltage suppressor diode SMBJ1 and the input terminal VIN of the DC-DC converter. The other end of the transient voltage suppressor diode SMBJ1 is grounded. The output terminal of the DC-DC converter is connected to one end of capacitor C5 and one end of the inductor. The other end of the inductor is connected to one end of capacitor C6 and the input terminal of the linear regulator, serving as a 5V output terminal. The other ends of capacitors C5 and C6 are grounded. The output terminal of the linear regulator is connected to one end of capacitor C7 and one end of capacitor C8, serving as a 3.3V output terminal. The other ends of capacitors C7 and C8 are both grounded.

[0039] 5V Conversion: The MP2307 DC-DC converter (high efficiency, suitable for battery power) is used. The 12V input is connected to VIN, and the 5V output is connected to VOUT. An inductor (10μH) and capacitors (10μF electrolytic capacitor + 100nF ceramic capacitor) form a filter network to ensure stable output.

[0040] 3.3V Conversion: A linear regulator LM1117-3.3 is used. The input is 5V connected to IN, and the output is 3.3V connected to OUT. A 10μF electrolytic capacitor and a 100nF ceramic capacitor are connected in parallel at the output terminal (to suppress ripple).

[0041] Protection circuit: 500mA self-resetting fuse in series at the input (to prevent overcurrent), and TVS diode (such as SMBJ15A) in parallel at the 12V input terminal to prevent voltage spikes from damaging the circuit.

[0042] 3. Input interface circuit

[0043] like Figure 9 As shown, assuming an NTC temperature sensor (outputting a 0-3.3V analog signal) is connected, the signal needs to be acquired through the STM32's ADC pin: one end of the NTC is connected to 3.3V, the other end is connected to GND through a 10kΩ fixed resistor, the intermediate node (voltage divider point) is connected to the STM32's ADC input pin (e.g., PA0), and a 100nF capacitor is connected in series to ground (to filter high-frequency noise). If the input signal is 5V (e.g., a TTL sensor), it needs to be connected to the STM32's GPIO through a 74HC245 level converter chip (5V→3.3V) to avoid high-level damage to the MCU.

[0044] 4. Output interface circuit

[0045] Output interface circuit such as Figure 10 As shown, controlling a 220V AC load (such as a light bulb) requires isolating the high-voltage and low-voltage circuits using a relay. The STM32's GPIO (such as PB0) is connected to the input pin of the ULN2003 driver chip. The ULN2003's output pin is connected to one end of the relay coil, and the other end of the coil is connected to a 5V power supply (the ULN2003 contains an internal freewheeling diode to protect the circuit from damage caused by the coil's reverse electromotive force). The relay's normally open contact is connected in series with the 220V load and the power supply, and in parallel with a freewheeling diode (1N4007) across the contact (to suppress sparking when the contact opens).

[0046] 5. Communication interface circuit

[0047] In this embodiment, as Figure 11 As shown, the communication interface circuit includes a communication interface, a level conversion chip, an STM32 chip, and five capacitors C9~C13. One end of the communication interface is grounded, and the other end is connected to the R2IN terminal of the level conversion chip. One end of capacitor C9 is connected to a 3.3V power supply, and the other end is connected to the V+ terminal of the STM32 chip. The C1+ terminal of the STM32 chip is connected to one end of capacitor C10, and the other end of C10 is connected to the C1- terminal of the STM32 chip. The C2+ terminal of the STM32 chip is connected to... Connect one end of capacitor C11, and connect the other end of C11 to C2- of the STM32 chip; connect the V- of the STM32 chip to one end of capacitor C12, and connect the other end of C12 to ground; connect the VCC of the STM32 chip to one end of capacitor C13 and the 3.3V power supply voltage; connect the GND of the STM32 chip to the other end of capacitor C13 and then to ground; connect PA9 and PA10 of the STM32 chip to the USART1_TX and USART1_RX terminals of the STM32 chip, respectively.

[0048] The communication interface circuit is used to realize serial communication with a host computer (such as a PC). That is, the USART1_TX (PA9) and USART1_RX (PA10) of the STM32 are connected to the DB9 interface through the level conversion chip MAX232 (3.3V→RS232 level). The MAX232 requires four external 1μF electrolytic capacitors.

[0049] In this embodiment, the tap coefficient output module is a key component in a digital signal processing system (such as a filter or equalizer), responsible for generating and outputting the tap coefficients of the filter. Its structure and circuit design need to be combined with specific application scenarios (such as fixed coefficients or adaptive updates), hardware platforms (such as FPGAs or ASICs), and resource constraints.

[0050] In this embodiment, the main function of the convolution operation module is to complete the output signal of the previous stage. With tap coefficient The convolution operation is used to achieve digital filtering. The convolution operation of discrete signals can be expressed as:

[0051]

[0052] Among them, the Input signal of stage filter The number of data is Tap coefficient The number of ,and . No. The stage filter needs to process the output signal of the previous stage. and the Tap coefficients of a stage filter Perform a complete convolution operation, and the result is denoted as... The corresponding calculation process is as follows:

[0053]

[0054] A single convolution operation takes approximately Multiplication operations and The number of addition operations results in an output data volume of... indivual.

[0055] The first-stage filter needs to process the output signal of the previous stage. and the tap coefficients of the first-stage filter Perform a complete convolution operation, and the result is denoted as... The second-level filter then needs to refine the result of the previous convolution operation. Tap coefficients of the second-stage filter Perform a complete convolution operation, and the result is denoted as And so on. The cascaded filter bank needs to be completed accordingly. The nth complete convolution operation, the cascaded filter's nth... The first-stage filter is in the 1st stage. Based on the previous level, the result of the convolution operation is... With the Tap coefficients of a stage filter Perform a complete convolution operation, and the result is denoted as .

[0056] If a traditional structure is used in the design, then Cascaded filter banks in circuit structure consist of The filter bank is constructed by cascading convolution operation modules. As the data bit width and the number of tap coefficients increase, the number of cascades increases, and the circuit complexity of the corresponding filter module increases proportionally, resulting in higher hardware resource consumption and power consumption. In order to minimize the consumption of hardware resources while maintaining the filtering effect on the input signal, the design of the digital filter bank was improved based on the concept of structure reuse, thereby achieving the goal of simplifying the structure of the digital filter bank.

[0057] The present invention uses a two-stage cascaded digital decimation filter bank as an example for specific illustration. This digital decimation filter bank consists of two cascaded FIR filters. The first-stage filter, FIR1, is of order 12, and the second-stage filter, FIR2, is of order 68. The tap coefficients of both filters are symmetrical. The digital decimation filter bank operates in three modes: a) Mode 1: Both FIR1 and FIR2 are in bypass mode; b) Mode 2: FIR1 is active, and FIR2 is in bypass mode; c) Mode 3: Both FIR1 and FIR2 are active.

[0058] Accordingly, in mode 1, only the tap coefficients of FIR1 and FIR2 do not participate in the convolution operation; in mode 2, only the tap coefficients of FIR1 participate in the convolution operation; in mode 3, the input data is first convolved with the tap coefficients of FIR1, and the result is then convolved with FIR2.

[0059] For Mode 3, if a traditional structural design is used, a two-stage decimation filter structure needs to be constructed in space, as shown in the diagram. Figure 3 As shown. Physically, the input data first enters FIR1, and its calculation result is then output to FIR2. The output of FIR2 is the output of the entire two-stage decimation filter.

[0060] If a reuse-based design is adopted, the same convolutional operation structure needs to perform two concatenated convolution operations sequentially. Because the tap coefficients used in the two convolution operations are different, the two sets of tap coefficients need to be periodically and alternately imported into the convolution operation module to complete the corresponding operations. The corresponding operation logic is as follows: Figure 4 .

[0061] Figure 4In the diagram, the tap coefficients of FIR1 and FIR2 are output periodically, which aligns with the previous design concept. Since FIR1 is the pre-stage and FIR2 is the post-stage, and both undergo 2x decimation, the input / output data ratio of FIR1 is 2:1, and the same ratio applies to FIR2. Correspondingly, within the same time period, the ratio of the number of complete convolution operations performed by FIR1 and FIR2 is 2:1. The tap coefficient generation module in the diagram outputs two complete FIR1 coefficients and one complete FIR2 coefficient in each cycle, which is also consistent with the design. Because both FIR1 and FIR2 are 2x decimation filters, the cascaded result corresponds to a 4x decimation filter, and the 4:1 input / output data ratio in the diagram matches the design objective.

[0062] As shown above, based on the design concept of multiplexing structure and single-stage decimation filter circuit, two-stage convolution operation is completed through time-division multiplexing, thereby realizing two-stage decimation filtering in logic. This will inevitably significantly reduce the consumption of hardware resources and reduce the overall power consumption of the circuit.

[0063] During the digital-to-analog conversion process, because the maximum operating frequency that the subsequent digital signal processing module can handle is relatively low, the intermediate frequency (IF) signal cannot be directly input into this module for processing. Therefore, the IF signal needs to be shifted to a lower frequency band by a digital down-conversion module before being output to the subsequent digital signal processing module.

[0064] The above-described embodiments further illustrate the purpose, technical solution, and advantages of the present invention. It should be understood that the above-described embodiments are merely preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made to the present invention within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A digital decimation filter bank based on a multiplexing structure, characterized in that, include: A digital decimation filter bank is formed by cascading multiple digital decimation filters. Each digital decimation filter includes a control module, a tap coefficient output module, and a convolution operation module. The control module acquires user configuration information and generates clock and control signals for the corresponding operating mode. The tap coefficient output module generates tap coefficients for multiple filter stages and periodically outputs them alternately to the convolution operation module. The convolution operation module performs convolution operations on the previous stage output signal and the tap coefficients, and performs digital filtering.

2. The digital decimation filter bank based on a multiplexing structure according to claim 1, characterized in that, A digital decimation filter bank contains n digital decimation filters, where n is an integer greater than or equal to 2.

3. A digital decimation filter bank based on a multiplexing structure according to claim 1, characterized in that, User configuration information is dynamically written to the configuration information storage module via SPI, and a configuration list is generated.

4. A digital decimation filter bank based on a multiplexing structure according to claim 1, characterized in that, The control module includes: a main controller, a power management unit, an input interface circuit, an output interface circuit, a clock and reset circuit, and a communication interface circuit. The communication interface circuit connects the various circuits, enabling their electrical conduction. The power management unit provides stable voltage to each module. The input interface acquires input signals and inputs them to the main controller. The clock and reset circuit provides a stable clock signal and reset function to the main controller. The main controller processes the input signals and inputs the processed signals to the output interface circuit, outputting the clock and control signals corresponding to the operating mode through the output interface.

5. A digital decimation filter bank based on a multiplexing structure according to claim 1, characterized in that, The tap coefficient output module includes a control module, a counter, an address decoding module, and a coefficient register module. A control signal is input to the control module, which generates an instruction signal and inputs it to the counter. The counter counts, sends the count result to the address decoding module, and feeds it back to the control module. The address decoding module performs address decoding based on the count result. The coefficient register module addresses the input based on the decoding result from the address decoding module and periodically outputs the corresponding coefficient values ​​alternately.

6. A digital decimation filter bank based on a multiplexing structure according to claim 1, characterized in that, The convolution operation module includes a selection module, a multiplier, and a multiplexer. The input signal is input to the selection module for signal selection, the selected signal is delayed, and the delayed selected signal is input to the multiplier. Simultaneously, the output signal from the coefficient output module is delayed and then input to the multiplier. The multiplier multiplies the delayed selected signal and the delayed output signal. The multiplier's output signal, the selected signal, the delayed selected signal, and the multiplier's delayed signal are input to the multiplexer for selection to obtain the output signal. The output signal is then delayed and fed back to the selection module.

7. A digital decimation filter bank based on a multiplexing structure according to claim 6, characterized in that, The convolution operation module performs convolution operations on the input signals, including: ； in, For the first The stage filter needs to process the output signal of the previous stage. For the first The number of tap coefficients in a stage filter, where n is the number of tap coefficients. For the first Input signal of stage filter The number of data points.

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