Driving circuit and driving device

Abstract

The invention discloses a driving circuit and a driving device, and relates to the field of circuits, the driving circuit comprises a delay module and a driving module, the driving module comprises a first driving unit and a second driving unit, and the first driving unit and the second driving unit generate driving signals under the action of the delay module and control signals at the same time. A control signal generated according to an input signal of the driving circuit can respectively control the first driving unit and the second driving unit to be switched on or switched off, and a logic signal is converted into a driving signal through the switched-on first driving unit or the switched-on second driving unit; in combination with the delay processing of the delay module on the signal and the effect of the control signal, the condition that the first driving unit and the second driving unit are conducted at the same time is avoided, so that the conduction power consumption caused by the simultaneous conduction of the first driving unit and the second driving unit in the driving circuit is avoided, and the influence of through current on the driving capability of the driving module is prevented; and the realization of a small-area and low-power-consumption driving circuit is facilitated.

Description

Technical Field

[0001] This invention relates to the field of circuits, and in particular to a driving circuit and driving device. Background Technology

[0002] MIPI (Mobile Industry Processor Interface) is a high-performance, low-power, low-cost serial communication interface that standardizes internal device interfaces, including camera, display, and RF / baseband interfaces, thereby reducing design complexity and increasing design flexibility. A unified interface standard allows manufacturers to flexibly choose different chips and modules to implement device designs, and design and functional modifications are quick and convenient. Communication interfaces require driver circuits to convert the logic signals from the transmitting end into physical signals suitable for stable transmission over media (such as cables, optical fibers, and wireless channels). Generally, this involves converting logic signals into voltage signals for signal transmission. Therefore, designing the driver circuits for communication interfaces has become an important area of ​​development. Summary of the Invention

[0003] The purpose of this invention is to provide a driving circuit and driving device, which aims to provide a driving circuit that can meet the requirements of low power consumption mode, suppress overshoot voltage, and support a wide load range.

[0004] To solve the above-mentioned technical problems, the present invention provides a driving circuit, including a delay module and a driving module, wherein the driving module includes a first driving unit and a second driving unit;

[0005] The delay module is connected to the input terminal of the first driving unit and the input terminal of the second driving unit, respectively. The output terminal of the first driving unit and the output terminal of the second driving unit are connected, and the common terminal of the connection is used as the output terminal of the driving circuit.

[0006] The first driving unit and the second driving unit are turned on or off under the action of the delay module and the control signal to generate a driving signal; wherein, the control signal is generated according to the input signal of the driving circuit, and the on or off states of the first driving unit and the second driving unit are opposite.

[0007] Optionally, the first driving unit includes N uplink driving branches, and the second driving unit includes corresponding N downlink driving branches; N is a positive integer;

[0008] The N uplink drive branches and the N downlink drive branches are sequentially turned on or off under the action of the delay module and the control signal to generate the drive signal whose single jump amplitude is limited to a preset range; wherein, the on or off states of the nth uplink drive branch and the corresponding nth downlink drive branch are opposite, and n is a positive integer less than or equal to N.

[0009] Optionally, the uplink drive branch includes a first control unit, an uplink switch, and an uplink resistor; the downlink drive branch includes a second control unit, a downlink switch, and a downlink resistor.

[0010] The control terminal of the first control unit is used to receive the control signal. The input terminal of the first control unit is connected to the output terminal of the delay module. The output terminal of the first control unit is connected to the control terminal of the uplink switch. The first terminal of the uplink switch is connected to the first terminal of the uplink resistor. The second terminal of the uplink switch is connected to a first preset power supply.

[0011] The control terminal of the second control unit is used to receive the control signal. The input terminal of the second control unit is connected to the output terminal of the delay module. The output terminal of the second control unit is connected to the control terminal of the downlink switch. The first terminal of the downlink switch is connected to the first terminal of the downlink resistor. The second terminal of the downlink switch is connected to a second preset power supply. The second terminal of the uplink resistor and the second terminal of the downlink resistor are connected, and the common connection point serves as the output terminal of the drive circuit.

[0012] The first control unit and the second control unit are used to turn on or off according to the control signal to control whether the delayed input signal is transmitted to the corresponding uplink switch and downlink switch respectively;

[0013] The uplink switch or the downlink switch is used to turn on under the action of the delayed input signal; wherein the on or off states of the first control unit and the second control unit are opposite.

[0014] Optionally, both the first control unit and the second control unit include a corresponding transmission module and a control switch;

[0015] The input terminal of the transmission module is connected to the output terminal of the delay module. The control terminal of the transmission module is used to receive the control signal. The transmission module is used to turn on or off according to the control signal to control whether the input signal delayed by the delay module is transmitted to the corresponding uplink switch and downlink switch.

[0016] The first end of the control switch is connected to a third preset power supply, and the second end of the control switch is connected to the control terminals of the corresponding uplink and downlink switching transistors and the output terminal of the transmission module, respectively. The control switch is used to turn on or off according to the control signal to control the turn-off of the corresponding uplink and downlink switching transistors; wherein, the on or off states of the transmission module and the control switch are opposite.

[0017] Optionally, the transmission module includes a first transmission switch and a second transmission switch, and the control signal includes a first control signal and a second control signal;

[0018] The control terminal of the first transmission switch is connected to the first control signal, and the control terminal of the second transmission switch is connected to the second control signal;

[0019] The first end of the second transmission switch is connected to the second end of the first transmission switch, and the common end of the connection is connected to the output end of the delay module. The second end of the second transmission switch is connected to the first end of the first transmission switch, and the common end of the connection is connected to the second end of the control switch.

[0020] Optionally, the delay module includes N delay units corresponding to the N uplink drive branches and the N downlink drive branches;

[0021] The input terminal of each uplink drive branch and the input terminal of each downlink drive branch are connected to the output terminal of each delay unit.

[0022] Optionally, it also includes a control signal generation module, the input terminal of which is connected to the input terminal of the drive circuit, and the output terminal of which is connected to the input terminal of the first drive unit and the input terminal of the second drive unit, respectively.

[0023] The control signal generation module is used to generate the control signal based on the input signal.

[0024] Optionally, the control signal generation module is a signal inversion module, which is used to invert the input signal multiple times to obtain the control signal.

[0025] Optionally, the signal inverting module includes 2N inverters;

[0026] The 2N inverters are connected in series, and the 2N inverters output 2N control sub-signals according to the input signal; wherein the control signal includes the 2N control sub-signals, and N is a positive integer.

[0027] To solve the above-mentioned technical problems, the present invention also provides a driving device, including a transmitting end, a load capacitor, a receiving end, and a driving circuit as described above. The input end of the driving circuit is connected to the transmitting end, the first end of the load capacitor is connected to the output end of the driving circuit and the receiving end respectively, and the second end is grounded.

[0028] This invention provides a driving circuit, including a delay module and a driving module. The driving module includes a first driving unit and a second driving unit. The first and second driving units simultaneously generate driving signals under the action of the delay module and a control signal. The control signal generated according to the input signal of the driving circuit can control the first and second driving units to be turned on or off respectively. The logic signal is converted into a driving signal by turning on the first or second driving unit. Furthermore, by combining the delay processing of the signal by the delay module and the action of the control signal, the simultaneous conduction of the first and second driving units is avoided, thereby avoiding the conduction power consumption caused by the simultaneous conduction of the first and second driving units in the driving circuit, preventing the influence of the through current on the driving capability of the driving module, and facilitating the realization of a small-area, low-power driving circuit.

[0029] The present invention also provides a driving device that has the same beneficial effects as the driving circuit described above. Attached Figure Description

[0030] To more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the prior art and embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0031] Figure 1 A schematic diagram of a driving circuit provided for the prior art;

[0032] Figure 2 A schematic diagram of a driving circuit provided by the present invention;

[0033] Figure 3 A schematic diagram of the circuit structure of a driving circuit provided by the present invention;

[0034] Figure 4 This invention provides a schematic diagram of the structure of a first control unit corresponding to a first driving unit;

[0035] Figure 5 This is a schematic diagram of the structure of a second control unit corresponding to a second driving unit provided by the present invention;

[0036] Figure 6This is a schematic diagram of the overall signal path corresponding to a set of uplink drive branches and downlink drive branches provided by the present invention. Detailed Implementation

[0037] The core of this invention is to provide a driving circuit and driving device that effectively avoids the power consumption caused by the simultaneous conduction of the first driving unit and the second driving unit in the driving circuit, prevents the influence of the through current on the driving capability of the driving module, and is conducive to realizing a driving circuit with small area, low power consumption and support for a wide load range.

[0038] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0039] It should be noted that, to adapt to power consumption constraints in non-high-speed transmission scenarios and ensure the stability of low-speed transmission, the MIPI DPHY (D-Physical Layer) protocol includes an LP (Low-Power) mode for the communication interface. In LP mode, the driver circuit of the communication interface, when driving different load capacitances Cload, needs to control the output waveform (e.g., the voltage waveform corresponding to a voltage signal) so that both Tr (Rise Time) and Tf (Fall Time) are less than 25ns, and SR (Voltage Slew Rate) is within the range of 30-500mV / ns. The load capacitance Cload refers to the total equivalent capacitance presented at the load terminal driven by the driver circuit of the communication interface. It is equivalent to the total capacitance of the parasitic capacitance of LPTX (Low-Power Transmitter) to LPRX (Low-Power Receiver) transmission path and LPRX, typically 0-70pF.

[0040] See Figure 1 As shown, Figure 1This diagram illustrates the structure of a driving circuit in the prior art. The driving circuit uses LPTX and LPRX to perform signal conversion and transmission in LP mode. LPTX receives logic signals, converts them into driving signals, and sends the driving signals to the transmission link to achieve stable transmission. LPRX receives the driving signals transmitted from LPTX and restores them to logic signals, thus realizing complete signal transmission and communication. The driving signals include voltage signals. LPTX consists of two stages of inverters, which are implemented using MOS transistors (Metal-Oxide-Semiconductor Field-Effect Transistors). The inverter consists of MOSFETs M1 and M2 forming the first-stage inverter, and MOSFETs M3 and M4 forming the second-stage inverter. The logic signal LP_DATA is inverted by the first-stage inverter and then output to the second-stage inverter to control the on / off state of MOSFETs M3 and M4. When MOSFET M3 is on, LPTX converts the logic signal into a voltage signal AVDD; when MOSFET M4 is on, LPTX converts the logic signal into a voltage signal AVSS. A variable resistor R1 is connected between the two inverter stages, and a variable capacitor C1 is included in the second-stage inverter. An output resistor R2 is provided at the output terminal of LPTX. The voltage signal converted by LPTX is output to LPRX through the output terminal PAD_OUT. AVDD and AVSS are two power supplies with different supply voltages.

[0041] The load capacitance Cload varies depending on the application scenario, typically ranging from 0-70pF, which is a very large range. Figure 1 The voltage waveform of the output signal of the LPTX shown is affected by the load capacitance Cload. When the load capacitance Cload is at its minimum, the output waveform SR reaches its maximum value; when the load capacitance Cload is at its maximum, the output waveform Tr / Tf is at its maximum, and SR is at its minimum. In other words, the maximum and minimum values ​​of SR are mutually restrictive, and the maximum value of SR is also mutually restrictive with the maximum value of Tr / Tf. When the load capacitance Cload decreases, the output waveform Tr / Tf decreases, but the output waveform SR increases. Therefore, to meet the requirements of different load conditions and LP mode, the values ​​of the variable resistor R1 and the variable capacitor C1 need to be adjusted during the conversion process.

[0042] When the load capacitance Cload is relatively small, taking Cload = 0pF (minimum load capacitance Cload) as an example, the resistance of variable resistor R1 and the capacitance of variable capacitor C1 need to be adjusted to their maximum values ​​through the configuration register. This controls MOSFETs M3 and M4 to turn on slowly, thereby suppressing the SR of the output waveform and ensuring that the maximum value of SR does not exceed the Specification (30-500mV / ns). When the load capacitance Cload is relatively large, taking Cload = 70pF (maximum load capacitance Cload) as an example, the resistance of variable resistor R1 and the capacitance of variable capacitor C1 need to be adjusted to their minimum values. This allows MOSFETs M3 and M4 to turn on as quickly as possible, ensuring that the maximum value of Tr / Tf does not exceed the Specification (i.e., less than 25ns as required by the specification), and that the minimum value of SR does not exceed the Specification.

[0043] In this case, the user needs to constantly adjust the variable resistor R1 and variable capacitor C1 in the drive circuit according to the actual changes in the load capacitance Cload in order to meet the low power consumption requirements. This is cumbersome to operate. Furthermore, in different application scenarios, since the load capacitance Cload is different, it is necessary to configure the registers separately to make the variable resistor R1 and variable capacitor C1 meet the conditions, which makes the universality of the drive circuit in the existing technology poor. Furthermore, when the load capacitance Cload is at its maximum, even if the variable resistor R1 and the variable capacitor C1 are adjusted to their minimum, the turn-on or turn-off actions of MOSFETs M3 and M4 will still be relatively slow. This can lead to a situation where MOSFETs M3 and M4 are simultaneously turned on for an extended period, increasing the power consumption of the entire drive circuit. Simultaneous conduction of MOSFETs M3 and M4 will also create a current flowing from the power supply AVDD to the power supply AVSS in the drive circuit. This current weakens the driving capability of MOSFETs M3 and M4. To meet the Tr / Tf specification, the area of ​​MOSFETs M3 and M4 needs to be set very large to ensure their driving capability, which significantly increases the area of ​​the entire drive circuit.

[0044] Furthermore, the existing technology provides Figure 1The circuit shown exhibits a relatively high overshoot voltage during the data transition of the logic signal under low load conditions. Furthermore, MOSFET M3 (P-channel MOSFET) and MOSFET M4 (N-channel MOSFET) both drive the same output resistor R2 to output voltage signals when turned on. Since the N-channel MOSFET has a stronger driving capability than the P-channel MOSFET, the output waveform's Tr is typically greater than Tf, resulting in an imbalance between the rise time Tr and the fall time Tf. To address these problems in existing drive circuits, this application provides a drive circuit capable of achieving output drive circuitry that meets the requirements of MIPI DPHY low-power mode and a wide load range. Detailed implementation is described below.

[0045] See Figure 2 As shown, Figure 2 This is a schematic diagram of a driving circuit provided by the present invention, where PAD_OUT is the output port of the driving circuit; to solve the above technical problems, the present invention provides a driving circuit, including a delay module 1 and a driving module 2, wherein the driving module 2 includes a first driving unit 21 and a second driving unit 22;

[0046] The delay module 1 is connected to the input terminal of the first driving unit 21 and the input terminal of the second driving unit 22, respectively. The output terminal of the first driving unit 21 and the output terminal of the second driving unit 22 are connected, and the common terminal of the connection is used as the output terminal of the driving circuit.

[0047] The first driving unit 21 and the second driving unit 22 are turned on or off under the action of the delay module 1 and the control signal to generate a driving signal; wherein, the control signal is generated according to the input signal of the driving circuit, and the on or off states of the first driving unit 21 and the second driving unit 22 are opposite.

[0048] It should be noted that the driving circuit provided in this application includes a driving module 2 to convert logic signals into driving signals, and includes a first driving unit 21 and a second driving unit 22. The first driving unit 21 is connected to a first preset power supply AVDD. When the first driving unit 21 is turned on, it converts the logic signals input to the driving circuit into a first driving signal output corresponding to the first preset power supply AVDD. The second driving unit 22 is connected to a second preset power supply AVSS. When the second driving unit 22 is turned on, it converts the logic signals input to the driving circuit into a second driving signal output corresponding to the second preset power supply AVSS. The driving signals include the first driving signal and the second driving signal, and the driving signals can be voltage signals. For the drive module 2, this application sets up a control signal and a delay module 1 to control the on / off state of the first drive unit 21 and the second drive unit 22. The input signal of the drive circuit refers to the logic signal input to the drive circuit. The input signal is input to the first drive unit 21 and the second drive unit 22 respectively through the delay module 1. After the input signal is processed by the delay module 1 and transmitted to the first drive unit 21 and the second drive unit 22, it is used to control the on / off state of the first drive unit 21 and the second drive unit 22. The control signal is directly input to the first drive unit 21 and the second drive unit 22 to control the on / off state of the transmission channel when the input signal is transmitted to the first drive unit 21 and the second drive unit 22. That is, the control signal input to the first drive unit 21 can realize the on / off control between the output terminal of the delay module 1 and the first drive unit 21, and the control signal input to the second drive unit 22 can realize the on / off control between the output terminal of the delay module 1 and the second drive unit 22; and the control signal is input to the drive module 2 earlier than the input signal.

[0049] It should be noted that the delay module 1 is used to delay the input signal so that the input signal is input to the first drive unit 21 and the second drive unit 22 after the control signal has completed the control of the first drive unit 21 and the second drive unit 22. The control signal is first input to the first drive unit 21 and the second drive unit 22 to control the conduction or deactivation of the first transmission channel between the output terminal of the delay module 1 and the first drive unit 21, and to control the conduction or deactivation of the second transmission channel between the output terminal of the delay module 1 and the second drive unit 22. The conduction or deactivation states of the first transmission channel and the second transmission channel are opposite. When the logic signal needs to be converted into the first drive signal corresponding to the first preset power supply AVDD, the first transmission channel is turned on and the second transmission channel is turned off; when the logic signal needs to be converted into the second drive signal corresponding to the second preset power supply AVSS, the first transmission channel is turned off and the second transmission channel is turned on. After the control of the transmission channels is completed, the input signal processed by the delay module 1 is then input to the first drive unit 21 and the second drive unit 22 through the corresponding transmission channels. The first drive unit and the second drive unit are turned on or off under the control of the input signal after the delay processing to generate the drive signal.

[0050] Specifically, the input signal includes two states: high level (logic 1) and low level (logic 0). Switching between these two states, the output of the driving circuit also has two corresponding scenarios: the first transmission channel is active, and the first driving unit outputs the first driving signal; and the second transmission channel is active, and the second driving unit outputs the second driving signal. Taking the case where the input signal is high (logic 1), corresponding to the first transmission channel being active and the first driving unit 21 outputting the first driving signal, and the input signal is low (logic 0), corresponding to the second transmission channel being active and the second driving unit 22 outputting the second driving signal, as an example: the first driving unit 21 detects a high input signal... When the input signal is at a high level (logic 1), the first transmission channel is turned on, thereby generating a voltage signal corresponding to the first preset power supply AVDD, i.e., the first drive signal, which is equivalent to converting the high level (logic 1) of the input signal into the voltage signal corresponding to the first preset power supply AVDD. When the second drive unit 22 detects that the input signal is at a high level (logic 1), the second transmission channel is turned off; when the second drive unit 22 detects that the input signal is at a low level (logic 0), the second transmission channel is turned on, thereby generating a voltage signal corresponding to the second preset power supply AVSS, i.e., the second drive signal, which is equivalent to converting the low level (logic 0) of the input signal into the voltage signal corresponding to the second preset power supply AVSS. The correspondence between the input signal and the two transmission channels, and the correspondence between the input signal and the two drive signals, is not limited to the above embodiments, and this application does not impose any special limitations on them.

[0051] It should be noted that when the input signal level switches, for example, when the input signal level switches to a high level, the input signal after being delayed by the delay module 1 is transmitted to the first driving unit 21 through the first transmission channel, controlling the first driving unit 21 to switch from the off state to the on state, thereby generating the first driving signal. Before this, the control signal cuts off the connection between the input signal and the second driving unit 22 by controlling the second transmission channel to turn off, so that the second driving unit 22 directly switches from the on state to the off state under the action of the control signal. Since the level switching speed of the control signal (i.e., the data flipping speed of the logic signal) is faster than the level switching speed of the input signal after being processed by the delay module 1, when the input signal level switches to a high level, the second driving unit 22 is turned off first under the action of the control signal, and then the first driving unit 21 is turned on under the action of the input signal after being delayed by the delay module 1. That is, the turn-off of the second driving unit 22 will precede the turn-on of the first driving unit 21.

[0052] When the input signal level switches to a low level, the input signal delayed by the delay module 1 is transmitted to the second drive unit 22 through the activated second transmission channel, controlling the second drive unit 22 to switch from the off state to the on state, thereby generating the second drive signal. Before this, the control signal cuts off the connection between the input signal and the first drive unit 21 by controlling the first transmission channel to turn off, so that the first drive unit 21 switches from the on state to the off state under the action of the control signal. That is, when the input signal level switches to a high level, the first drive unit 21 is turned off first under the action of the control signal, and then the second drive unit 22 is turned on under the action of the input signal delayed by the delay module 1. In other words, the turn-off of the first drive unit 21 will precede the turn-on of the second drive unit 22.

[0053] Furthermore, this application does not impose any special limitations on the specific type and implementation method of the delay module 1, as long as it can achieve signal delay processing; this application does not impose any special limitations on the specific type and implementation method of the first driving unit 21 and the second driving unit 22, which can achieve voltage signal output by using the corresponding power supply through their own conduction or cutoff, thereby realizing the conversion of logic signals; specifically, it can be implemented using MOSFETs or other methods. This application does not impose any special limitations on the specific implementation method of the control signal, which needs to change with the changes in the input signal, and can be generated by multiplexing the input signal received at the input terminal of the driving circuit. Therefore, the control signal is also implemented using a level signal including high level (logic 1) and low level (logic 0).

[0054] This application provides a driving circuit that, through the setting of control signals and delay module 1, controls the conduction or cutoff of the first driving unit 21 and the second driving unit 22, thereby effectively avoiding the simultaneous conduction of the first driving unit 21 and the second driving unit 22. This prevents excessive power consumption and reduced driving capability caused by the simultaneous conduction of the first driving unit 21 and the second driving unit 22, and avoids the use of excessively large MOSFETs to implement the driving module 2. It also avoids the problems of excessively small SR and excessively large Tr / Tf when the load capacitance is at its maximum, and excessively large SR and large voltage overshoot when the load capacitance is at its minimum, caused by the simultaneous conduction of the first driving unit 21 and the second driving unit 22. Through the cooperation of control signals and delay module 1, the first driving unit 21 and the second driving unit 22 are turned off in advance by the control signal, so that all the current in the circuit can flow to the load capacitor through the first driving unit 21 or the second driving unit 22 controlled by the input signal. Compared with the prior art, a smaller MOSFET can be used to meet the driving requirements.

[0055] See Figure 3 As shown, Figure 3 The present invention provides a schematic diagram of the circuit structure of a driving circuit; as an optional embodiment, the first driving unit 21 includes N uplink driving branches, and the second driving unit 22 includes corresponding N downlink driving branches; N is a positive integer;

[0056] The N uplink drive branches and N downlink drive branches are sequentially turned on or off under the action of delay module 1 and control signals to generate drive signals with single jump amplitude limited to a preset range; wherein, the on or off states of the nth uplink drive branch and the corresponding nth downlink drive branch are opposite, and n is a positive integer not greater than N.

[0057] It should be noted that, in order to further avoid output voltage overshoot in the drive circuit, this embodiment sets up N uplink drive branches for the first drive unit 21 to output the voltage signal, and correspondingly sets up N downlink drive branches for the second drive unit 22 to output the voltage signal, so as to ensure the consistency between the rising and falling edges of the output voltage. The output terminal of the delay module 1 is connected to the input terminals of the N uplink drive branches and the N downlink drive branches respectively. The N uplink drive branches and the N downlink drive branches correspond one-to-one, the first uplink drive branch corresponds to the first downlink drive branch, and the Nth uplink drive branch corresponds to the Nth downlink drive branch. The corresponding uplink drive branch and the corresponding downlink drive branch form a group of drive branches. The on or off states of the uplink drive branch and the corresponding downlink drive branch in a group of drive branches are opposite, and a group of drive branches will simultaneously receive the corresponding control signal and input signal to turn on or off.

[0058] For any set of drive branches, the uplink drive branch and the downlink drive branch will first receive the control signal. In a preferred embodiment, the uplink drive branch and the downlink drive branch receive the control signal at the same time. After the control signal controls the on / off of the transmission sub-channel between the delay module 1 and the uplink drive branch or the downlink drive branch, the input signal processed by the delay module 1 is respectively input to the uplink drive branch and the downlink drive branch to control the conduction or de-conduction of the drive branch. In a preferred embodiment, the uplink drive branch and the downlink drive branch simultaneously receive the input signal output by the delay module 1 at the current time.

[0059] Furthermore, sequentially turning on or off refers to differentiating the action times of each group of drive branches through the delay module 1. Depending on the actual situation, the action times may differ between some groups of drive branches, or all different groups of drive branches may have different action times. The actions include turning on and turning off, which is not specifically limited in this application. Specifically, the delay module 1 performs N different degrees of delay processing on the input signal to obtain N delayed input signals, which are then input to the N groups of drive branches respectively. The N delayed input signals are all input signals themselves, differing only in the degree of delay. That is, the same input signal is input to the N groups of drive branches at N different times; for example, it is input to the first group of drive branches at the first time, to the second group of drive branches at the second time, and so on, until the Nth group of drive branches at the Nth time; or it may be input to the first and second groups of drive branches at the first time, to the third group of drive branches at the second time, and so on, until the Nth group of drive branches at the (N-1)th time. For the first drive unit 21, the conduction of the first drive unit 21 includes the conduction of the first uplink drive branch at the first moment, the conduction of the second uplink drive branch at the second moment, ... the conduction of the Nth uplink drive branch at the Nth moment; the second drive unit 22 is similar.

[0060] It should be noted that the number of driving branches that are turned on is positively correlated with the switching speed and amplitude of the output voltage. The more driving branches that are turned on, the faster the switching speed of the output voltage and the larger the amplitude of the output voltage. Therefore, by gradually and sequentially controlling the turn-on of N driving branches to realize the turn-on of the corresponding driving units, the switching speed of the output voltage (from the first driving signal corresponding to the first preset power supply AVDD to the second driving signal corresponding to the second preset power supply AVSS, or from the second driving signal corresponding to the second preset power supply AVSS to the first driving signal corresponding to the first preset power supply AVDD) can be effectively controlled, so that the amplitude of a single switching is limited within a preset range, avoiding voltage overshoot caused by rapid switching of the output voltage, thereby realizing the control of the SR of the output voltage. This application does not make any special limitations on the specific types and implementation methods of the uplink and downlink driving branches. The value of N can be set and adjusted according to actual needs. In a preferred embodiment, N is a positive integer greater than 1.

[0061] As a specific embodiment, such as Figure 3 As shown, taking N=4 as an example, after the input signal LP_DATA is processed by delay module 1, four input signals with different delay levels are generated, such as the first input signal DA0, the second input signal DA1, the third input signal DA2, and the fourth input signal DA3. The first input signal DA0, the second input signal DA1, the third input signal DA2, and the fourth input signal DA3 are respectively input to a corresponding set of drive branches. The first input signal DA0 is input to the uplink drive branch corresponding to switch MP0 and the downlink drive branch corresponding to switch MN0. The second input signal DA1 is input to the uplink drive branch corresponding to switch MP1 and the downlink drive branch corresponding to switch MN1. The third input signal DA2 is input to the uplink drive branch corresponding to switch MP2 and the downlink drive branch corresponding to switch MN2. The fourth input signal DA3 is input to the uplink drive branch corresponding to switch MP3 and the downlink drive branch corresponding to switch MN3. The delay module 1 implements four different levels of delay to achieve inconsistent transmission delay between the four sets of drive branches. When the first drive unit 21 needs to be turned on, the switches MP0, MP1, MP2, and MP3 corresponding to the four uplink drive branches are turned on in sequence. When the second drive unit 22 needs to be turned on, the switches MN0, MN1, MN2, and MN3 corresponding to the four downlink drive branches are turned on in sequence, thereby effectively suppressing the maximum value of SR and the overshoot of the output voltage.

[0062] Specifically, this embodiment divides the drive unit into multiple drive branches and controls the operation of the entire drive unit by controlling the operation of each drive branch separately. This effectively controls the drive capability of the drive unit and avoids problems such as excessive LPTX drive or voltage overshoot and excessive SR caused by rapid voltage switching under light load. The transmission delay of each drive branch is controlled separately to meet the specifications required by the MIPI DPHY protocol under all load conditions.

[0063] As an optional embodiment, the uplink drive branch includes a first control unit, an uplink switch, and an uplink resistor; the downlink drive branch includes a second control unit, a downlink switch, and a downlink resistor.

[0064] The control terminal of the first control unit is used to receive control signals. The input terminal of the first control unit is connected to the output terminal of the delay module 1. The output terminal of the first control unit is connected to the control terminal of the uplink switch. The first terminal of the uplink switch is connected to the first terminal of the uplink resistor. The second terminal of the uplink switch is connected to the first preset power supply AVDD.

[0065] The control terminal of the second control unit is used to receive control signals. The input terminal of the second control unit is connected to the output terminal of the delay module 1. The output terminal of the second control unit is connected to the control terminal of the downlink switch. The first terminal of the downlink switch is connected to the first terminal of the downlink resistor. The second terminal of the downlink switch is connected to the second preset power supply AVSS. The second terminal of the uplink resistor and the second terminal of the downlink resistor are connected, and the common connection point serves as the output terminal of the drive circuit.

[0066] The first control unit and the second control unit are used to turn on or off according to the control signal to control whether the delayed input signal is transmitted to the corresponding uplink switch and downlink switch respectively.

[0067] The uplink or downlink switch is used to turn on under the action of the delayed input signal; wherein, the on or off states of the first control unit and the second control unit are opposite.

[0068] It should be noted that, in order to ensure the consistency of the rise time Tr and fall time Tf of the output voltage as much as possible, the first driving unit 21 and the second driving unit 22 should maintain the same setting method, and the uplink resistor corresponding to the first driving unit 21 and the downlink resistor corresponding to the second driving unit 22 should be set as the output resistors respectively. Each uplink driving branch specifically includes a first control unit, an uplink switch and an uplink resistor; each downlink driving branch specifically includes a second control unit, a downlink switch and a downlink resistor. The first control unit and the second control unit are used to control whether the input signal after being delayed by the delay module 1 is transmitted to the corresponding uplink switch and downlink switch, that is, to realize the on / off of the transmission channel between the delay module 1 and the corresponding driving unit. The uplink switch and the downlink switch are used to realize the on / off of the corresponding driving unit by their own conduction or turn-off. When the uplink switch is on, the first preset power supply AVDD connected to its second terminal is output through the conducting uplink switch and the uplink resistor; when the downlink switch is on, the second preset power supply AVSS connected to its second terminal is output through the conducting downlink switch and the downlink resistor.

[0069] Specifically, due to the function of delay module 1, the level switching time of the control signal is earlier than the level switching time of the delayed input signal. When the input signal has a level switching, the control signal is first input to the first control unit and the second control unit to control the on / off state of the transmission channel. At this time, the control unit (first control unit or second control unit) corresponding to one of the uplink or downlink switches in the set of uplink and downlink switches that is in the on state will switch to the off state under the action of the control signal, thereby using the disconnection of the transmission channel to control one of the uplink or downlink switches that is currently in the on state to switch to the off state. Afterwards, the input signal processed by delay module 1 will be transmitted through the on transmission channel to another uplink or downlink switch (the other uplink or downlink switch in the set of uplink and downlink switches besides one of the uplink or downlink switches), controlling the other uplink or downlink switch to switch from the off state to the on state, thereby effectively avoiding the simultaneous on and off of the uplink and downlink switches.

[0070] It should be noted that this application does not impose any special limitations on the specific types and implementation methods of the first control unit, uplink switch, uplink resistor, second control unit, downlink switch, and downlink resistor. The first and second control units only need to be able to switch the corresponding transmission channels on and off. The uplink and downlink switches can be implemented using MOSFETs or similar methods. The resistance values ​​of the uplink and downlink resistors need to be set and adjusted according to the actual rising and falling edges of the output voltage signal in the actual application. The uplink and downlink resistors can be implemented using fixed resistors or variable resistors. By adjusting the resistance values ​​of the uplink resistor and / or the downlink resistor, the rising edge time (Tr) and falling edge time (Tf) of the voltage signal can be made closer. When the load capacitance is fixed, the larger the resistance value, the longer the corresponding rising or falling edge time. For example, when the Tr of the voltage signal is greater than Tf, the resistance value of the uplink resistor can be decreased and / or the resistance value of the downlink resistor can be increased to make Tr and Tf consistent, thereby achieving compliance with the SR, Tr, and Tf specifications required by the protocol under all load conditions. A preferred embodiment is that each uplink drive branch implements the first control unit, uplink switch, and uplink resistor in the same manner, and each downlink drive branch implements the second control unit, downlink switch, and downlink resistor in the same manner. This application does not impose any particular limitations on the specific types and implementation methods of the first preset power supply AVDD and the second preset power supply AVSS.

[0071] As a specific embodiment, such as Figure 3As shown, the supply voltage of the first preset power supply AVDD is greater than the supply voltage of the second preset power supply AVSS. In the uplink drive branch, SW switches (including SW0 for the first uplink drive branch, SW1 for the second uplink drive branch, SW2 for the third uplink drive branch, and SW3 for the fourth uplink drive branch) serve as the first control unit. P-channel transistors (including PMOS transistors MP0 for the first uplink drive branch, MP1 for the second uplink drive branch, MP2 for the third uplink drive branch, and MP3 for the fourth uplink drive branch) are used as uplink switches, connected to resistors RU0, RU1, RU2, and RU3 corresponding to the four uplink drive branches, respectively, as uplink resistors. For each uplink drive branch, the input signal received from the delay module 1 (first input signal DA0, second input signal DA1, third input signal DA2, or fourth input signal DA3) is connected to the corresponding PMOS transistor via the SW switch, and then reaches the output port PAD_OUT after passing through the corresponding uplink resistor. In the downlink drive branch, SWX switches (including SWX0 for the first downlink drive branch, SWX1 for the second downlink drive branch, SWX2 for the third downlink drive branch, and SWX3 for the fourth downlink drive branch) serve as the second control unit. N-channel transistors (including NMOS transistors MN0 for the first downlink drive branch, MN1 for the second downlink drive branch, MN2 for the third downlink drive branch, and MN3 for the fourth downlink drive branch) act as downlink resistors, connected to resistors RD0, RD1, RD2, and RD3 for the four downlink drive branches respectively. For each downlink drive branch, the input signal received from delay module 1 (first input signal DA0, second input signal DA1, third input signal DA2, or fourth input signal DA3) is connected to the corresponding NMOS transistor via the SWX switch, and then reaches the output port PAD_OUT after passing through the corresponding downlink resistor. The SW and SWX switches are controlled by control signals generated by control signal generation module 3.

[0072] Furthermore, considering that the uplink switch is implemented using a P-type transistor and the downlink switch is implemented using an N-type transistor, when the input signal LP_DATA is a high-level signal, the corresponding drive circuit outputs the first drive signal corresponding to the first preset power supply AVDD. In order to ensure accurate corresponding control relationship, an inverter U0 can be added to the drive circuit. The input terminal of the inverter U0 is connected to the input signal, and the output terminal is connected to the input terminal of the delay module 1. This allows the delay module 1 to control the P-type transistor to conduct based on the low-level signal obtained by inverting the input signal by the inverter U0 when the input signal LP_DATA is a high-level signal, thereby realizing the output of the voltage signal corresponding to the first preset power supply AVDD, that is, the output of the first drive signal.

[0073] Specifically, by setting different uplink and downlink resistors independently in the two drive units, and by having the power supply voltage flow through different circuits in the uplink and downlink drive branches respectively, the rise time (Tr) and fall time (Tf) of the final output voltage signal can be made closer by adjusting the resistance value of the uplink resistor and / or the resistance value of the downlink resistor, so as to meet the Tr / Tf specification and improve the consistency of the rise time (Tr) and fall time (Tf) of the voltage signal.

[0074] See Figure 4 As shown, Figure 4 This is a schematic diagram of the structure of a first control unit corresponding to a first driving unit provided by the present invention; see also Figure 5 As shown, Figure 5 This invention provides a schematic diagram of the structure of a second control unit corresponding to a second drive unit; as an optional embodiment, both the first control unit and the second control unit include corresponding transmission modules and control switches;

[0075] The input terminal of the transmission module is connected to the output terminal of the delay module 1. The control terminal of the transmission module is used to receive control signals. The transmission module is used to turn on or off according to the control signals to control whether the input signal delayed by the delay module 1 is transmitted to the corresponding uplink switch and downlink switch.

[0076] The first end of the control switch is connected to the third preset power supply, and the second end of the control switch is connected to the control terminal of the corresponding uplink switch and downlink switch and the output terminal of the transmission module, respectively. The control switch is used to turn on or off according to the control signal to control the turn-off of the corresponding uplink switch and downlink switch; wherein, the on or off states of the transmission module and the control switch are opposite.

[0077] It should be noted that, to ensure the early turn-off of the uplink or downlink switch, the first control unit and / or the second control unit specifically employ a transmission module and a control switch in conjunction. The transmission module of the first control unit is used to control the connection and disconnection of the transmission channel between the delay module 1 and the corresponding uplink drive branch. The control switch of the first control unit is used to specifically control the turn-off of the uplink switch when it needs to transition from the on state to the off state, ensuring that the uplink switch is not turned off solely due to the disconnection of the transmission channel, but rather through active and controllable turn-off under the action of the control switch. Similarly, the transmission module of the second control unit is used to control the connection and disconnection of the transmission channel between the delay module 1 and the corresponding downlink drive branch. The control switch of the second control unit is used to specifically control the turn-off of the downlink switch when it needs to transition from the on state to the off state. This application does not specifically limit the specific types and implementation methods of the transmission modules and control switches; the control switches can be implemented using switching devices such as MOSFETs. This application does not impose any specific limitations on the type and implementation method of the third preset power supply. It can directly reuse the preset power supply connected to the corresponding uplink or downlink switch. For example, the third preset power supply of the control switch of the first control unit can be directly reused from the first preset power supply AVDD, and the third preset power supply of the control switch of the second control unit can be directly reused from the second preset power supply AVSS. The control terminal of the control switch can also be activated by connecting a control signal.

[0078] Specifically, the control unit is implemented by combining a transmission module and a control switch. This allows the control unit to not only control the transmission channel through the transmission module to achieve early turn-off of the uplink or downlink switch, but also to actively control the uplink or downlink switch to achieve early turn-off through the control switch. The transmission module also provides further isolation. Through the combination of physical isolation and active switch control, the accurate realization of early turn-off of the uplink or downlink switch is ensured, improving the controllability, flexibility, and reliability of the early turn-off control process. This reduces current leakage of the uplink or downlink switch in the off state, further reducing power consumption.

[0079] As an optional embodiment, the transmission module includes a first transmission switch and a second transmission switch, and the control signal includes a first control signal and a second control signal;

[0080] The control terminal of the first transmission switch is connected to the first control signal, and the control terminal of the second transmission switch is connected to the second control signal.

[0081] The first end of the second transmission switch is connected to the second end of the first transmission switch, and the common end of the connection is connected to the output end of the delay module 1. The second end of the second transmission switch is connected to the first end of the first transmission switch, and the common end of the connection is connected to the second end of the control switch.

[0082] It should be noted that the transmission module can be implemented using a combination of a first transmission switch and a second transmission switch. The operation of the first and second transmission switches controls the switching on and off of the corresponding transmission channels. Accordingly, the control signals need to include a first control signal controlling the first transmission switch and a second control signal controlling the second transmission switch, thus achieving independent control of the two transmission switches in the transmission module through a set of control signals. This application does not specifically limit the specific types and implementation methods of the first and second transmission switches; the on and off states of the first and second transmission switches are identical.

[0083] As a specific embodiment, such as Figure 4 As shown, Figure 4 The diagram illustrates the specific implementation of the transmission module and control switch of the first control unit. The control switch of the first control unit is implemented using a PMOS transistor SW_P1. The transmission module of the first control unit uses a PMOS transistor SW_P0 to implement the first transmission switch and an NMOS transistor SW_N to implement the second transmission switch. In this case, the control switch of the first control unit is of the same type as the first transmission switch. Therefore, the control terminal of the control switch of the first control unit can be connected to a second control signal. By multiplexing the second control signal, the uplink switch transistor can be turned off, making the conduction state of the control switch opposite to the conduction state of the transmission module. Similarly, as... Figure 5 As shown, Figure 5 The diagram illustrates the specific implementation of the transmission module and control switch of the second control unit. The control switch of the second control unit is implemented using an NMOS transistor SWX_N1. The transmission channel of the second control unit uses an NMOS transistor SWX_N0 to implement the first transmission switch and a PMOS transistor SWX_P to implement the second transmission switch. In this case, the control switch of the second control unit is of the same type as the first transmission switch. Therefore, the control terminal of the control switch of the second control unit can be connected to a second control signal. By multiplexing the second control signal, the uplink switch transistor can be turned off. At this time, the set of control signals required by the first and second transmission switches needs to be kept in opposite states; that is, when the first control signal is high, the second control signal is low, and when the first control signal is low, the second control signal is high.

[0084] Specifically, the transmission module is implemented by combining the first transmission switch and the second transmission switch. The operation of the two transmission switches can effectively realize the switching on and off of the transmission channel, while realizing the control redundancy of the transmission channel and improving the reliability of the switching on and off control of the transmission channel.

[0085] As an optional embodiment, the delay module 1 includes N delay units corresponding to N uplink drive branches and N downlink drive branches;

[0086] The input terminal of each uplink drive branch and the input terminal of each corresponding downlink drive branch are connected to the output terminal of each corresponding delay unit.

[0087] It should be noted that, in order to achieve N different levels of input signal delay corresponding to the N uplink drive branches and N downlink drive branches, delay module 1 specifically sets up N delay units corresponding one-to-one with the N uplink drive branches (or N downlink drive branches). Each delay unit outputs an input signal after delaying the input signal to a different degree. This application does not specifically limit the specific type and implementation method of each delay unit. The delay times of each delay unit can be set differently or the same, and the different degrees of delay of the input signal are achieved through the connection method. Specifically, the delay unit can be implemented using a delay resistor and a delay capacitor. The first end of the delay resistor serves as the input terminal of the delay unit, used to receive the input signal. The first end of the delay capacitor is grounded, and the second end of the delay capacitor is connected to the second end of the delay resistor and serves as the output terminal of the delay unit. In practical applications, the resistance value of the delay resistor and / or the capacitance value of the delay capacitor in the delay unit can be flexibly adjusted according to requirements to adjust the delay time corresponding to each delay unit.

[0088] As a specific embodiment, taking N delay units connected in series as an example, the input terminal of the first delay unit is connected to the input signal, the output terminal of the (i-1)th delay unit is connected to the input terminal of the ith delay unit and the input terminal of the ith group of driving branches, and the output terminal of the Nth delay unit is connected to the input terminal of the Nth group of driving branches; i is a positive integer greater than or equal to 2 and less than or equal to N. Figure 3As shown, taking N=4 as an example, the four delay units are connected in series. The first delay unit includes a resistor R0 as a delay resistor and a capacitor C0 as a delay capacitor. The second delay unit includes a resistor R1 as a delay resistor and a capacitor C1 as a delay capacitor. The third delay unit includes a resistor R2 as a delay resistor and a capacitor C2 as a delay capacitor. The fourth delay unit includes a resistor R3 as a delay resistor and a capacitor C3 as a delay capacitor. Assuming that the four delay units use the same resistance and capacitance values ​​for delay resistors and capacitors, respectively, meaning the delay times for all four units are identical (denoted as t), after the input signal is input to the drive circuit, after time t, the first delay unit outputs the delayed first input signal DA0. After another time t (2t from the start of the input), the second delay unit outputs the delayed second input signal DA1. After another time t (3t from the start of the input), the third delay unit outputs the delayed third input signal DA2. After another time t (4t from the start of the input), the fourth delay unit outputs the delayed fourth input signal DA3. Thus, by using the four signals DA0-DA3, the transmission delay inconsistency between the four different drive branches is achieved, effectively suppressing the maximum SR value and voltage overshoot.

[0089] Specifically, by independently setting N delay units corresponding to N groups of drive branches, it is possible to effectively delay the input signal to N different degrees. Each delay unit is implemented independently, which is conducive to flexibly adjusting the transmission delay corresponding to each group of drive branches and improving the flexibility of the entire drive circuit.

[0090] As an optional embodiment, it also includes a control signal generation module 3, the input terminal of which is connected to the input terminal of the drive circuit, and the output terminal of which is connected to the input terminal of the first drive unit 21 and the input terminal of the second drive unit 22, respectively.

[0091] The control signal generation module 3 is used to generate control signals based on the input signals.

[0092] It should be noted that the on / off states of both the first driving unit 21 and the second driving unit 22 require control signals. Specifically, the output of the control signal generation module 3 is connected to the control terminals of the first control unit and the second control unit, respectively. When the transmission module is implemented using a combination of the first and second transmission switches, the control signal generation module 3 generates a set of control signals. The first control signal is connected to the control terminals of the first transmission switch in the first control unit and the second transmission switch in the second control unit, respectively. The second control signal is connected to the control terminals of the second transmission switch in the first control unit and the first transmission switch in the second control unit, respectively. Simultaneously, the control switches in the first and second control units can reuse either the first or second control signal to control the on / off state, making the on / off state of the control switch opposite to that of the transmission module. In this embodiment, the reuse of the second control signal by the control switch is mainly used as an example. For instance, the first control signal is SX0, and the second control signal is S0. SX0 is connected to the control terminals of the first and second transmission switches in the first and second control units, respectively. Control signal S0 is connected to the control terminal of the second transmission switch in the first control unit and the control terminal of the first transmission switch in the second control unit, respectively. At the same time, the control switches in the first and second control units can reuse the second control signal S0 to control the on or off state. When the first and second transmission switches in the first control unit are on, the control switch in the first control unit is off, and the corresponding uplink switch is turned on under the action of the input signal delayed by delay module 1. At this time, the first and second transmission switches in the second control unit are off, while the control switch in the second control unit is on, and the corresponding downlink switch is turned off under the action of power supply AVSS. When the first and second transmission switches in the first control unit are off, the control switch in the first control unit is on, and the corresponding uplink switch is turned off under the action of power supply AVDD. At this time, the first and second transmission switches in the second control unit are on, while the control switch in the second control unit is off, and the corresponding downlink switch is turned on under the action of the input signal delayed by delay module 1. This application does not impose any special restrictions on the specific type and implementation method of the control signal generation module 3. The input signal can be directly reused to generate the control signal, or the control signal can be generated in response to the change of the input signal after receiving the input signal.

[0093] Specifically, a control signal is generated by independently setting a control signal generation module 3 in the drive circuit. The generated control signal, in conjunction with the input signal, effectively controls the drive module 2.

[0094] As an optional embodiment, the control signal generation module 3 is a signal inversion module, which is used to invert the input signal multiple times to obtain the control signal.

[0095] It should be noted that, to ensure consistency between the control signal and the input signal, the input signal can be directly reused, and the control signal can be generated by processing the input signal. Furthermore, considering that the input signal itself is a level signal, and the control of transmission switches or control switches in the drive unit can mostly be implemented directly based on level signals, the control signal generation module 3 can be directly implemented using a signal inversion module, obtaining the control signal by inverting the input signal. Considering that there are multiple drive branches in the drive unit, and each drive branch requires a set of control signals, the signal inversion module needs to invert the input signal multiple times to obtain multiple sets of control signals, which are then distributed to different drive branches. This application does not specifically limit the specific type and implementation method of the signal inversion module.

[0096] Specifically, the input signal can be directly reused to generate the control signal. The control signal generation module 3 is implemented by using a signal inversion module. Several sets of control signals can be obtained directly by using the inversion processing operation. This is simple, effective and easy to implement.

[0097] As an optional embodiment, the signal inverting module includes 2N inverters;

[0098] 2N inverters are connected in series, and each inverter outputs 2N control sub-signals based on the input signal; wherein the control signals include 2N control sub-signals, and N is a positive integer.

[0099] It should be noted that, in order to correspond one-to-one with the N groups of drive branches, and considering that the first and second control units in each group of drive branches require a set of control signals to achieve effective control, the signal inversion module specifically includes 2N inverters. Each inverter outputs a control sub-signal, and the control sub-signal output by any inverter will serve as the first or second control signal required by the corresponding group of drive branches. Specifically, the input terminal of the first inverter is connected to the input signal, and the output terminals of the 2j-1 and 2j inverters are connected to the input terminal of the first control unit in the j-th group of drive branches (the j-th group of drive branches includes the j-th uplink drive branch and the j-th downlink drive branch). The control sub-signal output by the 2j-1 inverter serves as the first control signal of the control unit (first or second control unit) in the j-th drive branch, and the control sub-signal output by the 2j inverter serves as the second control signal of the control unit in the j-th drive branch; j is a positive integer less than or equal to N. Figure 3As shown, the control signal generation module 3 is equipped with 8 inverters. The final generated SX0 signal is used as the first control signal in the first group of drive branches, S0 signal is used as the second control signal in the first group of drive branches, SX1 signal is used as the first control signal in the second group of drive branches, S1 signal is used as the second control signal in the second group of drive branches, SX2 signal is used as the first control signal in the third group of drive branches, S2 signal is used as the second control signal in the third group of drive branches, SX3 signal is used as the first control signal in the fourth group of drive branches, and S3 signal is used as the second control signal in the fourth group of drive branches.

[0100] As one specific embodiment, see Figure 6 As shown, Figure 6 This is a schematic diagram of the overall signal path corresponding to a set of uplink drive branches and downlink drive branches provided by the present invention; the supply voltage of the first preset power supply AVDD is greater than the supply voltage of the second preset power supply AVSS. Figure 3The working process of the drive circuit is further explained in detail using the first set of drive branches shown (the set of drive branches corresponding to the first input signal DA0) as an example. The set of control signals generated by the control signal generation module 3 includes a first control signal SX0 and a second control signal S0. The first control signal SX0 is output to the control terminal of the first transmission switch in the first control unit and the control terminal of the second transmission switch in the second control unit, respectively. The second control signal S0 is output to the control terminal of the first transmission switch in the first control unit, the control terminal of the control switch in the first control unit, the control terminal of the second transmission switch in the second control unit, and the control terminal of the control switch in the second control unit, respectively. When the input signal LP_DATA is 0, the first input signal DA0, after being processed by the inverter U0 and the delay module 1, is 1, the first control signal SX0 generated by the control signal generation module 3 is 1, and the second control signal S0 is 0. In the first control unit of the first uplink drive branch, the first transmission switch (SW_P0) and the second transmission switch (SW_N) in the corresponding transmission module SW0 are turned off, and the corresponding control switch (SW_P1) is turned on, so that the control terminal of the uplink switch (MP0) is connected to the first preset power supply AVDD through the turned-on control switch (SW_P1), and the uplink switch (MP0) is quickly turned off. In the second control unit of the first downlink drive branch, the first transmission switch (SWX_N0) and the second transmission switch (SWX_P) in the corresponding transmission module SWX0 are turned on, and the corresponding control switch (SWX_N1) is turned off, so that the control terminal of the downlink switch (MN0) is disconnected from the second preset power supply AVSS. After the first input signal DA0, which is delayed by the delay module 1, is output to the control terminal of the downlink switch (MN0) through the turned-on transmission module SWX0, the first input signal DA0 drives the downlink switch (MN0) to turn on. Then the second preset power supply AVSS is output through the resistor RD0, so that the output port PAD_OUT is represented as 0 (the power supply voltage signal of the lower second preset power supply AVSS is output).

[0101] When LP_DADA toggles from 0 to 1 for data switching, S0 changes from 0 to 1, and both the first input signals DA0 and SX0 change from 1 to 0. At this time, in the second control unit of the first downlink drive branch, the first transmission switch (SWX_N0) and the second transmission switch (SWX_P) in the corresponding transmission module SWX0 are turned off, and the corresponding control switch (SWX_N1) is turned on, connecting the control terminal of the downlink switch (MN0) to the second preset power supply AVSS, thus turning off the downlink switch (MN0). Simultaneously, in the first control unit of the first uplink drive branch, the first transmission switch (SW_P0) and the second transmission switch (SW_N) in the corresponding transmission module SW0 are turned on, and the corresponding control switch (SW_P1) is turned off. After the control signal is completed, the DA0 signal drives the uplink switch (MP0) to turn on through the turned-on transmission module SW0. Due to the presence of delay module 1 (specifically, delay resistor R0 and delay capacitor C0), the first input signal DA0 will flip more slowly than the first control signal SX0 and the second control signal S0. Therefore, the transmission module SWX0 will quickly turn off the downlink switch (MN0) first, and then the first input signal DA0 will drive the uplink switch (MP0) to turn on. This avoids the simultaneous conduction of the uplink switch (MP0) and the downlink switch (MN0) in the first group of drive branches. At this time, after the first input signal DA0 drives the uplink switch (MP0) to turn on, the signal output to the output port PAD_OUT through resistor RU0 is 1 (the higher first preset power supply AVDD power supply voltage signal is output). The working principle of other groups of drive branches is similar, only the corresponding control signals and corresponding delayed input signals are different, which will not be described in detail in this application.

[0102] The driving circuit provided in this application utilizes control signals and delay module 1 to control the uplink switch in the first driving unit 21 and the downlink switch in the second driving unit 22, respectively. This effectively prevents the simultaneous conduction of the uplink and downlink switches, avoiding problems such as high power consumption and excessive area. Through the design of multiple driving branches and the design of delay module 1 to achieve inconsistent transmission delays between different groups of driving branches, the moment the input signal data flips, all driving switches (uplink or downlink switches) in the driving unit will not be immediately turned on, thereby effectively avoiding voltage overshoot and suppressing the maximum SR value of the output voltage signal. The uplink and downlink driving branches are independently designed with corresponding uplink and downlink resistors, respectively, to achieve voltage signal output. This allows the problem of Tr / Tf imbalance to be solved by adjusting the resistance values ​​of the uplink and downlink resistors. Through these designs, the entire driving circuit does not require the design of additional variable resistors or variable capacitors. This general-purpose driving circuit can meet the low power consumption requirements of the protocol and is suitable for all load conditions.

[0103] To solve the above-mentioned technical problems, the present invention also provides a driving device, including a transmitting end, a load capacitor, a receiving end, and a driving circuit as described above. The input end of the driving circuit is connected to the transmitting end, the first end of the load capacitor is connected to the output end and the receiving end of the driving circuit respectively, and the second end is grounded.

[0104] It should be noted that the driving circuit converts the logic signal to be transmitted by the transmitting end into a voltage signal and then transmits it to the receiving end. This application does not impose any special limitations on the specific types and implementation methods of the transmitting end, load capacitor, and receiving end. The transmitting end can be implemented using LPTX, where the driving circuit provided in this application is integrated to implement the logic signal conversion. The receiving end can be implemented using LPRX, where the load capacitor is the total equivalent capacitance presented by the load end driven by the driving circuit.

[0105] For a description of the driving device provided by the present invention, please refer to the above-described embodiment of the driving circuit; the present invention will not be described in detail here.

[0106] The various embodiments described in this specification are presented in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. It should also be noted that in this specification, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0107] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A driving circuit, characterized in that, It includes a delay module and a drive module, wherein the drive module includes a first drive unit and a second drive unit; The delay module is connected to the input terminal of the first driving unit and the input terminal of the second driving unit, respectively. The output terminal of the first driving unit and the output terminal of the second driving unit are connected, and the common terminal of the connection is used as the output terminal of the driving circuit. The first driving unit and the second driving unit are turned on or off under the action of the delay module and the control signal to generate a driving signal; wherein, the control signal is generated according to the input signal of the driving circuit, and the on or off states of the first driving unit and the second driving unit are opposite.

2. The driving circuit according to claim 1, characterized in that, The first driving unit includes N uplink driving branches, and the second driving unit includes corresponding N downlink driving branches; N is a positive integer; The N uplink drive branches and the N downlink drive branches are sequentially turned on or off under the action of the delay module and the control signal to generate the drive signal whose single jump amplitude is limited to a preset range; wherein, the on or off states of the nth uplink drive branch and the corresponding nth downlink drive branch are opposite, and n is a positive integer less than or equal to N.

3. The driving circuit according to claim 2, characterized in that, The uplink drive branch includes a first control unit, an uplink switch, and an uplink resistor; the downlink drive branch includes a second control unit, a downlink switch, and a downlink resistor. The control terminal of the first control unit is used to receive the control signal. The input terminal of the first control unit is connected to the output terminal of the delay module. The output terminal of the first control unit is connected to the control terminal of the uplink switch. The first terminal of the uplink switch is connected to the first terminal of the uplink resistor. The second terminal of the uplink switch is connected to a first preset power supply. The control terminal of the second control unit is used to receive the control signal. The input terminal of the second control unit is connected to the output terminal of the delay module. The output terminal of the second control unit is connected to the control terminal of the downlink switch. The first terminal of the downlink switch is connected to the first terminal of the downlink resistor. The second terminal of the downlink switch is connected to a second preset power supply. The second terminal of the uplink resistor and the second terminal of the downlink resistor are connected, and the common connection point serves as the output terminal of the drive circuit. The first control unit and the second control unit are used to turn on or off according to the control signal to control whether the delayed input signal is transmitted to the corresponding uplink switch and downlink switch respectively; The uplink switch or the downlink switch is used to turn on under the action of the delayed input signal; wherein the on or off states of the first control unit and the second control unit are opposite.

4. The driving circuit according to claim 3, characterized in that, Both the first control unit and the second control unit include corresponding transmission modules and control switches; The input terminal of the transmission module is connected to the output terminal of the delay module. The control terminal of the transmission module is used to receive the control signal. The transmission module is used to turn on or off according to the control signal to control whether the input signal delayed by the delay module is transmitted to the corresponding uplink switch and downlink switch. The first end of the control switch is connected to a third preset power supply, and the second end of the control switch is connected to the control terminals of the corresponding uplink and downlink switching transistors and the output terminal of the transmission module, respectively. The control switch is used to turn on or off according to the control signal to control the turn-off of the corresponding uplink and downlink switching transistors; wherein, the on or off states of the transmission module and the control switch are opposite.

5. The driving circuit according to claim 4, characterized in that, The transmission module includes a first transmission switch and a second transmission switch, and the control signal includes a first control signal and a second control signal; The control terminal of the first transmission switch is connected to the first control signal, and the control terminal of the second transmission switch is connected to the second control signal; The first end of the second transmission switch is connected to the second end of the first transmission switch, and the common end of the connection is connected to the output end of the delay module. The second end of the second transmission switch is connected to the first end of the first transmission switch, and the common end of the connection is connected to the second end of the control switch.

6. The driving circuit according to any one of claims 2 to 5, characterized in that, The delay module includes N delay units corresponding to the N uplink drive branches and the N downlink drive branches; The input terminal of each uplink drive branch and the input terminal of each downlink drive branch are connected to the output terminal of each delay unit.

7. The driving circuit according to claim 1, characterized in that, It also includes a control signal generation module, the input terminal of which is connected to the input terminal of the drive circuit, and the output terminal of which is connected to the input terminal of the first drive unit and the input terminal of the second drive unit, respectively. The control signal generation module is used to generate the control signal based on the input signal.

8. The driving circuit according to claim 7, characterized in that, The control signal generation module is a signal inversion module, which is used to invert the input signal multiple times to obtain the control signal.

9. The driving circuit according to claim 8, characterized in that, The signal inverting module includes 2N inverters; The 2N inverters are connected in series, and the 2N inverters output 2N control sub-signals according to the input signal; wherein the control signal includes the 2N control sub-signals, and N is a positive integer.

10. A driving device, characterized in that, It includes a transmitting end, a load capacitor, a receiving end, and a driving circuit as described in any one of claims 1 to 9, wherein the input end of the driving circuit is connected to the transmitting end, the first end of the load capacitor is connected to the output end of the driving circuit and the receiving end respectively, and the second end is grounded.

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