A communication method and communication device

Abstract

This application discloses a communication method and a communication device, relating to the field of network testing. Addressing the difficulty of reliably statistically analyzing large-scale data streams in ultra-high-speed scenarios, a communication method is provided, comprising: statistically analyzing feature data extracted within the current time window to obtain current statistical state data; reading historical statistical state data from shared memory; wherein, shared memory is a memory space shared by the software processor and the hardware processor, and directly accessible by the software processor; obtaining full statistical state data based on the current and historical statistical state data, the full statistical state data reflecting the statistical results of feature data extracted within the current and historical time windows; and writing the full statistical state data back to the shared memory as new historical statistical state data through direct memory access. Based on the above, this method can achieve reliable statistical analysis of massive data streams in ultra-high-speed scenarios.

Description

Technical Field

[0001] This application relates to the field of network testing, and in particular to a communication method and communication device. Background Technology

[0002] Faced with new application scenarios characterized by ultra-high speed, low latency, and massive traffic, next-generation network testing instruments must be able to capture, process, and analyze high-speed traffic data in real time to provide fine-grained, high-precision performance insights. Within this capability framework, traffic statistics, as a fundamental function of Layer 2-3 (i.e., data link layer and network layer) network testing equipment, is particularly crucial. To meet the flexibility requirements of testing instruments in various scenarios, a solution for implementing data flow-level statistics using Field Programmable Gate Arrays (FPGAs) is proposed. Currently, common data flow statistics solutions implemented using FPGAs primarily employ on-chip random access memory (RAM) direct storage.

[0003] In this approach, on-chip RAM serves as the sole real-time storage medium for statistical data. When statistical data is needed, it can be retrieved from the on-chip RAM via commands. The problem with this approach is that large-scale traffic or long-term statistical analysis typically requires storing numerous results, necessitating significant storage space. However, the capacity of on-chip RAM is severely limited, making it unsuitable for such demanding scenarios.

[0004] Therefore, those skilled in the art urgently need a communication method to meet the stringent requirements of achieving reliable statistics on large-scale data streams in ultra-high-speed scenarios. Summary of the Invention

[0005] This application discloses a communication method and communication device to solve the problem that it is difficult to reliably perform statistics on large-scale data streams in ultra-high-speed scenarios.

[0006] In a first aspect, this application provides a communication method executed by a hardware processor, comprising: receiving network packets and extracting feature data from the network packets; performing statistics on the feature data extracted within a current time window to obtain current statistical status data; reading historical statistical status data from shared memory; wherein the shared memory is a memory space shared by a software processor and the hardware processor and directly accessible by the software processor, the historical statistical status data reflects the statistical results of the feature data extracted within one or more historical time windows, the historical time windows being time windows prior to the current time window; obtaining full statistical status data based on the current statistical status data and the historical statistical status data, the full statistical status data reflecting the statistical results of the feature data extracted within the current time window and the one or more historical time windows; and writing the full statistical status data back to the shared memory as new historical statistical status data via direct memory access, so that the software processor obtains the full statistical status data from the shared memory.

[0007] As described above, this method uses a hardware processor (which can be an FPGA) to statistically analyze the feature data of network packets within the current time window to obtain dynamically updated current statistical status data based on the current time window. This process, implemented by the hardware processor, ensures minimal processing latency, meeting the needs of high-speed data stream statistics. Furthermore, this process only analyzes the feature data within the current time window; therefore, the hardware processor only needs to cache the feature data extracted within the current time window. Compared to analyzing all feature data received throughout the entire traffic statistics phase, which requires caching all feature data received throughout the entire traffic statistics phase on the hardware processor, this application significantly reduces the amount of data that the hardware processor needs to cache, thereby alleviating the pressure on the on-chip cache of the hardware processor. In addition, although this process only analyzes the feature data within the current time window, it can combine historical statistical status data to obtain full statistical status data. That is, when calculating full statistical status data in this method, the statistical results of previous current time windows (i.e., historical time windows) can be reused. Compared to statistically analyzing all characteristic data received throughout the entire traffic statistics phase to obtain full statistical status data, this application significantly reduces the amount of data requiring statistical operations, thereby improving statistical efficiency. Furthermore, based on the statistical method described above, since the on-chip storage resources of the hardware processor (such as the on-chip RAM of an FPGA) only need to store the current statistical status data and do not need to store historical statistical status data, the capacity requirements of the hardware processor's on-chip storage resources (such as the on-chip RAM of an FPGA) are reduced, preventing it from becoming a performance bottleneck under ultra-high-speed, massive data stream statistics, improving the statistical rate and the line rate of network traffic statistics that can be supported, and supporting large-scale traffic or long-cycle statistical needs. Further, for historical statistical status data collected in historical time windows prior to the current time window, this method stores it in shared memory. First, the current statistical status information can be fused with the historical statistical status data stored in shared memory to obtain full statistical status data, ensuring that the needs of full statistics are met. Second, shared memory is storage space outside the hardware processor, but it can be shared and directly accessed by both the hardware processor and the software processor (such as the CPU). By storing historical statistical status data in shared memory, the hardware processor can directly read or write the statistical status data through direct memory access. This read / write efficiency is far superior to off-chip storage solutions and also solves the capacity limitation problem of on-chip RAM direct storage. Thirdly, shared memory can also be directly read by the software processor. Although the shared memory stores historical statistical status data, the hardware processor performs a full fusion of the current statistical status data for each time window and writes the resulting full statistical status data back to the shared memory as new historical statistical status data. Therefore, it can be considered that the shared memory stores periodically updated full statistical status data.When the software processor needs to read full statistical status data for analysis or visualization, it can read it directly from shared memory. Shared memory, as part of the memory directly connected to the software processor, has extremely high read efficiency, significantly better than reading indirectly from the FPGA's on-chip RAM or from off-chip memory such as DDR. Therefore, this method can further improve efficiency in reading full statistical status data directly from the software processor, meeting the stringent requirements for reliable statistics on large-scale data streams in ultra-high-speed scenarios.

[0008] In one possible implementation, the step of statistically analyzing the feature data extracted within the current time window to obtain current statistical status data includes: after each extraction of feature data, reading the on-chip statistical data stored in the on-chip memory of the hardware processor; wherein the on-chip statistical data is: the statistical result of the feature data obtained from the start time of the current time window to the last feature data extraction time; performing a statistical operation on the currently extracted feature data and the on-chip statistical data to obtain the current statistical status data; and writing the current statistical status data back to the on-chip memory as new on-chip statistical data.

[0009] In this embodiment, real-time statistics of received feature data within the current time window are achieved through the on-chip memory of the hardware processor. As the hardware processor extracting and statistically analyzing feature data, using its internal on-chip memory to perform feature data statistics results in the lowest processing latency, meeting the processing needs of ultra-high-speed data stream statistics scenarios. In one possible implementation, the on-chip memory only stores the statistical results (i.e., the current statistical state data) and does not store the feature data. This further reduces the occupation of on-chip memory resources and avoids the on-chip memory capacity becoming a performance bottleneck for data stream statistics.

[0010] In one possible implementation, the feature data includes one or more of the following: packet count, packet length, latency, and jitter; the intra-chip statistical data includes one or more of the following: total packet count, total packet length, latest latency, maximum / minimum packet length, maximum / minimum latency, and maximum / minimum jitter, wherein the maximum / minimum values ​​include a maximum value and / or a minimum value; the statistical operation includes one or more of the following: accumulation operation, replacement operation, and comparison operation; wherein, the accumulation operation corresponds to packet count and / or packet length, and includes: accumulating the currently extracted packet count to the total packet count of the intra-chip statistical data, and / or accumulating the currently extracted packet length to the total packet length of the intra-chip statistical data; the replacement operation corresponds to latency, and includes: replacing the latest latency value of the intra-chip statistical data with the currently extracted latency value; the comparison operation corresponds to packet length, latency, and jitter, and includes: comparing the currently extracted packet length, latency, and jitter values ​​with the corresponding maximum or minimum value of the intra-chip statistical data; if it is greater than the maximum value, then update the maximum value; if it is less than the minimum value, then update the minimum value.

[0011] This embodiment presents a specific feature information scheme, including key features in the current flow statistics scenario such as packet count, packet length, latency, and jitter. Furthermore, it provides specific statistical operations for these features, including accumulation, replacement, and comparison operations. The statistical operations provided in this embodiment can complete the statistical work for the corresponding feature information, thereby meeting the needs of flow statistics.

[0012] In one possible implementation, the window duration of the current time window satisfies one or more of the following: statistical value overflow constraint, real-time processing capability constraint, and window operation time constraint; wherein, the statistical value overflow constraint includes: the product of the maximum number of packets received within the current time window and the maximum contribution value per packet is less than or equal to the maximum bit width of the on-chip memory; the maximum contribution value per packet is: the maximum number of packets and / or the maximum packet length in the network packets received within the current time window; the real-time processing capability constraint includes: the product of the effective processing time of the current time window and the processing rate is greater than or equal to the product of the arrival rate of the network packets and the window duration of the current time window; the effective processing time is: the window duration, the time between reading historical statistical status data from shared memory and ... and reading historical statistical status data from shared memory and the time between reading historical statistical status data and reading historical statistical status data from shared memory and the time between reading historical statistical status data and reading historical statistical status data from shared memory and the time between reading historical statistical status data and reading historical statistical The difference between the total execution time of obtaining full statistical status data from the data and the historical statistical status data, and the total execution time of writing the full statistical status data back to the shared memory as new historical statistical status data via direct memory access; the processing rate is the ratio of the clock frequency of the hardware processor to the number of clock cycles required for the hardware processor to process one network packet; the achieved rate is the ratio of the network line speed to the average packet size; the window operation time constraint includes: the total execution time of reading historical statistical status data from shared memory, obtaining full statistical status data based on the current statistical status data and the historical statistical status data, and writing the full statistical status data back to the shared memory as new historical statistical status data via direct memory access is less than or equal to the window duration of the current time window.

[0013] In this embodiment, a scheme for determining the window duration of the current time window is provided. The window duration is determined based on one or more of the following constraints: statistical value overflow, real-time processing capability, and window operation time. Specifically, when the window duration satisfies the statistical value overflow constraint, it ensures that the corresponding statistical item results in the on-chip memory will not overflow when statistical operations are performed within the current time window, guaranteeing the reliability of the statistics. When the window duration satisfies the real-time processing capability constraint, it ensures that, after completing the three necessary steps of reading historical statistical status data, determining full statistical status data, and writing back full statistical status data within the current time window, the remaining available effective processing time is still sufficient to extract and statistically analyze the feature data of all network packets received within the entire current time window. When the window duration meets the window operation time constraint, this method can ensure that the full fusion statistics are completed and updated to shared memory within the current time window (i.e., the three steps of reading historical statistical status data, determining full statistical status data, and writing back full statistical status data). In other words, it ensures that the statistical results of the current time window can be updated to shared memory within the current time window without affecting the statistics and updates of the next current time window, thus ensuring the timeliness of the statistics and the reliability of the statistical results.

[0014] In one possible implementation, the feature data includes: a flow identifier and feature information corresponding to the flow identifier, wherein the flow identifier is used to identify the network packet. The step of statistically analyzing the feature data extracted within the current time window to obtain current statistical status data includes: statistically analyzing the feature information extracted within the current time window corresponding to a first flow identifier to obtain current statistical status data corresponding to the first flow identifier, wherein the first flow identifier is the flow identifier of the most recently received network packet. The step of reading historical statistical status data from shared memory includes: reading historical statistical status data corresponding to the first flow identifier from the shared memory based on the first flow identifier. The step of obtaining full statistical status data based on the current statistical status data and the historical statistical status data includes: obtaining full statistical status data corresponding to the first flow identifier based on the current statistical status data corresponding to the first flow identifier and the historical statistical status data corresponding to the first flow identifier. The step of writing the full statistical status data as new historical statistical status data back to the shared memory via direct memory access, so that the software processor can obtain the full statistical status data from the shared memory, includes: writing the full statistical status data corresponding to the first stream identifier as new historical statistical status data corresponding to the first stream identifier back to the shared memory via direct memory access, so that the software processor can obtain the full statistical status data corresponding to the first stream identifier from the shared memory.

[0015] In this embodiment, stream identifiers are used to distinguish the characteristic information of different data streams, thereby enabling targeted stream statistics for different data streams. Additionally, stream identifiers are also used to distinguish different statistical status data in on-chip memory and shared memory. When the hardware processor or software processor needs to read or write statistical status data, it uses stream identifiers to read data from or write data to a specific location, thus completing the reading or updating of the statistical status data. By distinguishing the characteristic information and statistical status data of different data streams using stream identifiers, targeted stream statistics and storage of statistical results for different data streams are achieved, which is beneficial for meeting users' statistical needs for specific data streams.

[0016] In one possible implementation, before writing the full statistical status data back to the shared memory as new historical statistical status data via direct memory access, the method further includes: receiving the address information of the shared memory sent by the software processor; the step of writing the full statistical status data back to the shared memory as new historical statistical status data via direct memory access includes: accessing the memory space corresponding to the address information through the direct memory access engine and writing the full statistical status data.

[0017] In this embodiment, the hardware processor obtains the access address of the shared memory by receiving the shared memory address information sent by the software processor. Furthermore, the hardware processor can bypass the software processor and access the shared memory via direct memory access. This direct shared memory access method can improve the hardware processor's efficiency in reading and writing historical statistical state data, thereby better meeting the data flow statistics needs in ultra-high-speed scenarios.

[0018] In one possible implementation, access to the shared memory is restricted to allow only the hardware processor and the software processor to access it.

[0019] In this embodiment, an access restriction scheme is adopted for shared memory. Access to shared memory is restricted to only hardware processors and software processors, meaning shared memory is limited to data flow statistics for this method only. This prevents unrelated control devices or software services from accessing or even tampering with the data, ensuring the reliability and security of the statistics.

[0020] In one possible implementation, reading historical statistical status data from shared memory includes: periodically reading the historical statistical status data from the shared memory according to a preset time interval, and storing it in a buffer inside the hardware processor.

[0021] In this embodiment, a scheme is adopted to periodically trigger the reading of historical statistical status information from shared memory. The purpose of reading the historical statistical status information in this method is to perform full-scale fusion statistics, and then update the shared memory with the obtained full-scale statistical status data as new historical statistical status information for the software processor to read. Therefore, this embodiment provides a scheme for periodically updating statistical data in shared memory. On the one hand, this embodiment provides a logically simple and easy-to-implement mechanism for updating statistical data in shared memory. On the other hand, this scheme, based on the periodic setting, can promptly update the real-time statistical results (i.e., current status data) obtained by the hardware processor within the current time window to shared memory, ensuring the timeliness of the statistical data stored in shared memory.

[0022] In one possible implementation, the shared memory has a capacity greater than 16MB.

[0023] In this embodiment, the shared memory capacity is greater than 16MB. 16MB is the maximum capacity that on-chip RAM can typically achieve in data flow statistics implemented using hardware processors such as FPGAs with on-chip RAM direct storage. Therefore, this method, by using shared memory instead of on-chip RAM to directly store historical statistical state data, leverages the large capacity and easy scalability of shared memory, avoiding storage capacity becoming a bottleneck for data flow statistics performance and meeting the needs of statistics on massive data flows.

[0024] Secondly, this application provides a communication device, including: a hardware processor, a software processor, and memory; the hardware processor is configured to: receive network packets and extract feature data from the network packets; perform statistics on the feature data extracted within the current time window to obtain current statistical status data; read historical statistical status data from shared memory; wherein the shared memory is shared by the software processor and the hardware processor, and the shared memory is a storage space located in the memory that the software processor can directly access; the historical statistical status data reflects the statistical results of the feature data extracted within one or more historical time windows, and the historical time window is a time window before the current time window; obtain full statistical status data based on the current statistical status data and the historical statistical status data, the full statistical status data reflecting the statistical results of the feature data extracted within the current time window and the one or more historical time windows; write the full statistical status data back to the shared memory as new historical statistical status data through direct memory access; the software processor is configured to: obtain the full statistical status data from the shared memory for analysis or visualization.

[0025] The communication device provided in this application includes a hardware processor, a software processor, and memory. The hardware processor extracts and statistically analyzes the feature data of network packets, while the software processor consumes the statistical results. The key point is that this communication device uses a hardware processor (which may be an FPGA) to statistically analyze the feature data of network packets within the current time window, obtaining dynamically updated current statistical status data based on the current time window. This process, implemented by the hardware processor, ensures minimal processing latency, meeting the needs of high-speed data stream statistics. Furthermore, this process only analyzes the feature data within the current time window; therefore, the hardware processor only needs to cache the feature data extracted within the current time window. Compared to statistically analyzing all feature data received throughout the entire traffic statistics phase, which requires caching all feature data received throughout the entire traffic statistics phase in the hardware processor, this application significantly reduces the amount of data that the hardware processor needs to cache, thereby alleviating the pressure on the on-chip cache of the hardware processor. In addition, although this process only analyzes the feature data within the current time window, it can combine historical statistical status data to obtain full statistical status data. In other words, when calculating the full statistical status data using this method, the statistical results of the previous current time window (i.e., the historical time window) can be reused. Compared to statistically analyzing all feature data received during the entire traffic statistics phase to obtain the full statistical status data, this application can significantly reduce the amount of data requiring statistical operations, thereby improving statistical efficiency. Furthermore, based on the statistical method described above, since the on-chip storage resources of the hardware processor (such as the on-chip RAM of an FPGA) only need to store the current statistical status data and do not need to store historical statistical status data, the capacity requirements of the on-chip storage resources of the hardware processor (such as the on-chip RAM of an FPGA) are reduced, avoiding it becoming a performance bottleneck under ultra-high-speed, massive data flow statistics, and improving the statistical rate and the line rate of network traffic statistics that can be supported. Furthermore, for the historical statistical status data calculated in the historical time window before the current time window, this method stores it in shared memory. Firstly, the current statistical status information can be fused with the historical statistical status data stored in shared memory to obtain the full statistical status data, ensuring that the full statistical requirements are met. Secondly, shared memory is storage space outside the hardware processor, but it can be shared and directly accessed by both hardware and software processors (such as the CPU). By storing historical statistical status data in shared memory, the hardware processor can directly read or write the statistical status data through direct memory access. The read / write efficiency is far greater than that of off-chip storage transfer solutions, and it also solves the capacity limitation problem of on-chip RAM direct storage. Thirdly, shared memory can also be directly read by the software processor.Although the shared memory stores historical statistical status data, the hardware processor performs a full fusion statistical analysis on the current statistical status data for each time window and writes the resulting full statistical status data back to the shared memory as new historical statistical status data. Therefore, the shared memory can be considered to store periodically updated full statistical status data. When the software processor needs to read the full statistical status data for analysis or visualization, it can read it directly from the shared memory. As a part of the memory directly connected to the software processor, the shared memory has extremely high read efficiency, significantly better than reading indirectly from the FPGA's on-chip RAM or from off-chip memory such as DDR. Therefore, this method can further improve efficiency by reading the full statistical status data directly from the software processor, meeting the stringent requirements for reliable statistics on large-scale data streams in ultra-high-speed scenarios.

[0026] In one possible implementation, the step of statistically analyzing the feature data extracted within the current time window to obtain current statistical status data includes: after each extraction of feature data, reading the on-chip statistical data stored in the on-chip memory of the hardware processor; wherein the on-chip statistical data is: the statistical result of the feature data obtained from the start time of the current time window to the last feature data extraction time; performing a statistical operation on the currently extracted feature data and the on-chip statistical data to obtain the current statistical status data; and writing the current statistical status data back to the on-chip memory as new on-chip statistical data.

[0027] In this embodiment, the communication device uses the on-chip memory of the hardware processor to perform real-time statistics on the feature data received within the current time window. As the hardware processor extracting and statistically analyzing feature data, using its internal on-chip memory to perform the statistics results in the lowest processing latency, meeting the processing needs of ultra-high-speed data stream statistics scenarios. In one possible implementation, the on-chip memory only stores the statistical results (i.e., the current statistical state data) and does not store the feature data. This further reduces the occupation of on-chip memory resources and avoids the on-chip memory capacity becoming a performance bottleneck for data stream statistics.

[0028] In one possible implementation, the feature data includes one or more of the following: packet count, packet length, latency, and jitter; the intra-chip statistical data includes one or more of the following: total packet count, total packet length, latest latency, maximum / minimum packet length, maximum / minimum latency, and maximum / minimum jitter, wherein the maximum / minimum values ​​include a maximum value and / or a minimum value; the statistical operation includes one or more of the following: accumulation operation, replacement operation, and comparison operation; wherein, the accumulation operation corresponds to packet count and / or packet length, and includes: accumulating the currently extracted packet count to the total packet count of the intra-chip statistical data, and / or accumulating the currently extracted packet length to the total packet length of the intra-chip statistical data; the replacement operation corresponds to latency, and includes: replacing the latest latency value of the intra-chip statistical data with the currently extracted latency value; the comparison operation corresponds to packet length, latency, and jitter, and includes: comparing the currently extracted packet length, latency, and jitter values ​​with the corresponding maximum or minimum value of the intra-chip statistical data; if it is greater than the maximum value, then update the maximum value; if it is less than the minimum value, then update the minimum value.

[0029] This embodiment presents a specific feature information scheme, including key features in the current flow statistics scenario such as packet count, packet length, latency, and jitter. Furthermore, it provides specific statistical operations for these features, including accumulation, replacement, and comparison operations. The statistical operations provided in this embodiment can complete the statistical work for the corresponding feature information, thereby meeting the needs of flow statistics.

[0030] In one possible implementation, the window duration of the current time window satisfies one or more of the following: statistical value overflow constraint, real-time processing capability constraint, and window operation time constraint; wherein, the statistical value overflow constraint includes: the product of the maximum number of packets received within the current time window and the maximum contribution value per packet is less than or equal to the maximum bit width of the on-chip memory; the maximum contribution value per packet is: the maximum number of packets and / or the maximum packet length in the network packets received within the current time window; the real-time processing capability constraint includes: the product of the effective processing time of the current time window and the processing rate is greater than or equal to the product of the arrival rate of the network packets and the window duration of the current time window; the effective processing time is: the window duration, the time between reading historical statistical status data from shared memory and ... and reading historical statistical status data from shared memory and the time between reading historical statistical status data and reading historical statistical status data from shared memory and the time between reading historical statistical status data and reading historical statistical status data from shared memory and the time between reading historical statistical status data and reading historical statistical The difference between the total execution time of obtaining full statistical status data from the data and the historical statistical status data, and the total execution time of writing the full statistical status data back to the shared memory as new historical statistical status data via direct memory access; the processing rate is the ratio of the clock frequency of the hardware processor to the number of clock cycles required for the hardware processor to process one network packet; the achieved rate is the ratio of the network line speed to the average packet size; the window operation time constraint includes: the total execution time of reading historical statistical status data from shared memory, obtaining full statistical status data based on the current statistical status data and the historical statistical status data, and writing the full statistical status data back to the shared memory as new historical statistical status data via direct memory access is less than or equal to the window duration of the current time window.

[0031] In this embodiment, a scheme for determining the window duration of the current time window is provided. The window duration is determined based on one or more of the following constraints: statistical value overflow, real-time processing capability, and window operation time. Specifically, when the window duration satisfies the statistical value overflow constraint, it ensures that the corresponding statistical item results in the on-chip memory will not overflow when statistical operations are performed within the current time window, guaranteeing the reliability of the statistics. When the window duration satisfies the real-time processing capability constraint, it ensures that, after completing the three necessary steps of reading historical statistical status data, determining full statistical status data, and writing back full statistical status data within the current time window, the remaining available effective processing time is still sufficient to extract and statistically analyze the feature data of all network packets received within the entire current time window. When the window duration meets the window operation time constraint, this method can ensure that the full fusion statistics are completed and updated to shared memory within the current time window (i.e., the three steps of reading historical statistical status data, determining full statistical status data, and writing back full statistical status data). In other words, it ensures that the statistical results of the current time window can be updated to shared memory within the current time window without affecting the statistics and updates of the next current time window, thus ensuring the timeliness of the statistics and the reliability of the statistical results.

[0032] In one possible implementation, the feature data includes: a flow identifier and feature information corresponding to the flow identifier, wherein the flow identifier is used to identify the network packet. The step of statistically analyzing the feature data extracted within the current time window to obtain current statistical status data includes: statistically analyzing the feature information extracted within the current time window corresponding to a first flow identifier to obtain current statistical status data corresponding to the first flow identifier, wherein the first flow identifier is the flow identifier of the most recently received network packet. The step of reading historical statistical status data from shared memory includes: reading historical statistical status data corresponding to the first flow identifier from the shared memory based on the first flow identifier. The step of obtaining full statistical status data based on the current statistical status data and the historical statistical status data includes: obtaining full statistical status data corresponding to the first flow identifier based on the current statistical status data corresponding to the first flow identifier and the historical statistical status data corresponding to the first flow identifier. The step of writing the full statistical status data as new historical statistical status data back to the shared memory via direct memory access, so that the software processor can obtain the full statistical status data from the shared memory, includes: writing the full statistical status data corresponding to the first stream identifier as new historical statistical status data corresponding to the first stream identifier back to the shared memory via direct memory access, so that the software processor can obtain the full statistical status data corresponding to the first stream identifier from the shared memory.

[0033] In this embodiment, stream identifiers are used to distinguish the characteristic information of different data streams, thereby enabling targeted stream statistics for different data streams. Additionally, stream identifiers are also used to distinguish different statistical status data in on-chip memory and shared memory. When the hardware processor or software processor needs to read or write statistical status data, it uses stream identifiers to read data from or write data to a specific location, thus completing the reading or updating of the statistical status data. By distinguishing the characteristic information and statistical status data of different data streams using stream identifiers, targeted stream statistics and storage of statistical results for different data streams are achieved, which is beneficial for meeting users' statistical needs for specific data streams.

[0034] In one possible implementation, the software processor is further configured to: allocate a storage space in the memory as the shared memory; and send the address information of the shared memory to the hardware processor; when the hardware processor accesses the shared memory, it accesses the memory space corresponding to the address information through a direct memory access engine.

[0035] In this embodiment, the software processor, acting as a direct memory management processor, not only consumes statistical data but also performs shared memory allocation tasks. After allocating a storage space in memory as shared memory, the software processor sends the corresponding address information to the hardware processor. This allows the hardware processor to bypass the software processor and directly write to or read data from the shared memory using the direct memory access engine, reducing performance bottlenecks caused by data read / write latency.

[0036] In one possible implementation, the storage space allocated to the shared memory in the memory is greater than 16MB.

[0037] In this embodiment, the shared memory in the communication device provides a storage capacity greater than 16MB. 16MB is the maximum capacity of on-chip RAM in commonly used FPGAs. Therefore, this communication device can use a larger capacity shared memory to replace on-chip RAM for storing historical statistical status data, thus solving the statistical performance bottleneck caused by the capacity limitation of on-chip RAM.

[0038] In one possible implementation, the software processor is further configured to restrict access to the shared memory to only the hardware processor and the software processor.

[0039] In this embodiment, the software processor, acting as a controller that directly manages memory, is also used to restrict access permissions to the shared memory within the main memory. Specifically, access permissions to the shared memory are restricted to allow only the hardware processor and the software processor to access it. That is, the shared memory is restricted to only allowing data flow statistics. Based on this, this embodiment can effectively prevent the data in the shared memory from being accidentally tampered with, ensuring the reliability and security of the data flow statistics results.

[0040] In one possible implementation, reading historical statistical status data from shared memory includes: periodically reading the historical statistical status data from the shared memory according to a preset time interval, and storing it in a buffer inside the hardware processor.

[0041] In this embodiment, the communication device periodically triggers the reading of historical statistical status information from shared memory. The purpose of reading this historical statistical status information is to perform full-scale fusion statistics, and the resulting full-scale statistical status data is then used as new historical statistical status information to update the shared memory for the software processor to read. Therefore, this embodiment provides a scheme for periodically updating statistical data in shared memory. On the one hand, this embodiment provides a logically simple and easy-to-implement mechanism for updating statistical data in shared memory. On the other hand, this scheme, based on periodic settings, can promptly update the real-time statistical results (i.e., current status data) obtained by the hardware processor within the current time window to the shared memory, ensuring the timeliness of the statistical data stored in the shared memory.

[0042] In one possible implementation, the communication device is a network tester.

[0043] In this embodiment, a specific implementation of the communication device is provided, namely, a network tester. As a commonly used device for data stream statistics, the network tester, when implemented using the communication device provided in this application, can bring the advantages of the aforementioned communication device, namely, it can reliably perform statistics on massive data streams in ultra-high-speed scenarios.

[0044] In one possible implementation, the hardware processor is an FPGA and the software processor is a CPU.

[0045] This embodiment provides further details on the implementation of the hardware and software processors. This embodiment leverages the unique advantages of FPGAs in data signal processing—low latency and high parallel processing capabilities—to better meet the reliable statistical needs of communication devices for massive data streams in ultra-high-speed scenarios. Attached Figure Description

[0046] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0047] Figure 1 This is a schematic diagram of an application scenario provided by an embodiment of this application;

[0048] Figure 2 A flowchart illustrating a communication method provided in an embodiment of this application;

[0049] Figure 3A schematic diagram of a time window provided for an embodiment of this application;

[0050] Figure 4 A flowchart illustrating another communication method provided in an embodiment of this application;

[0051] Figure 5 This is a structural diagram of a communication device provided in an embodiment of this application.

[0052] Explanation of reference numerals in the attached figures:

[0053] 11-Hardware processor;

[0054] 12-Software processor;

[0055] 13-Memory;

[0056] 131 - Shared memory. Detailed Implementation

[0057] This application discloses a communication method and a communication device to solve the problem that traditional on-chip random access memory (RAM) direct storage statistical schemes cannot meet the reliability statistical needs of massive data streams in ultra-high-speed scenarios.

[0058] First, the main application scenarios of this application are explained: This method is mainly applied to traffic statistical analysis scenarios implemented through a network tester in layers 2 and 3 (i.e., the data link layer and the network layer) of the Open System Interconnection (OSI) seven-layer model. For example... Figure 1 As shown, network testers typically have N (variable number) physical ports, capable of capturing and analyzing various traffic data (such as packet count, byte count, protocol type, etc.) flowing through the network under test in real time. Through built-in data flow statistics logic, the network tester can accurately process and aggregate network traffic information. Ultimately, detailed traffic results (including distribution, trends, etc.) after statistical processing are clearly and intuitively displayed on the user's client monitoring interface, providing crucial information for network performance evaluation and troubleshooting.

[0059] In related technologies, network testers primarily utilize Field-Programmable Gate Arrays (FPGAs) to perform data flow statistics. Specifically, common data flow statistics solutions implemented using FPGAs mainly include on-chip RAM direct storage and off-chip memory transfer.

[0060] The core of the on-chip RAM storage solution is to use the on-chip RAM within the FPGA as the sole real-time storage medium for statistical data. The FPGA hardware logic directly writes real-time generated flow-level statistics (such as packet counts and byte counts) into the pre-allocated on-chip RAM space for accumulation. When external devices (such as other controllers in a network tester and clients) require statistical data, they can read the results from the on-chip RAM via instructions. However, this solution suffers from severely limited on-chip RAM capacity, making it unable to support large-scale traffic or long-cycle statistical needs. Furthermore, reading large amounts of statistical data is inefficient due to bus bandwidth and latency limitations.

[0061] Example 1:

[0062] To address the aforementioned problems, this application provides a communication method executed by a hardware processor. The method flow is as follows: Figure 2 As shown, it includes:

[0063] S11: Receive network packets and extract the characteristic data of the network packets.

[0064] S12: Perform statistics on the feature data extracted within the current time window to obtain the current statistical status data.

[0065] S13: Read historical statistical status data from shared memory; where shared memory is a memory space shared by the software processor and the hardware processor and directly accessible by the software processor, and historical statistical status data reflects the statistical results of feature data extracted within one or more historical time windows, where the historical time window is the time window preceding the current time window.

[0066] S14: Obtain full statistical status data based on current statistical status data and historical statistical status data. Full statistical status data reflects the statistical results of feature data extracted within the current time window and one or more historical time windows.

[0067] S15: Write the full statistical status data back to shared memory as new historical statistical status data through direct memory access, so that the software processor can obtain the full statistical status data from shared memory.

[0068] First, it should be noted that the hardware processor in the above methods refers to a device that implements functions through hardware processing circuits that do not have program instruction processing capabilities. A typical example is the FPGA mentioned in the related technologies. Alternatively, application-specific integrated circuits (ASICs) and other devices can also serve as the hardware processor. The software processor in the above methods refers to a device that implements functions by reading and executing program instructions stored in memory. A typical example is the CPU mentioned in the related technologies. Alternatively, it can be implemented using graphics processing units (GPUs), microcontroller units (MCUs), and other devices.

[0069] Specifically, regarding the implementation of step S11 above, the hardware processor can receive raw network packets through the network interface (EthernetMAC IP); then, the internal logic of the hardware processor parses the network packets, extracting all the required feature data. Since the format of the network packets is known, the specific parsing process is determined by the type of specific feature data required. Furthermore, this application does not limit the type of feature data, so the specific parsing scheme should be determined based on the actual statistical needs of the feature data.

[0070] For example, this application provides an optional specific embodiment for feature data: the feature data includes a flow identifier and feature information corresponding to the flow identifier, whereby the flow identifier is used to identify network packets. In this embodiment, the feature information is the specific network traffic data to be used for statistics, and the flow identifier is a unique identifier that distinguishes different data flows. Based on the setting of the flow identifier, traffic statistics can be performed separately for different data flows in the network traffic to meet the requirements of more refined and accurate traffic statistics. However, it should be noted that setting a flow identifier does not mean that comprehensive statistics of multiple or even all data flows cannot be performed. For example, the flow identifiers of multiple data flows can be set to be the same, thereby realizing comprehensive statistics among multiple data flows.

[0071] Furthermore, flow identifiers include, but are not limited to, flow unique codes (IDs) and the Media Access Control (MAC) address of the network packet destination. When using a flow ID as the flow identifier, it can be extracted from the packet header of the network packet. Feature information refers to the specific network traffic characteristics that need to be statistically analyzed. For example, one or more of the following: packet count, packet length, latency, and jitter. Further, after extracting the feature data, including the flow identifier and feature information, step S11 can associate the flow identifier with the corresponding feature information to obtain a feature data unit for subsequent statistical operations. In addition, after extracting the feature data, preprocessing work such as data cleaning can be performed; this embodiment does not limit this.

[0072] Next, for step S12, the first thing to clarify is the current time window. A time window can be a fixed duration (e.g., 1 second) or a variable duration. The current time window includes the current time T0. That is, the start time T1 of the current time window is earlier than (or equal to) the current time T0, and the end time T2 of the current time window is later than (or equal to) the current time T0, but the start time T1 and the end time T2 cannot be the same (i.e., the window duration T2-T1 cannot be 0). During the process of the hardware processor receiving network packets and extracting feature data in real time, the feature data extracted in real time participates in the statistics within the current time window.

[0073] For example Figure 3 As shown, the historical time window is the opposite of the current time window, that is, the time window that occurred before the current time window. Alternatively, the current time window can be implemented using a sliding window; that is, the historical time window can be considered as the "slid-through" current time window. It should be noted that this embodiment does not limit the specific duration of each of the time windows mentioned above. However, it should be understood that the window length of the historical time window can be the same as the current time window (e.g., ...). Figure 3 The window length (as shown) can also be inconsistent; the larger the current time window length, the more feature data it collects, and the greater the demand on the on-chip storage resources of the hardware memory; conversely, the smaller the current time window length, the more frequent the interaction between the hardware processor and shared memory (steps S13 and S15), and the greater the impact on statistical latency. Therefore, in practical applications, a suitable window length can be determined comprehensively based on one or more of the various requirements. It should also be noted that the above requirements are only a few optional examples, and many other requirements can be considered in practical applications.

[0074] For example, this application provides an optional embodiment for determining the window duration of the current time window:

[0075] The current time window duration satisfies one or more of the following constraints: statistical value overflow, real-time processing capability, and window operation time. In some implementations, the current time window duration satisfies all three constraints simultaneously, which is beneficial for improving statistical performance. In some implementations, the historical time window duration can satisfy one or more of the above three constraints. Regarding the above three constraints:

[0076] 1. The statistical overflow constraint conditions include: the product of the maximum number of packets received in the current time window and the maximum contribution value of each packet is less than or equal to the maximum bit width of the on-chip memory; the maximum contribution value of each packet is: the maximum number of packets and / or the maximum packet length in the network packets received in the current time window.

[0077] It's important to note that packet count is somewhat special; in practical applications, each network packet contributes 1 to the packet count. That is, when the characteristic data being analyzed is packet count, the maximum contribution value per packet is... C max_per_pkt The value is 1. However, in practical applications, packet length is generally measured in bytes. Therefore, the maximum contribution value per packet corresponding to the specified packet length is... C max_per_pkt That is, the maximum packet length of all network packets received within the current time window. Furthermore, the statistical overflow constraint can be expressed by the following formula:

[0078] ;

[0079] In the formula, Rate Indicates network line speed (unit: bps); S packer Indicates the average message size (unit: bits / packet); T window Indicates the duration of the current time window; C max_per_pkt This indicates the maximum contribution value per package; W on_chip This represents the bit width (in bits) allocated to each statistic (such as the number of packets, packet length, latency, and jitter in the example above).

[0080] Satisfying the statistical overflow constraint ensures that the statistical data stored on the chip will not overflow when the hardware processor performs statistics on network packets received within the current time window.

[0081] 2. Real-time processing capability constraints include: the product of the effective processing time and processing rate of the current time window is greater than or equal to the product of the arrival rate of network packets and the window duration of the current time window; the effective processing time is the difference between the window duration and the total execution time of the steps of reading historical statistical status data from shared memory, obtaining full statistical status data based on the current statistical status data and historical statistical status data, and writing the full statistical status data back to shared memory as new historical statistical status data through direct memory access; the processing rate is the ratio of the clock frequency of the hardware processor to the number of clock cycles required for the hardware processor to process one network packet; the arrival rate is the ratio of the network line speed to the average packet size.

[0082] Specifically, the real-time processing capability constraint reflects the requirement that the hardware processor must be able to handle the packet flow at line speed without packet loss. This requires the hardware processor's processing speed to be no less than the network packet arrival rate. Furthermore, an intermediate variable is used... μ Characterizing the processing rate / arrival rate, μ This is named the hardware processor's processing capacity margin coefficient. Based on the above definitions of processing rate and arrival rate, the following can be obtained: μ The expression:

[0083] ;

[0084] In the formula, F fpga Indicates the clock frequency of the hardware processor (FPGA) (unit: Hz); C packer This represents the number of clock cycles required for a hardware processor to process one network packet. Therefore, the processing speed of the hardware processor must be no less than the arrival rate of network packets, which can be expressed as... μ ≥1.

[0085] Furthermore, in this method, besides processing network packets (extracting and statistically analyzing feature data), the current time window also needs to perform full statistics and updates in steps S13-S15. Due to resource constraints, the aforementioned network packet processing is usually not possible during steps S13-S15. Therefore, it is further required that the current time window, excluding the execution of steps S13-S15, can still meet the processing needs of all network packets received in the entire current time window (network packets are still being sent out during the execution of steps S13-S15). Based on this, the real-time processing capability constraint can be expressed as follows:

[0086] ;

[0087] In the formula, R pkt Indicates message arrival rate. R pkt = Rate / S packer ; T overhead This represents the total execution time required for steps S13 to S15. Further, in an optional embodiment, steps S13 to S15 can be implemented using a pipeline approach. Therefore, there is some time overlap during the execution of these three steps S13 to S15, i.e.:

[0088] ;

[0089] In the formula,T read This represents the time (in seconds) for reading historical statistical status data from shared memory, i.e., the execution time of step S13. T read The calculation is as follows:

[0090] ;

[0091] express, N stats Number of statistical items (i.e., the number of specific types of feature data); W The bit width (unit: bits) indicates the statistical item. BW_mem This represents the bandwidth of shared memory (in bits).

[0092] T com This represents the time (in seconds) to obtain the full statistical status data based on the current and historical statistical status data, i.e., the execution time of step S14. T com The calculation is as follows:

[0093] ;

[0094] In the formula, C fusion This represents the number of clock cycles required for the fusion operation of a single statistical item.

[0095] T write This represents the time (in seconds) for writing all statistical status data back to shared memory, i.e., the execution time of step S15. T write The calculation is as follows:

[0096] ;

[0097] Furthermore, the expression for the above real-time processing capability constraints can be replaced by... μ To simplify, as shown below:

[0098] ;

[0099] Based on this, we can discuss the above regarding μ constraints μ ≥1 is tightened, and the tightened constraint is: μ >1. Meeting the real-time processing capability constraint ensures that the hardware processor can process network packets in real time throughout the entire traffic statistics process, guaranteeing the reliability of traffic statistics.

[0100] 3. The window operation time constraints include: the total execution time of the steps of reading historical statistical status data from shared memory, obtaining full statistical status data based on current statistical status data and historical statistical status data, and writing the full statistical status data back to shared memory as new historical statistical status data through direct memory access is less than or equal to the window duration of the current time window.

[0101] The window operation time constraint and the real-time processing capability constraint mentioned above focus on different aspects. As can be seen from the above, the real-time processing capability constraint focuses on the ability to process network packets within the current time window (i.e., corresponding to steps S11 and S12). The window operation time constraint, on the other hand, focuses on the ability to perform full fusion statistics and update statistical data in shared memory within the current time window (i.e., corresponding to steps S13-S15). Specifically, the window operation time constraint requires that the read, fusion, and write-back operations corresponding to steps S13-S15 must be completed by the end of each current time window. Therefore:

[0102] ;

[0103] Meeting the window operation time constraint means that the full fusion statistics and update of the corresponding current time window (i.e., steps S13~S15) can be completed within this current time window without affecting the traffic statistics of the next current time window, thus ensuring the timeliness and reliability of traffic statistics.

[0104] Furthermore, from the expressions for the real-time processing capability constraint and the window operation time constraint mentioned above, it can be seen that when the real-time processing capability constraint is satisfied, the window operation time constraint is also satisfied. Therefore, when the real-time processing capability constraint and the window operation time constraint are implemented together, only the real-time processing capability constraint needs to be considered when calculating the window duration constraint for the current time window.

[0105] Furthermore, this application provides a further embodiment: the window duration of the current time window simultaneously satisfies the statistical value overflow constraint, the real-time processing capability constraint, and the window operation time constraint. Then, by combining the above three constraints, the window length can be obtained. T window Must meet:

[0106] ;

[0107] The lower limit of the above formula corresponds to the real-time processing capability constraint (while also ensuring the window operation time constraint is met), ensuring that the hardware processor has enough time to process network packets within the current time window and complete the full fusion statistics and data updates in shared memory (i.e., at least one complete set of steps S11~S15 can be completed within the current time window). The upper limit of the above formula corresponds to the statistical value overflow constraint, ensuring that the hardware processor will not experience statistical value overflow due to on-chip memory bandwidth limitations within the current time window. Furthermore, the design must satisfy the condition that the lower limit ≤ the upper limit; otherwise, the system is infeasible. Further, when the lower limit > the upper limit, it can be addressed by reasonably increasing... W on_chip (But it cannot exceed the total capacity of on-chip storage resources), or increase the bandwidth of shared memory to ensure that the interval is not empty.

[0108] In some embodiments, to ensure the real-time nature of the statistical results, the statistics performed in step S12 within the current time window are not performed all at once after the current time window ends, covering all feature data received within the current time window. Instead, statistics are performed each time a network packet is received and feature data is extracted within the current time window. Specifically, this embodiment provides a suitable alternative solution, and step S12 specifically includes:

[0109] S121: After extracting feature data every N times, read the on-chip statistical data stored in the on-chip memory of the hardware processor.

[0110] The in-film statistical data refers to the statistical results of the feature data obtained from the start time of the current time window to the last feature data extraction time; N is any positive integer.

[0111] S122: Perform statistical operations on the extracted feature data and in-chip statistical data to obtain the current statistical status data.

[0112] S123: Write the current statistical status data back to the on-chip memory as new on-chip statistical data.

[0113] It should be noted that the specific type of on-chip memory mentioned above in this embodiment should be determined according to the type of hardware processor. That is, the on-chip memory should use the storage media commonly used on-chip by the corresponding hardware processor. A typical embodiment is the on-chip RAM of the FPGA in the above-mentioned related technologies, where the FPGA is the hardware processor and the on-chip RAM is the on-chip memory of the hardware processor. In addition, other implementation combinations can be used, and this embodiment does not limit them.

[0114] In one optional embodiment, setting N=1 allows for the following: after each extraction of feature data, the on-chip statistical data stored in the hardware processor's on-chip memory is read; statistical operations are performed on the extracted feature data and the on-chip statistical data to obtain the current statistical state data; and the current statistical state data is written back to the on-chip memory as new on-chip statistical data. Therefore, real-time statistics of the feature data received within the current time window can be achieved through the hardware processor's on-chip memory. As a hardware processor extracting and statistically analyzing feature data, using its internal on-chip memory to perform feature data statistics has the lowest processing latency, meeting the processing needs of ultra-high-speed data stream statistics scenarios. Furthermore, the on-chip memory only stores the statistical results (i.e., the current statistical state data) and does not store the feature data. This further reduces the occupation of on-chip memory resources and avoids the on-chip memory capacity becoming a performance bottleneck for data stream statistics.

[0115] In other embodiments, setting N>1 allows for the following: within the current time window, a statistical analysis is performed after multiple network packets are received and feature data is extracted. This helps reduce interaction between the hardware processor and shared memory and conserves computing resources. For example, a statistical analysis is performed after a preset number of network packets are received and feature data is extracted. Another example is performing a statistical analysis every preset time interval. Yet another example is performing a statistical analysis on all feature data received within the current time window after the current time window ends.

[0116] On the other hand, as can be seen from the above optional embodiment, network packets can be distinguished by flow identifiers to perform separate statistics on different data streams. Correspondingly, in the real-time statistics implemented in step S12, separate real-time statistics for different data streams can also be achieved based on flow identifiers. Specifically, a suitable optional embodiment is: to perform statistics on the feature information extracted within the current time window corresponding to the first flow identifier, to obtain the current statistical status data corresponding to the first flow identifier, where the first flow identifier is the flow identifier of the most recently received network packet. Similar to the above embodiment, distinguishing different data streams based on flow identifiers can make traffic statistics more refined and accurate, and can meet more diverse traffic statistics needs.

[0117] Furthermore, this embodiment does not limit the specific statistical operations actually performed in step S12; the corresponding statistical operations should be determined based on the selected feature information. For example, this embodiment provides a suitable implementation based on one or more of the above-mentioned feature information, including packet count, packet length, latency, and jitter: the on-chip statistical data includes one or more of the following: total packet count, total packet length, latest latency, maximum / minimum packet length, maximum / minimum latency, and maximum / minimum jitter, where maximum / minimum values ​​include the maximum value and / or minimum value; the statistical operations include one or more of the following: accumulation operation, replacement operation, and comparison operation.

[0118] The accumulation operation corresponds to packet count and / or packet length, including: accumulating the extracted packet count to the total packet count in the intra-chip statistics, and / or accumulating the extracted packet length to the total packet length in the intra-chip statistics. In practical applications, packet length can be represented by the number of bytes. Therefore, the statistical item of total packet length in the intra-chip statistics can be implemented using a counter (named the total byte count counter). The replacement operation corresponds to latency, including: replacing the latest latency value in the intra-chip statistics with the latency value extracted this time. The comparison operation corresponds to packet length, latency, and jitter, including: comparing one or more values ​​of packet length, latency, and jitter extracted this time with the maximum or minimum value corresponding to the intra-chip statistics; if it is greater than the maximum value, then update the maximum value; and / or if it is less than the minimum value, then update the minimum value. This embodiment provides a suitable statistical operation implementation scheme for the packet count, packet length, latency, and jitter features that are of key concern in the current stream statistics scenario. The statistical operations specifically include accumulation, replacement, and comparison operations to meet the statistical needs of the corresponding feature information.

[0119] Furthermore, regarding step S13, as defined in step S12 above regarding the current time window and historical time window, the current statistical status data acquired in real-time by the hardware processor can only characterize the network's traffic statistics within the current time window. Unless the current time window is the first time window after the start of statistics, the current statistical status data in the hardware processor is necessarily not the full statistical status data for this statistical process. In this method, the historical statistical status data collected in the historical time window (past) is stored in shared memory to avoid occupying the limited capacity of the hardware processor's on-chip memory. Based on this, step S13 requires data preparation before full statistics, that is, reading historical statistical status data from shared memory.

[0120] First, let's clarify shared memory: In this method, shared memory refers to a memory space that can be shared by both the software processor and the hardware processor, and that the software processor can directly access. In practical applications, software processors such as CPUs are usually equipped with corresponding memory to perform their functions. Therefore, shared memory can specifically be a pre-allocated memory space within the memory used in conjunction with the software processor. However, this memory space also needs to be shareable by the hardware processor, meaning that the hardware processor can read and write data (historical statistical status data) to this memory space.

[0121] This application does not impose any restrictions on the size of the shared memory. However, for on-chip RAM direct storage solutions in related technologies that suffer from storage resource bottlenecks, the largest commonly used on-chip RAM capacity in FPGAs is currently 16MB. Therefore, as long as the shared memory capacity used in this method is greater than 16MB, it can alleviate the performance bottleneck problem caused by storage capacity compared to on-chip RAM direct storage solutions. Based on this, this embodiment provides a suitable implementation scheme: the shared memory capacity is greater than 16MB. Optionally, the shared memory capacity can be 32MB, 64MB, 128MB, or other capacities greater than 16MB to better meet the reliable statistical needs of massive data streams in ultra-high-speed scenarios.

[0122] Furthermore, the capacity of shared memory is not fixed. As a memory space directly managed by the software processor, the capacity of shared memory is determined by the amount of memory allocated by the software processor. Therefore, through flexible allocation by the software processor, the capacity of shared memory can be dynamically expanded to adapt to the traffic statistics needs of different scenarios. Additionally, when determining the window duration of the current time window as described above, if no feasible solution for the window duration is found, a feasible solution for the window duration can be attempted by adjusting the shared memory capacity.

[0123] On the other hand, this embodiment also provides another optional implementation for shared memory: the access permission of shared memory is restricted to allow only hardware processors and software processors to access it. In some embodiments, the hardware processor needs to read data (step S13) and write data (step S15) to the shared memory, while the software processor only needs to read data from the shared memory (after step S15, it reads statistical results for subsequent analysis or visualization). Therefore, the access permission restriction in this embodiment can specifically be: restricting the shared memory to allow only hardware processors to read and write, and software processors to read.

[0124] In this embodiment, an access restriction scheme is adopted for shared memory. Access to shared memory is restricted to only hardware processors and software processors, meaning shared memory is limited to data flow statistics for this method. This prevents unrelated control devices or software services from accessing or even tampering with the data, ensuring the reliability and security of the statistics.

[0125] Furthermore, for the historical state data stored in shared memory, as in the optional embodiment provided above, different statistical state data of different data streams can be distinguished by the stream identifier. That is, step S13 can specifically be: obtaining the full statistical state data corresponding to the first stream identifier based on the current statistical state data corresponding to the first stream identifier and the historical statistical state data corresponding to the first stream identifier.

[0126] In other words, in this embodiment, step S13 does not need to read all historical statistical status data in the shared memory; it only needs to read the historical statistical status data related to the full-scale fusion statistics to be performed in step S14. Specifically, it only needs to read the historical statistical status data corresponding to the flow identifiers present in the current status data. On the one hand, this embodiment can achieve more flexible traffic statistics. On the other hand, it also helps to reduce the amount of data that the hardware processor reads from the shared memory, further reducing processing latency.

[0127] Next, regarding the specific method for obtaining the full statistical status data in step S14, it's easy to see that the statistical operations for obtaining the full statistical status data are similar to those for the real-time statistics in step S12, the difference being the data objects targeted. Real-time statistics target the feature information extracted from the currently received network packets and the on-chip statistical data stored in the on-chip memory. The full fusion statistics in step S13 target the current statistical status data of the hardware processor (i.e., the on-chip statistical data in the on-chip memory) and the historical statistical status data stored in shared memory. As in the specific embodiment of step S12, for the feature information being one or more of packet length, latency, and jitter, the corresponding statistical operation can also be one or more of accumulation, replacement, and comparison operations, which will not be elaborated upon in this embodiment.

[0128] Similarly, when using stream identifiers to distinguish the feature information and statistical status data of different data streams, step S14 specifically involves: obtaining the full statistical status data corresponding to the first stream identifier based on the current statistical status data and the historical statistical status data corresponding to the first stream identifier. As mentioned above, full-scale fusion statistics based on stream identifiers are more flexible and targeted, reducing irrelevant full-scale fusion statistics and further reducing processing latency.

[0129] On the other hand, as mentioned above, step S13 is one of the prerequisites for the execution of step S14. Therefore, the execution of step S13 can be used as the trigger condition for step S14 (in some embodiments, step S12 is performed in real time and is uncontrollable, so although the current statistical status data is also one of the necessary data for step S14, step S12 may not be used as the trigger condition for step S14). Based on this, this embodiment provides an optional execution scheme for step S13, which further includes: periodically reading historical statistical status data from shared memory according to a preset time interval and storing it in a buffer inside the hardware processor.

[0130] This embodiment has two key points: First, step S13 reads historical statistical status data periodically according to a preset time interval; that is, the full-volume fusion statistics performed in steps S13 and S14 are performed periodically according to a preset time interval; furthermore, the update of historical statistical status data in shared memory in step S15 is also performed periodically according to a preset time interval; based on the setting of the preset time interval, the timeliness of the traffic statistics results stored in shared memory can be guaranteed. Second, the historical statistical status data read by the hardware processor from shared memory is temporarily stored in the buffer inside the hardware processor, rather than in the on-chip memory; that is, in this embodiment, the on-chip memory is only used to store the current statistical status data (on-chip statistical data), further reducing the occupation of on-chip storage resources of the hardware processor and reducing the possibility that the capacity of on-chip memory will become a performance bottleneck.

[0131] In this embodiment, the specific value of the preset time interval is not limited. On one hand, the preset time interval can be consistent with the window length of the current time window. That is, each time the hardware processor completes the real-time statistics for a current time window in step S12, it triggers a full-scale fusion statistics in steps S13-S14. On the other hand, the preset time interval can also be determined based on the timeliness requirements of the software processor for traffic statistics. The shorter the preset time interval, the higher the timeliness of the traffic statistics results (historical statistical status data) stored in the shared memory. However, setting the preset time interval too short can also affect the real-time statistics process of the hardware processor and introduce new performance bottlenecks due to more frequent data interactions. Therefore, in practical applications, the setting of the preset time interval can take both of these aspects into consideration.

[0132] Furthermore, regarding step S15, after completing the full-scale fusion statistics in step S14, the latest statistical results (full-scale statistical status data) are updated to the shared memory to ensure the timeliness of the statistical results (historical statistical status data) stored in the shared memory for the software processor to access. It's important to note that in step S15, the hardware processor uses Direct Memory Access (DMA) to write data to the shared memory. This direct write method contrasts with the indirect write method where the hardware processor writes data to the shared memory indirectly through the software processor. The core difference is that the direct write scheme does not require a software processor as an intermediary; data flows directly from the hardware processor to the shared memory, with the data path being: hardware processor—shared memory. The indirect write scheme, on the other hand, requires the hardware processor to first send the data to the direct manager of the shared memory—the software processor—before the software processor writes the data to the shared memory, with the data path being: hardware processor—software processor—shared memory. DMA writing can be implemented using DMA tools, such as the PCIe-DMA engine (PCIe: a high-speed serial computer expansion bus standard).

[0133] In some embodiments, prior to step S15, the method further includes:

[0134] S10: Receive the shared memory address information sent by the software processor.

[0135] Step S15 specifically includes: accessing the memory space corresponding to the address information through the direct memory access engine and writing full statistical status data.

[0136] It should be noted that this embodiment does not limit the specific information included in the address information mentioned above, and it should be determined according to the allocation method of the shared memory. For example, if the shared memory is a contiguous space in memory, the address information only needs to include the start address and the total size (or end address) of the space. Conversely, if the shared memory consists of multiple non-contiguous spaces in memory, then the start address and size (or end address) of each non-contiguous space need to be included. In addition, if the start address or end address of the shared memory is a special address in memory (such as the end address of the shared memory being the end address of the memory), then the corresponding address information can be omitted from the address information.

[0137] Based on this embodiment, the hardware processor can obtain the address information of the shared memory. Therefore, when writing data to the shared memory subsequently, it can bypass the software processor and write data directly to the shared memory. This avoids the additional latency caused by unnecessary data forwarding and intermediate processing, further improving overall efficiency. It should also be noted that, apart from the data writing in step S15, the hardware processor can also bypass the software processor and directly read data from the shared memory in step S13 through direct memory access, thereby improving data reading efficiency.

[0138] Furthermore, as in the specific embodiments described above, which further refine the relationship between data (feature information or statistical status data) and data streams based on stream identifiers, step S15 can also be further refined based on the setting of stream identifiers. A suitable alternative embodiment is: writing the full statistical status data corresponding to the first stream identifier back to shared memory as new historical statistical status data corresponding to the first stream identifier through direct memory access, so that the software processor can obtain the full statistical status data corresponding to the first stream identifier from the shared memory. The advantages of using stream identifiers to represent the relationship between data and data streams have been described in detail in the above embodiments, which can be referred to in the above embodiments, and will not be repeated here.

[0139] Finally, to better illustrate the communication method provided in this application, this embodiment also provides a complete communication method flow, which is detailed below, based on the above embodiments. Figure 4 As shown: First is the initialization phase, corresponding to step S10 above. After the software processor completes the allocation of shared memory, it sends the corresponding address information to the hardware processor. The subsequent phase corresponds to the statistical phases S11 to S15 above. Finally, corresponding to the analysis phase, the software processor can read the statistical results obtained by the hardware processor from the shared memory (i.e., the historical statistical status data stored in the shared memory, which is also the full statistical status data obtained by the hardware processor in the last statistical analysis before reading), for subsequent analysis or visualization.

[0140] However, it should be noted that Figure 4 The statistical stage shown in the diagram is for simplification, only illustrating a complete statistical process. In practical applications, as described in the above embodiments, steps such as full-volume fusion statistics can be triggered periodically according to preset time intervals, and multiple times may be performed in a single data stream statistical analysis. The software processor can read the statistical results from the shared memory at any time. As long as the statistical results are stored in the shared memory, the software processor can read the statistical results from the shared memory whenever needed.

[0141] In summary, this application provides a communication method that uses a hardware processor (which may be an FPGA) to statistically analyze the feature data of network packets within the current time window to obtain dynamically updated current statistical status data based on the current time window. This process, implemented by the hardware processor, ensures minimal processing latency, meeting the needs of high-speed data stream statistics. Furthermore, this process only analyzes the feature data within the current time window; therefore, the hardware processor only needs to cache the feature data within the current time window. Compared to analyzing all feature data received throughout the entire traffic statistics phase, which requires caching all feature data received throughout the entire traffic statistics phase, this application significantly reduces the amount of data that needs to be cached, thereby alleviating the pressure on the on-chip cache of the hardware processor. In addition, this process only analyzes the feature data within the current time window and combines it with historical statistical status data to obtain full statistical status data; that is, previous statistical results can be reused when calculating full statistical status data. Compared to analyzing all feature data received throughout the entire traffic statistics phase to obtain full statistical status data, this application significantly reduces the amount of data requiring statistical operations, thereby improving computational efficiency. Since the on-chip storage resources of the hardware processor (such as the on-chip RAM of an FPGA) only need to store the current statistical status data and do not need to store historical statistical status data, the capacity requirements of the on-chip storage resources of the hardware processor (such as the on-chip RAM of an FPGA) are reduced, avoiding it from becoming a performance bottleneck under ultra-high-speed, massive data stream statistics, and improving the statistical rate and the number of network packets that can be counted. Furthermore, for historical statistical status data collected in historical time windows before the current time window, this method stores it in shared memory. First, the current statistical status information can be fused with the historical statistical status data stored in shared memory to obtain the full statistical status data, ensuring that the full statistical needs are met. Second, shared memory is a storage space outside the hardware processor, but it can be shared and directly accessed by both the hardware processor and the software processor (such as the CPU). By storing historical statistical status data in shared memory, the hardware processor can directly read or write statistical status data in shared memory through direct memory access, and the read / write efficiency is much higher than that of off-chip storage transfer schemes, which also solves the capacity limitation problem of direct storage in on-chip RAM. Third, shared memory can also be directly read by the software processor. Although the shared memory stores historical statistical status data, the hardware processor performs a full fusion statistical analysis on the current statistical status data for each time window and writes the resulting full statistical status data back to the shared memory as new historical statistical status data. Therefore, the shared memory can be considered to store periodically updated full statistical status data. When the software processor needs to read the full statistical status data for analysis or visualization, it can read it directly from the shared memory.Shared memory, as part of the memory directly connected to the software processor, boasts extremely high read efficiency, significantly outperforming indirect reads from the FPGA's on-chip RAM or external memories such as DDR. Therefore, this method can further improve efficiency by reading the full statistical state data directly from the software processor, thus meeting the stringent requirements for reliable statistics on large-scale data streams in ultra-high-speed scenarios.

[0142] Example 2:

[0143] Based on the above embodiments, this embodiment also provides a communication device, such as... Figure 5 As shown, the system includes a hardware processor 11, a software processor 12, and memory 13. The hardware processor 11 is used to: receive network packets and extract feature data from them; perform statistical analysis on the feature data extracted within the current time window to obtain current statistical status data; read historical statistical status data from shared memory 131; wherein shared memory 131 is shared by the software processor 12 and the hardware processor 11, and is a storage space located in memory 13 that the software processor 12 can directly access; the historical statistical status data reflects the statistical results of the feature data extracted within a historical time window, where a historical time window is one or more time windows prior to the current time window; obtain full statistical status data based on the current and historical statistical status data, which reflects the statistical results of the feature data extracted within the current and historical time windows; and write the full statistical status data back to shared memory 131 as new historical statistical status data through direct memory access. The software processor 12 is used to: obtain full statistical status data from shared memory 131 for analysis or visualization.

[0144] First, it should be noted that the hardware processor 11 in the communication device provided in this embodiment can implement all the implementation schemes provided on the hardware processor 11 side of the above-described method embodiments. Therefore, for specific embodiments of the hardware processor 11 in this communication device, please refer to the embodiments in the above-described method section, which will not be repeated here. The following mainly focuses on the aspects not described in the above-described method embodiments, as well as further explanations from the software processor 12 and memory side.

[0145] As defined in the above method embodiment section regarding the hardware processor 11 and software processor 12, the hardware processor 11 in this communication device can be an FPGA, ASIC, etc., and the software processor 12 can be a CPU, GPU, MCU, etc. In an optional embodiment, the hardware processor 11 in this communication device is specifically an FPGA, and the software processor 12 is specifically a CPU. Furthermore, the above method also illustrates that one of its main application scenarios is traffic statistics analysis occurring at the data link layer and network layer. In related technologies, traffic statistics in this scenario are generally performed using a network tester. That is, the communication device provided in this embodiment can perform the functions of a network tester. Based on this, this embodiment also provides an optional embodiment: this communication device is a network tester. That is, this communication device is used as a network tester in practical applications to implement traffic statistics functions.

[0146] Furthermore, regarding the aforementioned memory 13 and shared memory 131: Memory 13 is the storage medium used in conjunction with the software processor 12 in practical applications. The software processor 12 can directly access the memory (including reading and writing), and memory 13 is generally managed by the software processor 12. Shared memory 131 is a memory space within memory 13. Because shared memory 131 is a part of memory 13, the software processor 12 has access permissions to shared memory 131 and can directly access it (in traffic statistics, this access mainly refers to reading data from shared memory 131). And since the software processor 12 is the manager of memory 13, shared memory 131 within memory 13 is allocated by the software processor 12.

[0147] Furthermore, the shared memory 131 in this communication device also needs to be shareable by the hardware processor 11. That is, the hardware processor 11 also needs access permissions to the shared memory 131 (including reading and writing data), and this permission is typically allocated by the memory manager—the software processor 12. Moreover, in common collaborative work scenarios involving a CPU (a type of software processor 12) and an FPGA (a type of hardware processor 11), if the FPGA needs to access the memory 13 (shared memory 131) directly managed by the CPU, it generally needs to indirectly access it through the CPU as an intermediary. This causes unnecessary data forwarding, resulting in additional processing latency, which is detrimental to meeting the traffic statistics requirements in ultra-high-speed scenarios. Therefore, this communication device requires the hardware processor 11 to bypass the software processor 12 and complete data reading and writing to the shared memory 131 through direct memory access.

[0148] To achieve this objective, this embodiment provides a suitable implementation scheme for the software processor 12: the software processor 12 is further configured to allocate a storage space in the memory 13 as shared memory 131; and send the address information of the shared memory 131 to the hardware processor 11. Based on this, when the hardware processor 11 accesses the shared memory 131, it can access the memory space corresponding to the address information through the direct memory access engine. This direct access method to the shared memory 131 can improve the read and write efficiency of the hardware processor 11 for historical statistical status data, thereby better meeting the data flow statistics needs in ultra-high-speed scenarios.

[0149] On the other hand, as can be seen from the description of related technologies in some embodiments of the above method, the maximum capacity of on-chip RAM in devices such as FPGAs is currently typically 16MB. Therefore, as long as the capacity of the shared memory 131 in this communication device is greater than 16MB, this communication device can alleviate the performance bottleneck caused by the limited on-chip storage resources of the hardware processor 11 to a certain extent through the shared memory 131. Based on this, this embodiment provides an optional implementation: the storage space allocated to the shared memory 131 in memory 13 is greater than 16MB.

[0150] On the other hand, as can be seen from the embodiments of the above method section, access permissions to shared memory 131 can also be restricted to prevent statistical data from being tampered with, thereby improving the reliability and security of traffic statistics. As described above, the software processor 12, as the direct manager of memory, can manage the access permissions to shared memory 131 in memory 13. Based on this, this embodiment provides an optional implementation scheme for the software processor 12: the software processor 12 is further used to restrict the access permissions to shared memory 131 to only allow access by hardware processor 11 and software processor 12. In this embodiment, the software processor 12, as the controller directly managing memory, is also used to restrict access permissions to shared memory 131 in memory 13. Specifically, the access permissions to shared memory 131 are restricted to only allow access by hardware processor 11 and software processor 12. That is, shared memory 131 is restricted to only allowing data flow statistics. Based on this, this implementation can effectively prevent the data in shared memory 131 from being tampered with, ensuring the reliability and security of data flow statistics results.

[0151] In summary, the communication device provided in this embodiment includes a hardware processor 11, a software processor 12, and memory 13. The hardware processor 11 is used to extract and statistically analyze feature data from network packets, while the software processor 12 consumes the statistical results. Crucially, the hardware processor 11 performs feature data statistics within a small range based on a preset time window (the current time window). This ensures that even when the communication device is used to analyze massive data streams, the amount of data directly analyzed and temporarily stored in the hardware processor 11 is not excessive, preventing the on-chip storage resources of the hardware processor 11 from becoming a performance bottleneck. Furthermore, the time window for statistical analysis by the hardware processor 11 is the current time window, corresponding to the feature data extracted from the real-time received network packets, ensuring low-latency processing for data statistics in ultra-high-speed scenarios. In addition, the statistical status data (full statistical status data) obtained by the hardware processor 11 in this communication device is ultimately stored in shared memory 131 (historical statistical status data). On the one hand, shared memory 131, as part of memory 13, has a larger capacity and is easier to expand than the on-chip RAM of the FPGA, effectively solving the problem of limited capacity of on-chip RAM direct storage solutions. On the other hand, as a storage space within memory 13 that can be directly accessed by both the hardware processor 11 and the software processor 12, shared memory 131 minimizes the access latency caused by using off-chip memory, thereby ensuring that this communication device can meet the data flow statistics needs in ultra-high-speed scenarios.

[0152] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc.

[0153] In this application, "functions implemented by a software processor" refers to the software processor reading and executing program instructions stored in memory to implement the functions of the above embodiments. A software processor refers to a processing circuit capable of executing program instructions, including but not limited to at least one of the following: a central processing unit (CPU), a microprocessor, a microcontroller unit (MCU), or an artificial intelligence processor, and other processing circuits capable of running program instructions. In other embodiments, the software processor may also include circuits with other processing functions (such as hardware circuits for hardware acceleration, bus and interface circuits, etc.). The software processor can be presented as an integrated chip, for example, as an integrated chip whose processing function only includes executing software instructions, or it can be presented as a SoC (system on a chip), that is, on a single chip, in addition to the processing circuit capable of running program instructions (often referred to as a "core"), it also includes other hardware circuits for implementing specific functions (of course, these hardware circuits can also be implemented separately based on ASICs or FPGAs). Correspondingly, the processing functions, in addition to executing software instructions, may also include various hardware acceleration functions (such as AI calculation, encoding / decoding, compression / decompression, etc.).

[0154] In this application, "implementing functions by a hardware processor" means implementing the functions of the above embodiments through a hardware processor that does not have program instruction processing capabilities. This hardware processor can be composed of discrete hardware components or integrated circuits. To reduce power consumption and size, integrated circuits are typically used. Hardware processing circuits can include FPGAs, ASICs (application-specific integrated circuits), or PLDs (programmable logic devices); PLDs can further include FPGAs (field-programmable gate arrays), CPLDs (complex programmable logic devices), etc. These hardware processing circuits can be a single packaged semiconductor chip (e.g., packaged as an ASIC); or they can be integrated with other circuits (e.g., CPUs, DSPs) and packaged into a single semiconductor chip. For example, multiple hardware circuits and a CPU can be formed on a silicon substrate and packaged into a single chip; this type of chip is also called a SoC. Alternatively, circuits for implementing FPGA functions and a CPU can be formed on a silicon substrate and encapsulated into a single chip; this type of chip is also called a SoPC (system on a programmable chip).

[0155] The foregoing preferred embodiments have further illustrated the objectives, technical solutions, and advantages of the present invention. It should be understood that the above descriptions are merely preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A communication method, characterized in that, Executed by the hardware processor, including: Receive network packets and extract the feature data of the network packets; The feature data extracted within the current time window are statistically analyzed to obtain the current statistical status data; Historical statistical status data is read from shared memory; wherein, the shared memory is a memory space shared by the software processor and the hardware processor and directly accessible by the software processor, and the historical statistical status data reflects the statistical results of the feature data extracted within one or more historical time windows, wherein the historical time window is a time window prior to the current time window; The full statistical status data is obtained based on the current statistical status data and the historical statistical status data. The full statistical status data reflects the statistical results of the feature data extracted within the current time window and the one or more historical time windows. The full statistical status data is written back to the shared memory as new historical statistical status data through direct memory access, so that the software processor can obtain the full statistical status data from the shared memory; The step of statistically analyzing the feature data extracted within the current time window to obtain the current statistical status data includes: After extracting the feature data N times, the on-chip statistical data stored in the on-chip memory of the hardware processor is read; wherein, the on-chip statistical data is: the statistical result of the feature data obtained from the start time of the current time window to the last feature data extraction time; N is any positive integer; Statistical operations are performed on the extracted feature data and the in-chip statistical data to obtain the current statistical status data; The current statistical status data is written back to the on-chip memory as new on-chip statistical data.

2. The communication method according to claim 1, characterized in that, The feature data includes one or more of the following: number of packets, packet length, latency and jitter. The in-chip statistics include one or more of the following: total number of packets, total packet length, latest latency, maximum and minimum values ​​of packet length, maximum and minimum values ​​of latency and jitter. The maximum and minimum values ​​include the maximum value and / or the minimum value. The statistical operations include one or more of the following: accumulation operation, replacement operation, and comparison operation; The accumulation operation corresponding to the number of packets and / or packet length includes: accumulating the number of packets extracted this time to the total number of packets in the intra-slice statistical data, and / or accumulating the packet length extracted this time to the total packet length in the intra-slice statistical data; The replacement operation corresponds to a delay, including: replacing the latest delay value of the in-chip statistical data with the delay value extracted this time; The comparison operation corresponds to one or more of packet length, latency, and jitter, and includes: comparing the value of one or more of the packet length, latency, and jitter extracted this time with the maximum or minimum value of the corresponding intra-chip statistical data; if it is greater than the maximum value, then update the maximum value; and / or if it is less than the minimum value, then update the minimum value.

3. The communication method according to claim 2, characterized in that, The window duration of the current time window satisfies one or more of the following constraints: statistical value overflow, real-time processing capability, and window operation time. The statistical overflow constraint includes: the product of the maximum number of packets received in the current time window and the maximum contribution value of each packet is less than or equal to the maximum bit width of the on-chip memory; the maximum contribution value of each packet is: the maximum number of packets and / or the maximum packet length in the network packets received in the current time window; The real-time processing capability constraints include: the product of the effective processing time and processing rate of the current time window is greater than or equal to the product of the arrival rate of the network packet and the window duration of the current time window; the effective processing time is the difference between the window duration and the total execution time of the steps of reading historical statistical status data from shared memory, obtaining full statistical status data based on the current statistical status data and the historical statistical status data, and writing the full statistical status data back to the shared memory as new historical statistical status data through direct memory access; the processing rate is the ratio of the clock frequency of the hardware processor to the number of clock cycles required for the hardware processor to process one network packet; the arrival rate is the ratio of the network line speed to the average packet size. The window operation time constraints include: the total execution time of the steps of reading historical statistical status data from shared memory, obtaining full statistical status data based on the current statistical status data and the historical statistical status data, and writing the full statistical status data back to the shared memory as new historical statistical status data through direct memory access is less than or equal to the window duration of the current time window.

4. The communication method according to claim 1, characterized in that, The feature data includes: a flow identifier and feature information corresponding to the flow identifier, wherein the flow identifier is used to identify the network packet; The step of statistically analyzing the feature data extracted within the current time window to obtain current statistical status data includes: statistically analyzing the feature information extracted within the current time window corresponding to the first flow identifier to obtain current statistical status data corresponding to the first flow identifier, wherein the first flow identifier is the flow identifier of the latest received network packet; The step of reading historical statistical status data from shared memory includes: reading historical statistical status data corresponding to the first stream identifier from the shared memory based on the first stream identifier; The step of obtaining full statistical status data based on the current statistical status data and the historical statistical status data includes: obtaining full statistical status data corresponding to the first stream identifier based on the current statistical status data corresponding to the first stream identifier and the historical statistical status data corresponding to the first stream identifier; The step of writing the full statistical status data as new historical statistical status data back to the shared memory via direct memory access, so that the software processor can obtain the full statistical status data from the shared memory, includes: writing the full statistical status data corresponding to the first stream identifier as new historical statistical status data corresponding to the first stream identifier back to the shared memory via direct memory access, so that the software processor can obtain the full statistical status data corresponding to the first stream identifier from the shared memory.

5. The communication method according to any one of claims 1 to 4, characterized in that, Before writing the full statistical status data back to the shared memory as new historical statistical status data via direct memory access, the method further includes: Receive the address information of the shared memory sent by the software processor; The step of writing the full statistical status data back to the shared memory as new historical statistical status data through direct memory access includes: accessing the memory space corresponding to the address information through the direct memory access engine and writing the full statistical status data.

6. The communication method according to any one of claims 1 to 4, characterized in that, Access to the shared memory is restricted to the hardware processor and the software processor.

7. The communication method according to any one of claims 1 to 4, characterized in that, The process of reading historical statistical status data from shared memory includes: The historical statistical status data is periodically read from the shared memory at preset time intervals and stored in a buffer inside the hardware processor.

8. The communication method according to any one of claims 1 to 4, characterized in that, The shared memory has a capacity greater than 16MB.

9. A communication device, characterized in that, include: Hardware processor, software processor, and memory; The hardware processor is used to: receive network packets and extract feature data from the network packets; The feature data extracted within the current time window is statistically analyzed to obtain current statistical status data; historical statistical status data is read from shared memory; wherein, the shared memory is shared by the software processor and the hardware processor, and the shared memory is a storage space located in the memory that the software processor can directly access; the historical statistical status data reflects the statistical results of the feature data extracted within one or more historical time windows, and the historical time windows are one or more time windows preceding the current time window; full statistical status data is obtained based on the current statistical status data and the historical statistical status data; the full statistical status data reflects the statistical results of the feature data extracted within the current time window and the one or more historical time windows; the full statistical status data is written back to the shared memory as new historical statistical status data through direct memory access; The step of statistically analyzing the feature data extracted within the current time window to obtain the current statistical status data includes: After extracting the feature data N times, the on-chip statistical data stored in the on-chip memory of the hardware processor is read; wherein, the on-chip statistical data is: the statistical result of the feature data obtained from the start time of the current time window to the last feature data extraction time; N is any positive integer; Statistical operations are performed on the extracted feature data and the in-chip statistical data to obtain the current statistical status data; Write the current statistical status data back to the on-chip memory as the new on-chip statistical data. The software processor is used to: obtain the full statistical status data from the shared memory for analysis or visualization.

10. The communication device according to claim 9, characterized in that, The feature data includes one or more of the following: number of packets, packet length, latency and jitter. The in-chip statistics include one or more of the following: total number of packets, total packet length, latest latency, maximum and minimum values ​​of packet length, maximum and minimum values ​​of latency and jitter. The maximum and minimum values ​​include the maximum value and / or the minimum value. The statistical operations include one or more of the following: accumulation operation, replacement operation, and comparison operation; The accumulation operation corresponding to the number of packets and / or packet length includes: accumulating the number of packets extracted this time to the total number of packets in the intra-slice statistical data, and / or accumulating the packet length extracted this time to the total packet length in the intra-slice statistical data; The replacement operation corresponds to a delay, including: replacing the latest delay value of the in-chip statistical data with the delay value extracted this time; The comparison operation corresponds to one or more of packet length, latency, and jitter, and includes: comparing the value of one or more of the packet length, latency, and jitter extracted this time with the maximum or minimum value of the corresponding intra-chip statistical data; if it is greater than the maximum value, then update the maximum value; and / or if it is less than the minimum value, then update the minimum value.

11. The communication device according to claim 10, characterized in that, The window duration of the current time window satisfies one or more of the following constraints: statistical value overflow, real-time processing capability, and window operation time. The statistical overflow constraint includes: the product of the maximum number of packets received in the current time window and the maximum contribution value of each packet is less than or equal to the maximum bit width of the on-chip memory; the maximum contribution value of each packet is: the maximum number of packets and / or the maximum packet length in the network packets received in the current time window; The real-time processing capability constraints include: the product of the effective processing time and processing rate of the current time window is greater than or equal to the product of the arrival rate of the network packet and the window duration of the current time window; the effective processing time is the difference between the window duration and the total execution time of the steps of reading historical statistical status data from shared memory, obtaining full statistical status data based on the current statistical status data and the historical statistical status data, and writing the full statistical status data back to the shared memory as new historical statistical status data through direct memory access; the processing rate is the ratio of the clock frequency of the hardware processor to the number of clock cycles required for the hardware processor to process one network packet; the arrival rate is the ratio of the network line speed to the average packet size. The window operation time constraints include: the total execution time of the steps of reading historical statistical status data from shared memory, obtaining full statistical status data based on the current statistical status data and the historical statistical status data, and writing the full statistical status data back to the shared memory as new historical statistical status data through direct memory access is less than or equal to the window duration of the current time window.

12. The communication device according to claim 9, characterized in that, The feature data includes: a flow identifier and feature information corresponding to the flow identifier, wherein the flow identifier is used to identify the network packet; The step of statistically analyzing the feature data extracted within the current time window to obtain current statistical status data includes: statistically analyzing the feature information extracted within the current time window corresponding to the first flow identifier to obtain current statistical status data corresponding to the first flow identifier, wherein the first flow identifier is the flow identifier of the latest received network packet; The step of reading historical statistical status data from shared memory includes: reading historical statistical status data corresponding to the first stream identifier from the shared memory based on the first stream identifier; The step of obtaining full statistical status data based on the current statistical status data and the historical statistical status data includes: obtaining full statistical status data corresponding to the first stream identifier based on the current statistical status data corresponding to the first stream identifier and the historical statistical status data corresponding to the first stream identifier; The step of writing the full statistical status data as new historical statistical status data back to the shared memory via direct memory access, so that the software processor can obtain the full statistical status data from the shared memory, includes: writing the full statistical status data corresponding to the first stream identifier as new historical statistical status data corresponding to the first stream identifier back to the shared memory via direct memory access, so that the software processor can obtain the full statistical status data corresponding to the first stream identifier from the shared memory.

13. The communication device according to any one of claims 9 to 12, characterized in that, The software processor is further configured to: allocate a storage space in the memory as the shared memory; and send the address information of the shared memory to the hardware processor; When the hardware processor accesses the shared memory, it accesses the memory space corresponding to the address information through the direct memory access engine.

14. The communication device according to claim 13, characterized in that, The storage space allocated to the shared memory in the memory is greater than 16MB.

15. The communication device according to any one of claims 9 to 12, characterized in that, The software processor is further configured to: restrict access permissions of the shared memory to allow only the hardware processor and the software processor to access it.

16. The communication device according to any one of claims 9 to 12, characterized in that, The process of reading historical statistical status data from shared memory includes: The historical statistical status data is periodically read from the shared memory at preset time intervals and stored in a buffer inside the hardware processor.

17. The communication device according to any one of claims 9 to 12, characterized in that, The communication device is a network tester.

18. The communication device according to any one of claims 9 to 12, characterized in that, The hardware processor is an FPGA, and the software processor is a CPU.

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