Serial port communication data receiving and analyzing method and system based on FPGA platform

Abstract

The invention discloses a serial port communication data receiving and analyzing method and system based on an FPGA (Field Programmable Gate Array) platform, and the method comprises the following steps: receiving data sent by a serial port chip according to bytes through an FPGA chip, and checking a start bit, a check bit and a stop bit in single-byte data; when the single-byte data passes the verification, generating an interrupt trigger mark, and caching and sending the single-byte data to a receiving analysis module; triggering an interrupt service function configured in the receiving analysis module through an interrupt trigger mark, and reading and buffering single-byte data; for the single-byte data, dynamically matching a preset frame header keyword through a sliding window algorithm to position the initial position of an effective frame, and calculating corresponding check bit data according to the frame length of the effective frame; and when the check bit data is successfully matched, analyzing the data of the corresponding frame, and sending the analyzed data to other modules for further data processing.

Description

Technical Field

[0001] This invention relates to the field of serial communication technology, and in particular to a method and system for receiving and parsing serial communication data based on an FPGA platform. Background Technology

[0002] RS422 (Electrical Characteristics of Balanced Voltage Digital Interface Circuits), as a differential serial communication standard, is widely used in industrial control, aerospace, and rail transportation due to its strong common-mode interference immunity and long transmission distance. However, in environments with strong electromagnetic interference, RS422 communication lines may still be affected by noise, leading to serial communication data errors, mainly manifested as follows: (1) Level transition interference: Noise may cause misjudgment of data bits, causing the receiver to mistakenly identify noise as valid data; (2) Frame structure corruption: Noise may cause frame header or frame tail markers to be tampered with, resulting in frame synchronization failure; (3) Frame concatenation and packet sticking: Due to noise interference or transmission delay, multiple data frames may be incorrectly merged, or a single data frame may be truncated, resulting in protocol parsing failure.

[0003] Currently, the main methods for addressing frame splicing / packet merging issues in RS422 communication are fixed-length frame protocols, frame timeout mechanisms, or delimiter methods based on frame headers / tails. However, these methods suffer from poor flexibility, susceptibility to misjudgments, or high complexity. Furthermore, existing technologies offer limited solutions for serial communication data errors applicable to FPGA (Field Programmable Gate Array) platforms, and their versatility is poor. Therefore, it is necessary to propose a serial communication data reception and parsing method and system based on an FPGA platform to improve the reliability of serial communication data reception.

[0004] The statements herein provide only background information in relation to this invention and do not necessarily constitute prior art. Summary of the Invention

[0005] The purpose of this invention is to address errors such as frame splicing / packet merging in serial communication data on FPGA platforms. By setting the receiving analysis module to receive and parse single-byte data after an interrupt is triggered, and by calculating and verifying the data using a sliding window algorithm, the frame splicing / packet merging problem can be effectively solved, thereby improving the reliability of serial communication data reception.

[0006] To achieve the above objectives, the present invention is implemented through the following technical solution: The first aspect of this invention provides a serial communication data receiving and parsing method based on an FPGA platform, comprising: The FPGA chip receives data sent by the serial port chip byte by byte, and verifies the start bit, parity bit, and stop bit in each byte of data. When the single-byte data passes the verification, an interrupt trigger flag is generated, the single-byte data is cached, and the data is sent to the receiving and analysis module. The interrupt service function configured in the receiving analysis module is triggered by the interrupt trigger flag, and the single-byte data is read and cached. For the single-byte data, a preset frame header keyword is dynamically matched using a sliding window algorithm to locate the start position of the valid frame, and the corresponding check bit data is calculated based on the frame length of the valid frame. When the check bit data is successfully matched, the data of the corresponding frame is parsed and sent to other modules for further data processing.

[0007] Optionally, the verification of the start bit, parity bit, and stop bit in the single-byte data includes: The level of the serial port receiving line is continuously monitored. When a falling edge is detected, the baud rate counter is started and the sample is taken at the midpoint of the start bit. Using a baud rate clock interval as the period, 8 bits of data are sampled sequentially and stored as data bits in the shift register; Determine whether to enable verification based on the communication protocol configuration; When verification is enabled, the verification bit is sampled from the data bits, and the corresponding verification result is calculated. Sample the stop bit after the check bit to determine if the stop bit is valid; When the stop bit is valid, perform a check on the data bits based on the check type.

[0008] Optionally, the check type includes odd check and even check.

[0009] Optionally, during the verification of the start bit, parity bit, and stop bit in the single-byte data, all calculations use the same clock.

[0010] Optionally, the single-byte data is sent to the receiving and analysis module via the AXI (Advanced eXtensible Interface) bus.

[0011] Optionally, the receiving and analysis module is an independent microprocessor core.

[0012] Optionally, the receiving and analysis module sends the parsed data to other modules via inter-core communication.

[0013] Optionally, the interrupt trigger flag returns to zero after 10 clock cycles; the interrupt service function adopts a rising edge triggering mechanism.

[0014] Optionally, the dynamic matching of preset frame header keywords via a sliding window algorithm includes: Define a data receiving array, the number of array elements of which is equal to the frame length of the data to be received and parsed; After the interrupt service function is triggered, all array elements in the data receiving array are shifted one position to the left, and the received single-byte data is assigned to the rightmost array element in the data receiving array. Check whether the updated data receiving array matches the preset frame header keyword.

[0015] A second aspect of the present invention provides a serial communication data receiving and parsing system based on an FPGA platform, comprising: The FPGA chip is used to receive data sent by the serial port chip byte by byte, and to verify the start bit, parity bit and stop bit in the single byte data. It is also used to generate an interrupt trigger flag when the single byte data passes the verification, and to buffer the single byte data. The receiving and analysis module is configured with an interrupt service function that can be triggered by the interrupt trigger flag. The receiving and analysis module is used to read and cache the single-byte data when the interrupt service function is triggered. The receiving and analysis module is also used to dynamically match preset frame header keywords for the single-byte data using a sliding window algorithm to locate the start position of the valid frame, and calculate the corresponding check bit data according to the frame length of the valid frame. The receiving and analysis module is also used to parse the data of the corresponding frame when the check bit data is successfully matched, and send it to other modules for further data processing.

[0016] This invention has at least the following technical effects: By receiving and parsing serial port data byte by byte, data packets in cases of frame splicing / packet merging and data packet lag can be parsed normally, and there will be no data frame loss due to timeout protection mechanism; By setting up an independent data receiving and parsing module, the data receiving and parsing module only receives and parses new single-byte data when the interrupt service function is triggered. The data is delivered with a delay, and it is sent to other functional modules after parsing, so it will not affect the operation of other functional modules. By dynamically matching preset frame header keywords using a sliding window algorithm and calculating the corresponding check bit data based on the frame length of the valid frame, it can be applied to mixed serial port data reception scenarios with different frame header lengths and has strong versatility. Attached Figure Description

[0017] Figure 1 This is a logical schematic diagram of a serial communication data receiving and parsing system provided in an embodiment of the present invention; Figure 2 This is a flowchart illustrating a serial communication data receiving and parsing method according to an embodiment of the present invention. Figure 3 This is a flowchart illustrating the process of verifying the start bit, parity bit, and stop bit in single-byte data according to an embodiment of the present invention. Figure 4 This is a schematic diagram of a matching process using a sliding window algorithm, provided in an embodiment of the present invention. Detailed Implementation

[0018] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a further detailed explanation of the serial communication data receiving and parsing method and system based on an FPGA platform proposed in this invention. The advantages and features of this invention will become clearer from the following description. It should be noted that the accompanying drawings are in a very simplified form and use non-precise proportions, used only to facilitate and clearly illustrate the embodiments of this invention. Please refer to the accompanying drawings to make the objectives, features, and advantages of this invention more apparent and understandable. It should be understood that the structures, proportions, sizes, etc., depicted in the accompanying drawings are only for illustrative purposes to aid those skilled in the art and are not intended to limit the implementation conditions of this invention. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to the size, without affecting the effects and objectives achieved by this invention, should still fall within the scope of the technical content disclosed in this invention.

[0019] This embodiment provides a serial communication data receiving and parsing system based on an FPGA platform, including an FPGA chip and a receiving and analysis module. The FPGA chip is used to receive data sent by the serial port chip byte by byte, and to verify the start bit, parity bit, and stop bit in each byte of data. It is also used to generate an interrupt trigger flag when a single byte of data passes the verification, and to buffer the single byte of data.

[0020] The receiving and analysis module is configured with an interrupt service function that can be triggered by an interrupt trigger flag. When the interrupt service function is triggered, the receiving and analysis module reads and buffers single-byte data. The receiving and analysis module is also used to dynamically match preset frame header keywords for single-byte data using a sliding window algorithm to locate the start position of the valid frame, and calculate the corresponding check bit data according to the frame length of the valid frame. When the check bit data is successfully matched, the receiving and analysis module is also used to parse the data of the corresponding frame and send it to other modules for further data processing.

[0021] Specifically, such as Figure 1As shown, the differential signal is converted by a differential signal conversion chip and then received by the FPGA chip. In the FPGA, the reception and verification of single-byte data can be implemented using a hardware programming language. After the single-byte verification passes, an interrupt trigger flag can be generated to trigger an interrupt. Simultaneously, the single-byte data Rec_Data_Byte is buffered and sent to the receiving analysis module via the AXI bus. In this embodiment, the receiving analysis module is set as an independent microprocessor core (MicroBlaze), for example... Figure 1 MicroBlaze .

[0022] Furthermore, a sliding window algorithm can be used in the data receiving and analysis module to receive, assemble, and verify data frame by frame, and send the verified data to the signal processing module MicroBlaze via inter-core communication. This further processing can be performed on the received data. Specifically, this further processing may include, for example, parsing the communication protocol, converting the data format, performing real-time signal analysis, and intelligent signal processing.

[0023] like Figure 2 As shown, this embodiment also provides a serial communication data receiving and parsing method based on an FPGA platform, which specifically includes the following steps: The FPGA chip receives data sent by the serial port chip byte by byte, and verifies the start bit, parity bit, and stop bit in each byte of data. When a single byte of data passes the verification, an interrupt trigger flag is generated, the single byte of data is buffered, and the data is sent to the receiving and analysis module. The interrupt service function configured in the receive analysis module is triggered by the interrupt trigger flag, and single-byte data is read and buffered. For single-byte data, a sliding window algorithm is used to dynamically match preset frame header keywords to locate the start position of the valid frame, and the corresponding check bit data is calculated based on the frame length of the valid frame. When the checksum data is successfully matched, the data of the corresponding frame is parsed and sent to other modules for further data processing.

[0024] Specifically, such as Figure 3 As shown, in this embodiment, verifying the start bit, parity bit, and stop bit in single-byte data includes the following steps: First, the serial port receive line level is continuously monitored. Upon detecting a falling edge, the baud rate counter is started, and sampling is performed at the midpoint of the start bit. Since the serial port receive line remains high in idle state, continuous monitoring of the receive line level allows for the detection of a falling edge (a high-to-low transition) as the start of the start bit, thus activating the baud rate counter. As those skilled in the art will understand, the baud rate counter can be based on the system clock and generate sampling timing according to a preset baud rate. Sampling at the midpoint of the start bit helps to offset the effects of transmission delay and jitter, ensuring sampling accuracy.

[0025] Furthermore, 8 bits of data can be sampled sequentially and stored as data bits in a shift register at baud rate clock intervals. Since shift registers are typically 8 bits wide, the sampled 8 bits can be shifted into the shift register sequentially from the least significant bit to the most significant bit at baud rate clock intervals. The sampling timing strictly follows the baud rate clock, ensuring that each data bit is sampled only in a stable state.

[0026] Furthermore, based on the communication protocol configuration, it can be determined whether to enable verification. If verification is enabled, a check bit can be sampled from the data bits, and the corresponding verification result can be calculated. A stop bit is sampled after the check bit, and its validity is determined. For example, it is checked whether the stop bit is the expected high level. If invalid, a frame error is marked to enable system diagnostics and retransmission mechanisms.

[0027] Finally, when the stop bit is valid, the received 8-bit data can be checked based on the check type. If the check passes, the data can be output to the internal AXI bus, and an interrupt trigger flag will be activated. If the check fails, the data is discarded to prevent erroneous data from affecting frame parsing.

[0028] Specifically, the parity check types include odd parity and even parity. Odd parity involves counting the number of "1"s in the data bits. If the count is odd, the expected parity bit is 0; if it is even, the expected parity bit is 1. Even parity involves counting the number of "1"s in the data bits. If the count is even, the expected parity bit is 0; if it is odd, the expected parity bit is 1. The actual sampled parity bit can be compared with the calculated expected parity bit. If they match, the check passes; otherwise, it is marked as a check error.

[0029] In this embodiment, during the verification of the start bit, parity bit, and stop bit in single-byte data, all calculations use the same clock to avoid metastability quadrants in the FPGA.

[0030] After the single-byte data verification passes, an interrupt trigger flag can be generated to trigger the interrupt service function. In this embodiment, the interrupt trigger flag returns to zero after 10 clock cycles and is regenerated when the next single-byte data arrives. Correspondingly, the interrupt service function adopts a rising-edge triggered mechanism, thereby effectively avoiding repeated interrupts.

[0031] Furthermore, after the interrupt service function is triggered, the receiving analysis module reads and caches single-byte data, and dynamically matches the preset frame header keywords through a sliding window algorithm to locate the start position of the valid frame, thereby calculating the corresponding check bit data according to the frame length of the valid frame.

[0032] The steps to achieve dynamic matching using the sliding window algorithm include: Define a data receiving array, the number of array elements of which is equal to the frame length of the data to be received and parsed; After the interrupt service function is triggered, all array elements in the data receive array are shifted one position to the left, and the received single-byte data is assigned to the rightmost array element in the data receive array. Check whether the updated data receive array matches the preset frame header keywords.

[0033] Specifically, such as Figure 4 As shown, the following receive array can be defined: ,in The frame length of the data packet to be received and parsed.

[0034] After triggering the interrupt, it can be made Shift all data to the left by one bit, which means discarding the original array elements. , will the original Assign to new array elements , will the original Assign to new array elements And so on. The newly received single-byte data is then assigned to the new array element. .

[0035] Furthermore, for the updated receive array It can match whether the frame header meets the requirements. When the frame header matches, it can further calculate and match the check bit data. When both the frame header and the check bit data match, it can be determined that the parsing of a frame of data is complete.

[0036] In this embodiment, the receiving and analysis module is only used to process the received RS422 serial port information, and after analyzing the received information, it sends it to the signal processing module through inter-core communication. All signal processing is completed in other modules that are not the receiving and analysis module.

[0037] In summary, the serial communication data receiving and parsing method and system provided by this invention can parse data packets normally under conditions of frame splicing / packet merging and data packet stuttering, without requiring a timeout protection mechanism. Furthermore, the receiving and parsing module in this invention is located on an independent microprocessor core, ensuring timely communication response and preventing interference with other signal processing modules. The frame length and frame header in this invention are arbitrarily configurable, thus making it applicable to mixed serial port data receiving scenarios with different frame headers and lengths, representing a significant improvement over existing technologies.

[0038] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0039] It should be noted that the apparatus and methods disclosed in the embodiments herein can also be implemented in other ways. The apparatus embodiments described above are merely illustrative; for example, the flowcharts and block diagrams in the accompanying drawings show the architecture, functionality, and operation of possible implementations of apparatus, methods, and computer program products according to various embodiments herein. In this regard, each block in a flowchart or block diagram may represent a module, program, or part of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram and / or flowchart, and combinations of blocks in block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system to perform the specified function or action, or can be implemented using a combination of dedicated hardware and computer instructions.

[0040] In addition, the functional modules in the various embodiments of this article can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0041] Although the present invention has been described in detail through the preferred embodiments above, it should be understood that the above description should not be considered as a limitation of the present invention. Various modifications and substitutions to the present invention will be apparent to those skilled in the art after reading the above description. Therefore, the scope of protection of the present invention should be defined by the appended claims.

Claims

1. A serial communication data receiving and parsing method based on an FPGA platform, characterized in that, include: The FPGA chip receives data sent by the serial port chip byte by byte, and verifies the start bit, parity bit, and stop bit in each byte of data. When the single-byte data passes the verification, an interrupt trigger flag is generated, the single-byte data is cached, and the data is sent to the receiving and analysis module. The interrupt service function configured in the receiving analysis module is triggered by the interrupt trigger flag, and the single-byte data is read and cached. For the single-byte data, a preset frame header keyword is dynamically matched using a sliding window algorithm to locate the start position of the valid frame, and the corresponding check bit data is calculated based on the frame length of the valid frame. When the check bit data is successfully matched, the data of the corresponding frame is parsed and sent to other modules for further data processing.

2. The serial communication data receiving and parsing method based on an FPGA platform according to claim 1, characterized in that, The verification of the start bit, parity bit, and stop bit in the single-byte data includes: The level of the serial port receiving line is continuously monitored. When a falling edge is detected, the baud rate counter is started and the sample is taken at the midpoint of the start bit. Using a baud rate clock interval as the period, 8 bits of data are sampled sequentially and stored as data bits in the shift register; Determine whether to enable verification based on the communication protocol configuration; When verification is enabled, the verification bit is sampled from the data bits, and the corresponding verification result is calculated. Sample the stop bit after the check bit to determine if the stop bit is valid; When the stop bit is valid, perform a check on the data bits based on the check type.

3. The serial communication data receiving and parsing method based on an FPGA platform according to claim 2, characterized in that, The check types include odd check and even check.

4. The serial communication data receiving and parsing method based on an FPGA platform according to claim 2, characterized in that, During the verification of the start bit, parity bit, and stop bit in the single-byte data, all calculations use the same clock.

5. The serial communication data receiving and parsing method based on an FPGA platform according to claim 1, characterized in that, The single-byte data is sent to the receiving and analysis module via the AXI bus.

6. The serial communication data receiving and parsing method based on an FPGA platform according to claim 1, characterized in that, The receiving and analysis module is an independent microprocessor core.

7. The serial communication data receiving and parsing method based on an FPGA platform according to claim 5, characterized in that, The receiving and analysis module sends the parsed data to other modules through inter-core communication.

8. The serial communication data receiving and parsing method based on an FPGA platform according to claim 6, characterized in that, The interrupt trigger flag returns to zero after 10 clock cycles; the interrupt service function uses a rising edge triggering mechanism.

9. The serial communication data receiving and parsing method based on an FPGA platform according to claim 1, characterized in that, The dynamic matching of preset frame header keywords via the sliding window algorithm includes: Define a data receiving array, the number of array elements of which is equal to the frame length of the data to be received and parsed; After the interrupt service function is triggered, all array elements in the data receiving array are shifted one position to the left, and the received single-byte data is assigned to the rightmost array element in the data receiving array. Check whether the updated data receiving array matches the preset frame header keyword.

10. A serial communication data receiving and parsing system based on an FPGA platform, characterized in that, include: The FPGA chip is used to receive data sent by the serial port chip byte by byte, and to verify the start bit, parity bit and stop bit in the single byte data. It is also used to generate an interrupt trigger flag when the single byte data passes the verification, and to buffer the single byte data. The receiving and analysis module is configured with an interrupt service function that can be triggered by the interrupt trigger flag. The receiving and analysis module is used to read and cache the single-byte data when the interrupt service function is triggered. The receiving and analysis module is also used to dynamically match preset frame header keywords for the single-byte data using a sliding window algorithm to locate the start position of the valid frame, and calculate the corresponding check bit data according to the frame length of the valid frame. The receiving and analysis module is also used to parse the data of the corresponding frame when the check bit data is successfully matched, and send it to other modules for further data processing.

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