LED monitoring circuit based on topological correlation model and control method thereof

Abstract

The invention discloses an LED monitoring chip based on a topological correlation model and a control method thereof, and relates to the technical field of control circuits. The circuit comprises a load circuit, a switch circuit, a control chip and a sampling circuit, the sampling circuit collects current signals of the load circuit, the control chip carries out dynamic time-frequency feature extraction on the signals to obtain an original feature vector set, and then a correlation model is constructed based on circuit topology parameters. An original feature vector set is input into a model for feature fusion to generate a topology enhancement feature vector, then risk quantification is performed on the topology enhancement feature vector by using an anomaly detection model to output an abnormal risk value, and once the abnormal risk value exceeds a preset threshold value, a control chip generates a switch control instruction, and the working state of a load circuit is adjusted through a switch circuit. According to the invention, the abnormal condition in the working state of the LED can be effectively monitored.

Description

Technical Field

[0001] This invention relates to the field of control circuit technology, specifically to an LED monitoring circuit and its control method based on a topological correlation model. Background Technology

[0002] With the continuous development of LED technology and the gradual reduction of costs, LEDs have become an indispensable and important component in modern lighting and display equipment.

[0003] However, when the LED load current is too high or too low, the LED may overheat, flicker, lose brightness, or even be damaged. Existing LED control systems often lack sufficient intelligent monitoring and protection mechanisms. When the LED malfunctions or operates abnormally, the existing system does not have the function of automatically stopping or adjusting, causing the LED to work in an abnormal state for a long time, affecting its service life and even causing safety hazards. Summary of the Invention

[0004] This invention provides an LED monitoring circuit and its control method based on a topology correlation model, which can realize real-time and accurate monitoring of the working status of the LED load circuit, timely detection and adjustment of abnormalities, and improve the reliability and stability of circuit operation.

[0005] An embodiment of the present invention provides an LED monitoring circuit based on a topology correlation model, including a load circuit, a control circuit, and a sampling circuit. The sampling circuit is used to collect the status signal of the load circuit. The input terminal of the sampling circuit is connected to the load circuit, and the output terminal of the sampling circuit is connected to the input terminal of the control circuit. The control circuit includes a switching circuit and a control chip. The output terminal of the control chip is connected to the controlled terminal of the switching circuit, the output terminal of the switching circuit is connected to the input terminal of the load circuit, and the output terminal of the sampling circuit is connected to the control port of the control chip. The control circuit includes a switching circuit and a control chip. The switching circuit is used to control the on / off state of the load circuit, and the control chip is used for: The current signal of the load circuit is acquired through the sampling circuit, and the current signal is subjected to dynamic time-frequency feature extraction processing to obtain the original feature vector set. Based on the circuit topology parameters of the LED monitoring circuit based on the topology association model, a circuit topology association model is constructed, and the original feature vector set is input into the circuit topology association model for feature fusion processing to generate topology enhanced feature vectors. The topology-enhanced feature vector is input into the anomaly detection model for risk quantification, and anomaly risk value is output. When the abnormal risk value exceeds a preset threshold, a switch control command is generated to adjust the working state of the load circuit.

[0006] Another embodiment of the present invention provides a control method for an LED monitoring circuit based on a topology association model, applied to the circuit described in any of the above claims, comprising the following steps; The current signal of the load circuit is acquired through the sampling circuit, and the current signal is subjected to dynamic time-frequency feature extraction processing to obtain the original feature vector set. Based on the circuit topology parameters of the LED monitoring circuit based on the topology association model, a circuit topology association model is constructed, and the original feature vector set is input into the circuit topology association model for feature fusion processing to generate topology enhanced feature vectors. The topology-enhanced feature vector is input into the anomaly detection model for risk quantification, and anomaly risk value is output. When the abnormal risk value exceeds a preset threshold, a switch control command is generated to adjust the working state of the load circuit.

[0007] Compared with the prior art, the embodiments of the present invention have the following beneficial effects: The current signal of the load circuit is acquired by a sampling circuit. The control chip performs dynamic time-frequency feature extraction on the current signal to obtain an original feature vector set that reflects the time-varying characteristics and frequency components of the signal. Then, a circuit topology association model is constructed based on the topology parameters of the LED monitoring circuit. The original feature vector set is input into this circuit topology association model for fusion, so that the features include circuit structure information, improving the feature's ability to represent anomalies. Then, the fused topology-enhanced feature vector is input into the anomaly detection model to quantify the risk and output an anomaly risk value. When the risk value exceeds the threshold, the control chip generates a switch control command to adjust the on / off state of the load circuit through the switch circuit. In this invention, dynamic time-frequency feature extraction can capture the instantaneous changes and frequency characteristics of the current signal, accurately reflecting the load's operating state; the circuit topology association model integrates topology parameters and signal features, combining feature analysis with circuit structure characteristics to enhance the accuracy of anomaly judgment; and the anomaly detection model quantifies the risk and links it with the switch control to achieve closed-loop control from detection to response. In summary, this embodiment of the invention can achieve real-time and accurate monitoring of the operating state of the LED load circuit, timely detection and adjustment of anomalies, and improve the reliability and stability of circuit operation. Attached Figure Description

[0008] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0009] Figure 1This is a structural block diagram of the first embodiment of the present invention; Figure 2 This is a structural block diagram of the second embodiment of the present invention; Figure 3 This is a circuit schematic diagram of the second embodiment of the present invention; Figure 4 This is a control flowchart of the control method for the LED monitoring circuit of the present invention.

[0010] Figure label: 100. Load circuit; 200. Control circuit; 210. Switching circuit; 220. Control chip; 300. Sampling circuit; 400. Linear constant current circuit; 500. Voltage source; 600. Rectifier circuit; 700. Voltage regulator circuit. Detailed Implementation

[0011] The present invention will be further described in detail below with reference to the accompanying drawings.

[0012] This specific embodiment is merely an explanation of the present invention and is not intended to limit the invention. After reading this specification, those skilled in the art can make modifications to this embodiment without contributing any inventive element, but such modifications are protected by patent law as long as they fall within the scope of the claims of the present invention.

[0013] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0014] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0015] First embodiment: Reference Figure 1This invention provides an LED monitoring circuit based on a topology correlation model, including a load circuit 100, a control circuit 200, and a sampling circuit 300. The sampling circuit 300 is used to collect the status signal of the load circuit 100, and the control circuit 200 is used to control the on / off state of the load circuit 100 according to the status signal. The control terminal of the control circuit 200 is connected to the input terminal of the load circuit 100, the input terminal of the sampling circuit 300 is connected to the load circuit 100, and the output terminal of the sampling circuit 300 is connected to the input terminal of the control circuit 200. The control circuit 200 includes a switching circuit 210 and a control chip 220. The output terminal of the control chip 220 is connected to the controlled terminal of the switching circuit 210, and the control terminal of the switching circuit 210 is connected to the input terminal of the load circuit 100. The output terminal of the sampling circuit 300 is connected to the control port of the control chip 220. The control circuit 200 includes a switching circuit 210 and a control chip 220. The switching circuit 210 is used to control the on / off state of the load circuit 100, and the control chip 220 is used to control the on / off state of the switching circuit 210.

[0016] The control chip is used for: The current signal of the load circuit is acquired through the sampling circuit, and the current signal is subjected to dynamic time-frequency feature extraction processing to obtain the original feature vector set. Based on the circuit topology parameters of the LED monitoring circuit based on the topology association model, a circuit topology constraint model is constructed, and the original feature vector set is input into the circuit topology constraint model for feature fusion processing to generate topology enhanced feature vectors. The topology-enhanced feature vector is input into the anomaly detection model for risk quantification, and anomaly risk value is output. When the abnormal risk value exceeds a preset threshold, a switch control command is generated to adjust the working state of the load circuit.

[0017] This invention, by introducing a sampling circuit into the circuit to collect the status signal of the load circuit in real time, can effectively monitor abnormal conditions in the LED's working state, such as excessively high or low current values, thereby avoiding problems such as overheating, flickering, and brightness decay of the LED.

[0018] Secondly, the control circuit automatically adjusts the on / off state of the LED load circuit based on the collected status signals. It can cut off the power supply or adjust the current in time when abnormal current occurs, so as to avoid the LED working in an abnormal state for a long time, significantly extend the service life of the LED, and improve the stability and safety of the system.

[0019] Specifically, in this embodiment, the sampling circuit 300 is responsible for acquiring the operating status signals of the LED load circuit 100 in real time and transmitting these signals to the control chip 220. The control chip 220 determines the operating status of the LED load based on the acquired signals, such as whether there are abnormal conditions such as excessively high or low current.

[0020] Specifically, the operating status signal can be voltage, current, etc.

[0021] Specifically, the control chip 220 controls the on / off state of the load circuit 100 by controlling the switching state of the switching circuit 210. When the sampling circuit 300 detects that the current value is normal, the control chip 220 keeps the switching circuit 210 closed to ensure the power supply of the load circuit 100 and the LED continues to work normally. When the current value is abnormal (such as too high or too low current), the control chip 220 sends a control signal according to the preset control logic to open or close the switching circuit 210, thereby cutting off the power supply of the LED or adjusting it to avoid problems such as overheating or damage to the LED.

[0022] Therefore, compared with the prior art, the embodiments of the present invention have the following beneficial effects: The current signal of the load circuit is acquired by a sampling circuit. The control chip performs dynamic time-frequency feature extraction on the current signal to obtain an original feature vector set that reflects the time-varying characteristics and frequency components of the signal. Then, a circuit topology association model is constructed based on the topology parameters of the LED monitoring circuit. The original feature vector set is input into this circuit topology association model for fusion, so that the features include circuit structure information, improving the feature's ability to represent anomalies. Then, the fused topology-enhanced feature vector is input into the anomaly detection model to quantify the risk and output an anomaly risk value. When the risk value exceeds the threshold, the control chip generates a switch control command to adjust the on / off state of the load circuit through the switch circuit. In this invention, dynamic time-frequency feature extraction can capture the instantaneous changes and frequency characteristics of the current signal, accurately reflecting the load's operating state; the circuit topology association model integrates topology parameters and signal features, combining feature analysis with circuit structure characteristics to enhance the accuracy of anomaly judgment; and the anomaly detection model quantifies the risk and links it with the switch control to achieve closed-loop control from detection to response. In summary, this embodiment of the invention can achieve real-time and accurate monitoring of the operating state of the LED load circuit, timely detection and adjustment of anomalies, and improve the reliability and stability of circuit operation.

[0023] Next, we will first introduce the specific circuit structure of this LED monitoring circuit, and then introduce the specific control method of the LED monitoring circuit.

[0024] First, as one example, a linear constant current circuit 400 is also included, which is used to provide a stable current to the load circuit 100. The output terminal of the linear constant current circuit 400 is connected to the input terminal of the load circuit 100, the control terminal of the switching circuit 210 is connected to the input terminal of the linear constant current circuit 400, and the input terminal of the sampling circuit 300 is connected to the sampling terminal of the linear constant current circuit 400.

[0025] In this embodiment, the linear constant current circuit 400 provides a stable current to the load circuit 100 through its output terminal, ensuring the normal operation of the LED load. The control terminal of the switching circuit 210 is connected to the input terminal of the linear constant current circuit 400. The control chip 220 adjusts the on / off state of the switching circuit 210 according to the current signal obtained by the sampling circuit 300, thereby adjusting the current output of the linear constant current circuit. When the current is normal, the switching circuit remains closed, and the linear constant current circuit continues to provide a stable current to the load circuit 100. When the current is abnormal, the sampling circuit 300 detects the current fluctuation, and the control chip 220 controls the switching circuit 210 to open or close, thereby adjusting the current output of the linear constant current circuit to ensure that the load circuit 100 is not affected by the abnormal current. In this way, the circuit not only realizes the state monitoring and control of the LED, but also ensures the stability of the LED load current and avoids faults caused by overcurrent or overvoltage.

[0026] Optionally, it also includes a voltage source 500 and a rectifier circuit 600. The voltage source 500 is used to provide an initial current, and the rectifier circuit 600 is used to process the current provided by the voltage source 500 in a polarity-independent manner. The output terminal of the voltage source 500 is connected to the input terminal of the rectifier circuit 600, and the output terminal of the rectifier circuit 600 is connected to the input terminal of the switching circuit 210.

[0027] In this embodiment, voltage source 500 provides initial current to ensure the basic power supply requirements of the circuit. Its output is connected to the input of rectifier circuit 600. Rectifier circuit 600 is responsible for polarity-independent processing of the current output by voltage source 500, converting alternating current (if any) into direct current to meet the working requirements of subsequent circuits. The rectified current is transmitted to the input of switching circuit 210 through the output of rectifier circuit 600 for use in subsequent circuit control. Switching circuit 210 adjusts the current on / off according to the instructions of control chip 220, thereby affecting the current output of linear constant current circuit 400 and load circuit 100. In this way, voltage source and rectifier circuit provide stable and suitable power supply, enabling the entire circuit system to operate efficiently and stably, providing the necessary current and voltage support for LED load circuit.

[0028] Optionally, a voltage regulator circuit 700 is also included. A first node is provided between the output terminal of the rectifier circuit 600 and the input terminal of the switching circuit 210. The input terminal of the voltage regulator circuit 700 is connected to the first node, and the output terminal of the voltage regulator circuit 700 is connected to the power supply terminal of the control chip 220.

[0029] In this embodiment, the output terminal of the rectifier circuit 600 is connected to the switching circuit 210 through the first node. The voltage regulator circuit 700 receives the current of the node, regulates it, and outputs it to the power supply terminal of the control chip 220, ensuring that the control chip 220 works normally under stable voltage conditions and avoiding voltage fluctuations from affecting the control accuracy and stability of the system.

[0030] Furthermore, the linear constant current circuit 400 includes a first switching transistor D6 and a linear constant current chip U1. The output terminal of the switching circuit 210 is connected to the first port VCC1, the second port VCC2 and the third port VCC3 of the linear constant current chip U1. The fifth port GND is grounded. The two ends of the first switching transistor D6 are connected to the sixth port F- and the fourth port F-.

[0031] Specifically, in this embodiment, the output terminal of the switching circuit 210 is connected to multiple ports (VCC1, VCC2, VCC3) of the linear constant current chip U1 to provide the required operating voltage for the constant current chip. The constant current chip U1 adjusts the current output through its ports to ensure a stable current for the load circuit 100. The first switching transistor D6 is connected to the F-port and the fourth port of the constant current chip to control the current flow to the LED load circuit.

[0032] Specifically, the switching transistor D6 adjusts the current magnitude according to the control signal of the constant current chip. When the current is abnormal, the switching transistor D6 will adjust the current path to achieve precise control of the LED load current, keep the current stable within the predetermined range, effectively prevent the LED from being damaged due to unstable current, and ensure the stability of the system and the long-term reliable operation of the LED.

[0033] Furthermore, a first capacitor C3 is provided between the first port VDD and the eighth port VSS of the control chip 220. A second node is provided between the first port VDD and one end of the first capacitor C3. The second node is the power supply terminal of the control chip 220. A third node is provided between the eighth port VSS and the other end of the first capacitor C3. The third node is connected to the ground terminal. The fourth port P7 / RST of the control chip 220 is connected to the controlled terminal of the switching circuit 210.

[0034] Specifically, a first capacitor C3 is provided between the first port VDD and the eighth port VSS to stabilize the power supply of the control chip 220. One end of the capacitor C3 is connected to the first port VDD and the other end is connected to the ground. Through the filtering effect of the capacitor, the power supply voltage is smoothed, the impact of voltage fluctuations on the operation of the control chip 220 is reduced, and the chip is ensured to operate stably.

[0035] Based on this, the second node is located between VDD and capacitor C3, serving as the power supply terminal for the control chip 220, providing a stable power supply. The third node connects VSS to the other end of capacitor C3 and is grounded to ensure a stable power supply ground.

[0036] In addition, the fourth port P7 / RST of the control chip 220 is connected to the controlled terminal of the switching circuit 210, which serves as a reset and start control. When an abnormality is detected, the control chip 220 controls the switching state of the switching circuit 210 through this port to achieve power switching or reset, ensuring the normal operation of the entire circuit and preventing the LED system from malfunctioning.

[0037] Specifically, the sampling circuit 300 includes a first resistor R6 and a second resistor R8. One end of the first resistor R6 is connected to one end of the second resistor R8 and a first switching transistor D6. The other end of the first resistor R6 is connected to the sixth port P1 of the control chip 220 and the load circuit 100. The other end of the second resistor R8 is connected to the fifth port P2 of the control chip 220 and the load circuit 100.

[0038] Specifically, the two ends of the first resistor R6 are connected to the second resistor R8 and the first switching transistor D6, respectively, and the other end is connected to the sixth port P1 of the control chip 220 and the load circuit 100 for sampling the load current. The current generates a voltage drop through the resistor R6, and this voltage drop is fed back to the control chip 220 through the sixth port P1, thereby realizing the monitoring of the LED load current.

[0039] Meanwhile, the other end of the second resistor R8 is connected to the fifth port P2 of the control chip 220 and the load circuit 100. The function of the second resistor R8 is to further adjust the voltage signal to ensure sampling accuracy. The control chip 220 makes a judgment based on the sampled voltage signal (reflecting current changes) and monitors the LED load current in real time. When the current is abnormal, the control chip 220 can adjust the switching circuit or perform other control actions to prevent the LED from being damaged or failing.

[0040] Furthermore, the switching circuit 210 includes a second switching transistor QP1, a third switching transistor QN1, a third resistor R3, a fourth resistor R5, and a fifth resistor R7. The first port (source) of the second switching transistor QP1 is connected to one end of the third resistor R3 and the output terminal of the rectifier circuit 600. The other end of the third resistor R3 is connected to the second port (gate) of the second switching transistor QP1 and one end of the fourth resistor R5. The third port (drain) of the second switching transistor QP1 is connected to the first port VCC1, the second port VCC2, and the third port VCC3 of the linear constant current chip U1. The other end of the fourth resistor R5 is connected to the first port (collector) of the third switching transistor QN1. The second port (base) of the third switching transistor QN1 is connected to one end of the fifth resistor R7. The other end of the fifth resistor R7 is connected to the fourth port P7 / RST of the control chip 220. The third port (emitter) of the third switching transistor QN1 is grounded.

[0041] First, the source of the second switching transistor QP1 is connected to one end of the third resistor R3, and the source is also connected to the output of the rectifier circuit 600 to provide power to the switching circuit. The other end of the third resistor R3 is connected to the gate of the second switching transistor QP1, and the gate is also connected to one end of the fourth resistor R5. The other end of the fourth resistor R5 is connected to the collector of the third switching transistor QN1. The drain of the second switching transistor QP1 is connected to the ports (VCC1, VCC2, VCC3) of the linear constant current chip U1 to provide a stable operating voltage for the constant current chip and regulate the constant current of the LED. The constant current chip U1 adjusts the magnitude of the LED current according to the voltage regulation signal to ensure the stable operation of the LED.

[0042] The base of the third switch QN1 is connected to one end of the fifth resistor R7, and the other end of the fifth resistor R7 is connected to the fourth port P7 / RST of the control chip 220. The control chip 220 sends a control signal to the third switch QN1 through this port to determine its operating state. When it is necessary to adjust or turn off the power supply, the control chip 220 will output a signal through the P7 port to affect the switching state of the third switch QN1, thereby regulating the current flow to the LED load.

[0043] The emitter of the third switch QN1 is grounded, completing the current loop closure. When the current is too high or too low, the control chip 220 can adjust the base voltage of QN1 through the P7 port, thereby affecting the switching state of its collector-emitter channel and controlling the flow of LED current. If the current is abnormal, the switching circuit 210 will adjust the switching states of the second switch QP1 and the third switch QN1 to realize the automatic adjustment or cut-off of LED current and prevent LED damage.

[0044] Furthermore, the voltage regulator circuit 700 includes a sixth resistor R1, a second capacitor C2, and a fifth switch D4. One end of the sixth resistor R1 is connected to the first node, and the other end of the sixth resistor R1 is connected to one end of the second capacitor C2, the second node, and the second port (cathode) of the fifth switch D4. The first port (anode) of the fifth switch D4 is connected to the other end of the second capacitor C2.

[0045] During operation, one end of the sixth resistor R1 is connected to the first node, and the other end is connected to one end of the second capacitor C2, the second node, and the cathode of the fifth switch D4. The current passing through the sixth resistor R1 generates a voltage drop, which is filtered by the capacitor C2 to stabilize the voltage output. The anode of the fifth switch D4 is connected to the other end of the second capacitor C2, which controls the voltage stability. When the input voltage fluctuates, the switch D4 adjusts the current flow to maintain a stable output voltage, thereby providing a reliable voltage supply for the entire circuit and ensuring stable system operation.

[0046] Furthermore, the rectifier circuit 600 includes a sixth switch D1, a seventh switch D2, an eighth switch D3, and a ninth switch D4. The first port (anode) of the sixth switch D1 is connected to the second port (cathode) of the seventh switch D2 and the first port of the voltage source 500. The second port (cathode) of the seventh switch D2 is connected to the second port (cathode) of the eighth switch D3 and the first port (source) of the second switch QP1. The first port (anode) of the eighth switch D3 is connected to the second port (cathode) of the ninth switch D4 and the second port of the voltage source 500. The first port (anode) of the seventh switch D2 is connected to the first port (anode) of the ninth switch D4 and the ground terminal.

[0047] Specifically, the anode of the sixth switch D1 is connected to the cathode of the seventh switch D2 and the first port of the voltage source 500, thus initiating the input of current from the voltage source into the rectifier circuit. The cathode of the seventh switch D2 is connected to the cathode of the eighth switch D3 and the source of the second switch QP1, allowing current to flow through this path into the eighth switch D3. The anode of the eighth switch D3 is connected to the cathode of the ninth switch D4 and the second port of the voltage source 500, forming the main path for current flow.

[0048] In addition, the anode of the seventh switch D2 is connected to the anode of the ninth switch D4 and grounded to complete the current loop. The entire rectifier circuit achieves polarity-independent processing of the input voltage through the switching of each switch, so that the current can adapt to different polarity inputs, ensuring that the subsequent circuits can receive the correct voltage stably, and avoiding circuit damage or unstable operation due to incorrect voltage polarity.

[0049] Furthermore, the load circuit 100 includes a first load LED1 and a second load LED2. The first port (anode) of the first load LED1 is connected to the first port VCC1 of the linear constant current chip U1 and the third port (drain) of the second switch QP1. The second port (cathode) of the first load LED1 is connected to the sixth port P1 of the control chip 220 and the other end of the first resistor R6. The first port (anode) of the second load LED2 is connected to the first port VCC1 of the linear constant current chip U1, the first port (anode) of the first load LED1, and the third port (drain) of the second switch QP1. The second port (cathode) of the second load LED2 is connected to the fifth port P2 of the control chip 220 and the other end of the second resistor R8.

[0050] Specifically, the load circuit 100 consists of a first load LED1 and a second load LED2. The current of both LEDs is regulated by a linear constant current chip U1 and a second switching transistor QP1. The anode of the first load LED1 is connected to the VCC1 port of the linear constant current chip U1 and the drain of the second switching transistor QP1, while the cathode is connected to the P1 port of the control chip 220 and the first resistor R6. The anode of the second load LED2 is connected to the VCC1 port of the linear constant current chip U1, the anode of the first load LED1, and the drain of the second switching transistor QP1, while its cathode is connected to the P2 port of the control chip 220 and the second resistor R8. The constant current chip U1 ensures the current of the two LEDs is stable and adjusts the brightness of the two LEDs according to the signal from the control chip 220. The second switching transistor QP1, as a key switching transistor, controls the current flow of the LED circuit, ensuring that the load current meets the preset conditions, and avoids LED damage or overheating by adjusting the current and brightness.

[0051] Next, we will introduce the control method of the LED monitoring circuit in detail, based on the specific circuit structure above: See Figure 4 The present invention also provides a control method for an LED monitoring circuit, applied to the circuit described in the above embodiments, comprising the following steps; S10, the current signal of the load circuit is acquired through the sampling circuit, and the current signal is subjected to dynamic time-frequency feature extraction processing to obtain the original feature vector set; S11. Based on the circuit topology parameters of the LED monitoring circuit, a circuit topology association model is constructed, and the original feature vector set is input into the circuit topology association model for feature fusion processing to generate a topology-enhanced feature vector. S12, Input the topology-enhanced feature vector into the anomaly detection model for risk quantification and output the anomaly risk value; S13, when the abnormal risk value exceeds a preset threshold, a switch control command is generated to adjust the working state of the load circuit.

[0052] Compared with the prior art, the embodiments of the present invention have the following beneficial effects: The current signal of the load circuit is acquired by a sampling circuit. The control chip performs dynamic time-frequency feature extraction on the current signal to obtain an original feature vector set that reflects the time-varying characteristics and frequency components of the signal. Then, a circuit topology association model is constructed based on the topology parameters of the LED monitoring circuit. The original feature vector set is input into this circuit topology association model for fusion, so that the features include circuit structure information, improving the feature's ability to represent anomalies. Then, the fused topology-enhanced feature vector is input into the anomaly detection model to quantify the risk and output an anomaly risk value. When the risk value exceeds the threshold, the control chip generates a switch control command to adjust the on / off state of the load circuit through the switch circuit. In this invention, dynamic time-frequency feature extraction can capture the instantaneous changes and frequency characteristics of the current signal, accurately reflecting the load's operating state; the circuit topology association model integrates topology parameters and signal features, combining feature analysis with circuit structure characteristics to enhance the accuracy of anomaly judgment; and the anomaly detection model quantifies the risk and links it with the switch control to achieve closed-loop control from detection to response. In summary, this embodiment of the invention can achieve real-time and accurate monitoring of the operating state of the LED load circuit, timely detection and adjustment of anomalies, and improve the reliability and stability of circuit operation.

[0053] As one example, the control chip, when performing the sampling circuit to acquire the current signal of the load circuit, performs dynamic time-frequency feature extraction processing on the current signal to obtain an original feature vector set, including: The sampling circuit acquires the first current signal of the first load LED1 and the second current signal of the second load LED2. The first current signal is subjected to time-domain waveform analysis processing to extract the rise time, fall time and pulse width modulation duty cycle features, and a first time-domain feature vector is generated. The second current signal is subjected to frequency domain transformation processing to extract the fundamental amplitude, third harmonic distortion rate and spectral energy distribution characteristics, and a second frequency domain feature vector is generated. Based on the physical connection topology of the first load LED1 and the second load LED2 on the circuit board, a dual load correlation matrix including impedance coupling coefficient is constructed; Align the first time-domain feature vector, the second frequency-domain feature vector, and the dual-load correlation matrix by feature dimension to generate an original feature vector set containing spatiotemporal correlation characteristics.

[0054] In this embodiment, for a load circuit including a first load LED1 and a second load LED2, the sampling circuit acquires the current signals of the two loads. The control chip performs time-domain waveform analysis on the current signal of the first load, extracting features such as rise time, fall time, and pulse width modulation duty cycle to generate a first time-domain feature vector, thereby capturing the time-dimensional variation characteristics of the first load current. The current signal of the second load is processed by frequency-domain transformation, extracting features such as fundamental amplitude, third harmonic distortion rate, and spectral energy distribution to generate a second frequency-domain feature vector, thereby analyzing the frequency components and energy distribution of the second load current. Subsequently, based on the physical connection topology of the two loads on the circuit board, a dual-load correlation matrix including impedance coupling coefficients is constructed. This matrix reflects the electrical connection characteristics between the two loads. Finally, the two feature vectors are aligned with the correlation matrix in terms of feature dimensions, fusing the time-domain and frequency-domain features with the spatial topological correlation characteristics between the loads to generate an original feature vector set containing spatiotemporal correlation characteristics, providing comprehensive and correlated feature data for subsequent anomaly detection. Therefore, this embodiment extracts targeted features from the current signals of different loads in the time and frequency domains respectively, and constructs an association matrix by combining the physical connection topology between loads. This enables in-depth analysis of the multi-dimensional and spatiotemporal correlation of the current signals of dual loads. Compared with the method of analyzing load signals in a single dimension or independently, it can capture the operating status characteristics of the load circuit more accurately and comprehensively, and effectively improve the accuracy and reliability of anomaly detection.

[0055] Specifically, the working process of this embodiment is as follows: In the actual operation of the LED monitoring circuit, the sampling circuit serves as the front end for signal acquisition. Its two sampling channels are connected in series in the current loops of the first load LED1 and the second load LED2, respectively, to periodically sample the circuit at a fixed sampling frequency (e.g., 100kHz). During each sampling, the first current signal of the first load LED1 and the second current signal of the second load LED2 are transmitted in real time to the designated pin of the control chip, completing the current signal acquisition.

[0056] After receiving the first current signal, the control chip initiates the time-domain waveform analysis process. First, the first current signal is preprocessed using a moving average filtering algorithm. By setting the size of the moving window (e.g., containing 10 sampling points), the continuously acquired signal is smoothed to remove high-frequency noise interference and improve signal quality. When extracting the rise time, this embodiment improves upon the traditional fixed threshold detection method by employing a dynamic threshold slope detection algorithm. Specifically, the process involves first calculating the signal within a certain time window (set as...). The average slope within 20 sampling points The formula is ,in For the first Current values ​​at each sampling point Set the sampling interval; then set the dynamic threshold. , This is an adjustment coefficient, with a value ranging from 1.5 to 2.5. When the signal slope first exceeds... Record the start time. The recording ends when the signal reaches 90% of its stable value. Rising time Falling edge time The extraction method is similar to that for the rising edge, achieving accurate detection through dynamic threshold adjustment. For pulse width modulation duty cycle... The calculation involves the control chip detecting the duration of the high-level signal. and a complete modulation cycle Using the formula The calculations show that the extracted rise time, fall time, and pulse width modulation duty cycle are arranged in a specific order to generate the first time-domain feature vector.

[0057] For the second current signal, the control chip performs frequency domain transformation processing. An improved Discrete Fourier Transform (DFT) algorithm is employed, introducing a phase compensation mechanism based on the traditional DFT. First, the second current signal is divided into multiple data segments, each with a length of... Sampling points (set) = 1024), to reduce spectral leakage, a 50% overlap rate is set between adjacent data segments. After performing a DFT transform on each data segment, the phase relationship between adjacent data segments is determined using the formula Phase compensation is performed, where This is the original DFT transform result. The phase compensation value is calculated based on adjacent data segments. This is the compensated spectral data. In the processed spectrum, the fundamental amplitude... For frequency Amplitude at the fundamental frequency (e.g., 50Hz) of the LED; Third harmonic distortion rate. Through formula Calculation, where for The amplitude at the third harmonic frequency is calculated; simultaneously, the energy proportion of each frequency component is calculated to obtain the spectral energy distribution characteristics. The fundamental amplitude, third harmonic distortion rate, and spectral energy distribution characteristics are combined according to a specified format to generate a second frequency domain feature vector.

[0058] Subsequently, the control chip constructs a dual-load correlation matrix, including the impedance coupling coefficient, based on the physical connection information of the first load LED1 and the second load LED2 on the circuit board. This is to accurately calculate the impedance coupling coefficient. This embodiment considers multiple influencing factors and uses a calculation formula. ,in This is an empirical coefficient (ranging from 0.8 to 1.2). The length of the conductor between the two loads. and These are the width and height of the conductor, respectively. The resistivity of the conductor material. Based on calculations... Construct a dual load correlation matrix This matrix reflects the electromagnetic coupling and electrical association characteristics between the two loads.

[0059] Finally, feature dimension alignment is performed to generate the original feature vector set. Since the first time-domain feature vector, the second frequency-domain feature vector, and the dual-load correlation matrix have different dimensions, the control chip first expands the dimensions of the dual-load correlation matrix. A linear interpolation algorithm is used to expand the matrix elements according to the dimensional requirements of the feature vectors, ensuring that the number of elements matches the total number of elements in both feature vectors. Then, a feature importance-based concatenation strategy is adopted: the first time-domain feature vector is placed at the beginning of the new vector, followed by the second frequency-domain feature vector, and finally, the expanded dual-load correlation matrix elements are sequentially filled into the remaining positions. During the concatenation process, to ensure the weight balance of different types of features, each feature value is normalized, mapping it to the range of 0-1, ultimately forming an original feature vector set containing spatiotemporal correlation characteristics. This provides a comprehensive and accurate data foundation for subsequent feature fusion and anomaly detection based on circuit topology.

[0060] As one example, the control chip executes the circuit topology parameters based on the LED monitoring circuit, constructs a circuit topology association model, and inputs the original feature vector set into the circuit topology association model for feature fusion processing to generate topology-enhanced feature vectors, including: Obtain the impedance parameters of the wires from the output terminal of the switching circuit to the input terminal of the linear constant current circuit; Obtain the current stability and voltage drop characteristic parameters from the output terminal of the linear constant current circuit to the input terminal of the load circuit; Based on the conductor impedance parameter, the current stability parameter, and the voltage drop characteristic parameter, a multi-dimensional topology edge weight calculation rule is defined. Each feature vector in the original feature vector set is weighted according to the multi-dimensional topological edge weight calculation rule to obtain the weight allocation result. Based on the weight allocation results, a three-level circuit topology association model is constructed, which includes switching circuit nodes, constant current circuit nodes, and load circuit nodes. The original feature vector set is input into the circuit topology association model for feature fusion processing to generate topology-enhanced feature vectors.

[0061] In this embodiment, under the architecture where a linear constant current circuit provides a stable current to the load circuit, the control chip first obtains the conductor impedance parameters from the output of the switching circuit to the input of the linear constant current circuit. These parameters reflect the impedance characteristics along the power transmission path. Next, it obtains the current stability and voltage drop characteristics from the output of the linear constant current circuit to the input of the load circuit. These parameters reflect the quality of power supply from the constant current circuit to the load. Based on these three types of parameters, a multi-dimensional topology edge weight calculation rule is defined. Each feature vector in the original feature vector set is weighted according to the rule to reflect the importance and correlation of different features in the circuit topology. Subsequently, based on the weight allocation results, a three-level topology circuit topology correlation model containing switching circuit nodes, constant current circuit nodes, and load circuit nodes is constructed. This model presents the connection relationships and feature importance of each part of the circuit in a graph structure. Finally, the original feature vector set is input into this model for feature fusion, so that the feature vectors not only contain the characteristics of the signal itself but also incorporate circuit topology information, generating topology-enhanced feature vectors. In summary, this embodiment constructs a three-level circuit topology association model and performs feature fusion, enabling the anomaly detection model to analyze the actual physical structure and electrical characteristics of the circuit. Compared with traditional detection methods based solely on signal features, it can more accurately identify potential faults caused by circuit topology anomalies, such as changes in conductor impedance and decreased stability of constant current circuits. This significantly improves the sensitivity and diagnostic accuracy for early latent faults, while providing a topological hierarchy for fault source location, thus enhancing the intelligence and reliability of the LED monitoring circuit.

[0062] Specifically, the working process of this embodiment is as follows: When the LED monitoring circuit is running, the control chip first initiates the acquisition of circuit topology parameters. This includes acquiring the impedance parameters of the conductors from the output of the switching circuit to the input of the linear constant current circuit (pre-measured and stored). Next, it acquires the current stability and voltage drop characteristics from the output of the linear constant current circuit to the input of the load circuit (these parameters are also pre-measured and stored; the measurement method is based on existing technology).

[0063] After obtaining the conductor impedance parameters, current stability parameters, and voltage drop characteristic parameters, the control chip defines the multi-dimensional topology edge weight calculation rules as follows: First, the objective weights of each parameter are calculated using the entropy weight method. The formula is (in For the first (Entropy values ​​of each parameter); then, the subjective weights are determined using the analytic hierarchy process. After constructing a judgment matrix and performing a consistency check, the subjective weights of each parameter are obtained; finally, the subjective and objective weights are combined and a weighted average formula is used. ( Using the fusion coefficient (valued at 0.6), the final weight calculation rule is obtained, assigning a weight value to each topological edge. .

[0064] Subsequently, the control chip performs weight allocation processing on each feature vector in the original feature vector set. Based on the circuit topology, a feature-topology mapping table is established to clarify the topological connection relationship corresponding to each feature value. For feature values ​​related to a specific topological edge, weighting is performed according to the edge's weight \(W\), using the formula... ( These are the original eigenvalues. (These are the weighted eigenvalues). After weighting all eigenvalues, they are recombined into a weighted eigenvector, forming the weight allocation result, which incorporates the topological importance information into the eigenvector.

[0065] Based on the weight allocation results, the control chip uses a Graph Convolutional Network (GCN) architecture to construct a three-level circuit topology association model. The switching circuit nodes, constant current circuit nodes, and load circuit nodes are encoded as follows: The connecting edges between nodes are Using the node feature matrix (Including attribute information of the circuit elements corresponding to each node) and edge weight matrix (Adjacency matrix form, where elements are edge weights) ), through graph convolution operations ( To add a self-loop adjacency matrix, for The degree matrix of the diagonal nodes, For the first Layer node feature matrix, For the first Layer weight matrix, (As an activation function), it learns the topological relationships between nodes and constructs a complete circuit topology relationship model.

[0066] Finally, the control chip inputs the original feature vector set into the circuit topology model for feature fusion. A fusion algorithm combining a gated recurrent unit (GRU) and a topological attention mechanism is employed. First, the topological attention mechanism calculates the attention weights of each part of the feature vector based on the weights of each node and edge in the circuit topology model. The formula is ( The eigenvector of the eigenvector Each part (A function to calculate the attention score). The attention weights and the original feature vector are then input into the GRU unit, and processed through a gating mechanism. , , ( As input features, For output features, To reset the door, To update the door, In the candidate hidden state, (Element-wise multiplication) enables selective fusion of features, ultimately generating a topology-enhanced feature vector, providing more accurate input data for subsequent anomaly detection.

[0067] As one example, the control chip, when performing the feature fusion processing of inputting the original feature vector set into the circuit topology association model to generate topology-enhanced feature vectors, includes: Based on the node hierarchy in the circuit topology association model, a topology node mapping process is performed to divide the original feature vector set into a first feature subset corresponding to the switching circuit node, a second feature subset corresponding to the constant current circuit node, and a third feature subset corresponding to the load circuit node. Perform switch control timing matching processing on the first feature subset to obtain a dynamic alignment result with the constant current characteristics of the constant current circuit node; The second feature subset is subjected to constant current characteristic association processing with the dynamic alignment result to generate an intermediate feature vector containing the constant current parameters of the linear constant current chip; Based on the physical connection topology in the dual load correlation matrix, the third feature subset and the intermediate feature vector are convolutionally fused to generate a topology-enhanced feature vector with uniform dimensions.

[0068] In this embodiment, for a linear constant current circuit including a first switching transistor and a linear constant current chip, the control chip divides the original feature vector set into three feature subsets corresponding to the switching circuit node, the constant current circuit node, and the load circuit node based on the node hierarchy relationship of the circuit topology association model. The first feature subset undergoes switching control timing matching processing to dynamically align it with the constant current characteristics of the constant current circuit node, ensuring the synergy between switching actions and constant current characteristics. The second feature subset is then correlated with the dynamic alignment result using constant current characteristics, incorporating the constant current parameters of the linear constant current chip to generate an intermediate feature vector, enhancing the correlation and accuracy of the constant current circuit's related features. Finally, based on the physical connection topology relationship reflected by the dual load association matrix, the third feature subset and the intermediate feature vector undergo convolutional fusion processing to deeply integrate the load characteristics and constant current circuit characteristics, unifying the feature dimensions, thereby generating a topology-enhanced feature vector. This provides more accurate and structured feature data for subsequent anomaly detection. Therefore, this embodiment effectively integrates the characteristic correlations of switching circuits, constant current circuits, and load circuits in the topology by performing hierarchical and targeted processing and fusion on the original feature vector set. This enables the generated topology-enhanced feature vectors to more comprehensively and accurately reflect the actual operating state of the circuit. Compared with traditional feature processing methods, it improves the detection accuracy and analysis depth of circuit anomalies. In particular, when identifying complex problems such as mismatch between switching timing and constant current characteristics, or abnormal load and constant current circuit parameters, it can enhance the accuracy and reliability of fault diagnosis of LED monitoring circuits and ensure stable circuit operation.

[0069] Specifically, the working process of this embodiment is as follows: During LED monitoring circuit operation, the control chip begins processing the original feature vector set. First, based on the constructed circuit topology association model, an improved topology node mapping algorithm is used to perform topology node mapping processing. This model presents the switching circuit nodes, constant current circuit nodes, and load circuit nodes in the circuit, along with their connections, in a graph structure. The control chip first analyzes the key attribute characteristics of each node, such as the switching frequency of the switching circuit nodes, the output current range of the constant current circuit nodes, and the impedance of the load circuit nodes, to construct a node feature library. For each feature vector in the original feature vector set... By calculating its correlation with the features of each node. To divide the feature subsets, the calculation formula is as follows: ,in These correspond to the switching circuit node, constant current circuit node, and load circuit node, respectively. Representing feature dimension, This represents the total number of feature dimensions. For the first The weight coefficients for each feature dimension are set according to the importance of that feature to the circuit function. It is an eigenvector In the dimensional eigenvalues It is the first The node at the th Feature values ​​of a dimension. Correlation degree. The feature subset corresponding to the smallest node is the subset to which the feature vector belongs, thus dividing the original feature vector set into the first feature subset, the second feature subset, and the third feature subset.

[0070] After completing the feature subset partitioning, switching control timing matching is performed on the first feature subset. The first switch is controlled by the PWM signal output by the control chip, and its switching timing directly affects the input stability and output constant current characteristics of the linear constant current chip. The control chip acquires the constant current characteristic data of the linear constant current chip under different input conditions and constructs a constant current characteristic database. To achieve dynamic alignment between the switching control timing and the constant current characteristics, the following timing matching algorithm is proposed: the particle position parameter is set to the frequency of the PWM signal. and duty cycle The speed parameters are and The deviation between the output current of the linear constant current chip and the target constant current value is used as the fitness function. ,in yes The actual output current of the linear constant current chip at any given time. It is the target constant current value. The sampling period is defined as follows. In each iteration, the particles are quantified according to the formula... , Update speed, according to the formula , Update location, where For the number of iterations, For inertial weights, As a learning factor, A random number between 0 and 1 This represents the particle's own historical optimal position. This is the globally optimal position. Iterative adjustments are made continuously. and until the fitness function Less than the set threshold This yields a dynamic alignment result that best matches the constant current characteristics of the constant current circuit nodes.

[0071] Subsequently, the second feature subset is correlated with the dynamic alignment results using constant current characteristics. The second feature subset includes various parameter features of the linear constant current chip, such as input voltage fluctuation, output current ripple, and power loss. The control chip employs an improved feature correlation fusion algorithm to construct a feature correlation matrix. For each feature in the second feature subset And each timing parameter in the dynamic alignment result Through formula Calculate the association weights, where Features and timing parameters cosine similarity, The number of features in the second feature subset. The number of parameters for the dynamic alignment result. Based on the association weight. The second feature subset is weighted and fused to generate an intermediate feature vector containing the constant current parameters of the linear constant current chip.

[0072] Finally, based on the physical connection topology in the dual-load correlation matrix, the third feature subset and the intermediate feature vector are subjected to convolutional fusion processing. The dual-load correlation matrix details the electrical connection and electromagnetic coupling characteristics between the first load LED1 and the second load LED2. The control chip employs an enhanced topology-aware convolutional fusion algorithm to convert the third feature subset, the intermediate feature vector, and the dual-load correlation matrix into a multidimensional tensor form. A special topology convolution kernel is designed. Its parameters are initialized based on the dual-load correlation matrix and circuit topology to better capture the topological relationships between loads. Topological weight coefficients are introduced during the convolution calculation. This coefficient is determined by the elements of the dual-load correlation matrix and the connection strength of the circuit nodes. The convolution calculation formula is: ,in It outputs tensor elements. It is the input tensor element. , The kernel size is denoted as . After multiple convolution, pooling, and activation operations, the output is dimensionality adjusted and normalized to generate a topology-enhanced feature vector with uniform dimensions. This provides more accurate, comprehensive, and integrated circuit topology information for subsequent anomaly detection.

[0073] As one example, the step of inputting the topology-enhanced feature vector into the anomaly detection model for risk quantification and outputting anomaly risk values ​​includes: The topology-enhanced feature vector is decomposed into time-domain feature components and frequency-domain feature components; The time-domain feature components and the frequency-domain feature components are input into a preset anomaly detection model, and the matching degree is calculated with the preset time-domain reference features and frequency-domain reference features respectively to generate time-domain matching degree scores and frequency-domain matching degree scores. Based on preset risk weight coefficients, the time-domain matching score and the frequency-domain matching score are subjected to weighted risk quantification to obtain anomaly risk values.

[0074] In this embodiment, the control chip decomposes the topology-enhanced feature vector into time-domain and frequency-domain feature components to restore the signal's characteristics in the time and frequency dimensions. Subsequently, these two feature components are input into a preset anomaly detection model and their matching degree is calculated against preset time-domain and frequency-domain benchmark features. By quantifying the difference between the actual features and the benchmark features, time-domain and frequency-domain matching degree scores are generated, intuitively reflecting the degree of deviation between the circuit's operating state and its normal state. Finally, based on preset risk weight coefficients, the time-domain and frequency-domain matching degree scores are weighted and quantified to comprehensively consider the differences in the impact of time-domain and frequency-domain features on circuit anomalies, converting the scores into anomaly risk values, thus achieving a quantitative assessment of the circuit's operational risk. In summary, this embodiment, by decomposing the topology-enhanced feature vector and calculating its matching degree against benchmark features, combined with risk weight coefficient weighting quantization, can comprehensively and meticulously evaluate the circuit's operating state in both the time and frequency domains. Compared to single-dimensional anomaly detection methods, this significantly improves the accuracy and reliability of anomaly judgment.

[0075] Specifically, the working process of this embodiment is as follows: During the operation of the LED monitoring circuit, after the control chip obtains the topology enhancement feature vector, it performs risk quantification processing.

[0076] First, the topology-enhanced feature vector is decomposed. The control chip employs the following improved feature decomposition algorithm: An attention weight calculation module is constructed for each element in the topology-enhanced feature vector. Through formula Calculate its attention weights, where It is a trainable weight matrix. It is a bias vector. This represents the number of elements in the feature vector. Based on the inherent characteristics of features in the time and frequency domains, and combined with attention weights, the topology-enhanced feature vector is decomposed into time-domain feature components. and frequency domain characteristic components For example, features with obvious time-series variation patterns are assigned higher temporal attention weights and classified into temporal feature components.

[0077] Next, the temporal and frequency domain feature components are input into a pre-defined anomaly detection model for matching degree calculation. The anomaly detection model employs an improved structure based on a generative adversarial network (GAN). For the temporal feature components, the generator... Based on time-domain feature components Generating time-domain features of the simulation Discriminator Then determine if the input is a true temporal reference feature. Or generated simulated features Through adversarial training, the parameters of the generator and discriminator are optimized to make the generated simulated features as close as possible to the real benchmark features. After training, the Structural Similarity Index (SSIM) algorithm is used to calculate the temporal matching degree. The formula is ,in , These are the mean values ​​of the time-domain baseline feature and the simulated feature, respectively. These are their variances. It is covariance. , It is a constant. For the frequency domain feature components, a GAN-based structure is also used, and a combined difference metric of frequency domain amplitude and phase is introduced when calculating the similarity, using the formula... Calculate the frequency domain matching score, where It is a frequency domain reference feature. It is a frequency domain characteristic component. It is the adjustment coefficient. These represent the amplitude and phase of the feature, respectively.

[0078] Finally, weighted risk quantification is performed based on preset risk weight coefficients. The control chip employs the following dynamic weight adjustment algorithm: defining multiple fuzzy variables, such as time-domain matching score. Frequency domain matching score Circuit operating environment temperature Working hours Etc. Construct a fuzzy rule base, for example, when Lower lower and When the risk level is high, appropriately increase the risk weighting coefficients in the time and frequency domains. and Through a fuzzy inference system, the risk weight coefficients are dynamically adjusted based on the actual values ​​of each fuzzy variable. Finally, the formula is used to... The abnormal risk value is calculated, thereby accurately quantifying the operational risk of the LED monitoring circuit, providing reliable data support for timely detection of potential circuit anomalies and ensuring stable circuit operation.

[0079] When the abnormal risk value calculated by the control chip exceeds a preset threshold, it indicates a potential fault risk in the LED monitoring circuit. At this point, the control chip generates a corresponding switching control command. This command adjusts the operating parameters of the first switching transistor and the linear constant current chip via the switching circuit in the control circuit. For example, it adjusts the output current of the linear constant current chip or controls the on / off state of the first switching transistor, thereby changing the power supply to the first load LED1 and the second load LED2 in the load circuit. This achieves dynamic adjustment of the load circuit's operating state, reduces the risk of circuit abnormalities, and ensures the safe and stable operation of the LED monitoring circuit.

[0080] The above is only used to illustrate the technical solution of the present invention and is not intended to limit it. Any other modifications or equivalent substitutions made by those skilled in the art to the technical solution of the present invention, as long as they do not depart from the spirit and scope of the technical solution of the present invention, should be covered within the scope of the claims of the present invention.

Claims

1. A control method for an LED monitoring circuit based on a topological correlation model, characterized in that, Includes the following steps; The current signal of the load circuit is acquired by a sampling circuit, and the current signal is subjected to dynamic time-frequency feature extraction processing to obtain the original feature vector set. Based on the circuit topology parameters of the LED monitoring circuit, a circuit topology association model is constructed, and the original feature vector set is input into the circuit topology association model for feature fusion processing to generate topology-enhanced feature vectors. The topology-enhanced feature vector is input into the anomaly detection model for risk quantification, and anomaly risk value is output. When the abnormal risk value exceeds a preset threshold, a switch control command is generated to adjust the working state of the load circuit. Based on the circuit topology parameters of the LED monitoring circuit, a circuit topology association model is constructed, and the original feature vector set is input into the circuit topology association model for feature fusion processing to generate topology-enhanced feature vectors, including: Obtain the impedance parameters of the wires from the output terminal of the switching circuit to the input terminal of the linear constant current circuit; Obtain the current stability parameters and voltage drop characteristic parameters from the output terminal of the linear constant current circuit to the input terminal of the load circuit; Based on the conductor impedance parameter, the current stability parameter, and the voltage drop characteristic parameter, a multi-dimensional topology edge weight calculation rule is defined. Each feature vector in the original feature vector set is weighted according to the multi-dimensional topological edge weight calculation rule to obtain the weight allocation result. Based on the weight allocation results, a circuit topology association model containing a three-level topology of switching circuit nodes, constant current circuit nodes, and load circuit nodes is constructed. The original feature vector set is input into the circuit topology association model for feature fusion processing to generate topology-enhanced feature vectors. The current signal of the load circuit is acquired through the sampling circuit, and the current signal is subjected to dynamic time-frequency feature extraction processing to obtain an original feature vector set, including: The sampling circuit acquires the first current signal of the first load LED1 and the second current signal of the second load LED2. The first current signal is subjected to time-domain waveform analysis processing to extract the rise time, fall time and pulse width modulation duty cycle features, and a first time-domain feature vector is generated. The second current signal is subjected to frequency domain transformation processing to extract the fundamental amplitude, third harmonic distortion rate and spectral energy distribution characteristics, and a second frequency domain feature vector is generated. Based on the physical connection topology of the first load LED1 and the second load LED2 on the circuit board, a dual load correlation matrix including impedance coupling coefficient is constructed; Align the first time-domain feature vector, the second frequency-domain feature vector, and the dual-load correlation matrix by feature dimension to generate an original feature vector set containing spatiotemporal correlation characteristics; The two sampling channels of the sampling circuit are connected in series in the current loops of the first load LED1 and the second load LED2, respectively, and the circuit is periodically sampled at a fixed sampling frequency of 100kHz. During each sampling, the first current signal of the first load LED1 and the second current signal of the second load LED2 are transmitted in real time to the designated pin of the control chip.

2. The control method for LED monitoring circuit based on topological association model according to claim 1, characterized in that, The step of inputting the original feature vector set into the circuit topology association model for feature fusion processing to generate topology-enhanced feature vectors includes: Based on the node hierarchy in the circuit topology association model, a topology node mapping process is performed to divide the original feature vector set into a first feature subset corresponding to the switching circuit node, a second feature subset corresponding to the constant current circuit node, and a third feature subset corresponding to the load circuit node. Perform switch control timing matching processing on the first feature subset to obtain a dynamic alignment result with the constant current characteristics of the constant current circuit node; The second feature subset is subjected to constant current characteristic association processing with the dynamic alignment result to generate an intermediate feature vector containing the constant current parameters of the linear constant current chip; Based on the physical connection topology in the dual load correlation matrix, the third feature subset and the intermediate feature vector are convolutionally fused to generate a topology-enhanced feature vector with uniform dimensions.

3. The control method for LED monitoring circuit based on topological correlation model according to claim 2, characterized in that, The step of inputting the topology-enhanced feature vector into the anomaly detection model for risk quantification and outputting anomaly risk values ​​includes: The topology-enhanced feature vector is decomposed into time-domain feature components and frequency-domain feature components; The time-domain feature components and the frequency-domain feature components are input into a preset anomaly detection model, and the matching degree is calculated with the preset time-domain reference features and frequency-domain reference features respectively to generate time-domain matching degree scores and frequency-domain matching degree scores. Based on preset risk weight coefficients, the time-domain matching score and the frequency-domain matching score are subjected to weighted risk quantification to obtain anomaly risk values.

4. An LED monitoring circuit based on a topological correlation model, characterized in that, The system includes a load circuit, a control circuit, and a sampling circuit. The sampling circuit is used to acquire the status signal of the load circuit. The input terminal of the sampling circuit is connected to the load circuit, and the output terminal of the sampling circuit is connected to the input terminal of the control circuit. The control circuit includes a switching circuit and a control chip. The output terminal of the control chip is connected to the controlled terminal of the switching circuit, the output terminal of the switching circuit is connected to the input terminal of the load circuit, and the output terminal of the sampling circuit is connected to the control port of the control chip. The switching circuit is used to control the on / off state of the load circuit. The two sampling channels of the sampling circuit are connected in series in the current loops of the first load and the second load, respectively, to periodically sample the circuit at a fixed sampling frequency of 100kHz. During each sampling, the first current signal of the first load and the second current signal of the second load are transmitted in real time to a designated pin of the control chip. The control chip is used for: The current signal of the load circuit is acquired through the sampling circuit, and the current signal is subjected to dynamic time-frequency feature extraction processing to obtain the original feature vector set. Based on the circuit topology parameters of the LED monitoring circuit, a circuit topology association model is constructed, and the original feature vector set is input into the circuit topology association model for feature fusion processing to generate topology-enhanced feature vectors. The topology-enhanced feature vector is input into the anomaly detection model for risk quantification, and anomaly risk value is output. When the abnormal risk value exceeds a preset threshold, a switch control command is generated to adjust the working state of the load circuit. The control chip is used to execute the control method of the LED monitoring circuit according to claim 1.

5. The LED monitoring circuit based on a topology association model according to claim 4, characterized in that, The load circuit includes a first load LED1 and a second load LED2, and the current signal collected by the sampling circuit includes a first current signal of the first load LED1 and a second current signal of the second load LED2. Specifically, when the control chip performs the following sub-steps to acquire the current signal of the load circuit through the sampling circuit and extract the dynamic time-frequency features of the current signal to obtain the original feature vector set: The sampling circuit acquires the first current signal of the first load LED1 and the second current signal of the second load LED2. The first current signal is subjected to time-domain waveform analysis processing to extract the rise time, fall time and pulse width modulation duty cycle features, and a first time-domain feature vector is generated. The second current signal is subjected to frequency domain transformation processing to extract the fundamental amplitude, third harmonic distortion rate and spectral energy distribution characteristics, and a second frequency domain feature vector is generated. Based on the physical connection topology of the first load LED1 and the second load LED2 on the circuit board, a dual load correlation matrix including impedance coupling coefficient is constructed; Align the first time-domain feature vector, the second frequency-domain feature vector, and the dual-load correlation matrix by feature dimension to generate an original feature vector set containing spatiotemporal correlation characteristics.

6. The LED monitoring circuit based on a topology association model according to claim 5, characterized in that, The circuit also includes a linear constant current circuit, which provides a stable current to the load circuit. The output of the linear constant current circuit is connected to the input of the load circuit. The output of the switching circuit is connected to the input of the linear constant current circuit. The input of the sampling circuit is connected to the sampling terminal of the linear constant current circuit. Specifically, when the control chip executes the circuit topology parameters based on the LED monitoring circuit to construct a circuit topology association model, and inputs the original feature vector set into the circuit topology association model for feature fusion processing to generate a topology-enhanced feature vector, it performs the following sub-steps: Obtain the impedance parameters of the wires from the output terminal of the switching circuit to the input terminal of the linear constant current circuit; Obtain the current stability parameters and voltage drop characteristic parameters from the output terminal of the linear constant current circuit to the input terminal of the load circuit; Based on the conductor impedance parameter, the current stability parameter, and the voltage drop characteristic parameter, a multi-dimensional topology edge weight calculation rule is defined. Each feature vector in the original feature vector set is weighted according to the multi-dimensional topological edge weight calculation rule to obtain the weight allocation result. Based on the weight allocation results, a circuit topology association model containing a three-level topology of switching circuit nodes, constant current circuit nodes, and load circuit nodes is constructed. The original feature vector set is input into the circuit topology association model for feature fusion processing to generate topology-enhanced feature vectors.

7. The LED monitoring circuit based on a topology association model according to claim 6, characterized in that, The linear constant current circuit includes a first switching transistor and a linear constant current chip. The output terminal of the switching circuit is connected to the input terminal of the linear constant current chip, and the output terminal of the linear constant current chip is connected to the input terminal of the load circuit. The first switching transistor is connected to the output terminal of the linear constant current chip. Specifically, when the control chip performs the feature fusion processing of inputting the original feature vector set into the circuit topology association model to generate topology-enhanced feature vectors, it executes the following sub-steps: Based on the node hierarchy in the circuit topology association model, a topology node mapping process is performed to divide the original feature vector set into a first feature subset corresponding to the switching circuit node, a second feature subset corresponding to the constant current circuit node, and a third feature subset corresponding to the load circuit node. Perform switch control timing matching processing on the first feature subset to obtain a dynamic alignment result with the constant current characteristics of the constant current circuit node; The second feature subset is subjected to constant current characteristic association processing with the dynamic alignment result to generate an intermediate feature vector containing the constant current parameters of the linear constant current chip; Based on the physical connection topology in the dual load correlation matrix, the third feature subset and the intermediate feature vector are convolutionally fused to generate a topology-enhanced feature vector with uniform dimensions.

8. The LED monitoring circuit based on a topology association model according to claim 7, characterized in that, When the control chip performs the process of inputting the topology enhancement feature vector into the anomaly detection model for risk quantification and outputting anomaly risk values, it specifically executes the following sub-steps: The topology-enhanced feature vector is decomposed into time-domain feature components and frequency-domain feature components; The time-domain feature components and the frequency-domain feature components are input into a preset anomaly detection model, and the matching degree is calculated with the preset time-domain reference features and frequency-domain reference features respectively to generate time-domain matching degree scores and frequency-domain matching degree scores. Based on preset risk weight coefficients, the time-domain matching score and the frequency-domain matching score are subjected to weighted risk quantification to obtain anomaly risk values.

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