Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a method for forming the same are disclosed. The method includes: performing multiple stacking processes; each stacking process includes: forming a sub-stacked structure consisting of alternating first and second stacked material layers stacked longitudinally; forming sub-vias penetrating the sub-stacked structure; filling the sub-vias between adjacent stacking processes to form a first sacrificial layer; removing the first sacrificial layer to form a via connected by a plurality of sub-vias; wherein, by controlling the thickness of the second stacked material layers in each sub-stacked structure to be different; or, prior to the step of filling the sub-vias to form the first sacrificial layer, by forming a sidewall protective layer on the sidewalls of the sub-stacked structure exposed by the sub-vias, the difference ratio between the surface areas of each exposed second stacked material layer of the formed via is greater than or equal to 0 and less than or equal to 5%. This disclosure is beneficial for improving the storage performance of a memory constructed from a stacked structure.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0002] In pursuit of the ultimate chip area utilization, major memory manufacturers (such as Dynamic Random Access Memory (DRAM)) use advanced semiconductor processes to minimize the area of ​​a single memory cell on the wafer, thereby increasing memory density.

[0003] With the increasing demand for memory density, the number of layers in 3D memory is constantly rising. In 3D random access memory (RAM), a stacked approach is typically used, vertically stacking multiple layers of data storage cells to achieve this stacked 3D RAM. To obtain this stacked 3D RAM, a stacked structure of two materials alternating layers needs to be formed on a silicon substrate, and deep holes need to be etched into the stacked structure. For high aspect ratio deep hole etching, the energy and directionality of the ions deteriorate due to energy decay and charge accumulation at the bottom of the deep holes during plasma etching. This leads to random lateral etching and systematic distortion of the deep hole morphology, which severely affects the device's memory performance. Summary of the Invention

[0004] The problem addressed by the embodiments of this disclosure is to provide a semiconductor structure and a method for forming the same, which is beneficial for improving the storage performance of a memory composed of a stacked structure.

[0005] To address the aforementioned problems, this disclosure provides a method for forming a semiconductor structure, comprising: performing multiple stacking processes along a longitudinal direction on a semiconductor substrate to form a stacked structure, wherein the semiconductor substrate includes an etch stop structure; wherein the stacking process includes: forming a sub-stacked structure composed of alternating first and second stacked material layers along a longitudinal direction, wherein all first stacked material layers in the sub-stacked structure have the same thickness, and all second stacked material layers in the sub-stacked structure have the same thickness; forming a sub-via penetrating the sub-stacked structure, wherein the projection of the sub-via on a horizontal plane lies within the projection of the etch stop structure on a horizontal plane, and the sub-via formed after the first stacking process exposes the etch stop structure; between two adjacent stacking processes, filling the sub-via to form a first sacrificial layer; wherein the sub-via formed in the later stacking process exposes the first sacrificial layer in the sub-via formed in the previous stacking process, and the previous stacking process... The first sacrificial layer in the sub-via formed by the stacking process serves as the etch stop layer for the subsequent stacking process to form the sub-via. The first sacrificial layer is removed to form a via connected by multiple sub-vias that expose the etch stop structure. The difference ratio between the surface areas of each exposed second-layer stacked material layer in the via is greater than or equal to 0 and less than or equal to 5%. Where removing the first sacrificial layer would damage the second-layer stacked material layers, the thickness of the second-layer stacked material layers in each sub-stack structure is controlled to be different, so that the difference ratio between the surface areas of each exposed second-layer stacked material layer in the formed via is greater than or equal to 0 and less than or equal to 5%. Alternatively, before filling the sub-via to form the first sacrificial layer, a sidewall protective layer is formed on the sidewall of the sub-stack structure exposed by the sub-via, so that the difference ratio between the surface areas of each exposed second-layer stacked material layer in the formed via is greater than or equal to 0 and less than or equal to 5%.

[0006] Optionally, the cross-section of the through hole is circular, and the difference ratio between the surface areas of each exposed second-layer material layer is greater than or equal to 0 and less than or equal to 5%. This means that the difference ratio between the product of the diameter of the through hole at the location of each second-layer material layer and the thickness of the second-layer material layer is greater than or equal to 0 and less than or equal to 5%.

[0007] Optionally, the material of the first sacrificial layer includes amorphous carbon, and the material of the first stacked material layer includes silicon oxide.

[0008] Optionally, a dry etching process can be used to remove the first sacrificial layer.

[0009] Optionally, the material of the second stacked material layer includes silicon nitride; by controlling the thickness of the second stacked material layer in each sub-stack structure to be different, the difference ratio between the surface areas of each second stacked material layer exposed by the formed through-hole is greater than or equal to 0 and less than or equal to 5%, specifically: controlling the thickness of the second stacked material layer in the lower sub-stack structure to be greater than the thickness of the second stacked material layer in the upper sub-stack structure.

[0010] Optionally, the material of the second stacked material layer includes silicon nitride; prior to the step of filling the sub-vias to form the first sacrificial layer, a sidewall protective layer is formed on the sidewalls of the sub-stacked structure exposed by the sub-vias, the material of the sidewall protective layer including silicon oxide; after removing the first sacrificial layer, the sidewall protective layer is further removed such that the difference ratio between the surface areas of each second stacked material layer exposed by the formed vias is greater than or equal to 0 and less than or equal to 5%.

[0011] Optionally, the difference ratio between the thicknesses of the second stacked material layers in each sub-stack structure is greater than or equal to 0 and less than or equal to 5%.

[0012] Optionally, a wet etching process can be used to remove the sidewall protective layer.

[0013] Accordingly, this disclosure also provides a semiconductor structure, including: a stacked structure including a plurality of sub-stacked structures stacked longitudinally, each sub-stacked structure including alternating layers of first and second stacked materials, all first stacked materials in the sub-stacked structure having the same thickness, and all second stacked materials in the sub-stacked structure having the same thickness; a via penetrating the stacked structure; wherein the difference ratio between the surface areas of each exposed second stacked material layer in the via is greater than or equal to 0 and less than or equal to 5%.

[0014] Optionally, the cross-section of the through hole is circular, and the diameter of the through hole is different in each sub-stack structure. The ratio between the diameter of the through hole in each sub-stack structure and the product of the thickness of the second stacked material layer in the corresponding sub-stack structure is greater than or equal to 0 and less than or equal to 5%.

[0015] Optionally, the material of the first stacked material layer includes silicon oxide, and the material of the second stacked material layer includes silicon nitride. The diameter of the via located in the upper sub-stack structure is larger than the diameter of the via located in the lower sub-stack structure. The thickness of the second stacked material layer in the upper sub-stack structure is smaller than the thickness of the second stacked material layer in the lower sub-stack structure.

[0016] Compared with the prior art, the technical solution of the present disclosure has the following advantages:

[0017] In the formation method provided in this embodiment, multiple stacking processes are used, with each stacking process forming a sub-stacked structure. By stacking to form a stacked structure, a stacked structure with a large total number of layers can be formed. Furthermore, the number of sub-stacked structures in each stacking process can be controlled to a low value, resulting in higher sidewall quality and dimensional accuracy of the formed sub-vias. This is beneficial for forming a stacked structure with a large total number of layers while improving the sidewall quality and dimensional accuracy of the vias, thus meeting the requirements for higher storage density. Moreover, the difference between the surface areas of each exposed second-layer stacked material layer of the via is greater than or equal to 0 and less than or equal to 5%, meaning that the difference between the surface areas of each exposed second-layer stacked material layer of the via is small. This makes the effective area of ​​the storage cell formed by each second-layer stacked material layer more uniform, thereby improving the storage performance of the memory formed by the stacked structure. Attached Figure Description

[0018] Figures 1 to 10 This is a schematic diagram of the structure corresponding to each step in one embodiment of the method for forming a semiconductor structure disclosed herein;

[0019] Figures 11 to 18 This is a schematic diagram of the structure corresponding to each step in another embodiment of the method for forming the semiconductor structure disclosed herein;

[0020] Figure 19 This is a schematic diagram of a corresponding embodiment of the semiconductor structure disclosed herein;

[0021] Figure 20 This is a schematic diagram of the device structure corresponding to the semiconductor structure disclosed herein. Detailed Implementation

[0022] As the background technology shows, with the continuous increase in the demand for memory density, the number of stacked layers in three-dimensional memory is constantly increasing, which brings about the following problems: the morphology of vias between different stacks is not uniform; the via etching process capability is limited, and the number of layers etched in a single operation is easy to reach a bottleneck, resulting in poor via quality for etching the ever-increasing number of stacked layers.

[0023] To address the aforementioned technical problems, this disclosure provides a method for forming a semiconductor structure, comprising: performing multiple stacking processes along a longitudinal direction on a semiconductor substrate to form a stacked structure, wherein the semiconductor substrate includes an etch stop structure; wherein the stacking process includes: forming a sub-stacked structure composed of alternating first and second stacked material layers along a longitudinal direction, wherein all first stacked material layers in the sub-stacked structure have the same thickness, and all second stacked material layers in the sub-stacked structure have the same thickness; forming a sub-via penetrating the sub-stacked structure, wherein the projection of the sub-via on a horizontal plane lies within the projection of the etch stop structure on a horizontal plane, and the sub-via formed after the first stacking process exposes the etch stop structure; between two adjacent stacking processes, filling the sub-via to form a first sacrificial layer; wherein the sub-via formed in the later stacking process exposes the first sacrificial layer in the sub-via formed in the previous stacking process, and the previous stacking process... The first sacrificial layer in the sub-via formed by the stacking process serves as the etch stop layer for the subsequent stacking process to form the sub-via. The first sacrificial layer is removed to form a via connected by multiple sub-vias that expose the etch stop structure. The difference ratio between the surface areas of each exposed second-layer stacked material layer in the via is greater than or equal to 0 and less than or equal to 5%. Where removing the first sacrificial layer would damage the second-layer stacked material layers, the thickness of the second-layer stacked material layers in each sub-stack structure is controlled to ensure that the difference ratio between the surface areas of each exposed second-layer stacked material layer in the formed via is greater than or equal to 0 and less than or equal to 5%. Alternatively, before filling the sub-via to form the first sacrificial layer, a sidewall protective layer is formed on the sidewall of the sub-stack structure exposed by the sub-via, ensuring that the difference ratio between the surface areas of each exposed second-layer stacked material layer in the formed via is greater than or equal to 0 and less than or equal to 5%.

[0024] By employing multiple stacking processes, with each stacking process forming a sub-layer structure, a stacking structure with a large total number of layers can be formed. Furthermore, the number of sub-layer structures in each stacking process can be controlled to a low value, resulting in higher sidewall quality and dimensional accuracy of the formed vias. This facilitates the formation of a large number of stacked structures while improving the sidewall quality and dimensional accuracy of the vias, meeting the requirements for higher storage density. Moreover, the difference in surface area between each exposed second-layer material layer of the via is greater than or equal to 0 and less than or equal to 5%, meaning the difference in surface area between each exposed second-layer material layer is small. This results in a more uniform effective area for the storage cells formed by each second-layer material layer, thereby improving the storage performance of the memory constructed with the stacked structure.

[0025] To make the above-mentioned objects, features and advantages of this disclosure more apparent and understandable, specific embodiments of this disclosure will be described in detail below with reference to the accompanying drawings.

[0026] Figures 1 to 10This is a schematic diagram of the structure corresponding to each step in one embodiment of the method for forming a semiconductor structure disclosed herein.

[0027] Reference Figures 1 to 7 On the semiconductor substrate 100 along the longitudinal direction (e.g. Figure 7 The semiconductor substrate 100 includes an etch stop structure 110 and undergoes multiple stacking processes (as shown in the Z direction).

[0028] Semiconductor substrate 100 provides the basis for the process operation of semiconductor structure formation.

[0029] In some embodiments, the semiconductor substrate 100 is made of silicon. In other embodiments, the semiconductor substrate may be made of other materials such as germanium, silicon germanide, gallium nitride, silicon carbide, gallium arsenide, or indium gallium nitride. The semiconductor substrate may also be other types of substrates such as silicon-on-insulator or germanium-on-insulator. The material of the semiconductor substrate may be a material suitable for process requirements or easy to integrate.

[0030] In some embodiments, the semiconductor substrate 100 includes an etch stop structure 110, which serves as an etch stop position for subsequent formation of sub-vias, thereby reducing the etch difficulty of forming sub-vias and improving the uniformity of the etch depth of the sub-vias.

[0031] In some embodiments, the etch stop structure 110 is a conductive block structure, which is used for subsequent electrical connection with the capacitor post.

[0032] The stacked structure 201 is used to subsequently form capacitor pillars and capacitor plates to constitute a memory.

[0033] In some embodiments, multiple stacking processes are performed to form a stacked structure 201. Each stacking process can be flexibly adjusted so that the resulting stacked structure 201 can adapt to various performance requirements.

[0034] Specifically, refer to Figure 1 The stacking process includes: forming a sub-stacked structure 200 consisting of alternating layers of first stacked material layers 210 and second stacked material layers 220 along the longitudinal direction, wherein all first stacked material layers 210 in the sub-stacked structure 200 have the same thickness t1, and all second stacked material layers 220 in the sub-stacked structure 200 have the same thickness t2.

[0035] The first stacked material layer 210 is used to isolate the longitudinally adjacent second stacked material layer 220.

[0036] In some embodiments, the first stacked material layer 210 is an insulating dielectric layer, which provides electrical isolation for the capacitor plates subsequently formed at the location of the second stacked material layer 220, so that the capacitor plates of adjacent storage capacitors do not affect each other.

[0037] In some embodiments, the insulating dielectric layer is made of an insulating material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, and silicon carbon oxynitride.

[0038] As an example, the material of the insulating dielectric layer includes silicon oxide, that is, the material of the first stacked material layer 210 includes silicon oxide.

[0039] The second layer of material 220 is used to form the capacitor plate.

[0040] In some embodiments, the second stacked material layer 220 is a second sacrificial layer used to occupy space for the subsequent formation of the capacitor plate.

[0041] In some embodiments, the material of the second sacrificial layer includes silicon nitride, that is, the material of the second stacked material layer 220 includes silicon nitride. Silicon nitride and silicon oxide have a large etching selectivity, thereby reducing damage to the first stacked material layer 210 when the second sacrificial layer is subsequently removed.

[0042] In other embodiments, the second stacked material layer may also be a capacitor plate, i.e., the first stacked material layer and the capacitor plate are directly stacked alternately.

[0043] Correspondingly, in other embodiments, the material of the capacitor plate includes tungsten, that is, the material of the second stacked material layer includes tungsten.

[0044] In some embodiments, the thickness t1 of all first stacked material layers 210 in the sub-stacked structure 200 is the same, and the thickness t2 of all second stacked material layers 220 in the sub-stacked structure 200 is the same. This makes the formation steps of the sub-stacked structure 200 simple and easy to operate. Furthermore, by performing multiple stacking processes, the number of layers of the sub-stacked structure 200 formed in each stacking process can be controlled to be relatively small. Thus, when the first sacrificial layer is removed subsequently, the damage to the multiple first stacked material layers 210 and the damage to the multiple second stacked material layers 220 in each sub-stacked structure 200 are almost the same. Therefore, the film parameters of all first stacked material layers 210 and all second stacked material layers 220 in the sub-stacked structure 200 can be controlled together. For this purpose, the thickness t1 of all first stacked material layers 210 and the thickness t2 of all second stacked material layers 220 in the sub-stacked structure 200 can be set to be the same.

[0045] refer to Figure 2 A sub-via 230 is formed through the sub-stacked structure 200. The projection of the sub-via 230 on the horizontal plane is located within the projection of the etch stop structure 110 on the horizontal plane. The sub-via 230 formed after the first stacking process exposes the etch stop structure 110.

[0046] The sub-via 230 is used to provide space for the subsequent formation of the first sacrificial layer. The subsequent sub-vias 230 are also used to connect to form vias to provide space for the formation of capacitor pillars. The projection of the sub-via 230 on the horizontal plane is located within the projection of the etch stop structure 110 on the horizontal plane, so that the projection of the capacitor pillars subsequently formed in the sub-via 230 on the horizontal plane is located within the projection of the etch stop structure 110 on the horizontal plane. The sub-vias 230 formed after the first stacking process expose the etch stop structure 110, so that the capacitor pillars subsequently formed in the sub-via 230 can contact the etch stop structure 110 for electrical connection.

[0047] In some embodiments, in the step of forming a sub-through hole 230 through the sub-stack structure 200, the cross-section of the sub-through hole 230 is circular, which is beneficial for adapting to the morphology of the subsequent capacitor pillars.

[0048] refer to Figure 3 Between two adjacent stacking processes, the sub-vias 230 are filled to form the first sacrificial layer 250.

[0049] The first sacrificial layer 250 is used to occupy space for the subsequent formation of capacitor pillars. Between two adjacent stacking processes, the sub-vias 230 are filled to form the first sacrificial layer 250. The first sacrificial layer 250 can fill the sub-vias 230 of the previous stacking process, so that the top surface of the previous sub-stack structure 200 has a higher flatness, providing a better process platform for the subsequent stacking process.

[0050] In some embodiments, in the step of filling the sub-via 230 to form the first sacrificial layer 250, the material of the first sacrificial layer 250 includes amorphous carbon.

[0051] Amorphous carbon is a readily available material with low cost and short production cycle. It is also easy to remove and can form a large etching selectivity with silicon nitride (i.e., the second stacked material layer 220) and silicon oxide (i.e., the first stacked material layer 210), thereby reducing damage to the first stacked material layer 210 and the second stacked material layer 220 when the first sacrificial layer 250 is subsequently removed.

[0052] It should be noted that in some embodiments, the depth and width of the sub-via 230 are relatively large. In the step of filling the sub-via 230 to form the first sacrificial layer 250, holes will be formed in the first sacrificial layer 250, which makes the first sacrificial layer 250 easier to remove in the future.

[0053] In some embodiments, the sub-via 230 formed in the subsequent stacking process exposes the first sacrificial layer 250 in the sub-via 230 formed in the previous stacking process, and the first sacrificial layer 250 in the sub-via 230 formed in the previous stacking process serves as the etching stop layer for the sub-via 230 formed in the subsequent stacking process.

[0054] The sub-via 230 formed in the next stacking process exposes the first sacrificial layer 250 in the sub-via 230 formed in the previous stacking process. Thus, the first sacrificial layer 250 formed in the sub-via 230 each time can be connected to form a stacked structure 201. After that, all the first sacrificial layers 250 can be removed together to form a through hole with multiple sub-via 230 connected. Furthermore, the first sacrificial layer 250 in the sub-via 230 formed in the previous stacking process serves as the etching stop layer for the sub-via 230 formed in the next stacking process. This helps to reduce the etching difficulty of forming the sub-via 230 and also helps to improve the uniformity of the etching depth of the sub-via 230.

[0055] Reference Figures 4 to 7 This example illustrates a process of performing three stacking operations. In other embodiments, the number of stacking operations is selected based on actual performance requirements, and the number of stacking operations is not limited here.

[0056] Specifically, refer to Figure 4 The stacking process is performed again, including: forming a second sub-stacked structure 200 on the previous sub-stacked structure 200, which consists of alternating layers of first stacked material layers 210 and second stacked material layers 220 in the longitudinal direction. All the first stacked material layers 210 in the sub-stacked structure 200 have the same thickness t1, and all the second stacked material layers 220 in the sub-stacked structure 200 have the same thickness t2.

[0057] refer to Figure 5 This forms a sub-via 230 that penetrates the sub-stacked structure 200. The projection of the sub-via 230 on the horizontal plane is located within the projection of the etch stop structure 110 on the horizontal plane. In other words, the projection of the sub-via 230 on the horizontal plane in each stacking process is located within the projection of the etch stop structure 110 on the horizontal plane, so that the projection of the through hole connecting multiple sub-vias 230 on the horizontal plane is located within the projection of the etch stop structure 110 on the horizontal plane.

[0058] refer to Figure 6 Before the next stacking process, the sub-vias 230 formed in the previous stacking process are filled to form a first sacrificial layer 250. Accordingly, the currently filled first sacrificial layer 250 is connected to the first sacrificial layer 250 in the sub-vias 230 of the previous stacking process as an integral structure.

[0059] refer to Figure 7 The final stacking process includes: forming a sub-stack structure 200 consisting of alternating layers of first stacked material layers 210 and second stacked material layers 220 along the longitudinal direction, wherein all first stacked material layers 210 in the sub-stack structure 200 have the same thickness t1, and all second stacked material layers 220 in the sub-stack structure 200 have the same thickness t2; forming a sub-via 230 penetrating the sub-stack structure 200, wherein the projection of the sub-via 230 on the horizontal plane is located within the projection of the etch stop structure 110 on the horizontal plane.

[0060] It should be noted that after the final stacking process, i.e., the first sacrificial layer 250 is removed to form a through hole 230 that connects multiple sub-through holes 230 through the stacked structure 201, there is no need to fill the sub-through holes 230 formed in the final stacking process to form the first sacrificial layer 250. This is beneficial to reduce process costs, reduce process steps, simplify process flow, and also facilitates the subsequent removal of the first sacrificial layer 250 through the sub-through holes 230 formed in the final stacking process.

[0061] In some embodiments, by employing multiple stacking processes, with each stacking process forming a sub-stack structure 200, and stacking to form a stack structure 201, a stack structure 201 with a large number of layers can be formed. Furthermore, the number of layers of the sub-stack structure 200 in each stacking process can be controlled to a low value, resulting in higher sidewall quality and dimensional accuracy of the formed sub-vias 230. This is beneficial for improving the sidewall quality and dimensional accuracy of the vias while forming a stack structure 201 with a large number of layers, thus meeting the requirements for higher storage density.

[0062] refer to Figure 8 The first sacrificial layer 250 is removed to form a via 260 that is connected by a plurality of sub-vias 230 and exposes the etch stop structure 110. The difference ratio between the surface areas of each second stacked material layer 220 exposed by the via 260 is greater than or equal to 0 and less than or equal to 5%.

[0063] The via 260 provides space for the subsequent formation of capacitor pillars, and the via 260 exposes the etch stop structure 110, so that the subsequently formed capacitor pillars can contact the etch stop structure 110 for electrical connection.

[0064] In some embodiments, the difference ratio between the surface areas of each second stacked material layer 220 exposed by the via 260 is greater than or equal to 0 and less than or equal to 5%, that is, the difference between the surface areas of each second stacked material layer 220 exposed by the via 260 is small, and also includes that the surface areas of each second stacked material layer 220 exposed by the via 260 are equal, so that the effective area of ​​the storage cell formed by each second stacked material layer 220 is more uniform, thereby helping to improve the storage performance of the memory formed by the stacked structure 201.

[0065] In some embodiments, the cross-section of the sub-via 230 is circular. Correspondingly, in the step of removing the first sacrificial layer 250 to form a via 260 that is connected by a plurality of sub-vias 230 and exposes the etch stop structure 110, the cross-section of the via 260 is circular.

[0066] The cross-section of the via 260 is circular, and the capacitor pillars subsequently formed in the via 260 are cylindrical. This helps to make the electric field distribution of the capacitor pillars more uniform and avoids electric field concentration at sharp corners, thereby improving the reliability and lifespan of the memory.

[0067] In some embodiments, the difference ratio between the surface areas of each second laminated material layer 220 exposed by the through-hole 260 is greater than or equal to 0 and less than or equal to 5%, meaning that the difference ratio between the product of the diameter d of the through-hole 260 at the location of each second laminated material layer 220 and the thickness t2 of the second laminated material layer 220 is greater than or equal to 0 and less than or equal to 5%.

[0068] Since the cross-section of the through-hole 260 is circular, the surface area of ​​each second-layer stacked material 220 exposed by the through-hole 260 is the product of the circumference of the through-hole 260 at the position of each second-layer stacked material 220 and the thickness t2 of the second-layer stacked material 220 at that position. The circumference of the through-hole 260 at the position of each second-layer stacked material 220 is the diameter d of the through-hole 260 at the position of each second-layer stacked material 220 multiplied by π. That is, the surface area of ​​each second-layer stacked material 220 exposed by the through-hole 260 = π * d * t2. Therefore, the ratio of the difference between the product of the diameter d of the through-hole 260 at the position of each second-layer stacked material 220 and the thickness t2 of the second-layer stacked material 220 is greater than or equal to 0 and less than or equal to 5%, which can characterize that the ratio of the difference between the surface areas of each second-layer stacked material 220 exposed by the through-hole 260 is greater than or equal to 0 and less than or equal to 5%.

[0069] In some embodiments, when the removal of the first sacrificial layer 250 causes damage to the second stacked material layer 220, the thickness t2 of the second stacked material layer 220 in each sub-stack structure 200 is controlled to be different, so that the difference ratio between the surface areas of each second stacked material layer 220 exposed by the formed via 260 is greater than or equal to 0 and less than or equal to 5%.

[0070] When the removal of the first sacrificial layer 250 causes damage to the second stacked material layer 220, the damage to the second stacked material layer 220 in each sub-stack structure 200 is inconsistent, resulting in different diameters d of the vias 260 at the positions of each second stacked material layer 220. Therefore, by adjusting the thickness t2 of the second stacked material layer 220 in each sub-stack structure 200, the surface area of ​​each second stacked material layer 220 exposed by the vias 260 can be adjusted so that the surface areas of each second stacked material layer 220 exposed by the vias 260 are more similar.

[0071] In some embodiments, by controlling the thickness t2 of the second stacked material layer 220 in each sub-stack structure 200 to be different, the difference ratio between the surface areas of each second stacked material layer 220 exposed by the subsequently formed through-hole is greater than or equal to 0 and less than or equal to 5%. Specifically, the thickness t2 of the second stacked material layer 220 in the lower sub-stack structure 200 is controlled to be greater than the thickness t2 of the second stacked material layer 220 in the upper sub-stack structure 200.

[0072] When the removal of the first sacrificial layer 250 causes damage to the second stacked material layer 220, since the removal process proceeds longitudinally from top to bottom, the time spent in the removal process environment in the stacked structure 201 gradually decreases from top to bottom. That is, the longer the time spent in the removal process environment in the multiple sub-stacked structures 200, the greater the damage to the second stacked material layer 220. Therefore, the damage to the second stacked material layer 220 in the multiple sub-stacked structures 200 gradually increases from bottom to top. In other words, after the removal of the first sacrificial layer 250, the diameter of the through-hole at the location of the second stacked material layer 220 in the lower sub-stacked structure 200 is smaller than... The diameter of the via at the position of the second layer 220 in the upper sub-stack structure 200 is such that the thickness t2 of the second layer 220 in the lower sub-stack structure 200 is controlled to be greater than the thickness t2 of the second layer 220 in the upper sub-stack structure 200. This ensures that after the first sacrificial layer 250 is subsequently removed, the product of the via diameter at the position of the second layer 220 in the lower sub-stack structure 200 and the thickness t2 of the second layer 220, and the product of the via diameter at the position of the second layer 220 in the upper sub-stack structure 200 and the thickness t2 of the second layer 220, achieve a difference ratio greater than or equal to 0 and less than or equal to 5%.

[0073] In some embodiments, a dry etching process is used to remove the first sacrificial layer 250.

[0074] The material of the first sacrificial layer 250 is amorphous carbon. The amorphous carbon can be easily removed by bombardment using a dry etching process. This also allows the first sacrificial layer 250 to form a large etching selectivity with the first stacked material layer 210 and the second stacked material layer 220, which helps to reduce damage to the stacked structure 201.

[0075] In some embodiments, reference Figure 9 The second stacked material layer 220 is a second sacrificial layer, and the material of the second sacrificial layer includes silicon nitride, which fills the through-hole 260 to form a capacitor pillar 310.

[0076] Capacitor pillar 310 is used as a conductive pillar in the memory.

[0077] In some embodiments, the capacitor post 310 includes a metal barrier layer and a metal layer. The metal barrier layer is made of titanium nitride, and the metal layer is made of tungsten. The metal barrier layer conformally covers the sidewalls and bottom wall of the through-hole 260, and the metal layer fills the groove formed by the metal barrier layer.

[0078] Accordingly, in some embodiments, during the step of filling the via 260 to form the capacitor post 310, the capacitor post 310 contacts the etch stop structure 110 for electrical connection.

[0079] refer to Figure 10 Remove the second layer of material 220 to form a groove that exposes the sidewall of the capacitor pillar 310; form a storage material layer 300 that conforms to the groove; fill the groove to form a capacitor plate 320 that covers the storage material layer 300.

[0080] The capacitor plate 320 is used as a conductive plate in the memory, and the storage material layer 300 is used as the storage capacitor material in the memory.

[0081] Specifically, in some embodiments, the difference ratio between the surface areas of the storage material layers 300 between each capacitor plate 320 and capacitor pillar 310 is greater than or equal to 0 and less than or equal to 5%, that is, the effective area of ​​the storage cell formed between each capacitor plate 320 and capacitor pillar 310 is relatively uniform, which is beneficial to improving the storage performance of the memory formed by the multilayer capacitor plate 320 and capacitor pillar 310.

[0082] In some embodiments, the capacitor plate 320 is made of titanium nitride and tungsten, forming a stacked structure of titanium nitride layer and tungsten layer, wherein the titanium nitride layer is located between the tungsten layer and the storage material layer 300, and serves as a metal barrier layer.

[0083] In some embodiments, the material of the storage material layer 300 includes ferroelectric materials, silicon nitride materials, phase change materials, or resistive switching materials.

[0084] In other embodiments, the second stacked material layer is a capacitor plate. Before filling the through-holes to form capacitor pillars, a storage material layer covering the sidewalls of the through-holes is formed, and then the through-holes are filled to form capacitor pillars covering the storage material layer. Accordingly, the multilayer capacitor plate and capacitor pillars constitute a memory.

[0085] Figures 11 to 18 This is a schematic diagram of the structure corresponding to each step in another embodiment of the method for forming the semiconductor structure disclosed herein.

[0086] The similarities between this embodiment and the foregoing embodiments will not be repeated here. The differences between this embodiment and the foregoing embodiments are as follows:

[0087] join Figure 11Before the step of forming the first sacrificial layer 250 by filling the sub-via 230, a sidewall protective layer 240 is formed on the sidewall of the sub-stacked structure 200 exposed by the sub-via 230, so that the difference ratio between the surface areas of each second stacked material layer 220 exposed by the formed via 260 is greater than or equal to 0 and less than or equal to 5%. It should be noted that while forming the sidewall protective layer 240 on the sidewall of the sub-stacked structure 200, the sidewall protective layer 240 also covers the bottom wall of the sub-via 230. The sidewall protective layer 240 located on the bottom wall of the sub-via 230 may not be removed in the first stacking process, but needs to be removed in subsequent stacking processes (e.g., by using dry anisotropic etching) to achieve the formation of the first sacrificial layer 250 of the subsequent integrated structure, so that it can be removed in one go.

[0088] The sidewall protective layer 240 is used to protect the first laminated material layer 210 and the second laminated material layer 220 in the subsequent step of removing the first sacrificial layer 250. Specifically, the sidewall protective layer 240 protects the second laminated material layer 220, so that the second laminated material layer 220 will not be damaged when the first sacrificial layer 250 is removed. This is beneficial to ensure that the difference ratio between the surface areas of each second laminated material layer 220 exposed by the through hole 260 is greater than or equal to 0 and less than or equal to 5%, so that the surface areas of each second laminated material layer 220 exposed by the through hole 260 are relatively close, including that the surface areas of each second laminated material layer 220 exposed by the through hole 260 are equal.

[0089] In some embodiments, prior to the step of forming the first sacrificial layer 250 by filling the sub-via 230, a sidewall protection layer 240 is formed on the sidewall of the sub-stack structure 200 exposed by the sub-via 230. The material of the sidewall protection layer 240 includes silicon oxide.

[0090] Since silicon oxide can form a large etching selectivity with amorphous carbon, the damage to the sidewall protective layer 240 can be reduced during the subsequent removal of the first sacrificial layer 250. Accordingly, the sidewall protective layer 240 can play a better protective role. Furthermore, since silicon oxide can form a large etching selectivity with silicon nitride, the damage to the second stacked material layer 220 can be reduced when the sidewall protective layer 240 is removed.

[0091] Accordingly, refer to Figure 12 In the step of filling the through-hole 230 to form the first sacrificial layer 250, the first sacrificial layer 250 covers the sidewall protective layer 240.

[0092] Reference Figures 13 to 16 This example illustrates a process of performing three stacking operations. In other embodiments, the number of stacking operations is selected based on actual performance requirements, and the number of stacking operations is not limited here.

[0093] Specifically, refer to Figure 13 The stacking process is performed again, including: forming a second sub-stacked structure 200 on the previous sub-stacked structure 200, which consists of alternating layers of first stacked material layers 210 and second stacked material layers 220 in the longitudinal direction. All the first stacked material layers 210 in the sub-stacked structure 200 have the same thickness t1, and all the second stacked material layers 220 in the sub-stacked structure 200 have the same thickness t2.

[0094] refer to Figure 14 This forms a sub-via 230 that penetrates the sub-stacked structure 200. The projection of the sub-via 230 on the horizontal plane is located within the projection of the etch stop structure 110 on the horizontal plane. In other words, the projection of the sub-via 230 on the horizontal plane in each stacking process is located within the projection of the etch stop structure 110 on the horizontal plane, so that the projection of the through hole connecting multiple sub-vias 230 on the horizontal plane is located within the projection of the etch stop structure 110 on the horizontal plane.

[0095] refer to Figure 15 Before the next stacking process, a sidewall protection layer 240 is formed on the sidewall of the sub-stacked structure 200 exposed by the sub-via 230 of the previous stacking process, filling the sub-via 230 formed in the previous stacking process, forming a first sacrificial layer 250 covering the sidewall protection layer 240. Correspondingly, the sidewall protection layer 240 on the sidewall of the current sub-stacked structure 200 is integrated with the sidewall protection layer 240 on the sidewall of the sub-stacked structure 200 exposed by the sub-via 230 of the previous stacking process, and the first sacrificial layer 250 filled at the moment is integrated with the first sacrificial layer 250 in the sub-via 230 of the previous stacking process.

[0096] refer to Figure 16 The final stacking process includes: forming a sub-stacked structure 200 consisting of alternating layers of first stacked material 210 and second stacked material 220 along the longitudinal direction; forming a sub-via 230 penetrating the sub-stacked structure 200, the projection of the sub-via 230 on the horizontal plane being located within the projection of the etch stop structure 110 on the horizontal plane; and after the final stacking process, forming a sidewall protection layer 240 on the sidewall of the sub-stacked structure 200 exposed by the sub-via 230.

[0097] It should be noted that after the final stacking process, i.e., the first sacrificial layer 250 is removed to form a through hole 230 that connects multiple sub-through holes 230 through the stacked structure 201, there is no need to fill the sub-through holes 230 formed in the final stacking process to form the first sacrificial layer 250. This is beneficial to reduce process costs, reduce process steps, simplify process flow, and also facilitates the subsequent removal of the first sacrificial layer 250 through the sub-through holes 230 formed in the final stacking process.

[0098] refer to Figure 17 Remove the first sacrificial layer 250 to expose the sidewall protective layer 240.

[0099] Removing the first sacrificial layer 250 provides space for the subsequent formation of capacitor pillars.

[0100] refer to Figure 18 After removing the first sacrificial layer 250, the process also includes removing the sidewall protective layer 240, such that the difference ratio between the surface areas of each second laminated material layer 220 exposed by the formed through hole 260 is greater than or equal to 0 and less than or equal to 5%.

[0101] During the removal of the first sacrificial layer 250, the second stacked material layer 220 is not damaged due to the protective effect of the sidewall protective layer 240. During the removal of the sidewall protective layer 240, the film thickness of the sidewall protective layer 240 is very thin and can be removed quickly, so that the stacked structure 201 is in the removal process for a very short time, and the second stacked material layer 220 is hardly damaged. Moreover, the material of the sidewall protective layer 240 is silicon oxide, so during the removal of silicon oxide, due to the large etching selectivity, the second stacked material layer 220 of silicon nitride is also hardly damaged. Therefore, after removing the sidewall protective layer 240, the size of the via 260 at the position of each second stacked material layer 220 is almost unchanged, which is beneficial to make the difference ratio between the surface areas of each second stacked material layer 220 exposed by the via 260 greater than or equal to 0 and less than or equal to 5%, so that the surface areas of each second stacked material layer 220 exposed by the via 260 are relatively close.

[0102] In some embodiments, the difference ratio between the thicknesses t2 of the second stacked material layers 220 in each sub-stack structure 200 is greater than or equal to 0 and less than or equal to 5%.

[0103] As mentioned above, after removing the sidewall protective layer 240, the size of the through hole 260 at the position of the second laminated material layer 220 in each sub-laminated structure 200 hardly changes. Therefore, the difference between the thicknesses t2 of the second laminated material layer 220 in each sub-laminated structure 200 is greater than or equal to 0 and less than or equal to 5%. That is, the difference between the thicknesses t2 of the second laminated material layer 220 in each sub-laminated structure 200 is also small. Thus, the difference between the surface area formed by the size of the through hole 260 and the thickness t2 of the second laminated material layer 220 at the position of the second laminated material layer 220 in each sub-laminated structure 200 can also satisfy the condition that the ratio is greater than or equal to 0 and less than or equal to 5%.

[0104] In some embodiments, a wet etching process is used to remove the sidewall protective layer 240.

[0105] The wet etching process is low-cost and easy to remove the sidewall protective layer 240. Furthermore, the wet etching process can easily obtain a large etching selectivity, thereby reducing damage to the second stacked material layer 220 during the removal of the sidewall protective layer 240.

[0106] For a detailed description of the formation method of this embodiment, please refer to the corresponding descriptions in the foregoing embodiments, which will not be repeated here.

[0107] Figure 19 This is a schematic diagram of one embodiment of the semiconductor structure disclosed herein.

[0108] refer to Figure 19 The semiconductor structure includes: a stacked structure 201, including a longitudinal (e.g., Figure 19 (As shown in the Z-direction) Multiple sub-stacked structures 200 are stacked, each sub-stacked structure 200 including alternating first stacked material layers 210 and second stacked material layers 220 along the longitudinal direction. All first stacked material layers 210 in the sub-stacked structure 200 have the same thickness t1, and all second stacked material layers 220 in the sub-stacked structure 200 have the same thickness t2. Through-holes 260 penetrate the stacked structure 201. The difference ratio between the surface areas of each second stacked material layer 220 exposed by the through-holes 260 is greater than or equal to 0 and less than or equal to 5%.

[0109] In some embodiments, the stacked structure 201 is located on a semiconductor substrate 100, which includes an etch stop structure 110.

[0110] Semiconductor substrate 100 provides the basis for the process operation of semiconductor structure formation.

[0111] In some embodiments, the semiconductor substrate 100 is made of silicon. In other embodiments, the semiconductor substrate may be made of other materials such as germanium, silicon germanide, gallium nitride, silicon carbide, gallium arsenide, or indium gallium nitride. The semiconductor substrate may also be other types of substrates such as silicon-on-insulator or germanium-on-insulator. The material of the semiconductor substrate may be a material suitable for process requirements or easy to integrate.

[0112] In some embodiments, the semiconductor substrate 100 includes an etch stop structure 110, which serves as an etch stop position for the via 260, thereby reducing the etch difficulty of forming the via 260 and improving the uniformity of the etch depth of the via 260.

[0113] In some embodiments, the etch stop structure 110 is a conductive block structure, which is used to electrically connect with the capacitor post.

[0114] The stacked structure 201 is used to form capacitor pillars and capacitor plates to constitute a memory.

[0115] In some embodiments, the stacked structure 201 includes a plurality of sub-stacked structures 200 stacked longitudinally, and each sub-stacked structure 200 can be flexibly adjusted so that the formed stacked structure 201 can be adapted to various performance requirements.

[0116] The first stacked material layer 210 is used to isolate the longitudinally adjacent second stacked material layer 220.

[0117] In some embodiments, the first stacked material layer 210 is an insulating dielectric layer, which provides electrical isolation to the capacitor plates formed at the location of the second stacked material layer 220, so that the capacitor plates of adjacent storage capacitors do not affect each other.

[0118] In some embodiments, the insulating dielectric layer is made of an insulating material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, and silicon carbon oxynitride.

[0119] As an example, the material of the insulating dielectric layer includes silicon oxide, that is, the material of the first stacked material layer 210 includes silicon oxide.

[0120] The second layer of material 220 is used to form the capacitor plate.

[0121] In some embodiments, the second stacked material layer 220 is a second sacrificial layer used to occupy space for forming the capacitor plate.

[0122] In some embodiments, the material of the second sacrificial layer includes silicon nitride, that is, the material of the second stacked material layer 220 includes silicon nitride. Silicon nitride and silicon oxide have a large etching selectivity, thereby reducing damage to the first stacked material layer 210 when the second sacrificial layer is removed.

[0123] In some embodiments, the thickness t1 of all first stacked material layers 210 in the sub-stacked structure 200 is the same, and the thickness t2 of all second stacked material layers 220 in the sub-stacked structure 200 is the same. This makes the formation steps of the sub-stacked structure 200 simple and easy to operate. Furthermore, the number of layers in each sub-stacked structure 200 can be controlled to be relatively small. Thus, the damage to the multiple first stacked material layers 210 and the damage to the multiple second stacked material layers 220 in each sub-stacked structure 200 when removing the first sacrificial layer are almost the same. As a result, the film parameters of all first stacked material layers 210 and all second stacked material layers 220 in the sub-stacked structure 200 can be controlled together. For this purpose, the thickness t1 of all first stacked material layers 210 and the thickness t2 of all second stacked material layers 220 in the sub-stacked structure 200 can be set to be the same.

[0124] The via 260 provides space for forming capacitor pillars, and the via 260 exposes the etch stop structure 110, allowing the formed capacitor pillars to contact the etch stop structure 110 for electrical connection.

[0125] In some embodiments, by using multiple sub-stacked structures 200 to stack and form a stacked structure 201, a stacked structure 201 with a large number of layers can be formed, and the number of layers of each sub-stacked structure 200 can be controlled at a low value, so that the sidewall quality and dimensional accuracy of some through holes 260 in each sub-stacked structure 200 are high. This is beneficial to form a stacked structure 201 with a large number of layers while improving the sidewall quality and dimensional accuracy of the through holes 260, thereby meeting the requirements of higher storage density.

[0126] In some embodiments, the difference ratio between the surface areas of each second stacked material layer 220 exposed by the via 260 is greater than or equal to 0 and less than or equal to 5%, that is, the difference between the surface areas of each second stacked material layer 220 exposed by the via 260 is small, so that the effective area of ​​the storage cell formed by each second stacked material layer 220 is more uniform, thereby helping to improve the storage performance of the memory formed by the stacked structure 201.

[0127] In some embodiments, the cross-section of the through hole 260 is circular.

[0128] The cross-section of the via 260 is circular, and the capacitor pillar formed in the via 260 is cylindrical. This helps to make the electric field distribution of the capacitor pillar more uniform and avoids electric field concentration at sharp corners, thereby improving the reliability and lifespan of the memory.

[0129] In some embodiments, the diameter d of the via 260 at each sub-stack structure 200 is different, and the ratio of the difference between the diameter d of the via 260 at each sub-stack structure 200 and the product of the thickness t2 of the second stacked material layer 220 in the corresponding sub-stack structure 200 is greater than or equal to 0 and less than or equal to 5%.

[0130] Since the cross-section of the through-hole 260 is circular, the surface area of ​​each second-layer stacked material 220 exposed by the through-hole 260 is the product of the circumference of the through-hole 260 at the position of each second-layer stacked material 220 and the thickness t2 of the second-layer stacked material 220 at that position. The circumference of the through-hole 260 at the position of each second-layer stacked material 220 is the diameter d of the through-hole 260 at the position of each second-layer stacked material 220 multiplied by π. That is, the surface area of ​​each second-layer stacked material 220 exposed by the through-hole 260 = π * d * t2. Therefore, the ratio of the difference between the surface areas of each second-layer stacked material 220 exposed by the through-hole 260 is greater than or equal to 0 and less than or equal to 5%, which means that the ratio of the difference between the product of the diameter d of the through-hole 260 at the position of each second-layer stacked material 220 and the thickness t2 of the second-layer stacked material 220 is greater than or equal to 0 and less than or equal to 5%.

[0131] In some embodiments, the diameter d of the through hole 260 located in the upper sub-stack structure 200 is greater than the diameter d of the through hole 260 located in the lower sub-stack structure 200, and the thickness t2 of the second stacked material layer 220 in the upper sub-stack structure 200 is less than the thickness t2 of the second stacked material layer 220 in the lower sub-stack structure 200.

[0132] The diameter d of the through hole 260 located in the upper sub-layer stack 200 is greater than the diameter d of the through hole 260 located in the lower sub-layer stack 200. The thickness t2 of the second layer material 220 in the upper sub-layer stack 200 is less than the thickness t2 of the second layer material 220 in the lower sub-layer stack 200. Therefore, the product of the diameter d of the through hole at the position of the second layer material 220 in the lower sub-layer stack 200 and the thickness t2 of the second layer material 220, and the product of the diameter d of the through hole at the position of the second layer material 220 in the upper sub-layer stack 200 and the thickness t2 of the second layer material 220, can achieve a difference ratio greater than or equal to 0 and less than or equal to 5%, which is a relatively close effect.

[0133] It should be noted that the semiconductor structure of this disclosure embodiment can be formed using the formation method of the foregoing embodiment, or it can be formed using other formation methods.

[0134] Figure 20 This is a schematic diagram of the device structure corresponding to the semiconductor structure of the present disclosure embodiment.

[0135] In the semiconductor structure of this embodiment, the second stacked material layer 220 is a second sacrificial layer, and the material of the second sacrificial layer includes silicon nitride. After the semiconductor structure of this embodiment is formed, capacitor pillars 310 are first formed in the via 260, then the second stacked material layer 220 is removed by side drilling, and then the storage material layer 300 and the capacitor plate 320 are formed sequentially.

[0136] refer to Figure 20 The second stacked material layer 220 is removed and filled to form a capacitor plate 320. The device structure also includes a storage material layer 300 covering the top and bottom surfaces of the capacitor plate 320 and the surface of the capacitor plate 320 facing the capacitor post 310.

[0137] Capacitor plate 320 is used as a conductive plate in the memory.

[0138] In some embodiments, the material of capacitor plate 320 includes tungsten.

[0139] The storage material layer 300 is used as the storage capacitor material in the memory.

[0140] In some embodiments, the material of the storage material layer 300 includes ferroelectric materials, silicon nitride materials, phase change materials, or resistive switching materials.

[0141] Continue to refer to Figure 20 The semiconductor structure also includes: capacitor pillar 310, located in through hole 260.

[0142] Capacitor pillar 310 is used as a conductive pillar in the memory.

[0143] In some embodiments, the material of the capacitor post 310 includes tungsten.

[0144] Accordingly, in some embodiments, the capacitor post 310 is in contact with the etch stop structure 110 for electrical connection.

[0145] Specifically, in some embodiments, the difference ratio between the surface areas of the storage material layers 300 between each capacitor plate 320 and capacitor pillar 310 is greater than or equal to 0 and less than or equal to 5%, that is, the effective area of ​​the storage cell formed between each capacitor plate 320 and capacitor pillar 310 is relatively uniform, which is beneficial to improving the storage performance of the memory formed by the multilayer capacitor plate 320 and capacitor pillar 310.

[0146] For a detailed description of the semiconductor structure in this embodiment, please refer to the corresponding descriptions in the foregoing embodiments, which will not be repeated here.

[0147] It should be noted that the semiconductor structure of this disclosure embodiment can be formed using the formation method of the foregoing embodiment, or it can be formed using other formation methods.

[0148] While the above disclosure is provided, it is not limited thereto. Any person skilled in the art may make various alterations and modifications without departing from the spirit and scope of this disclosure; therefore, the scope of protection of this disclosure shall be determined by the scope defined in the claims.

Claims

1. A method of forming a semiconductor structure, characterized by, include: Multiple stacking processes are performed longitudinally on a semiconductor substrate to form a stacked structure, the semiconductor substrate including an etch stop structure; wherein, the stacking process includes: forming a sub-stacked structure consisting of alternating first and second stacked material layers in the longitudinal direction, the first stacked material layers being used to isolate longitudinally adjacent second stacked material layers, the second stacked material layers being used to form a capacitor plate, all first stacked material layers in the sub-stacked structure having the same thickness, all second stacked material layers in the sub-stacked structure having the same thickness; forming a sub-via penetrating the sub-stacked structure, the projection of the sub-via on the horizontal plane being located within the projection of the etch stop structure on the horizontal plane, the sub-via formed after the first stacking process exposing the etch stop structure; Between two adjacent stacking processes, the sub-vias are filled to form a first sacrificial layer; wherein, the sub-vias formed in the later stacking process expose the first sacrificial layer in the sub-vias formed in the previous stacking process, and the first sacrificial layer in the sub-vias formed in the previous stacking process serves as an etch stop layer for the sub-vias formed in the later stacking process. The first sacrificial layer is removed to form a via that is connected by a plurality of the sub-vias and exposes the etching stop structure, wherein the difference ratio between the surface areas of each second stacked material layer exposed by the vias is greater than or equal to 0 and less than or equal to 5%; Specifically, by controlling the thickness of the second layer of material in different sub-layer structures to be different, the difference ratio between the surface areas of each second layer of material exposed in the formed through-hole is greater than or equal to 0 and less than or equal to 5%; or, before the step of filling the sub-through-hole to form the first sacrificial layer, a sidewall protective layer is formed on the sidewall of the sub-layer structure exposed by the sub-through-hole, so that the difference ratio between the surface areas of each second layer of material exposed in the formed through-hole is greater than or equal to 0 and less than or equal to 5%.

2. The formation method of claim 1, wherein, The cross-section of the through hole is circular. The difference ratio between the surface areas of each exposed second-layer material layer of the through hole is greater than or equal to 0 and less than or equal to 5%. This means that the difference ratio between the product of the diameter of the through hole at the position of each second-layer material layer and the thickness of the second-layer material layer is greater than or equal to 0 and less than or equal to 5%.

3. The forming method as described in claim 1, characterized in that, The material of the first sacrificial layer includes amorphous carbon, and the material of the first stacked material layer includes silicon oxide.

4. The forming method as described in claim 3, characterized in that, The first sacrificial layer was removed using a dry etching process.

5. The forming method as described in claim 4, characterized in that, The material of the second stacked material layer includes silicon nitride; by controlling the thickness of the second stacked material layer in each of the sub-stacked structures to be different, the difference ratio between the surface areas of each second stacked material layer exposed by the formed through-hole is greater than or equal to 0 and less than or equal to 5%, specifically: controlling the thickness of the second stacked material layer in the lower sub-stacked structure to be greater than the thickness of the second stacked material layer in the upper sub-stacked structure.

6. The forming method as described in claim 4, characterized in that, The material of the second stacked material layer includes silicon nitride; prior to the step of filling the sub-vias to form the first sacrificial layer, a sidewall protection layer is formed on the sidewalls of the sub-stacked structure exposed by the sub-vias, the material of the sidewall protection layer including silicon oxide; After removing the first sacrificial layer, the method further includes removing the sidewall protective layer, such that the difference ratio between the surface areas of each second-layer stacked material exposed by the formed through-hole is greater than or equal to 0 and less than or equal to 5%.

7. The forming method as described in claim 6, characterized in that, The difference ratio between the thicknesses of the second stacked material layers in each of the sub-stacked structures is greater than or equal to 0 and less than or equal to 5%.

8. The forming method as described in claim 6, characterized in that, The sidewall protective layer is removed using a wet etching process.

9. A semiconductor structure, characterized in that, include: A stacked structure includes multiple sub-stacked structures stacked longitudinally, each sub-stacked structure including a first stacked material layer and a second stacked material layer stacked alternately longitudinally, wherein the first stacked material layer is used to isolate longitudinally adjacent second stacked material layers, and the second stacked material layers are used to form a capacitor plate, wherein all first stacked material layers in the sub-stacked structure have the same thickness, and all second stacked material layers in the sub-stacked structure have the same thickness. Through-holes penetrating the stacked structure; Wherein, the difference ratio between the surface areas of each of the second stacked material layers exposed by the through holes is greater than or equal to 0 and less than or equal to 5%.

10. The semiconductor structure as described in claim 9, characterized in that, The cross-section of the through hole is circular, and the diameter of the through hole is different at each of the sub-layer structures. The ratio between the diameter of the through hole at each of the sub-layer structures and the product of the thickness of the second layer of material in the corresponding sub-layer structure is greater than or equal to 0 and less than or equal to 5%.

11. The semiconductor structure as claimed in claim 10, characterized in that, The material of the first stacked material layer includes silicon oxide, the material of the second stacked material layer includes silicon nitride, and the diameter of the via located in the upper sub-stack structure is larger than the diameter of the via located in the lower sub-stack structure; The thickness of the second layer of the sub-stacked structure in the upper layer is less than the thickness of the second layer of the sub-stacked structure in the lower layer.

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