Semiconductor device and preparation method thereof

Abstract

The invention discloses a semiconductor device and a preparation method thereof. The semiconductor device includes: a substrate; the channel layer, the barrier layer and the dielectric layer are sequentially arranged; the semiconductor device further comprises a groove; along the direction from the substrate to the dielectric layer, the side wall of the groove comprises a first wall surface, a second wall surface and a third wall surface which are connected in sequence; the first wall surface is located on the side, close to the center of the groove, of the third wall surface, a first corner is formed between the first wall surface and the second wall surface, and a second corner is formed between the third wall surface and the surface, back to the substrate, of the dielectric layer; the gate dielectric layer covers the dielectric layer; and the gate electrode covers the gate dielectric layer, a first step is formed on the part, corresponding to the first corner, of the gate electrode, and a second step is formed on the part, corresponding to the second corner, of the gate electrode.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more particularly to semiconductor devices and their fabrication methods. Background Technology

[0002] Semiconductor devices, such as high electron mobility transistors (HEMTs), are widely used in fields such as radio frequency communication and power electronics due to their high electron mobility, high breakdown voltage, and high frequency characteristics.

[0003] However, existing semiconductor devices still need improvement. Summary of the Invention

[0004] The purpose of this application is to provide a semiconductor device and a method for fabricating the same.

[0005] This application discloses a semiconductor device, including: Substrate; The semiconductor device further includes a trench layer, a barrier layer, and a dielectric layer arranged sequentially along a direction away from the substrate; the opening of the trench is located on the surface of the dielectric layer facing away from the substrate, and the trench extends from the dielectric layer into the barrier layer; along the direction from the substrate to the dielectric layer, the sidewalls of the trench include a first wall surface, a second wall surface, and a third wall surface connected sequentially; in a direction parallel to the substrate, the first wall surface is located on the side of the third wall surface near the center of the trench; a first corner is formed between the first wall surface and the second wall surface; and a second corner is formed between the third wall surface and the surface of the dielectric layer facing away from the substrate. A gate dielectric layer covers the dielectric layer and extends into the groove; A gate electrode, covering the gate dielectric layer, forms a first step at the portion of the gate electrode corresponding to the first corner and a second step at the portion corresponding to the second corner.

[0006] In some alternative embodiments, the third wall extends from the opening of the groove into the dielectric layer, and the first wall extends from the bottom wall of the groove into the dielectric layer.

[0007] In some alternative embodiments, along a direction away from the substrate, the dielectric layer includes an interlayer dielectric layer and an etch protection layer disposed sequentially, with both the third wall and the first wall extending into the interlayer dielectric layer.

[0008] In some alternative embodiments, the surface of the interlayer dielectric layer facing away from the substrate has a first protrusion, and the surface of the first protrusion facing the groove constitutes part of the third wall surface.

[0009] In some alternative embodiments, the surface of the etched protective layer facing away from the substrate has a second protrusion, and the surface of the second protrusion facing the groove constitutes part of the third wall surface.

[0010] In some alternative embodiments, the surface of the etched protective layer facing away from the substrate has a second protrusion, and the surface of the second protrusion facing the groove constitutes a portion of the third wall surface; the surface of the interlayer dielectric layer corresponding to the second protrusion facing away from the substrate is parallel to the substrate.

[0011] In some alternative embodiments, the edge of the gate electrode extends to the side of the second protrusion facing away from the substrate; or, in a direction parallel to the substrate, the edge of the gate electrode is located on the side of the second protrusion facing away from the groove.

[0012] In some alternative embodiments, the semiconductor device further includes a source and a drain disposed on opposite sides of the gate electrode in a direction parallel to the substrate, the interlayer dielectric layer surrounding at least a portion of the source and at least a portion of the drain, and the etch protection layer covering a portion of the source and a portion of the drain.

[0013] In some alternative embodiments, the second wall surface is connected to the third wall surface by a curved transition; and / or the first wall surface is connected to the second wall surface by a curved transition.

[0014] This application also discloses a method for fabricating a semiconductor device, comprising: Provide substrate; Along a direction away from the substrate, a channel layer, a first barrier sublayer, and a sacrificial gate are sequentially formed; A second barrier sublayer is formed that covers the first barrier sublayer; A dielectric layer is formed covering the second barrier sublayer; the orthogonal projection of the sacrificial gate on the substrate lies within the orthogonal projection of the dielectric layer on the substrate; The dielectric layer is etched to form a first sub-groove exposing the sacrificial gate, the orthographic projection of the sacrificial gate on the substrate being located within the orthographic projection of the first sub-groove on the substrate; the sidewall of the first sub-groove includes a third wall surface; the third wall surface forms a second corner with the surface of the dielectric layer facing away from the substrate; The sacrificial gate is removed to form a second sub-slot communicating with the first sub-slot; the sidewall of the second sub-slot includes a first wall surface; the first wall surface and the third wall surface are connected through a second wall surface at the bottom of the first sub-slot; a first corner is formed between the first wall surface and the second wall surface; A gate dielectric layer is formed, which covers the dielectric layer and extends into the first sub-slot and the second sub-slot; A gate electrode is formed covering the gate dielectric layer, wherein the portion of the gate electrode corresponding to the first corner forms a first step, and the portion corresponding to the second corner forms a second step.

[0015] In some alternative embodiments, along a direction away from the substrate, the dielectric layer includes an interlayer dielectric layer and an etching protection layer disposed sequentially, and the dielectric layer forming the layer covering the second barrier sublayer includes: Form an interlayer dielectric layer covering the second barrier sublayer; A first etching opening and a second etching opening are formed on the interlayer dielectric layer, and the first etching opening and the second etching opening are located on opposite sides of the sacrificial gate; A source electrode is formed at the first etched opening, and a drain electrode is formed at the second etched opening; An etching protection layer is formed, which covers the source, the drain, and the interlayer dielectric layer.

[0016] In some alternative implementations, removing the sacrificial gate includes: The semiconductor device is etched on the side with the etch protection layer using a preset medium, and the etch rate of the sacrificial gate is greater than the etch rate of the etch protection layer.

[0017] In some alternative implementations, the thickness of the second barrier sublayer is less than the thickness of the sacrificial gate.

[0018] In some alternative embodiments, the sacrificial gate includes a detection element, and any element in the dielectric layer is different from the detection element; the etching of the dielectric layer to form a first sub-groove exposing the sacrificial gate includes: The etched product is inspected, and etching is stopped when the detected element is detected.

[0019] In some alternative embodiments, the interlayer dielectric layer is above the sacrificial gate, the first sub-groove penetrates the etch protection layer and a portion of the interlayer dielectric layer, and the second sub-groove penetrates a portion of the interlayer dielectric layer and the second barrier sub-layer.

[0020] Compared with related technologies, the semiconductor device and its fabrication method of this application, on the one hand, first form a first barrier sublayer and a sacrificial gate, then form a second barrier sublayer, then remove the sacrificial gate, and then form a gate electrode, thereby realizing a grooved gate structure, avoiding etching damage to the first or second barrier sublayer when forming the first and second subgrooves, and the device takes into account high threshold voltage, high saturation current and high gate reliability; on the other hand, the gate electrode forms a first step corresponding to the first corner and a second step corresponding to the second corner, which is equivalent to a stepped gate field plate, which facilitates the control of the electric field.

[0021] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this specification. Attached Figure Description

[0022] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this specification and, together with the description, serve to explain the principles of this specification.

[0023] Figure 1 This is a schematic diagram of the semiconductor device fabrication method of this application after the formation of the first barrier sublayer.

[0024] Figure 2 This is a schematic diagram of the process of fabricating the semiconductor device according to this application after the sacrificial gate has been formed.

[0025] Figure 3 This is a schematic diagram showing the formation of the second barrier sublayer in the semiconductor device fabrication method of this application.

[0026] Figure 4 This is a schematic diagram of the semiconductor device fabrication method of this application after the formation of the interlayer dielectric layer.

[0027] Figure 5 This is a schematic diagram showing the formation of the source and drain electrodes in the fabrication method of the semiconductor device of this application.

[0028] Figure 6 This is a schematic diagram showing the formation of an etched protective layer in the fabrication method of the semiconductor device of this application.

[0029] Figure 7 This is a schematic diagram of the semiconductor device fabrication method of this application after the first sub-groove has been formed.

[0030] Figure 8A This is a schematic diagram of the semiconductor device fabrication method of this application after the second sub-groove has been formed.

[0031] Figure 8B for Figure 8A An enlarged schematic diagram of the middle W section.

[0032] Figure 9 This is a schematic diagram of the semiconductor device fabrication method of this application after the gate dielectric layer has been formed.

[0033] Figure 10 This is a schematic diagram of the semiconductor device fabrication method of this application after the gate electrode has been formed.

[0034] Figure 11 This is a schematic diagram showing the semiconductor device fabrication method of this application after the window has been formed.

[0035] Figure 12 This is another schematic diagram of the semiconductor device of this application.

[0036] Reference numerals: 1. Substrate; 2. Channel layer; 3. Barrier layer; 31. First barrier sub-layer; 32. Second barrier sub-layer; 4. Sacrificial gate; 5. Interlayer dielectric layer; 51. First protrusion; 6. Etching protection layer; 61. Second protrusion; 7. Source; 8. Drain; 9. Trench; 91. First wall; 92. Second wall; 93. Third wall; 94. First sub-groove; 95. Second sub-groove; 96. First corner; 97. Second corner; 98. Opening; 10. Gate dielectric layer; 11. Gate electrode; 12. Dielectric layer; 13. First step; 14. Second step; 15. Window. Detailed Implementation

[0037] The technical solutions in the embodiments (or "implementations") of this application will be clearly and completely described herein with reference to the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements.

[0038] If the embodiments of this application contain terms relating to directional indications or positional relationships (such as up, down, left, right, front, back, inside, outside, top, bottom, center, vertical, horizontal, longitudinal, transverse, length, width, counterclockwise, clockwise, axial, radial, circumferential, etc.), such terms are only used to explain the relative positional relationships and movement of the components in a specific posture (as shown in the attached figures); if the specific posture changes, the directional indications or positional relationships will also change accordingly. Furthermore, the terms "first" and "second" used in the embodiments of this application are only for descriptive convenience and should not be construed as indicating or implying relative importance.

[0039] This application provides a method for fabricating a semiconductor device. The method for fabricating the semiconductor device may include: Step S10, as follows Figure 1 As shown, substrate 1 is provided; Step S20, as Figure 1 and Figure 2As shown, a channel layer 2, a first barrier sublayer 31, and a sacrificial gate 4 are sequentially formed along a direction away from the substrate 1. Step S30, as Figure 3 As shown, a second barrier sublayer 32 is formed that covers the first barrier sublayer 31; Step S40, as Figure 6 As shown, a dielectric layer 12 is formed covering the second barrier sublayer 32; the orthogonal projection of the sacrificial gate 4 on the substrate 1 is located within the orthogonal projection of the dielectric layer 12 on the substrate 1; Step S50, as follows Figure 7 As shown, the dielectric layer 12 is etched to form a first sub-groove 94 that exposes the sacrificial gate 4. The orthogonal projection of the sacrificial gate 4 on the substrate 1 is located within the orthogonal projection of the first sub-groove 94 on the substrate 1. The sidewall of the first sub-groove 94 includes a third wall surface 93. The third wall surface 93 forms a second corner 97 with the surface of the dielectric layer 12 facing away from the substrate 1. Step S60, as follows Figure 8A and Figure 8B As shown, the sacrificial gate 4 is removed to form a second sub-slot 95 communicating with the first sub-slot 94; the sidewall of the second sub-slot 95 includes a first wall surface 91; the first wall surface 91 and the third wall surface 93 are connected through a second wall surface 92 at the bottom of the first sub-slot 94; a first corner 96 is formed between the first wall surface 91 and the second wall surface 92 (see...). Figure 8B ); Step S70, as follows Figure 9 As shown, a gate dielectric layer 10 is formed, which covers the dielectric layer 12 and extends into the first sub-slot 94 and the second sub-slot 95; Step S80, as follows Figure 10 As shown, a gate electrode 11 is formed covering the gate dielectric layer 10, and the gate electrode 11 corresponds to the first corner 96 (see...). Figure 8B The portion forming the first step 13 corresponds to the second corner 97 (see...). Figure 7 The second step 14 is formed by the part of ) .

[0040] The semiconductor device fabrication method of this application, on the one hand, firstly forms a first barrier sublayer 31 and a sacrificial gate 4, then forms a second barrier sublayer 32, then removes the sacrificial gate 4, and then forms a gate electrode 11, thereby realizing a recessed 9 gate structure, avoiding etching damage to the first barrier sublayer 31 or the second barrier sublayer 32 when forming the first sub-groove 94 and the second sub-groove 95, and the device takes into account high threshold voltage, high saturation current and high gate reliability; on the other hand, the gate electrode 11 forms a first step 13 corresponding to the first corner 96 and a second step 14 corresponding to the second corner 97, which is equivalent to a stepped gate field plate, which facilitates the control of the electric field.

[0041] The following is a detailed description of each part of the embodiments of this application: In step S10, as Figure 1 As shown, substrate 1 is provided.

[0042] Substrate 1 serves as the substrate for the device, and in this application, SiC substrate can be selected. SiC has a high thermal conductivity and a matching lattice constant, which can improve the heat dissipation performance and heterojunction quality of the device. In other embodiments, substrate 1 can also be made of other materials.

[0043] In step S20, as Figure 2 As shown, a channel layer 2, a first barrier sublayer 31, and a sacrificial gate 4 are sequentially formed along a direction away from the substrate 1.

[0044] This application describes a method for growing an undoped GaN layer on a substrate 1 using MOCVD to form a channel layer 2. It should be noted that, prior to forming the channel layer 2, a GaN buffer layer can be formed first, followed by the formation of the channel layer 2 on the GaN buffer layer. The function of this channel layer 2 is to provide a high-mobility two-dimensional electron gas (2DEG) channel.

[0045] This application allows for the growth of an AlGaN layer on the channel layer 2 to form a first barrier sublayer 31. This first barrier sublayer 31 forms a heterojunction with the channel layer 2, inducing a 2DEG through a polarization effect.

[0046] This application utilizes PECVD to deposit oxide or nitride to form a sacrificial material layer, which is then patterned using photolithography to form a sacrificial gate 4. The region containing the sacrificial gate 4 defines the gate region of the semiconductor device. The sacrificial gate 4 can be strip-shaped, and its extension direction can be parallel to the substrate 1.

[0047] In step S30, as Figure 3 As shown, a second barrier sublayer 32 is formed.

[0048] This application allows for the growth of an AlGaN layer on the first barrier sub-layer 31 via MOCVD as a second barrier sub-layer 32 (re-epitaxy technique). The thickness of the second barrier sub-layer 32 can be less than or equal to the thickness of the sacrificial gate 4, and the second barrier sub-layer 32 can cover the entire surface of the first barrier sub-layer 31 (including the area around the sacrificial gate 4).

[0049] The above step S40 may include steps S401 to S404, wherein: Step S401, as follows Figure 4 As shown, an interlayer dielectric layer 5 is formed covering the second barrier sublayer 32.

[0050] This application utilizes PECVD deposition of oxides or nitrides to form an interlayer dielectric layer 5. This interlayer dielectric layer 5 covers the entire surface of the second barrier sublayer 32. This interlayer dielectric layer 5 may be higher than the sacrificial gate 4. The material of the interlayer dielectric layer 5 differs from the material of the sacrificial gate 4.

[0051] Step S402: A first etch opening (not shown) and a second etch opening (not shown) are formed on the interlayer dielectric layer 5. The first etch opening and the second etch opening are located on opposite sides of the sacrificial gate 4.

[0052] The first and second etching openings are used to define the source region 7 and the drain region 8, respectively. In this application, the first and second etching openings can be formed on the interlayer dielectric layer 5 by CF4 / O2 dry etching for subsequent fabrication of ohmic contacts.

[0053] Step S403, as Figure 5 As shown, a source electrode 7 is formed at the first etch opening, and a drain electrode 8 is formed at the second etch opening.

[0054] This application utilizes electron beam evaporation to deposit a multilayer metal of Ti / Al / Ni / Au to fill etched openings. Subsequently, rapid thermal annealing in a nitrogen atmosphere forms an ohmic contact with low contact resistance.

[0055] Step S404, as follows Figure 6 As shown, an etched protective layer 6 is formed.

[0056] This application utilizes PECVD to deposit oxides or nitrides to form an etch protection layer 6. This etch protection layer 6 covers the entire surface of the source electrode 7, drain electrode 8, and interlayer dielectric layer 5, and its function is to protect the source electrode 7 and drain electrode 8 from damage during subsequent etching. The material of the etch protection layer 6 is different from the material of the sacrificial gate 4.

[0057] In step S50, as Figure 7 As shown, the first sub-slot 94 is formed.

[0058] This application uses CHF3 dry etching to form the first sub-groove 94. The interlayer dielectric layer 5 can be higher than the sacrificial gate 4. The first sub-groove 94 penetrates the etch protection layer 6 and part of the interlayer dielectric layer 5, that is, the first sub-groove 94 does not completely penetrate the interlayer dielectric layer 5. The size of the first sub-groove 94 can be larger than the sacrificial gate 4, and the orthographic projection of the sacrificial gate 4 on the substrate 1 is completely within the orthographic projection of the first sub-groove 94 on the substrate 1. The first sub-groove 94 can be strip-shaped, and its extension direction is the same as the extension direction of the sacrificial gate 4. In the direction perpendicular to the extension direction of the first sub-groove 94 (parallel to the substrate 1), the width of the first sub-groove 94 can be greater than the width of the sacrificial gate 4. In addition, the sidewall of the first sub-groove 94 is a third wall surface 93, which can be perpendicular to the substrate 1 (vertical surface) or the third wall surface 93 can be an inclined surface, and the third wall surface 93 forms a second corner 97 with the upper surface of the etch protection layer 6.

[0059] Furthermore, the sacrificial gate 4 may include a detection element, and any element in the dielectric layer 12 is different from the detection element; step S50 may further include: detecting the etching product, and stopping etching when the detection element is detected. Determining whether to terminate etching by whether the detection element is detected can prevent etching from damaging the second barrier sublayer 32. In one embodiment, the detection element may be oxygen; in another embodiment, the detection element may be nitrogen.

[0060] In step S60, as Figure 8A As shown, the sacrificial gate 4 is removed to form a second sub-slot 95 that communicates with the first sub-slot 94.

[0061] This application can remove the sacrificial gate 4 by dry etching or wet etching. Specifically, this application can use a preset dielectric to perform dry etching or wet etching (thinning) on ​​the side of the semiconductor device with the etching protection layer 6, and the etching rate of the sacrificial gate 4 is greater than the etching rate of the etching protection layer 6. The second sub-groove 95 penetrates part of the interlayer dielectric layer 5 and the second barrier sub-layer 32. The first wall surface 91 can be perpendicular to the substrate 1 (vertical surface) or the first wall surface 91 can be an inclined surface. The first wall surface 91 is connected to the second wall surface 92 (parallel to the substrate 1) at the bottom of the first sub-groove 94 to form a first corner 96 (see Figure 8B ).

[0062] In step S70, as Figure 9 As shown, a gate dielectric layer 10 is formed.

[0063] This application utilizes atomic layer deposition (ALD) to grow an Al2O3 gate dielectric layer 10. The gate dielectric layer 10 can cover the entire surface of the dielectric layer 12 and extend to the inner walls (including the first wall 91, the second wall 92, and the third wall 93) of the first sub-slot 94 and the second sub-slot 95, and the gate dielectric layer 10 conformally covers the inner walls of the first sub-slot 94 and the second sub-slot 95.

[0064] In step S80, as Figure 10 As shown, a gate electrode 11 is formed.

[0065] This application allows for the deposition of a gate electrode 11 via magnetron sputtering. Since the gate electrode 11 has a first step 13 and a second step 14, it functions as a stepped gate field plate, facilitating the control of the electric field. Furthermore, as... Figure 11 As shown, this application may also form a window 15. This window 15 exposes the source 7 (S) and the drain 8 (D).

[0066] This application also discloses a semiconductor device. This semiconductor device is prepared by the above-described semiconductor device fabrication method. The semiconductor device can be an enhancement-mode GaN HEMT, etc. Figure 8A and Figure 10 As shown, the semiconductor device may include: Substrate 1; The semiconductor device also includes a trench 9, a barrier layer 3, and a dielectric layer 12 arranged sequentially along a direction away from the substrate 1; the opening 98 of the trench 9 (see...) Figure 8A The groove 9 is located on the surface of the dielectric layer 12 facing away from the substrate 1, and extends from the dielectric layer 12 into the barrier layer 3; along the direction from the substrate 1 to the dielectric layer 12, the sidewalls of the groove 9 include a first wall surface 91, a second wall surface 92, and a third wall surface 93 connected in sequence. In a direction parallel to the substrate 1, the first wall surface 91 is located on the side of the third wall surface 93 closer to the center of the groove 9, and a first corner 96 is formed between the first wall surface 91 and the second wall surface 92 (see...). Figure 8B The third wall surface 93 forms a second corner 97 with the surface of the dielectric layer 12 facing away from the substrate 1 (see...). Figure 7 ); The gate dielectric layer 10 covers the dielectric layer 12 and extends into the groove 9; The gate electrode 11 covers the gate dielectric layer 10. The portion of the gate electrode 11 corresponding to the first corner 96 forms a first step 13, and the portion corresponding to the second corner 97 forms a second step 14.

[0067] In the semiconductor device of this application, the gate electrode 11 forms a first step 13 at the portion corresponding to the first corner 96 and a second step 14 at the portion corresponding to the second corner 97, which is equivalent to a stepped gate field plate, making it easy to control the electric field.

[0068] The following is a detailed description of each part of the embodiments of this application: Substrate 1 serves as the substrate for the device, and in this application, SiC substrate 1 can be selected. SiC has a high thermal conductivity and a matching lattice constant, which can improve the heat dissipation performance and heterojunction quality of the device. In other embodiments, the substrate 1 can also be made of other materials.

[0069] The channel layer 2 can be an undoped GaN layer (purity ≥ 99.999%). A buffer layer can also be provided between the channel layer 2 and the substrate 1. As the transport channel of 2DEG, the undoped nature of the channel layer 2 avoids impurity scattering.

[0070] The barrier layer 3 can be grown on the surface of the channel layer 2 facing away from the substrate 1. The barrier layer 3 can form a heterojunction with the channel layer 2, inducing a high areal density 2DEG at the interface through spontaneous polarization and piezoelectric polarization effects, providing a conductive channel for the device. The material of the barrier layer 3 can include AlGaN, etc. For example, along the direction away from the substrate 1, the barrier layer 3 can include a first barrier sublayer 31 and a second barrier sublayer 32 stacked together.

[0071] The dielectric layer 12 can cover the surface of the barrier layer 3 facing away from the substrate 1. Along the direction away from the substrate 1, the dielectric layer 12 may include an interlayer dielectric layer 5 and an etching protection layer 6 (both are dielectric materials) sequentially disposed. The interlayer dielectric layer 5 can be made of nitride or oxide and covers the entire surface of the barrier layer 3. The etching protection layer 6 can be made of nitride or oxide.

[0072] The opening 98 of the aforementioned groove 9 is located on the surface of the dielectric layer 12 facing away from the substrate 1, and extends from the dielectric layer 12 into the barrier layer 3 (i.e., reaching the depth of the barrier layer 3, but not penetrating to the channel layer 2). The orthographic projection of the groove 9 onto the substrate 1 can be strip-shaped. In the width direction of the groove 9 (perpendicular to the extension direction of the groove 9), the groove 9 can include two opposing sidewalls. Along the direction from the substrate 1 to the dielectric layer 12, each sidewall includes a first wall surface 91, a second wall surface 92, and a third wall surface 93 connected in sequence. In the width direction of the groove 9, the first wall surface 91 is located on the side of the third wall surface 93 closer to the center of the groove 9 (i.e., the first wall surface 91 is closer to the center of the groove 9), a first corner 96 (usually 90 degrees or an obtuse angle) is formed between the first wall surface 91 and the second wall surface 92, and a second corner 97 (also 90 degrees or an obtuse angle) is formed between the third wall surface 93 and the surface of the dielectric layer 12 facing away from the substrate 1. The number of the groove 9 is at least one (depending on the device structure, there may be multiple grooves 9, each groove 9 corresponding to a gate electrode 11). Based on the groove 9, the gate electrode 11 can be closer to the two-dimensional electron gas in the channel layer 2, improving the gate control capability; at the same time, the multi-wall structure of the sidewall (first wall 91, second wall 92, third wall 93) and the corner design help to improve the coverage of the gate electrode 11, reduce the stress concentration of the gate electrode 11 at the corner, and prevent the gate electrode 11 from breaking or leaking current.

[0073] Along the direction away from the substrate 1, the dielectric layer 12 includes an interlayer dielectric layer 5 and an etch protection layer 6 sequentially disposed. The interlayer dielectric layer 5 is located on the side of the barrier layer 3 away from the substrate 1; the etch protection layer 6 is located on the side of the interlayer dielectric layer 5 away from the substrate 1. At this time, the third wall surface 93 of the groove 9 extends from the opening into the interlayer dielectric layer 5 (i.e., the etch protection layer 6 is etched through, and the interlayer dielectric layer 5 is etched to a certain depth), and the first wall surface 91 extends from the bottom wall into the interlayer dielectric layer 5. For example... Figure 10 and Figure 11 As shown, the surface of the etched protective layer 6 facing away from the substrate 1 has a second protrusion 61 (i.e., the etched protective layer 6 protrudes upward in the region near the groove 9), and its surface facing the groove 9 constitutes a partial third wall surface 93. In one embodiment, as... Figure 10 and Figure 11 As shown, the surface of the interlayer dielectric layer 5 facing away from the substrate 1 has a first protrusion 51 (i.e., the interlayer dielectric layer 5 protrudes upward in the region near the groove 9), and its surface facing the groove 9 constitutes a portion of the third wall surface 93. The design of the first protrusion 51 and the second protrusion 61 can optimize the sidewall slope of the groove 9 (e.g., make the slope of the third wall surface 93 gentler), further improving the step coverage of the gate electrode 11 (i.e., the electrode material can cover the sidewall more uniformly, reducing the thickness thinning at the step). In another embodiment, as... Figure 12As shown, the surface of the interlayer dielectric layer 5 corresponding to the second protrusion 61 that faces away from the substrate 1 is parallel to the substrate 1. Taking the groove 9 as an example, which includes two opposing sidewalls, the number of the first protrusion 51 and the second protrusion 61 can both be two.

[0074] The second wall 92 and the third wall 93 of the aforementioned groove 9 are connected by a curved transition (i.e., the corners are rounded rather than sharp right angles), and the first wall 91 and the second wall 92 are also connected by a curved transition. This design can reduce electric field concentration at the corners (sharp corners can lead to a significant increase in electric field strength, which can easily cause breakdown), and improve the breakdown voltage of the device (i.e., the maximum voltage that the device can withstand). At the same time, the curved transition helps to conformally cover the gate dielectric layer 10 and the gate electrode 11 (i.e., the thin film material can cover the curved surface more uniformly, reducing interface defects), further improving the reliability of the device.

[0075] The semiconductor device also includes a source 7 (S) and a drain 8 (D), disposed on opposite sides of the gate electrode 11 (G) in a direction parallel to the substrate 1 (i.e., the source 7 is located on one side of the gate electrode 11, and the drain 8 is located on the other side, forming a "source-gate-drain" lateral structure). The source 7 and drain 8 are made of metal and form an ohmic contact (i.e., a low-resistance contact that allows free injection and collection of charge carriers) with the barrier layer 3 (such as AlGaN). An interlayer dielectric layer 5 surrounds at least a portion of the source 7 and drain 8 (i.e., the bottom of the source 7 and drain 8 is covered by the interlayer dielectric layer 5, and the top is exposed), and an etch protection layer 6 covers a portion of the source 7 and a portion of the drain 8 (i.e., the top portion of the source 7 and drain 8 is covered by the etch protection layer 6, and the top portion is exposed for lead generation).

[0076] The aforementioned gate dielectric layer 10 can cover the dielectric layer 12 and extend into the groove 9. The gate dielectric layer 10 is an insulating layer between the gate electrode 11 and the channel layer 2. The gate dielectric layer 10 is thin-film shaped and conformally covers the surface of the dielectric layer 12 and the sidewalls and bottom wall of the groove 9 (i.e., it is completely fitted to the shape of the groove 9).

[0077] The gate electrode 11 can cover the gate dielectric layer 10, and its material is typically a metallic material, such as titanium (Ti), aluminum (Al), gold (Au), or their alloys (such as Ti / Al alloy), or polysilicon. The gate electrode 11 is thin-film shaped, forming a first step 13 corresponding to the first corner 96 of the groove 9, and a second step 14 corresponding to the second corner 97 (i.e., completely fitting the sidewall shape of the groove 9, forming two step structures). The step structure helps improve the coverage of the gate electrode 11 (i.e., the electrode material can uniformly cover the sidewall and bottom wall of the groove 9), reducing the risk of electrode breakage or leakage at the corner, and improving the reliability of the device; at the same time, the gate electrode 11 with the first step 13 and the second step 14 is equivalent to a stepped gate field plate, which facilitates the control of the electric field. In addition, in one embodiment, the edge of the gate electrode 11 extends to the side of the second protrusion 61 facing away from the substrate 1. Further, in a direction parallel to the substrate 1, the edge of the gate electrode 11 is located on the side of the second protrusion 61 facing away from the groove 9.

[0078] It should be noted that the technical solutions or features described in the above embodiments can be combined or supplemented with each other without conflict. The scope of protection of this application is not limited to the precise structures described in the above embodiments and shown in the accompanying drawings; all modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A semiconductor device, characterized in that, include: Substrate; The semiconductor device includes a channel layer, a barrier layer, and a dielectric layer arranged sequentially along a direction away from the substrate. The device also includes a groove; the opening of the groove is located on the surface of the dielectric layer facing away from the substrate, and the groove extends from the dielectric layer into the barrier layer. Along the direction from the substrate to the dielectric layer, the sidewall of the groove includes a first wall, a second wall, and a third wall connected in sequence; in a direction parallel to the substrate, the first wall is located on the side of the third wall closer to the center of the groove, a first corner is formed between the first wall and the second wall, and a second corner is formed between the third wall and the surface of the dielectric layer facing away from the substrate; A gate dielectric layer covers the dielectric layer and extends into the groove; A gate electrode, covering the gate dielectric layer, forms a first step at the portion of the gate electrode corresponding to the first corner and a second step at the portion corresponding to the second corner.

2. The semiconductor device according to claim 1, characterized in that, The third wall extends from the opening of the groove into the dielectric layer, and the first wall extends from the bottom wall of the groove into the dielectric layer.

3. The semiconductor device according to claim 2, characterized in that, Along a direction away from the substrate, the dielectric layer includes an interlayer dielectric layer and an etching protection layer disposed sequentially, with the third wall and the first wall both extending into the interlayer dielectric layer.

4. The semiconductor device according to claim 3, characterized in that, The surface of the interlayer dielectric layer facing away from the substrate has a first protrusion, and the surface of the first protrusion facing the groove constitutes part of the third wall surface.

5. The semiconductor device according to claim 3 or 4, characterized in that, The surface of the etched protective layer facing away from the substrate has a second protrusion, and the surface of the second protrusion facing the groove constitutes part of the third wall surface.

6. The semiconductor device according to claim 3, characterized in that, The surface of the etched protective layer facing away from the substrate has a second protrusion, and the surface of the second protrusion facing the groove constitutes part of the third wall surface. The surface of the interlayer dielectric layer corresponding to the second protrusion, facing away from the substrate, is parallel to the substrate.

7. The semiconductor device according to claim 5, characterized in that, The edge of the gate electrode extends to the side of the second protrusion facing away from the substrate; or In a direction parallel to the substrate, the edge of the gate electrode is located on the side of the second protrusion facing away from the groove.

8. The semiconductor device according to claim 3, characterized in that, The semiconductor device further includes: The source and drain electrodes are disposed on opposite sides of the gate electrode in a direction parallel to the substrate, the interlayer dielectric layer surrounds at least a portion of the source electrode and at least a portion of the drain electrode, and the etch protection layer covers a portion of the source electrode and a portion of the drain electrode.

9. The semiconductor device according to claim 1, characterized in that, The second wall surface and the third wall surface are connected by a curved transition; and / or The first wall surface and the second wall surface are connected by a curved surface transition.

10. A method for fabricating a semiconductor device, characterized in that, include: Provide substrate; Along a direction away from the substrate, a channel layer, a first barrier sublayer, and a sacrificial gate are sequentially formed; A second barrier sublayer is formed that covers the first barrier sublayer; A dielectric layer is formed covering the second barrier sublayer; The orthogonal projection of the sacrificial gate onto the substrate lies within the orthogonal projection of the dielectric layer onto the substrate; The dielectric layer is etched to form a first sub-groove exposing the sacrificial gate, wherein the orthographic projection of the sacrificial gate on the substrate is located within the orthographic projection of the first sub-groove on the substrate; The sidewall of the first sub-slot includes a third wall surface; The third wall surface forms a second corner with the surface of the dielectric layer facing away from the substrate; The sacrificial gate is removed to form a second sub-slot communicating with the first sub-slot; the sidewall of the second sub-slot includes a first wall surface; the first wall surface and the third wall surface are connected through a second wall surface at the bottom of the first sub-slot; a first corner is formed between the first wall surface and the second wall surface; A gate dielectric layer is formed, which covers the dielectric layer and extends into the first sub-slot and the second sub-slot; A gate electrode is formed covering the gate dielectric layer, wherein the portion of the gate electrode corresponding to the first corner forms a first step, and the portion corresponding to the second corner forms a second step.

11. The method for fabricating a semiconductor device according to claim 10, characterized in that, Along a direction away from the substrate, the dielectric layer includes an interlayer dielectric layer and an etching protection layer disposed sequentially, and the dielectric layer forming the layer covering the second barrier sublayer includes: Form an interlayer dielectric layer covering the second barrier sublayer; A first etching opening and a second etching opening are formed on the interlayer dielectric layer, and the first etching opening and the second etching opening are located on opposite sides of the sacrificial gate; A source electrode is formed at the first etched opening, and a drain electrode is formed at the second etched opening; An etching protection layer is formed, which covers the source, the drain, and the interlayer dielectric layer.

12. The method for fabricating a semiconductor device according to claim 11, characterized in that, The removal of the sacrificial gate includes: The semiconductor device is etched on the side with the etch protection layer using a preset medium, and the etch rate of the sacrificial gate is greater than the etch rate of the etch protection layer.

13. The method for fabricating a semiconductor device according to claim 10, characterized in that, The thickness of the second barrier sublayer is less than the thickness of the sacrificial gate.

14. The method for fabricating a semiconductor device according to claim 10, characterized in that, The sacrificial gate includes a detection element, and any element in the dielectric layer is different from the detection element; the etching of the dielectric layer to form a first sub-groove exposing the sacrificial gate includes: The etched product is inspected, and etching is stopped when the detected element is detected.

15. The method for fabricating a semiconductor device according to claim 11, characterized in that, The interlayer dielectric layer is higher than the sacrificial gate, the first sub-groove penetrates the etch protection layer and a portion of the interlayer dielectric layer, and the second sub-groove penetrates a portion of the interlayer dielectric layer and the second barrier sub-layer.

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