A backflow semiconductor device, a preparation method, a memory and a brain-like chip

Abstract

The application discloses a hysteresis semiconductor device, a preparation method, a memory and a brain-like chip, which comprises a substrate, and a spacer gate, a gate dielectric layer, a semiconductor active layer, a source-drain electrode and a gate electrode on the substrate. The semiconductor active layer extends along a first direction, and both ends of the semiconductor active layer are connected with the source-drain electrode, and the semiconductor active layer comprises a channel region controlled vertically by the spacer gate and a semiconductor region corresponding to a gate spacer region; the gate dielectric layer covers the whole semiconductor active layer, a plurality of spacer gates are connected with the gate electrode, and the gate dielectric layer is separated from the semiconductor active layer, a conductive channel is formed in the semiconductor under the vertical regulation of the gate voltage, and the localized electric field of the spacer gate extends to the semiconductor region corresponding to the gate spacer region and induces carrier accumulation / depletion delay. The application realizes controllable hysteresis without charge traps or ion migration, and has the advantages of controllable hysteresis, high stability, strong process compatibility, low power consumption, high reliability, excellent device consistency and the like, and is suitable for multiple scene applications.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, and particularly to a hysteresis semiconductor device, a preparation method, a memory and a brain-like chip. BACKGROUND

[0002] With the rapid development of cloud computing, artificial intelligence, 5G communication and other fields, the application demand of semiconductor devices in neuromorphic computing, low-power memory, high-precision sensor and other scenes is increasingly urgent. As one of the core functions of such devices, the implementation of hysteresis characteristics directly determines the stability, controllability, power consumption and process compatibility of the device. At present, the hysteresis characteristics of semiconductor devices in the prior art mainly rely on physical mechanisms such as charge traps, ion migration or ferroelectric polarization. However, these mechanisms all have defects that are difficult to overcome, which seriously restricts the performance improvement and large-scale application of the device.

[0003] In the defect charge trap mechanism, the formation and distribution of charge traps have natural randomness, resulting in that the hysteresis characteristics of the device are strongly dependent on test conditions (such as gate voltage scan frequency, operating temperature), and the performance repeatability is poor. For example, in two-dimensional material-based transistors such as MoS2, the hysteresis width will change linearly with the thickness of the insulating layer, making it difficult to accurately predict the performance of sub-nanometer equivalent oxide thickness (EOT) devices, and unable to meet the needs of high-precision application scenarios. At the same time, the deposition process of the dielectric layer (such as atomic layer deposition of SiOx / HfOx stacked dielectric layer) is prone to introduce interface state defects. The density and distribution of these defects vary significantly between different batches and different devices, resulting in a hysteresis characteristic fluctuation amplitude of ±30% between devices, which seriously hinders the standardized production and large-scale application of the device.

[0004] The ion migration mechanism (such as oxygen vacancy migration in memristors, ion transport in nanofluidic channels) changes the conductance of the device by moving ions to achieve hysteresis. However, this mechanism also has obvious shortcomings. In oxide memristors such as HfO2, the hysteresis characteristics depend on the growth and breakage process of the conductive filament formed by oxygen vacancies. This process is strongly random due to factors such as local electric field, temperature fluctuations, resulting in poor consistency of the device switching ratio, with a fluctuation amplitude of up to 40%. High-density cycle operation can accelerate the fatigue and breakage of the conductive filament, significantly shortening the service life of the device. In nanofluidic channel type devices, the ion migration process is easily affected by factors such as interface charge disturbance and dielectric layer aging. After long-term operation, the conductance drift coefficient is as high as 0.092, which seriously affects the conductance regulation accuracy of the device, especially cannot meet the application demand of high-precision update of synaptic weights in neuromorphic computing.

[0005] Ferroelectric materials achieve hysteresis characteristics through polarization reversal, but in the process of semiconductor device integration, it faces the technical bottleneck of low polarization efficiency and poor process compatibility. The in-plane polarization field strength of two-dimensional ferroelectric materials (such as GaSe and In2Se3) is weak. In order to achieve effective polarization reversal to produce obvious hysteresis, a gate drive voltage higher than 40V needs to be applied, which not only leads to a sharp rise in device power consumption, but also is incompatible with the low voltage working window of the existing CMOS process, making it difficult to realize system integration. In the van der Waals heterojunction structure (such as graphene / ferroelectric stack), the high conductivity layer will produce a Coulomb shielding effect, which significantly weakens the regulation efficiency of the ferroelectric polarization on the channel carriers. In order to compensate for this effect, a complex heterojunction stack structure needs to be designed, which not only increases the process complexity and manufacturing cost, but also reduces the long-term reliability of the device.

[0006] In summary, the existing hysteresis characteristic implementation schemes based on charge traps, ion migration or ferroelectric polarization all have core defects such as insufficient stability, significant randomness, excessive power consumption or poor process compatibility, which cannot meet the needs of emerging fields such as neuromorphic computing and low-power memory for high-performance, high-reliability, low-power and standardized production of devices. Therefore, developing a new type of stable, controllable and compatible hysteresis characteristic device has become a technical problem to be solved in the field. SUMMARY

[0007] To this end, the technical problem to be solved by the present application is to overcome the problem of insufficient stability and controllability of the hysteresis characteristic of the existing components, and to provide a hysteresis semiconductor device, a preparation method, a memory and a brain-like chip.

[0008] To solve the above technical problems, the present application provides a hysteresis semiconductor device, which comprises a substrate and a plurality of spaced gates, a gate dielectric layer, a semiconductor active layer, a source electrode, a drain electrode and a gate electrode arranged on the substrate, wherein the semiconductor active layer continuously extends along a first direction, the two ends of the first direction are electrically connected to the source electrode and the drain electrode respectively, and the semiconductor active layer comprises a channel region and a semiconductor region, and the semiconductor region is located between adjacent channel regions; the gate dielectric layer covers the surface of the semiconductor active layer, and the coverage range of the gate dielectric layer includes the channel region and the semiconductor region; a plurality of spaced gates are connected to the gate electrode and are isolated from the semiconductor active layer by the gate dielectric layer, a plurality of spaced gates are arranged in the same direction and are arranged in the first direction, and the orthogonal projection of a plurality of spaced gates on the semiconductor active layer coincides with the channel region, so that the channel region forms a conductive channel under the regulation of the gate voltage, and the localized electric field generated by the spaced gate can extend to the semiconductor region and induce the semiconductor region to produce carrier accumulation / depletion hysteresis.

[0009] In one embodiment of the present application, the plurality of the spacer gates are uniformly spaced along the first direction, and the distance between adjacent spacer gates is less than 5 μm.

[0010] In one embodiment of the present application, the spacer gate is disposed on the substrate, and the gate dielectric layer is connected to the substrate and covers the spacer gate, and the semiconductor active layer, the source electrode, the drain electrode and the gate electrode are disposed on the gate dielectric layer.

[0011] In one embodiment of the present application, the substrate is disposed on one side of the semiconductor active layer in the thickness direction, and the spacer gate and the gate dielectric layer are disposed on the other side of the semiconductor active layer in the thickness direction, and the source electrode, the drain electrode and the gate electrode are disposed on the gate dielectric layer.

[0012] In one embodiment of the present application, the spacer gate comprises a plurality of top gates and a plurality of bottom gates, and the gate dielectric layer comprises a top gate dielectric layer and a bottom gate dielectric layer, wherein the bottom gate is disposed on the substrate, the bottom gate dielectric layer is connected to the substrate and covers the bottom gate, one side of the semiconductor active layer is connected to the bottom gate dielectric layer, and the other side is connected to the top gate dielectric layer, and the plurality of the top gates are disposed in the top gate dielectric layer.

[0013] In one embodiment of the present application, the gate electrode comprises a top gate electrode and a bottom gate electrode, wherein the top gate electrode is connected to the plurality of the top gates, and the bottom gate electrode is connected to the plurality of the bottom gates.

[0014] In one embodiment of the present application, the semiconductor active layer substrate is one or more of indium gallium zinc oxide, zinc oxide, indium tin oxide, indium gallium zinc oxide, aluminum indium tin zinc oxide.

[0015] The present application also provides a preparation method of a backscattering semiconductor device, which is used to prepare the backscattering semiconductor device described above, and the preparation method comprises:

[0016] Preparation of a plurality of spacer gates, a gate dielectric layer and a semiconductor active layer on a clean substrate, wherein the spacer gates are separated from the semiconductor active layer by the gate dielectric layer, the plurality of the spacer gates are disposed in the same direction and are spaced along a first direction;

[0017] The semiconductor active layer preparation process is:

[0018] Step S1, dividing a channel region and a semiconductor region on the semiconductor active layer substrate, wherein the semiconductor region is located between adjacent channel regions, and the orthogonal projection of the plurality of the spacer gates on the semiconductor active layer is coincident with the channel region;

[0019] Step S2, connecting the source electrode and the drain electrode to the two ends of the semiconductor active layer in the first direction respectively, and leading out the gate electrode of the interval gate, so that the channel region forms a conductive channel under the control of the gate voltage, and the localized electric field generated by the interval gate can extend to the semiconductor region, and induce the semiconductor region to generate carrier accumulation / depletion hysteresis.

[0020] In an embodiment of the present application, the method for preparing the hysteresis semiconductor device specifically comprises:

[0021] Step a1, preparing a plurality of interval gates arranged at intervals in the first direction on a clean substrate;

[0022] Step a2, depositing a gate dielectric layer on the substrate, so that the gate dielectric layer completely covers the surface of the interval gate;

[0023] Step a3, preparing the semiconductor active layer on the side of the gate dielectric layer away from the substrate;

[0024] Step a4, preparing a contact hole after depositing passivation on the semiconductor active layer;

[0025] Step a5, preparing a source electrode, a drain electrode and a gate electrode, so that the two ends of the semiconductor active layer in the first direction are connected to the source electrode and the drain electrode respectively, and so that a plurality of the interval gates are connected to the gate electrode, thereby obtaining the hysteresis semiconductor device.

[0026] In an embodiment of the present application, the method for preparing the hysteresis semiconductor device specifically comprises:

[0027] Step b1, preparing a semiconductor active layer on a clean substrate;

[0028] Step b2, depositing a gate dielectric layer on the semiconductor active layer, so that the gate dielectric layer completely covers the semiconductor active layer;

[0029] Step b3, preparing a plurality of interval gates arranged at intervals in the first direction on the gate dielectric layer;

[0030] Step b4, preparing a contact hole after depositing passivation on the interval gate and the gate dielectric layer;

[0031] Step b5, preparing a source electrode, a drain electrode and a gate electrode, so that the two ends of the semiconductor active layer in the first direction are connected to the source electrode and the drain electrode respectively, and so that a plurality of the interval gates are connected to the gate electrode, thereby obtaining the hysteresis semiconductor device.

[0032] In an embodiment of the present application, the method for preparing the hysteresis semiconductor device specifically comprises:

[0033] Step c1, preparing a plurality of bottom gates arranged at intervals along a first direction on a clean substrate;

[0034] Step c2, depositing a bottom gate dielectric layer on the substrate, so that the bottom gate dielectric layer completely covers the surface of the bottom gate;

[0035] Step c3, preparing the semiconductor active layer on the side of the bottom gate dielectric layer away from the substrate;

[0036] Step c4, depositing a top gate dielectric layer on the semiconductor active layer, and making the top gate dielectric layer completely cover the semiconductor active layer;

[0037] Step c5, preparing a plurality of top gates arranged at intervals along the first direction on the top gate dielectric layer;

[0038] Step c6, preparing a contact hole after depositing and passivating on the top gate and the top gate dielectric layer;

[0039] Step c7, preparing a source electrode, a drain electrode and a gate electrode, so that the two ends of the semiconductor active layer in the first direction are connected to the source electrode and the drain electrode respectively, and the plurality of interval gates are connected to the gate electrode, thereby obtaining a hysteretic semiconductor device.

[0040] The application also provides a memory comprising the above-mentioned hysteretic semiconductor device.

[0041] The application also provides a brain-like chip comprising the above-mentioned hysteretic semiconductor device.

[0042] The above technical solutions of the application have the following advantages compared with the prior art:

[0043] The hysteretic semiconductor device, the preparation method, the memory and the brain-like chip provided by the application realize the controllable hysteresis characteristic of the semiconductor device without introducing charge traps or ion migration, through the interval gate layout and the special design of the channel region and the semiconductor region on the semiconductor active layer, which has the following advantages compared with the conventional device at the present stage:

[0044] 1. The controllability of the hysteresis characteristic of the application is significantly improved, which abandons the traditional hysteresis implementation method relying on defect charge traps (strong randomness) or ion migration (uncontrollable), and through the interval of the interval gate, the arrangement density and the gate voltage scanning parameter, the hysteresis amplitude and response speed of the carrier accumulation / depletion of the semiconductor region can be accurately controlled. At the same time, the semiconductor region is not intentionally doped, which avoids the problems of defect state density fluctuation and ion migration fatigue, and greatly improves the long-term stability.

[0045] 2. The process of the present application is compatible, without the need to introduce special materials or complex processes, the spacer gate, gate dielectric layer and semiconductor active layer are prepared by semiconductor conventional process, and the semiconductor active layer substrate is compatible with the existing CMOS process. In addition, the device structure has no additional stacking or heterojunction design, and the process steps are simplified, thereby effectively reducing the process complexity and production cost, avoiding the high voltage drive and interface shielding problem of traditional ferroelectric integration.

[0046] 3. The present application has low power consumption and high reliability, and is suitable for multiple scene applications. The localized electric field of the spacer gate can be effectively extended to the semiconductor region with low gate voltage, inducing hysteresis characteristics. Compared with the high drive voltage of the traditional ferroelectric mechanism, the power consumption can be significantly reduced. At the same time, due to the interface damage caused by charge trap capture / release or ion migration, the device leakage current is small, the static power consumption is significantly optimized, and the stable and controllable hysteresis characteristics can be widely adapted to low-power memory, neuromorphic computing chips, high-precision sensors and other scenes, especially for portable electronic devices, industrial control and other fields with strict requirements on reliability and power consumption.

[0047] 4. The device consistency of the present application is excellent, which can well overcome the problem that the randomness of defect distribution and ion migration path in the traditional mechanism leads to significant differences in hysteresis characteristics between devices, thereby hindering standardized production. The present application precisely controls the structure to make the hysteresis consistency between devices much better than the traditional scheme, providing a reliable foundation for large-scale production and system integration. BRIEF DESCRIPTION OF DRAWINGS

[0048] In order to make the content of the present application more easily understood, the present application will be further described in detail below according to specific embodiments of the present application and in conjunction with the drawings.

[0049] Figure 1 is a structure diagram of a hysteresis semiconductor device in a preferred embodiment of the present application;

[0050] Figure 2 is a top view of the hysteresis semiconductor device shown in FIG. 1; Figure 1

[0051] Figure 3 is a transfer curve of forward and reverse measurement of a traditional single-gate structure device;

[0052] Figure 4 is a transfer curve of forward and reverse measurement of the hysteresis semiconductor device shown in FIG. 1; Figure 1

[0053] Figure 5 is a structure diagram of a hysteresis semiconductor device in another embodiment of the present application;

[0054] Figure 6 is a top view of the hysteresis semiconductor device shown in FIG. 3; Figure 5 ​​A top view of the hysteresis semiconductor device shown;

[0055] Figure 7 This is a schematic diagram of the structure of the hysteresis semiconductor device in the third embodiment of the present invention;

[0056] Figure 8 yes Figure 7 A top view of the hysteresis semiconductor device shown.

[0057] Explanation of reference numerals in the accompanying drawings: 100, substrate; 200, spacer gate; 210, top gate; 220, bottom gate; 300, gate dielectric layer; 310, top gate dielectric layer; 320, bottom gate dielectric layer; 400, semiconductor active layer; 500, source electrode; 600, drain electrode; 700, gate electrode; 710, top gate electrode; 720, bottom gate electrode; X, first direction; Y, second direction; Z, third direction. Detailed Implementation

[0058] The present invention will be further described below with reference to the accompanying drawings and specific embodiments, so that those skilled in the art can better understand and implement the present invention. However, the embodiments described are not intended to limit the present invention.

[0059] Example 1: See Figure 1 and Figure 2 As shown, this embodiment provides a hysteresis semiconductor device, comprising: a substrate 100 and a plurality of spacer gates 200, a gate dielectric layer 300, a semiconductor active layer 400, a source electrode 500, a drain electrode 600, and a gate electrode 700 disposed on the substrate 100. The semiconductor active layer 400 extends continuously along a first direction X, and its two ends in the first direction X are electrically connected to the source electrode 500 and the drain electrode 600, respectively. The semiconductor active layer 400 includes a channel region and a semiconductor region, with the semiconductor region located between adjacent channel regions. The gate dielectric layer 300 covers the surface of the semiconductor active layer 400. The gate dielectric layer 300 covers both the channel region and the semiconductor region. Multiple spacer gates 200 are connected to the gate electrode 700 and isolated from the semiconductor active layer 400 via the gate dielectric layer 300. The multiple spacer gates 200 are arranged in the same direction and spaced apart along a first direction X. The orthogonal projection of the multiple spacer gates 200 onto the semiconductor active layer 400 coincides with the channel region, so that the channel region forms a conductive channel under gate voltage control. The localized electric field generated by the spacer gates 200 can extend to the semiconductor region and induce carrier accumulation / depletion hysteresis in the semiconductor region.

[0060] It should be noted that, for the convenience of description, the length direction of the hysteresis semiconductor device in the embodiment is defined as the first direction X, the width direction of the hysteresis semiconductor device is defined as the second direction Y, and the thickness direction of the hysteresis semiconductor device is defined as the third direction Z, wherein the first direction X, the second direction Y and the third direction Z are perpendicular to each other, and the first direction X and the second direction Y are located in the same plane.

[0061] In the embodiment, the substrate 100 serves as the basic support structure of the whole device, provides a physical bearing platform for all functional layers on the substrate 100, such as the interval gate 200, the gate dielectric layer 300, the semiconductor active layer 400, the source electrode 500, the drain electrode 600, the gate electrode 700, etc., and guarantees the stable adhesion and accurate positioning of each layer structure. In different embodiments, it can be selected according to the device requirements to select conductive, semi-conductive or insulating materials to assist in controlling the electrical performance of the device as a whole.

[0062] The semiconductor active layer 400 is the core functional layer of the device to realize the electrical signal transmission and hysteresis characteristics. Its structure continuously extends along the first direction X to provide a path for the migration of charge carriers, and the two ends are electrically connected with the source electrode 500 and the drain electrode 600 respectively to form the main channel of current transmission. Among them, the channel region is the key area to form a conductive channel under the control of gate voltage, which provides a basic site for the conduction of charge carriers; the semiconductor region is located between adjacent channel regions, and its core role is to respond to the localized electric field generated by the interval gate 200, and under the action of the electric field, the accumulation or depletion of charge carriers occurs, and the accumulation / depletion process has a hysteresis effect, thereby forming the core structure of the device to realize the hysteresis characteristic. In the embodiment, the channel region is doped to generate a large number of movable charge carriers in the channel region, while the semiconductor region itself does not have the charge carriers introduced by doping. In different embodiments, different doping methods or no doping can be set according to actual design requirements, and the present application does not make specific limitations.

[0063] Specifically, the semiconductor active layer 400 substrate in the embodiment is indium gallium zinc oxide, and in different embodiments, the semiconductor active layer 400 substrate is one or more of indium gallium zinc oxide, zinc oxide, indium tin oxide, indium gallium zinc oxide, aluminum indium tin zinc oxide, and the present application does not make specific limitations.

[0064] The source electrode 500 and the drain electrode 600 are respectively electrically connected with the two ends of the semiconductor active layer 400, wherein the source electrode 500 injects charge carriers into the semiconductor active layer 400, and the drain electrode 600 collects the charge carriers transmitted through the semiconductor active layer 400, and the two cooperate to complete the input and output of current in the device to form a complete current loop; at the same time, the good ohmic contact between the electrode and the semiconductor active layer 400 can reduce the contact resistance and guarantee the efficient injection and collection of charge carriers.

[0065] The plurality of interval gates 200 are connected with the gate electrode 700, can synchronously receive the gate voltage signal applied by the gate electrode 700, and realize unified regulation and control of each interval gate 200; the plurality of interval gates 200 are arranged at intervals along the first direction X, and the orthographic projection of the interval gate 200 on the semiconductor active layer 400 coincides with the channel region. This structural design can ensure that the electric field applied by the interval gate 200 precisely acts on the channel region, and under the regulation of the gate voltage, the channel region forms a conductive channel to provide a path for the conduction of the carriers; at the same time, the localized electric field generated by the interval gate 200 can break through the range of the channel region and extend to the adjacent semiconductor region, and through the action of the localized electric field, the accumulation / depletion hysteresis of the carriers in the semiconductor region is induced, which is a key structure for regulating the hysteresis characteristics of the device; the gate electrode 700 serves as an input port of the gate voltage signal and provides synchronous voltage driving for all interval gates 200, ensuring the consistency and coordination of the electric field regulation of each interval gate 200.

[0066] Further, in the embodiment, the plurality of interval gates 200 are uniformly arranged at intervals along the first direction X, so that the orthographic projection of each interval gate 200 on the channel region of the semiconductor active layer 400 is uniformly distributed, the consistency of the conductive channel formed by each channel region under the regulation of the gate voltage is strong, the difference in channel conduction efficiency caused by uneven distribution of the interval gate 200 is avoided, and the stability of the device current transmission is ensured; at the same time, the localized electric field generated by the uniformly distributed interval gate 200 can form an ordered electric field gradient between adjacent interval gates 200, ensuring that the electric field can stably extend to the semiconductor region between the channel regions.

[0067] Specifically, in the embodiment, the interval distance between adjacent interval gates 200 is 4.8 μm. In actual processing and use, an interval of less than 5.0 μm can avoid rapid attenuation of the electric field of the interval gate 200 due to too far distance, ensure that the localized electric field of the adjacent interval gate 200 is effectively superimposed within the range of the semiconductor region, and enhance the regulation and control effect on the carrier accumulation / depletion process of the semiconductor region; at the same time, the small interval design can reduce the size of the device along the first direction X, which is beneficial to the miniaturization and integration of the device and meets the application requirements of high-density integration of semiconductor devices.

[0068] The gate dielectric layer 300, acting as an insulating isolation layer, covers the entire surface of the semiconductor active layer 400, encompassing both the channel region and the semiconductor region. On one hand, the gate dielectric layer 300 enables electrical isolation between the spacer gate 200, the gate electrode 700, and the semiconductor active layer 400, preventing short circuits caused by direct contact between the electrode and the semiconductor active layer 400, thus ensuring the effectiveness of gate voltage regulation. On the other hand, the gate dielectric layer 300 serves as a medium for electric field transmission, efficiently transferring the electric field applied by the spacer gate 200 to the underlying semiconductor active layer 400, particularly precisely acting on the channel region and the semiconductor region. This provides the physical basis for electric field conduction, enabling the formation of conductive channels and the generation of hysteresis effects. Consequently, it improves the film quality of the semiconductor active layer 400, reduces losses during carrier migration, and efficiently conducts the electric field generated by the spacer gate 200, reducing the attenuation of the electric field during transmission.

[0069] In this embodiment, see Figure 1 As shown, the spacer gate 200 is disposed on the substrate 100, and the gate dielectric layer 300 is connected to the substrate 100 and covers the spacer gate 200. The semiconductor active layer 400, the source electrode 500, the drain electrode 600, and the gate electrode 700 are all disposed on the gate dielectric layer 300. This top-down integrated layout facilitates the precise patterning of each layer structure using standard semiconductor processes such as photolithography and deposition. The semiconductor active layer 400 forms good electrical connections with the source electrode 500 and the drain electrode 600, respectively, constituting a complete circuit for carrier transport. The source electrode 500 is responsible for injecting carriers into the semiconductor active layer 400, and the drain electrode 600 is responsible for collecting the carriers transported through the semiconductor active layer 400. Together, they ensure efficient current input and output.

[0070] The semiconductor active layer 400 includes a channel region and a semiconductor region. The semiconductor region is located between adjacent channel regions. The orthographic projection of the plurality of spacer gates 200 on the semiconductor active layer 400 coincides with the channel region, and all of the spacer gates 200 are electrically connected to the gate electrode 700, enabling them to synchronously receive the gate voltage signal input from the gate electrode 700. When a gate voltage is applied to the gate electrode 700, the localized electric field generated by the spacer gates 200 is precisely applied to the channel region below through the electric field conduction of the gate dielectric layer 300, causing the channel region to form a conductive channel. At the same time, since the spacing between adjacent spacer gates 200 is <5μm, the localized electric field can extend beyond the channel region to the adjacent semiconductor region, inducing the accumulation / depletion hysteresis effect of charge carriers in the semiconductor region, thereby enabling the device to achieve stable hysteresis characteristics and meeting the functional requirements of related electronic devices for signal storage and control.

[0071] Based on the above design idea, the application provides a backflow semiconductor device preparation method. First, a substrate 100 that meets the cleanliness standard and meets the device performance requirements is selected as the preparation base. The substrate 100 needs to be pretreated to remove surface impurities, oxide layers and contaminants to ensure that the subsequent functional layer can be stably attached and form a good interface bond. Based on the clean substrate 100, a plurality of spaced gates 200, gate dielectric layers 300 and semiconductor active layers 400 are prepared in turn. The core layout relationship needs to be strictly controlled: the spaced gates 200 and the semiconductor active layer 400 are completely isolated by the gate dielectric layer 300, which not only avoids electrical short circuiting but also ensures efficient conduction of the electric field; the plurality of spaced gates 200 are arranged in the same direction and are spaced along a predetermined first direction X, which lays the foundation for the subsequent precise corresponding semiconductor active layer 400 channel region.

[0072] After the semiconductor active layer 400 is prepared, the electrode preparation and connection process is performed: the two ends of the target semiconductor active layer 400 along the first direction X are respectively electrically connected with the source electrode 500 and the drain electrode 600 to form a complete carrier transport loop, ensuring that the source electrode 500 can efficiently inject carriers and the drain electrode 600 can stably collect carriers; at the same time, all the spaced gates 200 are simultaneously led out and electrically connected with the gate electrode 700, so that the gate electrode 700 can synchronously input a gate voltage signal to the plurality of spaced gates 200, realizing unified regulation and control of each spaced gate 200.

[0073] The semiconductor active layer 400 preparation process includes the following steps: step S1, dividing a channel region and a semiconductor region on the semiconductor active layer 400 substrate, wherein the semiconductor region is located between adjacent channel regions, and the orthogonal projection of the plurality of spaced gates 200 on the semiconductor active layer 400 overlaps the channel region;

[0074] Step S2, doping in the channel region to obtain a target semiconductor active layer 400. The doping treatment can generate a large number of movable carriers in the channel region, becoming a functional region with potential conductivity, providing a material basis for the formation of a conductive channel under the subsequent gate voltage regulation. The semiconductor region has no large number of carriers introduced by doping, and its carrier concentration completely depends on the induction and regulation of the external electric field. The functional difference between the high carrier concentration of the channel region and the low carrier concentration of the semiconductor region is the core premise for the formation of a conductive channel in the channel region and the generation of carrier accumulation / depletion delay in the semiconductor region under the subsequent gate voltage regulation. In different embodiments, different doping methods or no doping can be set according to actual design requirements, and the application does not make specific limitations.

[0075] Through the above preparation process, the final obtained hysteresis semiconductor device can realize the preset function: when the gate voltage is applied to the gate electrode 700, the localized electric field generated by the interval gate 200 is conducted to the lower channel region through the gate dielectric layer 300, which promotes the formation of a conductive channel in the channel region; at the same time, due to the interval arrangement of the interval gate 200 along the first direction X and the reasonable interval, the localized electric field can break through the range of the channel region and extend to the adjacent semiconductor region, inducing the semiconductor region to produce carrier accumulation / depletion hysteresis effect, thereby making the device stably present hysteresis characteristics, meeting the application requirements of related electronic equipment.

[0076] Specifically, the method for preparing the hysteresis semiconductor device of the present embodiment specifically comprises:

[0077] Step a1, preparing a plurality of interval gates 200 spaced along the first direction X on a clean substrate 100; specifically, using a magnetron sputtering process to deposit gate material, then defining the pattern of the interval gate 200 through a photolithography process, and then etching to obtain interval gates 200 spaced along the first direction X; finally, stripping the photoresist to obtain a plurality of interval gate 200 structures;

[0078] Step a2, depositing a gate dielectric layer 300 on the substrate 100, so that the gate dielectric layer 300 completely covers the surface of the interval gate 200; specifically, selecting a high dielectric constant material HfO2 as the gate dielectric layer 300, and using an atomic layer deposition process to deposit, ensuring that the gate dielectric layer 300 completely covers the surface of the substrate 100 and the top and sidewall of the interval gate 200 during the deposition process, without missing coverage areas, forming a dense and uniform insulating layer, and in the present embodiment, the dielectric constant is ≥20, which can not only achieve electrical isolation of the interval gate 200 and the upper structure, but also efficiently conduct the electric field.

[0079] Step a3, preparing the semiconductor active layer 400 on the side of the gate dielectric layer 300 away from the substrate 100; specifically, the present embodiment selects gallium oxide as the material of the semiconductor active layer 400, and uses a pulsed laser deposition process to prepare. After deposition, annealing treatment is performed in a nitrogen atmosphere; then the gallium oxide film is patterned to obtain a semiconductor active layer 400 continuously extending along the first direction X, and ensure that the orthographic projection position of the interval gate 200 on the semiconductor active layer corresponds accurately to the subsequent channel region.

[0080] Step a4, preparing a contact hole after depositing a passivation layer on the semiconductor active layer 400; specifically, the passivation layer is deposited using a plasma-enhanced chemical vapor deposition process until it completely covers the exposed areas of the semiconductor active layer 400 and the gate dielectric layer 300, achieving surface protection and surface state optimization of the semiconductor active layer. Contact holes are etched at both ends of the semiconductor active layer 400 in the first direction X and the corresponding areas of the interval gate 200, respectively, to ensure that the bottom of the contact hole accurately exposes the surface of the semiconductor active layer and the top of the interval gate 200, without residual passivation layer.

[0081] Step a5, preparing source electrode 500, drain electrode 600 and gate electrode 700, connecting both ends of the semiconductor active layer 400 in the first direction X to the source electrode 500 and the drain electrode 600 respectively, and connecting the plurality of the spacer gate 200 to the gate electrode 700, and obtaining the negative differential resistance semiconductor device after annealing. Specifically, in this embodiment, the electrodes are deposited by electron beam evaporation process, and then the source electrode 500, the drain electrode 600 and the gate electrode 700 pattern are defined by photolithography and wet etching process. After stripping the photoresist, the source electrode 500 and the drain electrode 600 form ohmic contact with the semiconductor active layer 400 at both ends through the contact hole, and the gate electrode 700 realizes electrical connection with all the spacer gates 200 through the contact hole. After annealing, the contact resistance between the electrode and the semiconductor active layer and the spacer gate 200 can be reduced, and the process internal stress can be eliminated, and the stability of the device structure is improved.

[0082] Referring to Figure 3 and Figure 4 , the transfer curve of the conventional single-gate structure device measured in the positive and negative directions with the gate voltage changing between -10V and 15V is compared with the transfer curve of the negative differential resistance semiconductor device measured in the positive and negative directions under the same gate voltage change condition. It can be seen that the negative differential resistance semiconductor device prepared by the present application has obvious hysteresis phenomenon, while the conventional single-gate structure device has almost completely coincident transfer curves whether scanning from negative to positive or from positive to negative, which proves that the conventional single-gate structure device has significantly improved controllability of hysteresis characteristics.

[0083] Embodiment two: referring to Figure 5 and Figure 6 , this embodiment provides another negative differential resistance semiconductor device, which has similar design ideas and main structures as embodiment one, and the same parts will not be described in detail here. In this embodiment, the substrate 100 is arranged on one side of the semiconductor active layer 400 in the thickness direction, the spacer gate 200 and the gate dielectric layer 300 are arranged on the other side of the semiconductor active layer 400 in the thickness direction, and the source electrode 500, the drain electrode 600 and the gate electrode 700 are arranged on the gate dielectric layer 300.

[0084] Compared with the bottom gate structure of embodiment one, in this embodiment, the localized electric field generated by the spacer gate 200 can act on the semiconductor active layer in one direction, avoiding the scattering or shielding interference of the substrate 100 side to the electric field, so that the electric field is more accurately focused on the channel region and efficiently extended to the semiconductor region, and finally the response speed and control sensitivity of the carrier accumulation / depletion hysteresis effect of the device are improved.

[0085] Further, the semiconductor active layer 400 in the embodiment can be first bonded with the substrate 100 and preliminarily processed, and then the gate dielectric layer 300 and the spacer gate 200 are prepared on the other side of the semiconductor active layer 400, which effectively avoids the compatibility conflict between the material of the spacer gate 200 and the deposition process of the semiconductor active layer, adapts to more semiconductor active layer 400 materials with high melting point and high activity, and the source electrode 500, the drain electrode 600 and the gate electrode 700 are concentrated on the surface of the gate dielectric layer 300 on the same side, which can complete the electrode preparation through one-time photolithography and deposition process, simplifies the process flow and reduces the process cost. In terms of performance stability and integration, the substrate 100 in the embodiment has no direct electrical connection with the functional structures such as the spacer gate 200 and the electrode, which can effectively isolate the influence of the surface defects and impurities of the substrate 100 on the carrier transport of the semiconductor active layer, reduce the carrier recombination loss, improve the long-term stability and consistency of the device hysteresis characteristics, and the same-side concentrated layout of the electrode and the spacer gate 200 makes the structure symmetry of the device along the thickness direction stronger, which is more conducive to high-density array integration and adapts to the miniaturization and integration of semiconductor device application scenarios.

[0086] Correspondingly, the hysteresis semiconductor device preparation method in the embodiment specifically includes:

[0087] Step b1, preparing a semiconductor active layer 400 on a clean substrate 100;

[0088] Step b2, depositing a gate dielectric layer 300 on the semiconductor active layer 400, and making the gate dielectric layer 300 completely cover the semiconductor active layer 400;

[0089] Step b3, preparing a plurality of spacer gates 200 spaced along a first direction X on the gate dielectric layer 300;

[0090] Step b4, preparing a contact hole after depositing and passivating on the spacer gate 200 and the gate dielectric layer 300;

[0091] Step b5, preparing a source electrode 500, a drain electrode 600 and a gate electrode 700, making both ends of the semiconductor active layer 400 in the first direction X respectively connected to the source electrode 500 and the drain electrode 600, and making a plurality of the spacer gates 200 all connected to the gate electrode 700, and obtaining a hysteresis semiconductor device after annealing.

[0092] Embodiment three: see Figure 7 and Figure 8As shown, the embodiment provides a hysteresis semiconductor device with another structure, the spacer gate 200 includes a plurality of top gates 210 and a plurality of bottom gates 220, and the gate dielectric layer 300 includes a top gate dielectric layer 310 and a bottom gate dielectric layer 320, wherein the bottom gate 220 is arranged on the substrate 100, the bottom gate dielectric layer 320 is connected to the substrate 100 and covers the bottom gate 220, one side of the semiconductor active layer 400 is connected to the bottom gate dielectric layer 320, and the other side is connected to the top gate dielectric layer 310, and a plurality of top gates 210 are arranged in the top gate dielectric layer 310.

[0093] Compared with the first and second embodiments, the present embodiment provides a double-gate structure. This double-gate cooperative structure design breaks through the limitations of single-side gate electric field regulation. The bottom gate 220 and the top gate 210 can respectively apply independent gate voltages, or can be simultaneously input with a regulation signal. The localized electric field can act on the channel region and the semiconductor region from both the upper and lower sides of the semiconductor active layer 400. This not only greatly enhances the regulation strength of the electric field on the conductive channel of the channel region, improves the channel conduction efficiency and stability, but also enables the electric field to cover the semiconductor region in all directions, strengthens the regulation of the carrier accumulation / depletion process of the semiconductor region, and makes the hysteresis characteristic regulation range of the device wider, the response speed faster, and the stability stronger. Meanwhile, the double-layer insulation isolation design of the double-gate dielectric layer 300 further improves the electrical safety performance of the device, effectively avoids the risk of electric leakage caused by defects in a single dielectric layer, and adapts to higher-precision and higher-reliability semiconductor device application scenarios.

[0094] Further, the gate electrode 700 includes a top gate electrode 710 and a bottom gate electrode 720, wherein the top gate electrode 710 is connected to a plurality of top gates 210, and the bottom gate electrode 720 is connected to a plurality of bottom gates 220. The localized electric field generated by the bottom gate electrode 720 driving the bottom gate 220 is conducted to the lower surface of the semiconductor active layer through the bottom gate dielectric layer 320, and the localized electric field generated by the top gate electrode 710 driving the top gate 210 is conducted to the upper surface of the semiconductor active layer through the top gate dielectric layer 310. The bidirectional electric field forms a wrapping action on the semiconductor active layer from both the upper and lower sides. This not only further enhances the regulation strength of the electric field on the conductive channel of the channel region, improves the stability and response speed of the channel conduction, but also enables the electric field to cover the semiconductor region in all directions, accurately controls the accumulation and depletion process of the carriers in the semiconductor region, makes the hysteresis characteristic regulation range of the device wider, and the precision higher. Meanwhile, the independent design of the top gate electrode 710 and the bottom gate electrode 720 can effectively avoid the signal interference problem when a single electrode is driven, improve the electrical anti-interference ability and operation reliability of the device, and adapt to high-precision and high-stability semiconductor device application requirements.

[0095] Correspondingly, the hysteresis semiconductor device preparation method in the embodiment specifically includes:

[0096] Step c1, preparing a plurality of bottom gates 220 arranged at intervals along the first direction X on the clean substrate 100;

[0097] Step c2, depositing a bottom gate dielectric layer 320 on the substrate 100, so that the bottom gate dielectric layer 320 completely covers the surface of the bottom gate 220;

[0098] Step c3, preparing the semiconductor active layer 400 on the side of the bottom gate dielectric layer 320 away from the substrate 100;

[0099] Step c4, depositing a top gate dielectric layer 310 on the semiconductor active layer 400, and making the top gate dielectric layer 310 completely cover the semiconductor active layer 400;

[0100] Step c5, preparing a plurality of top gates 210 arranged at intervals along the first direction X on the top gate dielectric layer 310;

[0101] Step c6, preparing a contact hole after depositing and passivating on the top gate 210 and the top gate dielectric layer 310;

[0102] Step c7, preparing a source electrode 500, a drain electrode 600 and a gate electrode 700, making the two ends of the semiconductor active layer 400 in the first direction X respectively connected to the source electrode 500 and the drain electrode 600, and making a plurality of the interval gates 200 connected to the gate electrode 700, and obtaining a hysteretic semiconductor device after annealing.

[0103] Embodiment four: the embodiment provides a memory comprising the hysteretic semiconductor device of embodiment one.

[0104] Embodiment five: the embodiment provides a brain-like chip comprising the hysteretic semiconductor device of embodiment one.

[0105] In summary, the hysteretic semiconductor device, the preparation method, the memory and the brain-like chip provided by the application realize the controllable hysteresis characteristic of the semiconductor device without introducing charge traps or ion migration, through the interval gate layout and the special design of the channel region and the semiconductor region on the semiconductor active layer, which has the following advantages compared with the conventional device at the present stage:

[0106] 1. The controllability of the hysteresis characteristic of the application is significantly improved, which abandons the traditional hysteresis implementation method relying on defect charge traps (strong randomness) or ion migration (uncontrollable), and through the interval of the interval gate, the arrangement density and the gate voltage scanning parameter, the hysteresis amplitude and response speed of the carrier accumulation / depletion of the semiconductor region can be accurately controlled. At the same time, the semiconductor region is not intentionally doped, which avoids the problems of defect state density fluctuation and ion migration fatigue, and greatly improves the long-term stability.

[0107] 2. The process is compatible, without the need to introduce special materials or complex processes, the spacer gate, gate dielectric layer and semiconductor active layer are prepared by conventional semiconductor process, and the semiconductor active layer substrate is compatible with the existing CMOS process. In addition, the device structure has no additional stacking or heterojunction design, and the process steps are simplified, thereby effectively reducing the process complexity and production cost, avoiding the high voltage drive and interface shielding problem of traditional ferroelectric integration.

[0108] 3. The application has low power consumption and high reliability, and is suitable for multiple scene applications. The localized electric field of the spacer gate can be effectively extended to the semiconductor region with low gate voltage, inducing hysteresis characteristics. Compared with the high drive voltage of the traditional ferroelectric mechanism, the power consumption can be significantly reduced. At the same time, due to the interface damage caused by charge trap capture / release or ion migration, the device leakage current is small, the static power consumption is significantly optimized, and its stable and controllable hysteresis characteristics can be widely adapted to low-power memory, neuromorphic computing chips, high-precision sensors and other scenes, especially for portable electronic devices, industrial control and other fields that require high reliability and power consumption.

[0109] 4. The device consistency of the application is excellent, which can well overcome the problem that the randomness of defect distribution and ion migration path in the traditional mechanism leads to significant differences in hysteresis characteristics between devices, thereby hindering standardized production. The present scheme precisely controls the structure, so that the hysteresis consistency between devices is much better than the traditional scheme, providing a reliable foundation for large-scale production and system integration.

[0110] Obviously, the above embodiments are only examples for clear illustration, and are not limited to the embodiments. For ordinary skilled in the art, other different forms of changes or variations can be made on the basis of the above description. Here, all the embodiments are not required to be exhausted. The obvious changes or variations derived therefrom are still within the protection scope of the present application.

Claims

1. A regenerative semiconductor device, characterized by: Comprising: a substrate and a plurality of spacer gates, a gate dielectric layer, a semiconductor active layer, a source electrode, a drain electrode and a gate electrode disposed on the substrate, wherein the semiconductor active layer continuously extends along a first direction, both ends of the first direction are electrically connected to the source electrode and the drain electrode, respectively, and the semiconductor active layer comprises a channel region and a semiconductor region, the semiconductor region is located between adjacent channel regions; the gate dielectric layer covers the surface of the semiconductor active layer, and the coverage range of the gate dielectric layer simultaneously contains the channel region and the semiconductor region; a plurality of spacer gates are connected to the gate electrode and are isolated by the gate dielectric layer and the semiconductor active layer, a plurality of spacer gates are disposed in the same direction and are spaced along the first direction, the orthogonal projection of a plurality of spacer gates on the semiconductor active layer coincides with the channel region, so that the channel region forms a conductive channel under the control of the gate voltage, and the localized electric field generated by the spacer gate can extend to the semiconductor region and induce the semiconductor region to generate carrier accumulation / depletion delay.

2. The nonreciprocal semiconductor device according to claim 1, characterized by: A plurality of spacer gates are uniformly spaced along the first direction, and the spacing distance between adjacent spacer gates is <5μm.

3. The nonreciprocal semiconductor device according to claim 1, wherein: The spacer gate is disposed on the substrate, the gate dielectric layer is connected to the substrate and covers the spacer gate, and the semiconductor active layer, the source electrode, the drain electrode and the gate electrode are disposed on the gate dielectric layer.

4. The nonreciprocal semiconductor device according to claim 1, wherein: The substrate is disposed on one side of the semiconductor active layer in the thickness direction, and the spacer gate and the gate dielectric layer are disposed on the other side of the semiconductor active layer in the thickness direction, and the source electrode, the drain electrode and the gate electrode are disposed on the gate dielectric layer.

5. The nonreciprocal semiconductor device according to claim 1, wherein: The spacer gate includes a plurality of top gates and a plurality of bottom gates, and the gate dielectric layer includes a top gate dielectric layer and a bottom gate dielectric layer, wherein the bottom gate is disposed on the substrate, the bottom gate dielectric layer is connected to the substrate and covers the bottom gate, one side of the semiconductor active layer is connected to the bottom gate dielectric layer, and the other side is connected to the top gate dielectric layer, and a plurality of top gates are disposed in the top gate dielectric layer.

6. The nonreciprocal semiconductor device according to claim 5, wherein: The gate electrode includes a top gate electrode and a bottom gate electrode, wherein the top gate electrode is connected to a plurality of top gates, and the bottom gate electrode is connected to a plurality of bottom gates.

7. The nonreciprocal semiconductor device according to claim 1, wherein: The semiconductor active layer substrate is one or more of indium gallium zinc oxide, zinc oxide, indium tin oxide, indium gallium zinc oxide, aluminum indium tin zinc oxide.

8. A method of making a regenerative semiconductor device, the method comprising: A method for preparing a backscattering semiconductor device according to any one of claims 1-7, comprising: preparing a plurality of spacer gates, a gate dielectric layer and a semiconductor active layer on a clean substrate, wherein the spacer gates are isolated by the gate dielectric layer and the semiconductor active layer, a plurality of spacer gates are disposed in the same direction and are spaced along a first direction; the semiconductor active layer preparation process is: step S1, dividing a channel region and a semiconductor region on the semiconductor active layer substrate, wherein the semiconductor region is located between adjacent channel regions, and the orthogonal projection of a plurality of spacer gates on the semiconductor active layer coincides with the channel region; Step S2, connecting the source electrode and the drain electrode to the two ends of the semiconductor active layer in the first direction respectively, and leading out the gate electrode of the interval gate to form a conductive channel in the channel region under the control of the gate voltage, and the localized electric field generated by the interval gate can extend to the semiconductor region and induce the semiconductor region to generate carrier accumulation / depletion hysteresis.

9. The method of claim 8, wherein: The preparation method of the hysteresis semiconductor device specifically comprises: Step a1, preparing a plurality of interval gates arranged in the first direction on a clean substrate; Step a2, depositing a gate dielectric layer on the substrate, so that the gate dielectric layer completely covers the surface of the interval gate; Step a3, preparing the semiconductor active layer on the side of the gate dielectric layer away from the substrate; Step a4, preparing a contact hole after depositing passivation on the semiconductor active layer; Step a5, preparing a source electrode, a drain electrode and a gate electrode, connecting the source electrode and the drain electrode to the two ends of the semiconductor active layer in the first direction respectively, and connecting the plurality of interval gates to the gate electrode, thereby obtaining the hysteresis semiconductor device.

10. The method of claim 8, wherein: The preparation method of the hysteresis semiconductor device specifically comprises: Step b1, preparing a semiconductor active layer on a clean substrate; Step b2, depositing a gate dielectric layer on the semiconductor active layer, so that the gate dielectric layer completely covers the semiconductor active layer; Step b3, preparing a plurality of interval gates arranged in the first direction on the gate dielectric layer; Step b4, preparing a contact hole after depositing passivation on the interval gate and the gate dielectric layer; Step b5, preparing a source electrode, a drain electrode and a gate electrode, connecting the source electrode and the drain electrode to the two ends of the semiconductor active layer in the first direction respectively, and connecting the plurality of interval gates to the gate electrode, thereby obtaining the hysteresis semiconductor device.

11. The method of claim 8, wherein: The preparation method of the hysteresis semiconductor device specifically comprises: Step c1, preparing a plurality of bottom gates arranged in the first direction on a clean substrate; Step c2, depositing a bottom gate dielectric layer on the substrate, so that the bottom gate dielectric layer completely covers the surface of the bottom gate; Step c3, preparing the semiconductor active layer on the side of the bottom gate dielectric layer away from the substrate; Step c4, depositing a top gate dielectric layer on the semiconductor active layer, so that the top gate dielectric layer completely covers the semiconductor active layer; Step c5, preparing a plurality of top gates arranged in the first direction on the top gate dielectric layer; Step c6, preparing a contact hole after depositing passivation on the top gate and the top gate dielectric layer; Step c7, preparing a source electrode, a drain electrode and a gate electrode, connecting the source electrode and the drain electrode to the two ends of the semiconductor active layer in the first direction respectively, and connecting the plurality of interval gates to the gate electrode, thereby obtaining the hysteresis semiconductor device.

12. A memory, comprising: The hysteresis semiconductor device according to any one of claims 1-7.

13. A brain-like chip, characterized by: The hysteresis semiconductor device according to any one of claims 1-7.

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